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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI Express I/O Virtualization (IOV) support
4 * Address Translation Service 1.0
5 * Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
6 * PASID support added by Joerg Roedel <joerg.roedel@amd.com>
7 *
8 * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
9 * Copyright (C) 2011 Advanced Micro Devices,
10 */
11
12#include <linux/export.h>
13#include <linux/pci-ats.h>
14#include <linux/pci.h>
15#include <linux/slab.h>
16
17#include "pci.h"
18
19void pci_ats_init(struct pci_dev *dev)
20{
21 int pos;
22
23 if (pci_ats_disabled())
24 return;
25
26 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
27 if (!pos)
28 return;
29
30 dev->ats_cap = pos;
31}
32
33/**
34 * pci_ats_supported - check if the device can use ATS
35 * @dev: the PCI device
36 *
37 * Returns true if the device supports ATS and is allowed to use it, false
38 * otherwise.
39 */
40bool pci_ats_supported(struct pci_dev *dev)
41{
42 if (!dev->ats_cap)
43 return false;
44
45 return (dev->untrusted == 0);
46}
47EXPORT_SYMBOL_GPL(pci_ats_supported);
48
49/**
50 * pci_enable_ats - enable the ATS capability
51 * @dev: the PCI device
52 * @ps: the IOMMU page shift
53 *
54 * Returns 0 on success, or negative on failure.
55 */
56int pci_enable_ats(struct pci_dev *dev, int ps)
57{
58 u16 ctrl;
59 struct pci_dev *pdev;
60
61 if (!pci_ats_supported(dev))
62 return -EINVAL;
63
64 if (WARN_ON(dev->ats_enabled))
65 return -EBUSY;
66
67 if (ps < PCI_ATS_MIN_STU)
68 return -EINVAL;
69
70 /*
71 * Note that enabling ATS on a VF fails unless it's already enabled
72 * with the same STU on the PF.
73 */
74 ctrl = PCI_ATS_CTRL_ENABLE;
75 if (dev->is_virtfn) {
76 pdev = pci_physfn(dev);
77 if (pdev->ats_stu != ps)
78 return -EINVAL;
79 } else {
80 dev->ats_stu = ps;
81 ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
82 }
83 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
84
85 dev->ats_enabled = 1;
86 return 0;
87}
88EXPORT_SYMBOL_GPL(pci_enable_ats);
89
90/**
91 * pci_disable_ats - disable the ATS capability
92 * @dev: the PCI device
93 */
94void pci_disable_ats(struct pci_dev *dev)
95{
96 u16 ctrl;
97
98 if (WARN_ON(!dev->ats_enabled))
99 return;
100
101 pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
102 ctrl &= ~PCI_ATS_CTRL_ENABLE;
103 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
104
105 dev->ats_enabled = 0;
106}
107EXPORT_SYMBOL_GPL(pci_disable_ats);
108
109void pci_restore_ats_state(struct pci_dev *dev)
110{
111 u16 ctrl;
112
113 if (!dev->ats_enabled)
114 return;
115
116 ctrl = PCI_ATS_CTRL_ENABLE;
117 if (!dev->is_virtfn)
118 ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
119 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
120}
121
122/**
123 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
124 * @dev: the PCI device
125 *
126 * Returns the queue depth on success, or negative on failure.
127 *
128 * The ATS spec uses 0 in the Invalidate Queue Depth field to
129 * indicate that the function can accept 32 Invalidate Request.
130 * But here we use the `real' values (i.e. 1~32) for the Queue
131 * Depth; and 0 indicates the function shares the Queue with
132 * other functions (doesn't exclusively own a Queue).
133 */
134int pci_ats_queue_depth(struct pci_dev *dev)
135{
136 u16 cap;
137
138 if (!dev->ats_cap)
139 return -EINVAL;
140
141 if (dev->is_virtfn)
142 return 0;
143
144 pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
145 return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
146}
147
148/**
149 * pci_ats_page_aligned - Return Page Aligned Request bit status.
150 * @pdev: the PCI device
151 *
152 * Returns 1, if the Untranslated Addresses generated by the device
153 * are always aligned or 0 otherwise.
154 *
155 * Per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit
156 * is set, it indicates the Untranslated Addresses generated by the
157 * device are always aligned to a 4096 byte boundary.
158 */
159int pci_ats_page_aligned(struct pci_dev *pdev)
160{
161 u16 cap;
162
163 if (!pdev->ats_cap)
164 return 0;
165
166 pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);
167
168 if (cap & PCI_ATS_CAP_PAGE_ALIGNED)
169 return 1;
170
171 return 0;
172}
173
174#ifdef CONFIG_PCI_PRI
175void pci_pri_init(struct pci_dev *pdev)
176{
177 u16 status;
178
179 pdev->pri_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
180
181 if (!pdev->pri_cap)
182 return;
183
184 pci_read_config_word(pdev, pdev->pri_cap + PCI_PRI_STATUS, &status);
185 if (status & PCI_PRI_STATUS_PASID)
186 pdev->pasid_required = 1;
187}
188
189/**
190 * pci_enable_pri - Enable PRI capability
191 * @pdev: PCI device structure
192 * @reqs: outstanding requests
193 *
194 * Returns 0 on success, negative value on error
195 */
196int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
197{
198 u16 control, status;
199 u32 max_requests;
200 int pri = pdev->pri_cap;
201
202 /*
203 * VFs must not implement the PRI Capability. If their PF
204 * implements PRI, it is shared by the VFs, so if the PF PRI is
205 * enabled, it is also enabled for the VF.
206 */
207 if (pdev->is_virtfn) {
208 if (pci_physfn(pdev)->pri_enabled)
209 return 0;
210 return -EINVAL;
211 }
212
213 if (WARN_ON(pdev->pri_enabled))
214 return -EBUSY;
215
216 if (!pri)
217 return -EINVAL;
218
219 pci_read_config_word(pdev, pri + PCI_PRI_STATUS, &status);
220 if (!(status & PCI_PRI_STATUS_STOPPED))
221 return -EBUSY;
222
223 pci_read_config_dword(pdev, pri + PCI_PRI_MAX_REQ, &max_requests);
224 reqs = min(max_requests, reqs);
225 pdev->pri_reqs_alloc = reqs;
226 pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs);
227
228 control = PCI_PRI_CTRL_ENABLE;
229 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
230
231 pdev->pri_enabled = 1;
232
233 return 0;
234}
235
236/**
237 * pci_disable_pri - Disable PRI capability
238 * @pdev: PCI device structure
239 *
240 * Only clears the enabled-bit, regardless of its former value
241 */
242void pci_disable_pri(struct pci_dev *pdev)
243{
244 u16 control;
245 int pri = pdev->pri_cap;
246
247 /* VFs share the PF PRI */
248 if (pdev->is_virtfn)
249 return;
250
251 if (WARN_ON(!pdev->pri_enabled))
252 return;
253
254 if (!pri)
255 return;
256
257 pci_read_config_word(pdev, pri + PCI_PRI_CTRL, &control);
258 control &= ~PCI_PRI_CTRL_ENABLE;
259 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
260
261 pdev->pri_enabled = 0;
262}
263EXPORT_SYMBOL_GPL(pci_disable_pri);
264
265/**
266 * pci_restore_pri_state - Restore PRI
267 * @pdev: PCI device structure
268 */
269void pci_restore_pri_state(struct pci_dev *pdev)
270{
271 u16 control = PCI_PRI_CTRL_ENABLE;
272 u32 reqs = pdev->pri_reqs_alloc;
273 int pri = pdev->pri_cap;
274
275 if (pdev->is_virtfn)
276 return;
277
278 if (!pdev->pri_enabled)
279 return;
280
281 if (!pri)
282 return;
283
284 pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs);
285 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
286}
287
288/**
289 * pci_reset_pri - Resets device's PRI state
290 * @pdev: PCI device structure
291 *
292 * The PRI capability must be disabled before this function is called.
293 * Returns 0 on success, negative value on error.
294 */
295int pci_reset_pri(struct pci_dev *pdev)
296{
297 u16 control;
298 int pri = pdev->pri_cap;
299
300 if (pdev->is_virtfn)
301 return 0;
302
303 if (WARN_ON(pdev->pri_enabled))
304 return -EBUSY;
305
306 if (!pri)
307 return -EINVAL;
308
309 control = PCI_PRI_CTRL_RESET;
310 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
311
312 return 0;
313}
314
315/**
316 * pci_prg_resp_pasid_required - Return PRG Response PASID Required bit
317 * status.
318 * @pdev: PCI device structure
319 *
320 * Returns 1 if PASID is required in PRG Response Message, 0 otherwise.
321 */
322int pci_prg_resp_pasid_required(struct pci_dev *pdev)
323{
324 if (pdev->is_virtfn)
325 pdev = pci_physfn(pdev);
326
327 return pdev->pasid_required;
328}
329
330/**
331 * pci_pri_supported - Check if PRI is supported.
332 * @pdev: PCI device structure
333 *
334 * Returns true if PRI capability is present, false otherwise.
335 */
336bool pci_pri_supported(struct pci_dev *pdev)
337{
338 /* VFs share the PF PRI */
339 if (pci_physfn(pdev)->pri_cap)
340 return true;
341 return false;
342}
343EXPORT_SYMBOL_GPL(pci_pri_supported);
344#endif /* CONFIG_PCI_PRI */
345
346#ifdef CONFIG_PCI_PASID
347void pci_pasid_init(struct pci_dev *pdev)
348{
349 pdev->pasid_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
350}
351
352/**
353 * pci_enable_pasid - Enable the PASID capability
354 * @pdev: PCI device structure
355 * @features: Features to enable
356 *
357 * Returns 0 on success, negative value on error. This function checks
358 * whether the features are actually supported by the device and returns
359 * an error if not.
360 */
361int pci_enable_pasid(struct pci_dev *pdev, int features)
362{
363 u16 control, supported;
364 int pasid = pdev->pasid_cap;
365
366 /*
367 * VFs must not implement the PASID Capability, but if a PF
368 * supports PASID, its VFs share the PF PASID configuration.
369 */
370 if (pdev->is_virtfn) {
371 if (pci_physfn(pdev)->pasid_enabled)
372 return 0;
373 return -EINVAL;
374 }
375
376 if (WARN_ON(pdev->pasid_enabled))
377 return -EBUSY;
378
379 if (!pdev->eetlp_prefix_path)
380 return -EINVAL;
381
382 if (!pasid)
383 return -EINVAL;
384
385 pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
386 supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
387
388 /* User wants to enable anything unsupported? */
389 if ((supported & features) != features)
390 return -EINVAL;
391
392 control = PCI_PASID_CTRL_ENABLE | features;
393 pdev->pasid_features = features;
394
395 pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
396
397 pdev->pasid_enabled = 1;
398
399 return 0;
400}
401EXPORT_SYMBOL_GPL(pci_enable_pasid);
402
403/**
404 * pci_disable_pasid - Disable the PASID capability
405 * @pdev: PCI device structure
406 */
407void pci_disable_pasid(struct pci_dev *pdev)
408{
409 u16 control = 0;
410 int pasid = pdev->pasid_cap;
411
412 /* VFs share the PF PASID configuration */
413 if (pdev->is_virtfn)
414 return;
415
416 if (WARN_ON(!pdev->pasid_enabled))
417 return;
418
419 if (!pasid)
420 return;
421
422 pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
423
424 pdev->pasid_enabled = 0;
425}
426EXPORT_SYMBOL_GPL(pci_disable_pasid);
427
428/**
429 * pci_restore_pasid_state - Restore PASID capabilities
430 * @pdev: PCI device structure
431 */
432void pci_restore_pasid_state(struct pci_dev *pdev)
433{
434 u16 control;
435 int pasid = pdev->pasid_cap;
436
437 if (pdev->is_virtfn)
438 return;
439
440 if (!pdev->pasid_enabled)
441 return;
442
443 if (!pasid)
444 return;
445
446 control = PCI_PASID_CTRL_ENABLE | pdev->pasid_features;
447 pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
448}
449
450/**
451 * pci_pasid_features - Check which PASID features are supported
452 * @pdev: PCI device structure
453 *
454 * Returns a negative value when no PASI capability is present.
455 * Otherwise is returns a bitmask with supported features. Current
456 * features reported are:
457 * PCI_PASID_CAP_EXEC - Execute permission supported
458 * PCI_PASID_CAP_PRIV - Privileged mode supported
459 */
460int pci_pasid_features(struct pci_dev *pdev)
461{
462 u16 supported;
463 int pasid;
464
465 if (pdev->is_virtfn)
466 pdev = pci_physfn(pdev);
467
468 pasid = pdev->pasid_cap;
469 if (!pasid)
470 return -EINVAL;
471
472 pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
473
474 supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
475
476 return supported;
477}
478EXPORT_SYMBOL_GPL(pci_pasid_features);
479
480#define PASID_NUMBER_SHIFT 8
481#define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT)
482/**
483 * pci_max_pasid - Get maximum number of PASIDs supported by device
484 * @pdev: PCI device structure
485 *
486 * Returns negative value when PASID capability is not present.
487 * Otherwise it returns the number of supported PASIDs.
488 */
489int pci_max_pasids(struct pci_dev *pdev)
490{
491 u16 supported;
492 int pasid;
493
494 if (pdev->is_virtfn)
495 pdev = pci_physfn(pdev);
496
497 pasid = pdev->pasid_cap;
498 if (!pasid)
499 return -EINVAL;
500
501 pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
502
503 supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
504
505 return (1 << supported);
506}
507EXPORT_SYMBOL_GPL(pci_max_pasids);
508#endif /* CONFIG_PCI_PASID */
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI Express I/O Virtualization (IOV) support
4 * Address Translation Service 1.0
5 * Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
6 * PASID support added by Joerg Roedel <joerg.roedel@amd.com>
7 *
8 * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
9 * Copyright (C) 2011 Advanced Micro Devices,
10 */
11
12#include <linux/bitfield.h>
13#include <linux/export.h>
14#include <linux/pci-ats.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17
18#include "pci.h"
19
20void pci_ats_init(struct pci_dev *dev)
21{
22 int pos;
23
24 if (pci_ats_disabled())
25 return;
26
27 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
28 if (!pos)
29 return;
30
31 dev->ats_cap = pos;
32}
33
34/**
35 * pci_ats_supported - check if the device can use ATS
36 * @dev: the PCI device
37 *
38 * Returns true if the device supports ATS and is allowed to use it, false
39 * otherwise.
40 */
41bool pci_ats_supported(struct pci_dev *dev)
42{
43 if (!dev->ats_cap)
44 return false;
45
46 return (dev->untrusted == 0);
47}
48EXPORT_SYMBOL_GPL(pci_ats_supported);
49
50/**
51 * pci_enable_ats - enable the ATS capability
52 * @dev: the PCI device
53 * @ps: the IOMMU page shift
54 *
55 * Returns 0 on success, or negative on failure.
56 */
57int pci_enable_ats(struct pci_dev *dev, int ps)
58{
59 u16 ctrl;
60 struct pci_dev *pdev;
61
62 if (!pci_ats_supported(dev))
63 return -EINVAL;
64
65 if (WARN_ON(dev->ats_enabled))
66 return -EBUSY;
67
68 if (ps < PCI_ATS_MIN_STU)
69 return -EINVAL;
70
71 /*
72 * Note that enabling ATS on a VF fails unless it's already enabled
73 * with the same STU on the PF.
74 */
75 ctrl = PCI_ATS_CTRL_ENABLE;
76 if (dev->is_virtfn) {
77 pdev = pci_physfn(dev);
78 if (pdev->ats_stu != ps)
79 return -EINVAL;
80 } else {
81 dev->ats_stu = ps;
82 ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
83 }
84 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
85
86 dev->ats_enabled = 1;
87 return 0;
88}
89EXPORT_SYMBOL_GPL(pci_enable_ats);
90
91/**
92 * pci_disable_ats - disable the ATS capability
93 * @dev: the PCI device
94 */
95void pci_disable_ats(struct pci_dev *dev)
96{
97 u16 ctrl;
98
99 if (WARN_ON(!dev->ats_enabled))
100 return;
101
102 pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, &ctrl);
103 ctrl &= ~PCI_ATS_CTRL_ENABLE;
104 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
105
106 dev->ats_enabled = 0;
107}
108EXPORT_SYMBOL_GPL(pci_disable_ats);
109
110void pci_restore_ats_state(struct pci_dev *dev)
111{
112 u16 ctrl;
113
114 if (!dev->ats_enabled)
115 return;
116
117 ctrl = PCI_ATS_CTRL_ENABLE;
118 if (!dev->is_virtfn)
119 ctrl |= PCI_ATS_CTRL_STU(dev->ats_stu - PCI_ATS_MIN_STU);
120 pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl);
121}
122
123/**
124 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
125 * @dev: the PCI device
126 *
127 * Returns the queue depth on success, or negative on failure.
128 *
129 * The ATS spec uses 0 in the Invalidate Queue Depth field to
130 * indicate that the function can accept 32 Invalidate Request.
131 * But here we use the `real' values (i.e. 1~32) for the Queue
132 * Depth; and 0 indicates the function shares the Queue with
133 * other functions (doesn't exclusively own a Queue).
134 */
135int pci_ats_queue_depth(struct pci_dev *dev)
136{
137 u16 cap;
138
139 if (!dev->ats_cap)
140 return -EINVAL;
141
142 if (dev->is_virtfn)
143 return 0;
144
145 pci_read_config_word(dev, dev->ats_cap + PCI_ATS_CAP, &cap);
146 return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) : PCI_ATS_MAX_QDEP;
147}
148
149/**
150 * pci_ats_page_aligned - Return Page Aligned Request bit status.
151 * @pdev: the PCI device
152 *
153 * Returns 1, if the Untranslated Addresses generated by the device
154 * are always aligned or 0 otherwise.
155 *
156 * Per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit
157 * is set, it indicates the Untranslated Addresses generated by the
158 * device are always aligned to a 4096 byte boundary.
159 */
160int pci_ats_page_aligned(struct pci_dev *pdev)
161{
162 u16 cap;
163
164 if (!pdev->ats_cap)
165 return 0;
166
167 pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);
168
169 if (cap & PCI_ATS_CAP_PAGE_ALIGNED)
170 return 1;
171
172 return 0;
173}
174
175#ifdef CONFIG_PCI_PRI
176void pci_pri_init(struct pci_dev *pdev)
177{
178 u16 status;
179
180 pdev->pri_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
181
182 if (!pdev->pri_cap)
183 return;
184
185 pci_read_config_word(pdev, pdev->pri_cap + PCI_PRI_STATUS, &status);
186 if (status & PCI_PRI_STATUS_PASID)
187 pdev->pasid_required = 1;
188}
189
190/**
191 * pci_enable_pri - Enable PRI capability
192 * @pdev: PCI device structure
193 * @reqs: outstanding requests
194 *
195 * Returns 0 on success, negative value on error
196 */
197int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
198{
199 u16 control, status;
200 u32 max_requests;
201 int pri = pdev->pri_cap;
202
203 /*
204 * VFs must not implement the PRI Capability. If their PF
205 * implements PRI, it is shared by the VFs, so if the PF PRI is
206 * enabled, it is also enabled for the VF.
207 */
208 if (pdev->is_virtfn) {
209 if (pci_physfn(pdev)->pri_enabled)
210 return 0;
211 return -EINVAL;
212 }
213
214 if (WARN_ON(pdev->pri_enabled))
215 return -EBUSY;
216
217 if (!pri)
218 return -EINVAL;
219
220 pci_read_config_word(pdev, pri + PCI_PRI_STATUS, &status);
221 if (!(status & PCI_PRI_STATUS_STOPPED))
222 return -EBUSY;
223
224 pci_read_config_dword(pdev, pri + PCI_PRI_MAX_REQ, &max_requests);
225 reqs = min(max_requests, reqs);
226 pdev->pri_reqs_alloc = reqs;
227 pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs);
228
229 control = PCI_PRI_CTRL_ENABLE;
230 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
231
232 pdev->pri_enabled = 1;
233
234 return 0;
235}
236
237/**
238 * pci_disable_pri - Disable PRI capability
239 * @pdev: PCI device structure
240 *
241 * Only clears the enabled-bit, regardless of its former value
242 */
243void pci_disable_pri(struct pci_dev *pdev)
244{
245 u16 control;
246 int pri = pdev->pri_cap;
247
248 /* VFs share the PF PRI */
249 if (pdev->is_virtfn)
250 return;
251
252 if (WARN_ON(!pdev->pri_enabled))
253 return;
254
255 if (!pri)
256 return;
257
258 pci_read_config_word(pdev, pri + PCI_PRI_CTRL, &control);
259 control &= ~PCI_PRI_CTRL_ENABLE;
260 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
261
262 pdev->pri_enabled = 0;
263}
264EXPORT_SYMBOL_GPL(pci_disable_pri);
265
266/**
267 * pci_restore_pri_state - Restore PRI
268 * @pdev: PCI device structure
269 */
270void pci_restore_pri_state(struct pci_dev *pdev)
271{
272 u16 control = PCI_PRI_CTRL_ENABLE;
273 u32 reqs = pdev->pri_reqs_alloc;
274 int pri = pdev->pri_cap;
275
276 if (pdev->is_virtfn)
277 return;
278
279 if (!pdev->pri_enabled)
280 return;
281
282 if (!pri)
283 return;
284
285 pci_write_config_dword(pdev, pri + PCI_PRI_ALLOC_REQ, reqs);
286 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
287}
288
289/**
290 * pci_reset_pri - Resets device's PRI state
291 * @pdev: PCI device structure
292 *
293 * The PRI capability must be disabled before this function is called.
294 * Returns 0 on success, negative value on error.
295 */
296int pci_reset_pri(struct pci_dev *pdev)
297{
298 u16 control;
299 int pri = pdev->pri_cap;
300
301 if (pdev->is_virtfn)
302 return 0;
303
304 if (WARN_ON(pdev->pri_enabled))
305 return -EBUSY;
306
307 if (!pri)
308 return -EINVAL;
309
310 control = PCI_PRI_CTRL_RESET;
311 pci_write_config_word(pdev, pri + PCI_PRI_CTRL, control);
312
313 return 0;
314}
315
316/**
317 * pci_prg_resp_pasid_required - Return PRG Response PASID Required bit
318 * status.
319 * @pdev: PCI device structure
320 *
321 * Returns 1 if PASID is required in PRG Response Message, 0 otherwise.
322 */
323int pci_prg_resp_pasid_required(struct pci_dev *pdev)
324{
325 if (pdev->is_virtfn)
326 pdev = pci_physfn(pdev);
327
328 return pdev->pasid_required;
329}
330
331/**
332 * pci_pri_supported - Check if PRI is supported.
333 * @pdev: PCI device structure
334 *
335 * Returns true if PRI capability is present, false otherwise.
336 */
337bool pci_pri_supported(struct pci_dev *pdev)
338{
339 /* VFs share the PF PRI */
340 if (pci_physfn(pdev)->pri_cap)
341 return true;
342 return false;
343}
344EXPORT_SYMBOL_GPL(pci_pri_supported);
345#endif /* CONFIG_PCI_PRI */
346
347#ifdef CONFIG_PCI_PASID
348void pci_pasid_init(struct pci_dev *pdev)
349{
350 pdev->pasid_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
351}
352
353/**
354 * pci_enable_pasid - Enable the PASID capability
355 * @pdev: PCI device structure
356 * @features: Features to enable
357 *
358 * Returns 0 on success, negative value on error. This function checks
359 * whether the features are actually supported by the device and returns
360 * an error if not.
361 */
362int pci_enable_pasid(struct pci_dev *pdev, int features)
363{
364 u16 control, supported;
365 int pasid = pdev->pasid_cap;
366
367 /*
368 * VFs must not implement the PASID Capability, but if a PF
369 * supports PASID, its VFs share the PF PASID configuration.
370 */
371 if (pdev->is_virtfn) {
372 if (pci_physfn(pdev)->pasid_enabled)
373 return 0;
374 return -EINVAL;
375 }
376
377 if (WARN_ON(pdev->pasid_enabled))
378 return -EBUSY;
379
380 if (!pdev->eetlp_prefix_path && !pdev->pasid_no_tlp)
381 return -EINVAL;
382
383 if (!pasid)
384 return -EINVAL;
385
386 if (!pci_acs_path_enabled(pdev, NULL, PCI_ACS_RR | PCI_ACS_UF))
387 return -EINVAL;
388
389 pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
390 supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
391
392 /* User wants to enable anything unsupported? */
393 if ((supported & features) != features)
394 return -EINVAL;
395
396 control = PCI_PASID_CTRL_ENABLE | features;
397 pdev->pasid_features = features;
398
399 pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
400
401 pdev->pasid_enabled = 1;
402
403 return 0;
404}
405EXPORT_SYMBOL_GPL(pci_enable_pasid);
406
407/**
408 * pci_disable_pasid - Disable the PASID capability
409 * @pdev: PCI device structure
410 */
411void pci_disable_pasid(struct pci_dev *pdev)
412{
413 u16 control = 0;
414 int pasid = pdev->pasid_cap;
415
416 /* VFs share the PF PASID configuration */
417 if (pdev->is_virtfn)
418 return;
419
420 if (WARN_ON(!pdev->pasid_enabled))
421 return;
422
423 if (!pasid)
424 return;
425
426 pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
427
428 pdev->pasid_enabled = 0;
429}
430EXPORT_SYMBOL_GPL(pci_disable_pasid);
431
432/**
433 * pci_restore_pasid_state - Restore PASID capabilities
434 * @pdev: PCI device structure
435 */
436void pci_restore_pasid_state(struct pci_dev *pdev)
437{
438 u16 control;
439 int pasid = pdev->pasid_cap;
440
441 if (pdev->is_virtfn)
442 return;
443
444 if (!pdev->pasid_enabled)
445 return;
446
447 if (!pasid)
448 return;
449
450 control = PCI_PASID_CTRL_ENABLE | pdev->pasid_features;
451 pci_write_config_word(pdev, pasid + PCI_PASID_CTRL, control);
452}
453
454/**
455 * pci_pasid_features - Check which PASID features are supported
456 * @pdev: PCI device structure
457 *
458 * Returns a negative value when no PASI capability is present.
459 * Otherwise is returns a bitmask with supported features. Current
460 * features reported are:
461 * PCI_PASID_CAP_EXEC - Execute permission supported
462 * PCI_PASID_CAP_PRIV - Privileged mode supported
463 */
464int pci_pasid_features(struct pci_dev *pdev)
465{
466 u16 supported;
467 int pasid;
468
469 if (pdev->is_virtfn)
470 pdev = pci_physfn(pdev);
471
472 pasid = pdev->pasid_cap;
473 if (!pasid)
474 return -EINVAL;
475
476 pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
477
478 supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
479
480 return supported;
481}
482EXPORT_SYMBOL_GPL(pci_pasid_features);
483
484/**
485 * pci_max_pasids - Get maximum number of PASIDs supported by device
486 * @pdev: PCI device structure
487 *
488 * Returns negative value when PASID capability is not present.
489 * Otherwise it returns the number of supported PASIDs.
490 */
491int pci_max_pasids(struct pci_dev *pdev)
492{
493 u16 supported;
494 int pasid;
495
496 if (pdev->is_virtfn)
497 pdev = pci_physfn(pdev);
498
499 pasid = pdev->pasid_cap;
500 if (!pasid)
501 return -EINVAL;
502
503 pci_read_config_word(pdev, pasid + PCI_PASID_CAP, &supported);
504
505 return (1 << FIELD_GET(PCI_PASID_CAP_WIDTH, supported));
506}
507EXPORT_SYMBOL_GPL(pci_max_pasids);
508#endif /* CONFIG_PCI_PASID */