Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * arch/arm/mach-tegra/gpio.c
4 *
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author:
9 * Erik Gilling <konkers@google.com>
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/irq.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/gpio/driver.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/module.h>
21#include <linux/irqdomain.h>
22#include <linux/irqchip/chained_irq.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/pm.h>
25
26#define GPIO_BANK(x) ((x) >> 5)
27#define GPIO_PORT(x) (((x) >> 3) & 0x3)
28#define GPIO_BIT(x) ((x) & 0x7)
29
30#define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
31 GPIO_PORT(x) * 4)
32
33#define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
34#define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
35#define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
36#define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
37#define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
38#define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
39#define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
40#define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
41#define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
42
43
44#define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
45#define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
46#define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
47#define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
48#define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
49#define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
50#define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
51
52#define GPIO_INT_LVL_MASK 0x010101
53#define GPIO_INT_LVL_EDGE_RISING 0x000101
54#define GPIO_INT_LVL_EDGE_FALLING 0x000100
55#define GPIO_INT_LVL_EDGE_BOTH 0x010100
56#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
57#define GPIO_INT_LVL_LEVEL_LOW 0x000000
58
59struct tegra_gpio_info;
60
61struct tegra_gpio_bank {
62 unsigned int bank;
63 unsigned int irq;
64 spinlock_t lvl_lock[4];
65 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
66#ifdef CONFIG_PM_SLEEP
67 u32 cnf[4];
68 u32 out[4];
69 u32 oe[4];
70 u32 int_enb[4];
71 u32 int_lvl[4];
72 u32 wake_enb[4];
73 u32 dbc_enb[4];
74#endif
75 u32 dbc_cnt[4];
76 struct tegra_gpio_info *tgi;
77};
78
79struct tegra_gpio_soc_config {
80 bool debounce_supported;
81 u32 bank_stride;
82 u32 upper_offset;
83};
84
85struct tegra_gpio_info {
86 struct device *dev;
87 void __iomem *regs;
88 struct irq_domain *irq_domain;
89 struct tegra_gpio_bank *bank_info;
90 const struct tegra_gpio_soc_config *soc;
91 struct gpio_chip gc;
92 struct irq_chip ic;
93 u32 bank_count;
94};
95
96static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
97 u32 val, u32 reg)
98{
99 writel_relaxed(val, tgi->regs + reg);
100}
101
102static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
103{
104 return readl_relaxed(tgi->regs + reg);
105}
106
107static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
108 unsigned int bit)
109{
110 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
111}
112
113static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
114 unsigned int gpio, u32 value)
115{
116 u32 val;
117
118 val = 0x100 << GPIO_BIT(gpio);
119 if (value)
120 val |= 1 << GPIO_BIT(gpio);
121 tegra_gpio_writel(tgi, val, reg);
122}
123
124static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
125{
126 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
127}
128
129static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
130{
131 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
132}
133
134static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
135{
136 return pinctrl_gpio_request(chip->base + offset);
137}
138
139static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
140{
141 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
142
143 pinctrl_gpio_free(chip->base + offset);
144 tegra_gpio_disable(tgi, offset);
145}
146
147static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
148 int value)
149{
150 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
151
152 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
153}
154
155static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
156{
157 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
158 unsigned int bval = BIT(GPIO_BIT(offset));
159
160 /* If gpio is in output mode then read from the out value */
161 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
162 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
163
164 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
165}
166
167static int tegra_gpio_direction_input(struct gpio_chip *chip,
168 unsigned int offset)
169{
170 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
171 int ret;
172
173 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
174 tegra_gpio_enable(tgi, offset);
175
176 ret = pinctrl_gpio_direction_input(chip->base + offset);
177 if (ret < 0)
178 dev_err(tgi->dev,
179 "Failed to set pinctrl input direction of GPIO %d: %d",
180 chip->base + offset, ret);
181
182 return ret;
183}
184
185static int tegra_gpio_direction_output(struct gpio_chip *chip,
186 unsigned int offset,
187 int value)
188{
189 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
190 int ret;
191
192 tegra_gpio_set(chip, offset, value);
193 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
194 tegra_gpio_enable(tgi, offset);
195
196 ret = pinctrl_gpio_direction_output(chip->base + offset);
197 if (ret < 0)
198 dev_err(tgi->dev,
199 "Failed to set pinctrl output direction of GPIO %d: %d",
200 chip->base + offset, ret);
201
202 return ret;
203}
204
205static int tegra_gpio_get_direction(struct gpio_chip *chip,
206 unsigned int offset)
207{
208 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
209 u32 pin_mask = BIT(GPIO_BIT(offset));
210 u32 cnf, oe;
211
212 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
213 if (!(cnf & pin_mask))
214 return -EINVAL;
215
216 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
217
218 if (oe & pin_mask)
219 return GPIO_LINE_DIRECTION_OUT;
220
221 return GPIO_LINE_DIRECTION_IN;
222}
223
224static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
225 unsigned int debounce)
226{
227 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
228 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
229 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
230 unsigned long flags;
231 unsigned int port;
232
233 if (!debounce_ms) {
234 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
235 offset, 0);
236 return 0;
237 }
238
239 debounce_ms = min(debounce_ms, 255U);
240 port = GPIO_PORT(offset);
241
242 /* There is only one debounce count register per port and hence
243 * set the maximum of current and requested debounce time.
244 */
245 spin_lock_irqsave(&bank->dbc_lock[port], flags);
246 if (bank->dbc_cnt[port] < debounce_ms) {
247 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
248 bank->dbc_cnt[port] = debounce_ms;
249 }
250 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
251
252 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
253
254 return 0;
255}
256
257static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
258 unsigned long config)
259{
260 u32 debounce;
261
262 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
263 return -ENOTSUPP;
264
265 debounce = pinconf_to_config_argument(config);
266 return tegra_gpio_set_debounce(chip, offset, debounce);
267}
268
269static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
270{
271 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
272
273 return irq_find_mapping(tgi->irq_domain, offset);
274}
275
276static void tegra_gpio_irq_ack(struct irq_data *d)
277{
278 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
279 struct tegra_gpio_info *tgi = bank->tgi;
280 unsigned int gpio = d->hwirq;
281
282 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
283}
284
285static void tegra_gpio_irq_mask(struct irq_data *d)
286{
287 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
288 struct tegra_gpio_info *tgi = bank->tgi;
289 unsigned int gpio = d->hwirq;
290
291 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
292}
293
294static void tegra_gpio_irq_unmask(struct irq_data *d)
295{
296 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
297 struct tegra_gpio_info *tgi = bank->tgi;
298 unsigned int gpio = d->hwirq;
299
300 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
301}
302
303static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
304{
305 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
306 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
307 struct tegra_gpio_info *tgi = bank->tgi;
308 unsigned long flags;
309 u32 val;
310 int ret;
311
312 switch (type & IRQ_TYPE_SENSE_MASK) {
313 case IRQ_TYPE_EDGE_RISING:
314 lvl_type = GPIO_INT_LVL_EDGE_RISING;
315 break;
316
317 case IRQ_TYPE_EDGE_FALLING:
318 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
319 break;
320
321 case IRQ_TYPE_EDGE_BOTH:
322 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
323 break;
324
325 case IRQ_TYPE_LEVEL_HIGH:
326 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
327 break;
328
329 case IRQ_TYPE_LEVEL_LOW:
330 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
331 break;
332
333 default:
334 return -EINVAL;
335 }
336
337 spin_lock_irqsave(&bank->lvl_lock[port], flags);
338
339 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
340 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
341 val |= lvl_type << GPIO_BIT(gpio);
342 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
343
344 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
345
346 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
347 tegra_gpio_enable(tgi, gpio);
348
349 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
350 if (ret) {
351 dev_err(tgi->dev,
352 "unable to lock Tegra GPIO %u as IRQ\n", gpio);
353 tegra_gpio_disable(tgi, gpio);
354 return ret;
355 }
356
357 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
358 irq_set_handler_locked(d, handle_level_irq);
359 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
360 irq_set_handler_locked(d, handle_edge_irq);
361
362 return 0;
363}
364
365static void tegra_gpio_irq_shutdown(struct irq_data *d)
366{
367 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
368 struct tegra_gpio_info *tgi = bank->tgi;
369 unsigned int gpio = d->hwirq;
370
371 tegra_gpio_irq_mask(d);
372 gpiochip_unlock_as_irq(&tgi->gc, gpio);
373}
374
375static void tegra_gpio_irq_handler(struct irq_desc *desc)
376{
377 unsigned int port, pin, gpio;
378 bool unmasked = false;
379 u32 lvl;
380 unsigned long sta;
381 struct irq_chip *chip = irq_desc_get_chip(desc);
382 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
383 struct tegra_gpio_info *tgi = bank->tgi;
384
385 chained_irq_enter(chip, desc);
386
387 for (port = 0; port < 4; port++) {
388 gpio = tegra_gpio_compose(bank->bank, port, 0);
389 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
390 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
391 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
392
393 for_each_set_bit(pin, &sta, 8) {
394 tegra_gpio_writel(tgi, 1 << pin,
395 GPIO_INT_CLR(tgi, gpio));
396
397 /* if gpio is edge triggered, clear condition
398 * before executing the handler so that we don't
399 * miss edges
400 */
401 if (!unmasked && lvl & (0x100 << pin)) {
402 unmasked = true;
403 chained_irq_exit(chip, desc);
404 }
405
406 generic_handle_irq(irq_find_mapping(tgi->irq_domain,
407 gpio + pin));
408 }
409 }
410
411 if (!unmasked)
412 chained_irq_exit(chip, desc);
413
414}
415
416#ifdef CONFIG_PM_SLEEP
417static int tegra_gpio_resume(struct device *dev)
418{
419 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
420 unsigned int b, p;
421
422 for (b = 0; b < tgi->bank_count; b++) {
423 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
424
425 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
426 unsigned int gpio = (b << 5) | (p << 3);
427
428 tegra_gpio_writel(tgi, bank->cnf[p],
429 GPIO_CNF(tgi, gpio));
430
431 if (tgi->soc->debounce_supported) {
432 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
433 GPIO_DBC_CNT(tgi, gpio));
434 tegra_gpio_writel(tgi, bank->dbc_enb[p],
435 GPIO_MSK_DBC_EN(tgi, gpio));
436 }
437
438 tegra_gpio_writel(tgi, bank->out[p],
439 GPIO_OUT(tgi, gpio));
440 tegra_gpio_writel(tgi, bank->oe[p],
441 GPIO_OE(tgi, gpio));
442 tegra_gpio_writel(tgi, bank->int_lvl[p],
443 GPIO_INT_LVL(tgi, gpio));
444 tegra_gpio_writel(tgi, bank->int_enb[p],
445 GPIO_INT_ENB(tgi, gpio));
446 }
447 }
448
449 return 0;
450}
451
452static int tegra_gpio_suspend(struct device *dev)
453{
454 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
455 unsigned int b, p;
456
457 for (b = 0; b < tgi->bank_count; b++) {
458 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
459
460 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
461 unsigned int gpio = (b << 5) | (p << 3);
462
463 bank->cnf[p] = tegra_gpio_readl(tgi,
464 GPIO_CNF(tgi, gpio));
465 bank->out[p] = tegra_gpio_readl(tgi,
466 GPIO_OUT(tgi, gpio));
467 bank->oe[p] = tegra_gpio_readl(tgi,
468 GPIO_OE(tgi, gpio));
469 if (tgi->soc->debounce_supported) {
470 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
471 GPIO_MSK_DBC_EN(tgi, gpio));
472 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
473 bank->dbc_enb[p];
474 }
475
476 bank->int_enb[p] = tegra_gpio_readl(tgi,
477 GPIO_INT_ENB(tgi, gpio));
478 bank->int_lvl[p] = tegra_gpio_readl(tgi,
479 GPIO_INT_LVL(tgi, gpio));
480
481 /* Enable gpio irq for wake up source */
482 tegra_gpio_writel(tgi, bank->wake_enb[p],
483 GPIO_INT_ENB(tgi, gpio));
484 }
485 }
486
487 return 0;
488}
489
490static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
491{
492 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
493 unsigned int gpio = d->hwirq;
494 u32 port, bit, mask;
495 int err;
496
497 err = irq_set_irq_wake(bank->irq, enable);
498 if (err)
499 return err;
500
501 port = GPIO_PORT(gpio);
502 bit = GPIO_BIT(gpio);
503 mask = BIT(bit);
504
505 if (enable)
506 bank->wake_enb[port] |= mask;
507 else
508 bank->wake_enb[port] &= ~mask;
509
510 return 0;
511}
512#endif
513
514#ifdef CONFIG_DEBUG_FS
515
516#include <linux/debugfs.h>
517#include <linux/seq_file.h>
518
519static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
520{
521 struct tegra_gpio_info *tgi = s->private;
522 unsigned int i, j;
523
524 for (i = 0; i < tgi->bank_count; i++) {
525 for (j = 0; j < 4; j++) {
526 unsigned int gpio = tegra_gpio_compose(i, j, 0);
527
528 seq_printf(s,
529 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
530 i, j,
531 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
532 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
533 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
534 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
535 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
536 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
537 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
538 }
539 }
540 return 0;
541}
542
543DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio);
544
545static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
546{
547 debugfs_create_file("tegra_gpio", 0444, NULL, tgi,
548 &tegra_dbg_gpio_fops);
549}
550
551#else
552
553static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
554{
555}
556
557#endif
558
559static const struct dev_pm_ops tegra_gpio_pm_ops = {
560 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
561};
562
563static int tegra_gpio_probe(struct platform_device *pdev)
564{
565 struct tegra_gpio_info *tgi;
566 struct tegra_gpio_bank *bank;
567 unsigned int gpio, i, j;
568 int ret;
569
570 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
571 if (!tgi)
572 return -ENODEV;
573
574 tgi->soc = of_device_get_match_data(&pdev->dev);
575 tgi->dev = &pdev->dev;
576
577 ret = platform_irq_count(pdev);
578 if (ret < 0)
579 return ret;
580
581 tgi->bank_count = ret;
582
583 if (!tgi->bank_count) {
584 dev_err(&pdev->dev, "Missing IRQ resource\n");
585 return -ENODEV;
586 }
587
588 tgi->gc.label = "tegra-gpio";
589 tgi->gc.request = tegra_gpio_request;
590 tgi->gc.free = tegra_gpio_free;
591 tgi->gc.direction_input = tegra_gpio_direction_input;
592 tgi->gc.get = tegra_gpio_get;
593 tgi->gc.direction_output = tegra_gpio_direction_output;
594 tgi->gc.set = tegra_gpio_set;
595 tgi->gc.get_direction = tegra_gpio_get_direction;
596 tgi->gc.to_irq = tegra_gpio_to_irq;
597 tgi->gc.base = 0;
598 tgi->gc.ngpio = tgi->bank_count * 32;
599 tgi->gc.parent = &pdev->dev;
600 tgi->gc.of_node = pdev->dev.of_node;
601
602 tgi->ic.name = "GPIO";
603 tgi->ic.irq_ack = tegra_gpio_irq_ack;
604 tgi->ic.irq_mask = tegra_gpio_irq_mask;
605 tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
606 tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
607 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
608#ifdef CONFIG_PM_SLEEP
609 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
610#endif
611
612 platform_set_drvdata(pdev, tgi);
613
614 if (tgi->soc->debounce_supported)
615 tgi->gc.set_config = tegra_gpio_set_config;
616
617 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
618 sizeof(*tgi->bank_info), GFP_KERNEL);
619 if (!tgi->bank_info)
620 return -ENOMEM;
621
622 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
623 tgi->gc.ngpio,
624 &irq_domain_simple_ops, NULL);
625 if (!tgi->irq_domain)
626 return -ENODEV;
627
628 for (i = 0; i < tgi->bank_count; i++) {
629 ret = platform_get_irq(pdev, i);
630 if (ret < 0)
631 return ret;
632
633 bank = &tgi->bank_info[i];
634 bank->bank = i;
635 bank->irq = ret;
636 bank->tgi = tgi;
637 }
638
639 tgi->regs = devm_platform_ioremap_resource(pdev, 0);
640 if (IS_ERR(tgi->regs))
641 return PTR_ERR(tgi->regs);
642
643 for (i = 0; i < tgi->bank_count; i++) {
644 for (j = 0; j < 4; j++) {
645 int gpio = tegra_gpio_compose(i, j, 0);
646
647 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
648 }
649 }
650
651 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
652 if (ret < 0) {
653 irq_domain_remove(tgi->irq_domain);
654 return ret;
655 }
656
657 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
658 int irq = irq_create_mapping(tgi->irq_domain, gpio);
659 /* No validity check; all Tegra GPIOs are valid IRQs */
660
661 bank = &tgi->bank_info[GPIO_BANK(gpio)];
662
663 irq_set_chip_data(irq, bank);
664 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
665 }
666
667 for (i = 0; i < tgi->bank_count; i++) {
668 bank = &tgi->bank_info[i];
669
670 irq_set_chained_handler_and_data(bank->irq,
671 tegra_gpio_irq_handler, bank);
672
673 for (j = 0; j < 4; j++) {
674 spin_lock_init(&bank->lvl_lock[j]);
675 spin_lock_init(&bank->dbc_lock[j]);
676 }
677 }
678
679 tegra_gpio_debuginit(tgi);
680
681 return 0;
682}
683
684static const struct tegra_gpio_soc_config tegra20_gpio_config = {
685 .bank_stride = 0x80,
686 .upper_offset = 0x800,
687};
688
689static const struct tegra_gpio_soc_config tegra30_gpio_config = {
690 .bank_stride = 0x100,
691 .upper_offset = 0x80,
692};
693
694static const struct tegra_gpio_soc_config tegra210_gpio_config = {
695 .debounce_supported = true,
696 .bank_stride = 0x100,
697 .upper_offset = 0x80,
698};
699
700static const struct of_device_id tegra_gpio_of_match[] = {
701 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
702 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
703 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
704 { },
705};
706
707static struct platform_driver tegra_gpio_driver = {
708 .driver = {
709 .name = "tegra-gpio",
710 .pm = &tegra_gpio_pm_ops,
711 .of_match_table = tegra_gpio_of_match,
712 },
713 .probe = tegra_gpio_probe,
714};
715
716static int __init tegra_gpio_init(void)
717{
718 return platform_driver_register(&tegra_gpio_driver);
719}
720subsys_initcall(tegra_gpio_init);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * arch/arm/mach-tegra/gpio.c
4 *
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author:
9 * Erik Gilling <konkers@google.com>
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/irq.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/gpio/driver.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/module.h>
21#include <linux/seq_file.h>
22#include <linux/irqdomain.h>
23#include <linux/irqchip/chained_irq.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/pm.h>
26
27#define GPIO_BANK(x) ((x) >> 5)
28#define GPIO_PORT(x) (((x) >> 3) & 0x3)
29#define GPIO_BIT(x) ((x) & 0x7)
30
31#define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
32 GPIO_PORT(x) * 4)
33
34#define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
35#define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
36#define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
37#define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
38#define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
39#define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
40#define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
41#define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
42#define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
43
44
45#define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
46#define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
47#define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
48#define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
49#define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
50#define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
51#define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
52
53#define GPIO_INT_LVL_MASK 0x010101
54#define GPIO_INT_LVL_EDGE_RISING 0x000101
55#define GPIO_INT_LVL_EDGE_FALLING 0x000100
56#define GPIO_INT_LVL_EDGE_BOTH 0x010100
57#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
58#define GPIO_INT_LVL_LEVEL_LOW 0x000000
59
60struct tegra_gpio_info;
61
62struct tegra_gpio_bank {
63 unsigned int bank;
64
65 /*
66 * IRQ-core code uses raw locking, and thus, nested locking also
67 * should be raw in order not to trip spinlock debug warnings.
68 */
69 raw_spinlock_t lvl_lock[4];
70
71 /* Lock for updating debounce count register */
72 spinlock_t dbc_lock[4];
73
74#ifdef CONFIG_PM_SLEEP
75 u32 cnf[4];
76 u32 out[4];
77 u32 oe[4];
78 u32 int_enb[4];
79 u32 int_lvl[4];
80 u32 wake_enb[4];
81 u32 dbc_enb[4];
82#endif
83 u32 dbc_cnt[4];
84};
85
86struct tegra_gpio_soc_config {
87 bool debounce_supported;
88 u32 bank_stride;
89 u32 upper_offset;
90};
91
92struct tegra_gpio_info {
93 struct device *dev;
94 void __iomem *regs;
95 struct tegra_gpio_bank *bank_info;
96 const struct tegra_gpio_soc_config *soc;
97 struct gpio_chip gc;
98 u32 bank_count;
99 unsigned int *irqs;
100};
101
102static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
103 u32 val, u32 reg)
104{
105 writel_relaxed(val, tgi->regs + reg);
106}
107
108static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
109{
110 return readl_relaxed(tgi->regs + reg);
111}
112
113static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
114 unsigned int bit)
115{
116 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
117}
118
119static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
120 unsigned int gpio, u32 value)
121{
122 u32 val;
123
124 val = 0x100 << GPIO_BIT(gpio);
125 if (value)
126 val |= 1 << GPIO_BIT(gpio);
127 tegra_gpio_writel(tgi, val, reg);
128}
129
130static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
131{
132 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
133}
134
135static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
136{
137 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
138}
139
140static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
141{
142 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
143
144 pinctrl_gpio_free(chip, offset);
145 tegra_gpio_disable(tgi, offset);
146}
147
148static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
149 int value)
150{
151 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
152
153 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
154}
155
156static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
157{
158 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
159 unsigned int bval = BIT(GPIO_BIT(offset));
160
161 /* If gpio is in output mode then read from the out value */
162 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
163 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
164
165 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
166}
167
168static int tegra_gpio_direction_input(struct gpio_chip *chip,
169 unsigned int offset)
170{
171 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
172 int ret;
173
174 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
175 tegra_gpio_enable(tgi, offset);
176
177 ret = pinctrl_gpio_direction_input(chip, offset);
178 if (ret < 0)
179 dev_err(tgi->dev,
180 "Failed to set pinctrl input direction of GPIO %d: %d",
181 chip->base + offset, ret);
182
183 return ret;
184}
185
186static int tegra_gpio_direction_output(struct gpio_chip *chip,
187 unsigned int offset,
188 int value)
189{
190 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
191 int ret;
192
193 tegra_gpio_set(chip, offset, value);
194 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
195 tegra_gpio_enable(tgi, offset);
196
197 ret = pinctrl_gpio_direction_output(chip, offset);
198 if (ret < 0)
199 dev_err(tgi->dev,
200 "Failed to set pinctrl output direction of GPIO %d: %d",
201 chip->base + offset, ret);
202
203 return ret;
204}
205
206static int tegra_gpio_get_direction(struct gpio_chip *chip,
207 unsigned int offset)
208{
209 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
210 u32 pin_mask = BIT(GPIO_BIT(offset));
211 u32 cnf, oe;
212
213 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
214 if (!(cnf & pin_mask))
215 return -EINVAL;
216
217 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
218
219 if (oe & pin_mask)
220 return GPIO_LINE_DIRECTION_OUT;
221
222 return GPIO_LINE_DIRECTION_IN;
223}
224
225static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
226 unsigned int debounce)
227{
228 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
229 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
230 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
231 unsigned long flags;
232 unsigned int port;
233
234 if (!debounce_ms) {
235 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
236 offset, 0);
237 return 0;
238 }
239
240 debounce_ms = min(debounce_ms, 255U);
241 port = GPIO_PORT(offset);
242
243 /* There is only one debounce count register per port and hence
244 * set the maximum of current and requested debounce time.
245 */
246 spin_lock_irqsave(&bank->dbc_lock[port], flags);
247 if (bank->dbc_cnt[port] < debounce_ms) {
248 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
249 bank->dbc_cnt[port] = debounce_ms;
250 }
251 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
252
253 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
254
255 return 0;
256}
257
258static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
259 unsigned long config)
260{
261 u32 debounce;
262
263 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
264 return -ENOTSUPP;
265
266 debounce = pinconf_to_config_argument(config);
267 return tegra_gpio_set_debounce(chip, offset, debounce);
268}
269
270static void tegra_gpio_irq_ack(struct irq_data *d)
271{
272 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
273 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
274 unsigned int gpio = d->hwirq;
275
276 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
277}
278
279static void tegra_gpio_irq_mask(struct irq_data *d)
280{
281 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
282 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
283 unsigned int gpio = d->hwirq;
284
285 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
286 gpiochip_disable_irq(chip, gpio);
287}
288
289static void tegra_gpio_irq_unmask(struct irq_data *d)
290{
291 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
292 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
293 unsigned int gpio = d->hwirq;
294
295 gpiochip_enable_irq(chip, gpio);
296 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
297}
298
299static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
300{
301 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
302 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
303 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
304 struct tegra_gpio_bank *bank;
305 unsigned long flags;
306 int ret;
307 u32 val;
308
309 bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
310
311 switch (type & IRQ_TYPE_SENSE_MASK) {
312 case IRQ_TYPE_EDGE_RISING:
313 lvl_type = GPIO_INT_LVL_EDGE_RISING;
314 break;
315
316 case IRQ_TYPE_EDGE_FALLING:
317 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
318 break;
319
320 case IRQ_TYPE_EDGE_BOTH:
321 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
322 break;
323
324 case IRQ_TYPE_LEVEL_HIGH:
325 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
326 break;
327
328 case IRQ_TYPE_LEVEL_LOW:
329 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
330 break;
331
332 default:
333 return -EINVAL;
334 }
335
336 raw_spin_lock_irqsave(&bank->lvl_lock[port], flags);
337
338 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
339 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
340 val |= lvl_type << GPIO_BIT(gpio);
341 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
342
343 raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
344
345 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
346 tegra_gpio_enable(tgi, gpio);
347
348 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
349 if (ret) {
350 dev_err(tgi->dev,
351 "unable to lock Tegra GPIO %u as IRQ\n", gpio);
352 tegra_gpio_disable(tgi, gpio);
353 return ret;
354 }
355
356 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
357 irq_set_handler_locked(d, handle_level_irq);
358 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
359 irq_set_handler_locked(d, handle_edge_irq);
360
361 if (d->parent_data)
362 ret = irq_chip_set_type_parent(d, type);
363
364 return ret;
365}
366
367static void tegra_gpio_irq_shutdown(struct irq_data *d)
368{
369 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
370 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
371 unsigned int gpio = d->hwirq;
372
373 tegra_gpio_irq_mask(d);
374 gpiochip_unlock_as_irq(&tgi->gc, gpio);
375}
376
377static void tegra_gpio_irq_handler(struct irq_desc *desc)
378{
379 struct tegra_gpio_info *tgi = irq_desc_get_handler_data(desc);
380 struct irq_chip *chip = irq_desc_get_chip(desc);
381 struct irq_domain *domain = tgi->gc.irq.domain;
382 unsigned int irq = irq_desc_get_irq(desc);
383 struct tegra_gpio_bank *bank = NULL;
384 unsigned int port, pin, gpio, i;
385 bool unmasked = false;
386 unsigned long sta;
387 u32 lvl;
388
389 for (i = 0; i < tgi->bank_count; i++) {
390 if (tgi->irqs[i] == irq) {
391 bank = &tgi->bank_info[i];
392 break;
393 }
394 }
395
396 if (WARN_ON(bank == NULL))
397 return;
398
399 chained_irq_enter(chip, desc);
400
401 for (port = 0; port < 4; port++) {
402 gpio = tegra_gpio_compose(bank->bank, port, 0);
403 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
404 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
405 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
406
407 for_each_set_bit(pin, &sta, 8) {
408 int ret;
409
410 tegra_gpio_writel(tgi, 1 << pin,
411 GPIO_INT_CLR(tgi, gpio));
412
413 /* if gpio is edge triggered, clear condition
414 * before executing the handler so that we don't
415 * miss edges
416 */
417 if (!unmasked && lvl & (0x100 << pin)) {
418 unmasked = true;
419 chained_irq_exit(chip, desc);
420 }
421
422 ret = generic_handle_domain_irq(domain, gpio + pin);
423 WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin);
424 }
425 }
426
427 if (!unmasked)
428 chained_irq_exit(chip, desc);
429}
430
431static int tegra_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
432 unsigned int hwirq,
433 unsigned int type,
434 unsigned int *parent_hwirq,
435 unsigned int *parent_type)
436{
437 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
438 *parent_type = type;
439
440 return 0;
441}
442
443static int tegra_gpio_populate_parent_fwspec(struct gpio_chip *chip,
444 union gpio_irq_fwspec *gfwspec,
445 unsigned int parent_hwirq,
446 unsigned int parent_type)
447{
448 struct irq_fwspec *fwspec = &gfwspec->fwspec;
449
450 fwspec->fwnode = chip->irq.parent_domain->fwnode;
451 fwspec->param_count = 3;
452 fwspec->param[0] = 0;
453 fwspec->param[1] = parent_hwirq;
454 fwspec->param[2] = parent_type;
455
456 return 0;
457}
458
459#ifdef CONFIG_PM_SLEEP
460static int tegra_gpio_resume(struct device *dev)
461{
462 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
463 unsigned int b, p;
464
465 for (b = 0; b < tgi->bank_count; b++) {
466 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
467
468 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
469 unsigned int gpio = (b << 5) | (p << 3);
470
471 tegra_gpio_writel(tgi, bank->cnf[p],
472 GPIO_CNF(tgi, gpio));
473
474 if (tgi->soc->debounce_supported) {
475 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
476 GPIO_DBC_CNT(tgi, gpio));
477 tegra_gpio_writel(tgi, bank->dbc_enb[p],
478 GPIO_MSK_DBC_EN(tgi, gpio));
479 }
480
481 tegra_gpio_writel(tgi, bank->out[p],
482 GPIO_OUT(tgi, gpio));
483 tegra_gpio_writel(tgi, bank->oe[p],
484 GPIO_OE(tgi, gpio));
485 tegra_gpio_writel(tgi, bank->int_lvl[p],
486 GPIO_INT_LVL(tgi, gpio));
487 tegra_gpio_writel(tgi, bank->int_enb[p],
488 GPIO_INT_ENB(tgi, gpio));
489 }
490 }
491
492 return 0;
493}
494
495static int tegra_gpio_suspend(struct device *dev)
496{
497 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
498 unsigned int b, p;
499
500 for (b = 0; b < tgi->bank_count; b++) {
501 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
502
503 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
504 unsigned int gpio = (b << 5) | (p << 3);
505
506 bank->cnf[p] = tegra_gpio_readl(tgi,
507 GPIO_CNF(tgi, gpio));
508 bank->out[p] = tegra_gpio_readl(tgi,
509 GPIO_OUT(tgi, gpio));
510 bank->oe[p] = tegra_gpio_readl(tgi,
511 GPIO_OE(tgi, gpio));
512 if (tgi->soc->debounce_supported) {
513 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
514 GPIO_MSK_DBC_EN(tgi, gpio));
515 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
516 bank->dbc_enb[p];
517 }
518
519 bank->int_enb[p] = tegra_gpio_readl(tgi,
520 GPIO_INT_ENB(tgi, gpio));
521 bank->int_lvl[p] = tegra_gpio_readl(tgi,
522 GPIO_INT_LVL(tgi, gpio));
523
524 /* Enable gpio irq for wake up source */
525 tegra_gpio_writel(tgi, bank->wake_enb[p],
526 GPIO_INT_ENB(tgi, gpio));
527 }
528 }
529
530 return 0;
531}
532
533static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
534{
535 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
536 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
537 struct tegra_gpio_bank *bank;
538 unsigned int gpio = d->hwirq;
539 u32 port, bit, mask;
540 int err;
541
542 bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
543
544 port = GPIO_PORT(gpio);
545 bit = GPIO_BIT(gpio);
546 mask = BIT(bit);
547
548 err = irq_set_irq_wake(tgi->irqs[bank->bank], enable);
549 if (err)
550 return err;
551
552 if (d->parent_data) {
553 err = irq_chip_set_wake_parent(d, enable);
554 if (err) {
555 irq_set_irq_wake(tgi->irqs[bank->bank], !enable);
556 return err;
557 }
558 }
559
560 if (enable)
561 bank->wake_enb[port] |= mask;
562 else
563 bank->wake_enb[port] &= ~mask;
564
565 return 0;
566}
567#endif
568
569static int tegra_gpio_irq_set_affinity(struct irq_data *data,
570 const struct cpumask *dest,
571 bool force)
572{
573 if (data->parent_data)
574 return irq_chip_set_affinity_parent(data, dest, force);
575
576 return -EINVAL;
577}
578
579static int tegra_gpio_irq_request_resources(struct irq_data *d)
580{
581 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
582 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
583
584 tegra_gpio_enable(tgi, d->hwirq);
585
586 return gpiochip_reqres_irq(chip, d->hwirq);
587}
588
589static void tegra_gpio_irq_release_resources(struct irq_data *d)
590{
591 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
592 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
593
594 gpiochip_relres_irq(chip, d->hwirq);
595 tegra_gpio_enable(tgi, d->hwirq);
596}
597
598static void tegra_gpio_irq_print_chip(struct irq_data *d, struct seq_file *s)
599{
600 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
601
602 seq_printf(s, dev_name(chip->parent));
603}
604
605static const struct irq_chip tegra_gpio_irq_chip = {
606 .irq_shutdown = tegra_gpio_irq_shutdown,
607 .irq_ack = tegra_gpio_irq_ack,
608 .irq_mask = tegra_gpio_irq_mask,
609 .irq_unmask = tegra_gpio_irq_unmask,
610 .irq_set_type = tegra_gpio_irq_set_type,
611#ifdef CONFIG_PM_SLEEP
612 .irq_set_wake = tegra_gpio_irq_set_wake,
613#endif
614 .irq_print_chip = tegra_gpio_irq_print_chip,
615 .irq_request_resources = tegra_gpio_irq_request_resources,
616 .irq_release_resources = tegra_gpio_irq_release_resources,
617 .flags = IRQCHIP_IMMUTABLE,
618};
619
620static const struct irq_chip tegra210_gpio_irq_chip = {
621 .irq_shutdown = tegra_gpio_irq_shutdown,
622 .irq_ack = tegra_gpio_irq_ack,
623 .irq_mask = tegra_gpio_irq_mask,
624 .irq_unmask = tegra_gpio_irq_unmask,
625 .irq_set_affinity = tegra_gpio_irq_set_affinity,
626 .irq_set_type = tegra_gpio_irq_set_type,
627#ifdef CONFIG_PM_SLEEP
628 .irq_set_wake = tegra_gpio_irq_set_wake,
629#endif
630 .irq_print_chip = tegra_gpio_irq_print_chip,
631 .irq_request_resources = tegra_gpio_irq_request_resources,
632 .irq_release_resources = tegra_gpio_irq_release_resources,
633 .flags = IRQCHIP_IMMUTABLE,
634};
635
636#ifdef CONFIG_DEBUG_FS
637
638#include <linux/debugfs.h>
639
640static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
641{
642 struct tegra_gpio_info *tgi = dev_get_drvdata(s->private);
643 unsigned int i, j;
644
645 for (i = 0; i < tgi->bank_count; i++) {
646 for (j = 0; j < 4; j++) {
647 unsigned int gpio = tegra_gpio_compose(i, j, 0);
648
649 seq_printf(s,
650 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
651 i, j,
652 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
653 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
654 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
655 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
656 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
657 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
658 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
659 }
660 }
661 return 0;
662}
663
664static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
665{
666 debugfs_create_devm_seqfile(tgi->dev, "tegra_gpio", NULL,
667 tegra_dbg_gpio_show);
668}
669
670#else
671
672static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
673{
674}
675
676#endif
677
678static const struct dev_pm_ops tegra_gpio_pm_ops = {
679 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
680};
681
682static const struct of_device_id tegra_pmc_of_match[] = {
683 { .compatible = "nvidia,tegra210-pmc", },
684 { /* sentinel */ },
685};
686
687static int tegra_gpio_probe(struct platform_device *pdev)
688{
689 struct tegra_gpio_bank *bank;
690 struct tegra_gpio_info *tgi;
691 struct gpio_irq_chip *irq;
692 struct device_node *np;
693 unsigned int i, j;
694 int ret;
695
696 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
697 if (!tgi)
698 return -ENODEV;
699
700 tgi->soc = of_device_get_match_data(&pdev->dev);
701 tgi->dev = &pdev->dev;
702
703 ret = platform_irq_count(pdev);
704 if (ret < 0)
705 return ret;
706
707 tgi->bank_count = ret;
708
709 if (!tgi->bank_count) {
710 dev_err(&pdev->dev, "Missing IRQ resource\n");
711 return -ENODEV;
712 }
713
714 tgi->gc.label = "tegra-gpio";
715 tgi->gc.request = pinctrl_gpio_request;
716 tgi->gc.free = tegra_gpio_free;
717 tgi->gc.direction_input = tegra_gpio_direction_input;
718 tgi->gc.get = tegra_gpio_get;
719 tgi->gc.direction_output = tegra_gpio_direction_output;
720 tgi->gc.set = tegra_gpio_set;
721 tgi->gc.get_direction = tegra_gpio_get_direction;
722 tgi->gc.base = 0;
723 tgi->gc.ngpio = tgi->bank_count * 32;
724 tgi->gc.parent = &pdev->dev;
725
726 platform_set_drvdata(pdev, tgi);
727
728 if (tgi->soc->debounce_supported)
729 tgi->gc.set_config = tegra_gpio_set_config;
730
731 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
732 sizeof(*tgi->bank_info), GFP_KERNEL);
733 if (!tgi->bank_info)
734 return -ENOMEM;
735
736 tgi->irqs = devm_kcalloc(&pdev->dev, tgi->bank_count,
737 sizeof(*tgi->irqs), GFP_KERNEL);
738 if (!tgi->irqs)
739 return -ENOMEM;
740
741 for (i = 0; i < tgi->bank_count; i++) {
742 ret = platform_get_irq(pdev, i);
743 if (ret < 0)
744 return ret;
745
746 bank = &tgi->bank_info[i];
747 bank->bank = i;
748
749 tgi->irqs[i] = ret;
750
751 for (j = 0; j < 4; j++) {
752 raw_spin_lock_init(&bank->lvl_lock[j]);
753 spin_lock_init(&bank->dbc_lock[j]);
754 }
755 }
756
757 irq = &tgi->gc.irq;
758 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
759 irq->child_to_parent_hwirq = tegra_gpio_child_to_parent_hwirq;
760 irq->populate_parent_alloc_arg = tegra_gpio_populate_parent_fwspec;
761 irq->handler = handle_simple_irq;
762 irq->default_type = IRQ_TYPE_NONE;
763 irq->parent_handler = tegra_gpio_irq_handler;
764 irq->parent_handler_data = tgi;
765 irq->num_parents = tgi->bank_count;
766 irq->parents = tgi->irqs;
767
768 np = of_find_matching_node(NULL, tegra_pmc_of_match);
769 if (np) {
770 irq->parent_domain = irq_find_host(np);
771 of_node_put(np);
772
773 if (!irq->parent_domain)
774 return -EPROBE_DEFER;
775
776 gpio_irq_chip_set_chip(irq, &tegra210_gpio_irq_chip);
777 } else {
778 gpio_irq_chip_set_chip(irq, &tegra_gpio_irq_chip);
779 }
780
781 tgi->regs = devm_platform_ioremap_resource(pdev, 0);
782 if (IS_ERR(tgi->regs))
783 return PTR_ERR(tgi->regs);
784
785 for (i = 0; i < tgi->bank_count; i++) {
786 for (j = 0; j < 4; j++) {
787 int gpio = tegra_gpio_compose(i, j, 0);
788
789 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
790 }
791 }
792
793 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
794 if (ret < 0)
795 return ret;
796
797 tegra_gpio_debuginit(tgi);
798
799 return 0;
800}
801
802static const struct tegra_gpio_soc_config tegra20_gpio_config = {
803 .bank_stride = 0x80,
804 .upper_offset = 0x800,
805};
806
807static const struct tegra_gpio_soc_config tegra30_gpio_config = {
808 .bank_stride = 0x100,
809 .upper_offset = 0x80,
810};
811
812static const struct tegra_gpio_soc_config tegra210_gpio_config = {
813 .debounce_supported = true,
814 .bank_stride = 0x100,
815 .upper_offset = 0x80,
816};
817
818static const struct of_device_id tegra_gpio_of_match[] = {
819 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
820 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
821 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
822 { },
823};
824MODULE_DEVICE_TABLE(of, tegra_gpio_of_match);
825
826static struct platform_driver tegra_gpio_driver = {
827 .driver = {
828 .name = "tegra-gpio",
829 .pm = &tegra_gpio_pm_ops,
830 .of_match_table = tegra_gpio_of_match,
831 },
832 .probe = tegra_gpio_probe,
833};
834module_platform_driver(tegra_gpio_driver);
835
836MODULE_DESCRIPTION("NVIDIA Tegra GPIO controller driver");
837MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
838MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
839MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
840MODULE_AUTHOR("Erik Gilling <konkers@google.com>");
841MODULE_LICENSE("GPL v2");