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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * TI DaVinci GPIO Support
4 *
5 * Copyright (c) 2006-2007 David Brownell
6 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7 */
8
9#include <linux/gpio/driver.h>
10#include <linux/errno.h>
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/platform_device.h>
22#include <linux/platform_data/gpio-davinci.h>
23#include <linux/irqchip/chained_irq.h>
24#include <linux/spinlock.h>
25
26#include <asm-generic/gpio.h>
27
28#define MAX_REGS_BANKS 5
29#define MAX_INT_PER_BANK 32
30
31struct davinci_gpio_regs {
32 u32 dir;
33 u32 out_data;
34 u32 set_data;
35 u32 clr_data;
36 u32 in_data;
37 u32 set_rising;
38 u32 clr_rising;
39 u32 set_falling;
40 u32 clr_falling;
41 u32 intstat;
42};
43
44typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
45
46#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
47
48static void __iomem *gpio_base;
49static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
50
51struct davinci_gpio_irq_data {
52 void __iomem *regs;
53 struct davinci_gpio_controller *chip;
54 int bank_num;
55};
56
57struct davinci_gpio_controller {
58 struct gpio_chip chip;
59 struct irq_domain *irq_domain;
60 /* Serialize access to GPIO registers */
61 spinlock_t lock;
62 void __iomem *regs[MAX_REGS_BANKS];
63 int gpio_unbanked;
64 int irqs[MAX_INT_PER_BANK];
65};
66
67static inline u32 __gpio_mask(unsigned gpio)
68{
69 return 1 << (gpio % 32);
70}
71
72static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
73{
74 struct davinci_gpio_regs __iomem *g;
75
76 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
77
78 return g;
79}
80
81static int davinci_gpio_irq_setup(struct platform_device *pdev);
82
83/*--------------------------------------------------------------------------*/
84
85/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
86static inline int __davinci_direction(struct gpio_chip *chip,
87 unsigned offset, bool out, int value)
88{
89 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
90 struct davinci_gpio_regs __iomem *g;
91 unsigned long flags;
92 u32 temp;
93 int bank = offset / 32;
94 u32 mask = __gpio_mask(offset);
95
96 g = d->regs[bank];
97 spin_lock_irqsave(&d->lock, flags);
98 temp = readl_relaxed(&g->dir);
99 if (out) {
100 temp &= ~mask;
101 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
102 } else {
103 temp |= mask;
104 }
105 writel_relaxed(temp, &g->dir);
106 spin_unlock_irqrestore(&d->lock, flags);
107
108 return 0;
109}
110
111static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
112{
113 return __davinci_direction(chip, offset, false, 0);
114}
115
116static int
117davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
118{
119 return __davinci_direction(chip, offset, true, value);
120}
121
122/*
123 * Read the pin's value (works even if it's set up as output);
124 * returns zero/nonzero.
125 *
126 * Note that changes are synched to the GPIO clock, so reading values back
127 * right after you've set them may give old values.
128 */
129static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
130{
131 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
132 struct davinci_gpio_regs __iomem *g;
133 int bank = offset / 32;
134
135 g = d->regs[bank];
136
137 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
138}
139
140/*
141 * Assuming the pin is muxed as a gpio output, set its output value.
142 */
143static void
144davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
145{
146 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
147 struct davinci_gpio_regs __iomem *g;
148 int bank = offset / 32;
149
150 g = d->regs[bank];
151
152 writel_relaxed(__gpio_mask(offset),
153 value ? &g->set_data : &g->clr_data);
154}
155
156static struct davinci_gpio_platform_data *
157davinci_gpio_get_pdata(struct platform_device *pdev)
158{
159 struct device_node *dn = pdev->dev.of_node;
160 struct davinci_gpio_platform_data *pdata;
161 int ret;
162 u32 val;
163
164 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
165 return dev_get_platdata(&pdev->dev);
166
167 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
168 if (!pdata)
169 return NULL;
170
171 ret = of_property_read_u32(dn, "ti,ngpio", &val);
172 if (ret)
173 goto of_err;
174
175 pdata->ngpio = val;
176
177 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
178 if (ret)
179 goto of_err;
180
181 pdata->gpio_unbanked = val;
182
183 return pdata;
184
185of_err:
186 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
187 return NULL;
188}
189
190static int davinci_gpio_probe(struct platform_device *pdev)
191{
192 int bank, i, ret = 0;
193 unsigned int ngpio, nbank, nirq;
194 struct davinci_gpio_controller *chips;
195 struct davinci_gpio_platform_data *pdata;
196 struct device *dev = &pdev->dev;
197
198 pdata = davinci_gpio_get_pdata(pdev);
199 if (!pdata) {
200 dev_err(dev, "No platform data found\n");
201 return -EINVAL;
202 }
203
204 dev->platform_data = pdata;
205
206 /*
207 * The gpio banks conceptually expose a segmented bitmap,
208 * and "ngpio" is one more than the largest zero-based
209 * bit index that's valid.
210 */
211 ngpio = pdata->ngpio;
212 if (ngpio == 0) {
213 dev_err(dev, "How many GPIOs?\n");
214 return -EINVAL;
215 }
216
217 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
218 ngpio = ARCH_NR_GPIOS;
219
220 /*
221 * If there are unbanked interrupts then the number of
222 * interrupts is equal to number of gpios else all are banked so
223 * number of interrupts is equal to number of banks(each with 16 gpios)
224 */
225 if (pdata->gpio_unbanked)
226 nirq = pdata->gpio_unbanked;
227 else
228 nirq = DIV_ROUND_UP(ngpio, 16);
229
230 chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
231 if (!chips)
232 return -ENOMEM;
233
234 gpio_base = devm_platform_ioremap_resource(pdev, 0);
235 if (IS_ERR(gpio_base))
236 return PTR_ERR(gpio_base);
237
238 for (i = 0; i < nirq; i++) {
239 chips->irqs[i] = platform_get_irq(pdev, i);
240 if (chips->irqs[i] < 0) {
241 if (chips->irqs[i] != -EPROBE_DEFER)
242 dev_info(dev, "IRQ not populated, err = %d\n",
243 chips->irqs[i]);
244 return chips->irqs[i];
245 }
246 }
247
248 chips->chip.label = dev_name(dev);
249
250 chips->chip.direction_input = davinci_direction_in;
251 chips->chip.get = davinci_gpio_get;
252 chips->chip.direction_output = davinci_direction_out;
253 chips->chip.set = davinci_gpio_set;
254
255 chips->chip.ngpio = ngpio;
256 chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
257
258#ifdef CONFIG_OF_GPIO
259 chips->chip.of_gpio_n_cells = 2;
260 chips->chip.parent = dev;
261 chips->chip.of_node = dev->of_node;
262 chips->chip.request = gpiochip_generic_request;
263 chips->chip.free = gpiochip_generic_free;
264#endif
265 spin_lock_init(&chips->lock);
266
267 nbank = DIV_ROUND_UP(ngpio, 32);
268 for (bank = 0; bank < nbank; bank++)
269 chips->regs[bank] = gpio_base + offset_array[bank];
270
271 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
272 if (ret)
273 return ret;
274
275 platform_set_drvdata(pdev, chips);
276 ret = davinci_gpio_irq_setup(pdev);
277 if (ret)
278 return ret;
279
280 return 0;
281}
282
283/*--------------------------------------------------------------------------*/
284/*
285 * We expect irqs will normally be set up as input pins, but they can also be
286 * used as output pins ... which is convenient for testing.
287 *
288 * NOTE: The first few GPIOs also have direct INTC hookups in addition
289 * to their GPIOBNK0 irq, with a bit less overhead.
290 *
291 * All those INTC hookups (direct, plus several IRQ banks) can also
292 * serve as EDMA event triggers.
293 */
294
295static void gpio_irq_disable(struct irq_data *d)
296{
297 struct davinci_gpio_regs __iomem *g = irq2regs(d);
298 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
299
300 writel_relaxed(mask, &g->clr_falling);
301 writel_relaxed(mask, &g->clr_rising);
302}
303
304static void gpio_irq_enable(struct irq_data *d)
305{
306 struct davinci_gpio_regs __iomem *g = irq2regs(d);
307 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
308 unsigned status = irqd_get_trigger_type(d);
309
310 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
311 if (!status)
312 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
313
314 if (status & IRQ_TYPE_EDGE_FALLING)
315 writel_relaxed(mask, &g->set_falling);
316 if (status & IRQ_TYPE_EDGE_RISING)
317 writel_relaxed(mask, &g->set_rising);
318}
319
320static int gpio_irq_type(struct irq_data *d, unsigned trigger)
321{
322 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
323 return -EINVAL;
324
325 return 0;
326}
327
328static struct irq_chip gpio_irqchip = {
329 .name = "GPIO",
330 .irq_enable = gpio_irq_enable,
331 .irq_disable = gpio_irq_disable,
332 .irq_set_type = gpio_irq_type,
333 .flags = IRQCHIP_SET_TYPE_MASKED,
334};
335
336static void gpio_irq_handler(struct irq_desc *desc)
337{
338 struct davinci_gpio_regs __iomem *g;
339 u32 mask = 0xffff;
340 int bank_num;
341 struct davinci_gpio_controller *d;
342 struct davinci_gpio_irq_data *irqdata;
343
344 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
345 bank_num = irqdata->bank_num;
346 g = irqdata->regs;
347 d = irqdata->chip;
348
349 /* we only care about one bank */
350 if ((bank_num % 2) == 1)
351 mask <<= 16;
352
353 /* temporarily mask (level sensitive) parent IRQ */
354 chained_irq_enter(irq_desc_get_chip(desc), desc);
355 while (1) {
356 u32 status;
357 int bit;
358 irq_hw_number_t hw_irq;
359
360 /* ack any irqs */
361 status = readl_relaxed(&g->intstat) & mask;
362 if (!status)
363 break;
364 writel_relaxed(status, &g->intstat);
365
366 /* now demux them to the right lowlevel handler */
367
368 while (status) {
369 bit = __ffs(status);
370 status &= ~BIT(bit);
371 /* Max number of gpios per controller is 144 so
372 * hw_irq will be in [0..143]
373 */
374 hw_irq = (bank_num / 2) * 32 + bit;
375
376 generic_handle_irq(
377 irq_find_mapping(d->irq_domain, hw_irq));
378 }
379 }
380 chained_irq_exit(irq_desc_get_chip(desc), desc);
381 /* now it may re-trigger */
382}
383
384static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
385{
386 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
387
388 if (d->irq_domain)
389 return irq_create_mapping(d->irq_domain, offset);
390 else
391 return -ENXIO;
392}
393
394static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
395{
396 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
397
398 /*
399 * NOTE: we assume for now that only irqs in the first gpio_chip
400 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
401 */
402 if (offset < d->gpio_unbanked)
403 return d->irqs[offset];
404 else
405 return -ENODEV;
406}
407
408static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
409{
410 struct davinci_gpio_controller *d;
411 struct davinci_gpio_regs __iomem *g;
412 u32 mask, i;
413
414 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
415 g = (struct davinci_gpio_regs __iomem *)d->regs[0];
416 for (i = 0; i < MAX_INT_PER_BANK; i++)
417 if (data->irq == d->irqs[i])
418 break;
419
420 if (i == MAX_INT_PER_BANK)
421 return -EINVAL;
422
423 mask = __gpio_mask(i);
424
425 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
426 return -EINVAL;
427
428 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
429 ? &g->set_falling : &g->clr_falling);
430 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
431 ? &g->set_rising : &g->clr_rising);
432
433 return 0;
434}
435
436static int
437davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
438 irq_hw_number_t hw)
439{
440 struct davinci_gpio_controller *chips =
441 (struct davinci_gpio_controller *)d->host_data;
442 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
443
444 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
445 "davinci_gpio");
446 irq_set_irq_type(irq, IRQ_TYPE_NONE);
447 irq_set_chip_data(irq, (__force void *)g);
448 irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
449
450 return 0;
451}
452
453static const struct irq_domain_ops davinci_gpio_irq_ops = {
454 .map = davinci_gpio_irq_map,
455 .xlate = irq_domain_xlate_onetwocell,
456};
457
458static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
459{
460 static struct irq_chip_type gpio_unbanked;
461
462 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
463
464 return &gpio_unbanked.chip;
465};
466
467static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
468{
469 static struct irq_chip gpio_unbanked;
470
471 gpio_unbanked = *irq_get_chip(irq);
472 return &gpio_unbanked;
473};
474
475static const struct of_device_id davinci_gpio_ids[];
476
477/*
478 * NOTE: for suspend/resume, probably best to make a platform_device with
479 * suspend_late/resume_resume calls hooking into results of the set_wake()
480 * calls ... so if no gpios are wakeup events the clock can be disabled,
481 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
482 * (dm6446) can be set appropriately for GPIOV33 pins.
483 */
484
485static int davinci_gpio_irq_setup(struct platform_device *pdev)
486{
487 unsigned gpio, bank;
488 int irq;
489 int ret;
490 struct clk *clk;
491 u32 binten = 0;
492 unsigned ngpio;
493 struct device *dev = &pdev->dev;
494 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
495 struct davinci_gpio_platform_data *pdata = dev->platform_data;
496 struct davinci_gpio_regs __iomem *g;
497 struct irq_domain *irq_domain = NULL;
498 const struct of_device_id *match;
499 struct irq_chip *irq_chip;
500 struct davinci_gpio_irq_data *irqdata;
501 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
502
503 /*
504 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
505 */
506 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
507 match = of_match_device(of_match_ptr(davinci_gpio_ids),
508 dev);
509 if (match)
510 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
511
512 ngpio = pdata->ngpio;
513
514 clk = devm_clk_get(dev, "gpio");
515 if (IS_ERR(clk)) {
516 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
517 return PTR_ERR(clk);
518 }
519
520 ret = clk_prepare_enable(clk);
521 if (ret)
522 return ret;
523
524 if (!pdata->gpio_unbanked) {
525 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
526 if (irq < 0) {
527 dev_err(dev, "Couldn't allocate IRQ numbers\n");
528 clk_disable_unprepare(clk);
529 return irq;
530 }
531
532 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
533 &davinci_gpio_irq_ops,
534 chips);
535 if (!irq_domain) {
536 dev_err(dev, "Couldn't register an IRQ domain\n");
537 clk_disable_unprepare(clk);
538 return -ENODEV;
539 }
540 }
541
542 /*
543 * Arrange gpio_to_irq() support, handling either direct IRQs or
544 * banked IRQs. Having GPIOs in the first GPIO bank use direct
545 * IRQs, while the others use banked IRQs, would need some setup
546 * tweaks to recognize hardware which can do that.
547 */
548 chips->chip.to_irq = gpio_to_irq_banked;
549 chips->irq_domain = irq_domain;
550
551 /*
552 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
553 * controller only handling trigger modes. We currently assume no
554 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
555 */
556 if (pdata->gpio_unbanked) {
557 /* pass "bank 0" GPIO IRQs to AINTC */
558 chips->chip.to_irq = gpio_to_irq_unbanked;
559 chips->gpio_unbanked = pdata->gpio_unbanked;
560 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
561
562 /* AINTC handles mask/unmask; GPIO handles triggering */
563 irq = chips->irqs[0];
564 irq_chip = gpio_get_irq_chip(irq);
565 irq_chip->name = "GPIO-AINTC";
566 irq_chip->irq_set_type = gpio_irq_type_unbanked;
567
568 /* default trigger: both edges */
569 g = chips->regs[0];
570 writel_relaxed(~0, &g->set_falling);
571 writel_relaxed(~0, &g->set_rising);
572
573 /* set the direct IRQs up to use that irqchip */
574 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
575 irq_set_chip(chips->irqs[gpio], irq_chip);
576 irq_set_handler_data(chips->irqs[gpio], chips);
577 irq_set_status_flags(chips->irqs[gpio],
578 IRQ_TYPE_EDGE_BOTH);
579 }
580
581 goto done;
582 }
583
584 /*
585 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
586 * then chain through our own handler.
587 */
588 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
589 /* disabled by default, enabled only as needed
590 * There are register sets for 32 GPIOs. 2 banks of 16
591 * GPIOs are covered by each set of registers hence divide by 2
592 */
593 g = chips->regs[bank / 2];
594 writel_relaxed(~0, &g->clr_falling);
595 writel_relaxed(~0, &g->clr_rising);
596
597 /*
598 * Each chip handles 32 gpios, and each irq bank consists of 16
599 * gpio irqs. Pass the irq bank's corresponding controller to
600 * the chained irq handler.
601 */
602 irqdata = devm_kzalloc(&pdev->dev,
603 sizeof(struct
604 davinci_gpio_irq_data),
605 GFP_KERNEL);
606 if (!irqdata) {
607 clk_disable_unprepare(clk);
608 return -ENOMEM;
609 }
610
611 irqdata->regs = g;
612 irqdata->bank_num = bank;
613 irqdata->chip = chips;
614
615 irq_set_chained_handler_and_data(chips->irqs[bank],
616 gpio_irq_handler, irqdata);
617
618 binten |= BIT(bank);
619 }
620
621done:
622 /*
623 * BINTEN -- per-bank interrupt enable. genirq would also let these
624 * bits be set/cleared dynamically.
625 */
626 writel_relaxed(binten, gpio_base + BINTEN);
627
628 return 0;
629}
630
631static const struct of_device_id davinci_gpio_ids[] = {
632 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
633 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
634 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
635 { /* sentinel */ },
636};
637MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
638
639static struct platform_driver davinci_gpio_driver = {
640 .probe = davinci_gpio_probe,
641 .driver = {
642 .name = "davinci_gpio",
643 .of_match_table = of_match_ptr(davinci_gpio_ids),
644 },
645};
646
647/**
648 * GPIO driver registration needs to be done before machine_init functions
649 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
650 */
651static int __init davinci_gpio_drv_reg(void)
652{
653 return platform_driver_register(&davinci_gpio_driver);
654}
655postcore_initcall(davinci_gpio_drv_reg);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * TI DaVinci GPIO Support
4 *
5 * Copyright (c) 2006-2007 David Brownell
6 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7 */
8
9#include <linux/gpio/driver.h>
10#include <linux/errno.h>
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/platform_device.h>
21#include <linux/platform_data/gpio-davinci.h>
22#include <linux/property.h>
23#include <linux/irqchip/chained_irq.h>
24#include <linux/spinlock.h>
25#include <linux/pm_runtime.h>
26
27#define MAX_REGS_BANKS 5
28#define MAX_INT_PER_BANK 32
29
30struct davinci_gpio_regs {
31 u32 dir;
32 u32 out_data;
33 u32 set_data;
34 u32 clr_data;
35 u32 in_data;
36 u32 set_rising;
37 u32 clr_rising;
38 u32 set_falling;
39 u32 clr_falling;
40 u32 intstat;
41};
42
43typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
44
45#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
46
47static void __iomem *gpio_base;
48static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
49
50struct davinci_gpio_irq_data {
51 void __iomem *regs;
52 struct davinci_gpio_controller *chip;
53 int bank_num;
54};
55
56struct davinci_gpio_controller {
57 struct gpio_chip chip;
58 struct irq_domain *irq_domain;
59 /* Serialize access to GPIO registers */
60 spinlock_t lock;
61 void __iomem *regs[MAX_REGS_BANKS];
62 int gpio_unbanked;
63 int irqs[MAX_INT_PER_BANK];
64 struct davinci_gpio_regs context[MAX_REGS_BANKS];
65 u32 binten_context;
66};
67
68static inline u32 __gpio_mask(unsigned gpio)
69{
70 return 1 << (gpio % 32);
71}
72
73static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
74{
75 struct davinci_gpio_regs __iomem *g;
76
77 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
78
79 return g;
80}
81
82static int davinci_gpio_irq_setup(struct platform_device *pdev);
83
84/*--------------------------------------------------------------------------*/
85
86/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
87static inline int __davinci_direction(struct gpio_chip *chip,
88 unsigned offset, bool out, int value)
89{
90 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
91 struct davinci_gpio_regs __iomem *g;
92 unsigned long flags;
93 u32 temp;
94 int bank = offset / 32;
95 u32 mask = __gpio_mask(offset);
96
97 g = d->regs[bank];
98 spin_lock_irqsave(&d->lock, flags);
99 temp = readl_relaxed(&g->dir);
100 if (out) {
101 temp &= ~mask;
102 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
103 } else {
104 temp |= mask;
105 }
106 writel_relaxed(temp, &g->dir);
107 spin_unlock_irqrestore(&d->lock, flags);
108
109 return 0;
110}
111
112static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
113{
114 return __davinci_direction(chip, offset, false, 0);
115}
116
117static int
118davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
119{
120 return __davinci_direction(chip, offset, true, value);
121}
122
123/*
124 * Read the pin's value (works even if it's set up as output);
125 * returns zero/nonzero.
126 *
127 * Note that changes are synched to the GPIO clock, so reading values back
128 * right after you've set them may give old values.
129 */
130static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
131{
132 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
133 struct davinci_gpio_regs __iomem *g;
134 int bank = offset / 32;
135
136 g = d->regs[bank];
137
138 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
139}
140
141/*
142 * Assuming the pin is muxed as a gpio output, set its output value.
143 */
144static void
145davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
146{
147 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
148 struct davinci_gpio_regs __iomem *g;
149 int bank = offset / 32;
150
151 g = d->regs[bank];
152
153 writel_relaxed(__gpio_mask(offset),
154 value ? &g->set_data : &g->clr_data);
155}
156
157static struct davinci_gpio_platform_data *
158davinci_gpio_get_pdata(struct platform_device *pdev)
159{
160 struct device_node *dn = pdev->dev.of_node;
161 struct davinci_gpio_platform_data *pdata;
162 int ret;
163 u32 val;
164
165 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
166 return dev_get_platdata(&pdev->dev);
167
168 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
169 if (!pdata)
170 return NULL;
171
172 ret = of_property_read_u32(dn, "ti,ngpio", &val);
173 if (ret)
174 goto of_err;
175
176 pdata->ngpio = val;
177
178 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
179 if (ret)
180 goto of_err;
181
182 pdata->gpio_unbanked = val;
183
184 return pdata;
185
186of_err:
187 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
188 return NULL;
189}
190
191static int davinci_gpio_probe(struct platform_device *pdev)
192{
193 int bank, i, ret = 0;
194 unsigned int ngpio, nbank, nirq;
195 struct davinci_gpio_controller *chips;
196 struct davinci_gpio_platform_data *pdata;
197 struct device *dev = &pdev->dev;
198
199 pdata = davinci_gpio_get_pdata(pdev);
200 if (!pdata) {
201 dev_err(dev, "No platform data found\n");
202 return -EINVAL;
203 }
204
205 dev->platform_data = pdata;
206
207 /*
208 * The gpio banks conceptually expose a segmented bitmap,
209 * and "ngpio" is one more than the largest zero-based
210 * bit index that's valid.
211 */
212 ngpio = pdata->ngpio;
213 if (ngpio == 0) {
214 dev_err(dev, "How many GPIOs?\n");
215 return -EINVAL;
216 }
217
218 /*
219 * If there are unbanked interrupts then the number of
220 * interrupts is equal to number of gpios else all are banked so
221 * number of interrupts is equal to number of banks(each with 16 gpios)
222 */
223 if (pdata->gpio_unbanked)
224 nirq = pdata->gpio_unbanked;
225 else
226 nirq = DIV_ROUND_UP(ngpio, 16);
227
228 chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
229 if (!chips)
230 return -ENOMEM;
231
232 gpio_base = devm_platform_ioremap_resource(pdev, 0);
233 if (IS_ERR(gpio_base))
234 return PTR_ERR(gpio_base);
235
236 for (i = 0; i < nirq; i++) {
237 chips->irqs[i] = platform_get_irq(pdev, i);
238 if (chips->irqs[i] < 0)
239 return chips->irqs[i];
240 }
241
242 chips->chip.label = dev_name(dev);
243
244 chips->chip.direction_input = davinci_direction_in;
245 chips->chip.get = davinci_gpio_get;
246 chips->chip.direction_output = davinci_direction_out;
247 chips->chip.set = davinci_gpio_set;
248
249 chips->chip.ngpio = ngpio;
250 chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
251
252#ifdef CONFIG_OF_GPIO
253 chips->chip.parent = dev;
254 chips->chip.request = gpiochip_generic_request;
255 chips->chip.free = gpiochip_generic_free;
256#endif
257 spin_lock_init(&chips->lock);
258
259 nbank = DIV_ROUND_UP(ngpio, 32);
260 for (bank = 0; bank < nbank; bank++)
261 chips->regs[bank] = gpio_base + offset_array[bank];
262
263 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
264 if (ret)
265 return ret;
266
267 platform_set_drvdata(pdev, chips);
268 ret = davinci_gpio_irq_setup(pdev);
269 if (ret)
270 return ret;
271
272 return 0;
273}
274
275/*--------------------------------------------------------------------------*/
276/*
277 * We expect irqs will normally be set up as input pins, but they can also be
278 * used as output pins ... which is convenient for testing.
279 *
280 * NOTE: The first few GPIOs also have direct INTC hookups in addition
281 * to their GPIOBNK0 irq, with a bit less overhead.
282 *
283 * All those INTC hookups (direct, plus several IRQ banks) can also
284 * serve as EDMA event triggers.
285 */
286
287static void gpio_irq_disable(struct irq_data *d)
288{
289 struct davinci_gpio_regs __iomem *g = irq2regs(d);
290 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
291
292 writel_relaxed(mask, &g->clr_falling);
293 writel_relaxed(mask, &g->clr_rising);
294}
295
296static void gpio_irq_enable(struct irq_data *d)
297{
298 struct davinci_gpio_regs __iomem *g = irq2regs(d);
299 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
300 unsigned status = irqd_get_trigger_type(d);
301
302 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
303 if (!status)
304 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
305
306 if (status & IRQ_TYPE_EDGE_FALLING)
307 writel_relaxed(mask, &g->set_falling);
308 if (status & IRQ_TYPE_EDGE_RISING)
309 writel_relaxed(mask, &g->set_rising);
310}
311
312static int gpio_irq_type(struct irq_data *d, unsigned trigger)
313{
314 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
315 return -EINVAL;
316
317 return 0;
318}
319
320static struct irq_chip gpio_irqchip = {
321 .name = "GPIO",
322 .irq_enable = gpio_irq_enable,
323 .irq_disable = gpio_irq_disable,
324 .irq_set_type = gpio_irq_type,
325 .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE,
326};
327
328static void gpio_irq_handler(struct irq_desc *desc)
329{
330 struct davinci_gpio_regs __iomem *g;
331 u32 mask = 0xffff;
332 int bank_num;
333 struct davinci_gpio_controller *d;
334 struct davinci_gpio_irq_data *irqdata;
335
336 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
337 bank_num = irqdata->bank_num;
338 g = irqdata->regs;
339 d = irqdata->chip;
340
341 /* we only care about one bank */
342 if ((bank_num % 2) == 1)
343 mask <<= 16;
344
345 /* temporarily mask (level sensitive) parent IRQ */
346 chained_irq_enter(irq_desc_get_chip(desc), desc);
347 while (1) {
348 u32 status;
349 int bit;
350 irq_hw_number_t hw_irq;
351
352 /* ack any irqs */
353 status = readl_relaxed(&g->intstat) & mask;
354 if (!status)
355 break;
356 writel_relaxed(status, &g->intstat);
357
358 /* now demux them to the right lowlevel handler */
359
360 while (status) {
361 bit = __ffs(status);
362 status &= ~BIT(bit);
363 /* Max number of gpios per controller is 144 so
364 * hw_irq will be in [0..143]
365 */
366 hw_irq = (bank_num / 2) * 32 + bit;
367
368 generic_handle_domain_irq(d->irq_domain, hw_irq);
369 }
370 }
371 chained_irq_exit(irq_desc_get_chip(desc), desc);
372 /* now it may re-trigger */
373}
374
375static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
376{
377 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
378
379 if (d->irq_domain)
380 return irq_create_mapping(d->irq_domain, offset);
381 else
382 return -ENXIO;
383}
384
385static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
386{
387 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
388
389 /*
390 * NOTE: we assume for now that only irqs in the first gpio_chip
391 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
392 */
393 if (offset < d->gpio_unbanked)
394 return d->irqs[offset];
395 else
396 return -ENODEV;
397}
398
399static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
400{
401 struct davinci_gpio_controller *d;
402 struct davinci_gpio_regs __iomem *g;
403 u32 mask, i;
404
405 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
406 g = (struct davinci_gpio_regs __iomem *)d->regs[0];
407 for (i = 0; i < MAX_INT_PER_BANK; i++)
408 if (data->irq == d->irqs[i])
409 break;
410
411 if (i == MAX_INT_PER_BANK)
412 return -EINVAL;
413
414 mask = __gpio_mask(i);
415
416 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
417 return -EINVAL;
418
419 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
420 ? &g->set_falling : &g->clr_falling);
421 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
422 ? &g->set_rising : &g->clr_rising);
423
424 return 0;
425}
426
427static int
428davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
429 irq_hw_number_t hw)
430{
431 struct davinci_gpio_controller *chips =
432 (struct davinci_gpio_controller *)d->host_data;
433 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
434
435 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
436 "davinci_gpio");
437 irq_set_irq_type(irq, IRQ_TYPE_NONE);
438 irq_set_chip_data(irq, (__force void *)g);
439 irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
440
441 return 0;
442}
443
444static const struct irq_domain_ops davinci_gpio_irq_ops = {
445 .map = davinci_gpio_irq_map,
446 .xlate = irq_domain_xlate_onetwocell,
447};
448
449static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
450{
451 static struct irq_chip_type gpio_unbanked;
452
453 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
454
455 return &gpio_unbanked.chip;
456};
457
458static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
459{
460 static struct irq_chip gpio_unbanked;
461
462 gpio_unbanked = *irq_get_chip(irq);
463 return &gpio_unbanked;
464};
465
466static const struct of_device_id davinci_gpio_ids[];
467
468/*
469 * NOTE: for suspend/resume, probably best to make a platform_device with
470 * suspend_late/resume_resume calls hooking into results of the set_wake()
471 * calls ... so if no gpios are wakeup events the clock can be disabled,
472 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
473 * (dm6446) can be set appropriately for GPIOV33 pins.
474 */
475
476static int davinci_gpio_irq_setup(struct platform_device *pdev)
477{
478 unsigned gpio, bank;
479 int irq;
480 int ret;
481 struct clk *clk;
482 u32 binten = 0;
483 unsigned ngpio;
484 struct device *dev = &pdev->dev;
485 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
486 struct davinci_gpio_platform_data *pdata = dev->platform_data;
487 struct davinci_gpio_regs __iomem *g;
488 struct irq_domain *irq_domain = NULL;
489 struct irq_chip *irq_chip;
490 struct davinci_gpio_irq_data *irqdata;
491 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
492
493 /*
494 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
495 */
496 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
497 if (dev->of_node)
498 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)device_get_match_data(dev);
499
500 ngpio = pdata->ngpio;
501
502 clk = devm_clk_get(dev, "gpio");
503 if (IS_ERR(clk)) {
504 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
505 return PTR_ERR(clk);
506 }
507
508 ret = clk_prepare_enable(clk);
509 if (ret)
510 return ret;
511
512 if (!pdata->gpio_unbanked) {
513 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
514 if (irq < 0) {
515 dev_err(dev, "Couldn't allocate IRQ numbers\n");
516 clk_disable_unprepare(clk);
517 return irq;
518 }
519
520 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
521 &davinci_gpio_irq_ops,
522 chips);
523 if (!irq_domain) {
524 dev_err(dev, "Couldn't register an IRQ domain\n");
525 clk_disable_unprepare(clk);
526 return -ENODEV;
527 }
528 }
529
530 /*
531 * Arrange gpiod_to_irq() support, handling either direct IRQs or
532 * banked IRQs. Having GPIOs in the first GPIO bank use direct
533 * IRQs, while the others use banked IRQs, would need some setup
534 * tweaks to recognize hardware which can do that.
535 */
536 chips->chip.to_irq = gpio_to_irq_banked;
537 chips->irq_domain = irq_domain;
538
539 /*
540 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
541 * controller only handling trigger modes. We currently assume no
542 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
543 */
544 if (pdata->gpio_unbanked) {
545 /* pass "bank 0" GPIO IRQs to AINTC */
546 chips->chip.to_irq = gpio_to_irq_unbanked;
547 chips->gpio_unbanked = pdata->gpio_unbanked;
548 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
549
550 /* AINTC handles mask/unmask; GPIO handles triggering */
551 irq = chips->irqs[0];
552 irq_chip = gpio_get_irq_chip(irq);
553 irq_chip->name = "GPIO-AINTC";
554 irq_chip->irq_set_type = gpio_irq_type_unbanked;
555
556 /* default trigger: both edges */
557 g = chips->regs[0];
558 writel_relaxed(~0, &g->set_falling);
559 writel_relaxed(~0, &g->set_rising);
560
561 /* set the direct IRQs up to use that irqchip */
562 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
563 irq_set_chip(chips->irqs[gpio], irq_chip);
564 irq_set_handler_data(chips->irqs[gpio], chips);
565 irq_set_status_flags(chips->irqs[gpio],
566 IRQ_TYPE_EDGE_BOTH);
567 }
568
569 goto done;
570 }
571
572 /*
573 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
574 * then chain through our own handler.
575 */
576 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
577 /* disabled by default, enabled only as needed
578 * There are register sets for 32 GPIOs. 2 banks of 16
579 * GPIOs are covered by each set of registers hence divide by 2
580 */
581 g = chips->regs[bank / 2];
582 writel_relaxed(~0, &g->clr_falling);
583 writel_relaxed(~0, &g->clr_rising);
584
585 /*
586 * Each chip handles 32 gpios, and each irq bank consists of 16
587 * gpio irqs. Pass the irq bank's corresponding controller to
588 * the chained irq handler.
589 */
590 irqdata = devm_kzalloc(&pdev->dev,
591 sizeof(struct
592 davinci_gpio_irq_data),
593 GFP_KERNEL);
594 if (!irqdata) {
595 clk_disable_unprepare(clk);
596 return -ENOMEM;
597 }
598
599 irqdata->regs = g;
600 irqdata->bank_num = bank;
601 irqdata->chip = chips;
602
603 irq_set_chained_handler_and_data(chips->irqs[bank],
604 gpio_irq_handler, irqdata);
605
606 binten |= BIT(bank);
607 }
608
609done:
610 /*
611 * BINTEN -- per-bank interrupt enable. genirq would also let these
612 * bits be set/cleared dynamically.
613 */
614 writel_relaxed(binten, gpio_base + BINTEN);
615
616 return 0;
617}
618
619static void davinci_gpio_save_context(struct davinci_gpio_controller *chips,
620 u32 nbank)
621{
622 struct davinci_gpio_regs __iomem *g;
623 struct davinci_gpio_regs *context;
624 u32 bank;
625 void __iomem *base;
626
627 base = chips->regs[0] - offset_array[0];
628 chips->binten_context = readl_relaxed(base + BINTEN);
629
630 for (bank = 0; bank < nbank; bank++) {
631 g = chips->regs[bank];
632 context = &chips->context[bank];
633 context->dir = readl_relaxed(&g->dir);
634 context->set_data = readl_relaxed(&g->set_data);
635 context->set_rising = readl_relaxed(&g->set_rising);
636 context->set_falling = readl_relaxed(&g->set_falling);
637 }
638
639 /* Clear all interrupt status registers */
640 writel_relaxed(GENMASK(31, 0), &g->intstat);
641}
642
643static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips,
644 u32 nbank)
645{
646 struct davinci_gpio_regs __iomem *g;
647 struct davinci_gpio_regs *context;
648 u32 bank;
649 void __iomem *base;
650
651 base = chips->regs[0] - offset_array[0];
652
653 if (readl_relaxed(base + BINTEN) != chips->binten_context)
654 writel_relaxed(chips->binten_context, base + BINTEN);
655
656 for (bank = 0; bank < nbank; bank++) {
657 g = chips->regs[bank];
658 context = &chips->context[bank];
659 if (readl_relaxed(&g->dir) != context->dir)
660 writel_relaxed(context->dir, &g->dir);
661 if (readl_relaxed(&g->set_data) != context->set_data)
662 writel_relaxed(context->set_data, &g->set_data);
663 if (readl_relaxed(&g->set_rising) != context->set_rising)
664 writel_relaxed(context->set_rising, &g->set_rising);
665 if (readl_relaxed(&g->set_falling) != context->set_falling)
666 writel_relaxed(context->set_falling, &g->set_falling);
667 }
668}
669
670static int davinci_gpio_suspend(struct device *dev)
671{
672 struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
673 struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
674 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
675
676 davinci_gpio_save_context(chips, nbank);
677
678 return 0;
679}
680
681static int davinci_gpio_resume(struct device *dev)
682{
683 struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
684 struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
685 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
686
687 davinci_gpio_restore_context(chips, nbank);
688
689 return 0;
690}
691
692static DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend,
693 davinci_gpio_resume);
694
695static const struct of_device_id davinci_gpio_ids[] = {
696 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
697 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
698 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
699 { /* sentinel */ },
700};
701MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
702
703static struct platform_driver davinci_gpio_driver = {
704 .probe = davinci_gpio_probe,
705 .driver = {
706 .name = "davinci_gpio",
707 .pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops),
708 .of_match_table = of_match_ptr(davinci_gpio_ids),
709 },
710};
711
712/*
713 * GPIO driver registration needs to be done before machine_init functions
714 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
715 */
716static int __init davinci_gpio_drv_reg(void)
717{
718 return platform_driver_register(&davinci_gpio_driver);
719}
720postcore_initcall(davinci_gpio_drv_reg);
721
722static void __exit davinci_gpio_exit(void)
723{
724 platform_driver_unregister(&davinci_gpio_driver);
725}
726module_exit(davinci_gpio_exit);
727
728MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
729MODULE_DESCRIPTION("DAVINCI GPIO driver");
730MODULE_LICENSE("GPL");
731MODULE_ALIAS("platform:gpio-davinci");