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1// SPDX-License-Identifier: GPL-2.0
2/***************************************************************************/
3
4/*
5 * m523x.c -- platform support for ColdFire 523x based boards
6 *
7 * Sub-architcture dependent initialization code for the Freescale
8 * 523x CPUs.
9 *
10 * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com)
11 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
12 */
13
14/***************************************************************************/
15
16#include <linux/kernel.h>
17#include <linux/param.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <asm/machdep.h>
21#include <asm/coldfire.h>
22#include <asm/mcfsim.h>
23#include <asm/mcfclk.h>
24
25/***************************************************************************/
26
27DEFINE_CLK(pll, "pll.0", MCF_CLK);
28DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
29DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
30DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
31DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
32DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
33DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
34DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
35DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
36DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
37DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
38DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
39
40struct clk *mcf_clks[] = {
41 &clk_pll,
42 &clk_sys,
43 &clk_mcfpit0,
44 &clk_mcfpit1,
45 &clk_mcfpit2,
46 &clk_mcfpit3,
47 &clk_mcfuart0,
48 &clk_mcfuart1,
49 &clk_mcfuart2,
50 &clk_mcfqspi0,
51 &clk_fec0,
52 &clk_mcfi2c0,
53 NULL
54};
55
56/***************************************************************************/
57
58static void __init m523x_qspi_init(void)
59{
60#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
61 u16 par;
62
63 /* setup QSPS pins for QSPI with gpio CS control */
64 writeb(0x1f, MCFGPIO_PAR_QSPI);
65 /* and CS2 & CS3 as gpio */
66 par = readw(MCFGPIO_PAR_TIMER);
67 par &= 0x3f3f;
68 writew(par, MCFGPIO_PAR_TIMER);
69#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
70}
71
72/***************************************************************************/
73
74static void __init m523x_i2c_init(void)
75{
76#if IS_ENABLED(CONFIG_I2C_IMX)
77 u8 par;
78
79 /* setup Port AS Pin Assignment Register for I2C */
80 /* set PASPA0 to SCL and PASPA1 to SDA */
81 par = readb(MCFGPIO_PAR_FECI2C);
82 par |= 0x0f;
83 writeb(par, MCFGPIO_PAR_FECI2C);
84#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
85}
86
87/***************************************************************************/
88
89static void __init m523x_fec_init(void)
90{
91 /* Set multi-function pins to ethernet use */
92 writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
93}
94
95/***************************************************************************/
96
97void __init config_BSP(char *commandp, int size)
98{
99 mach_sched_init = hw_timer_init;
100 m523x_fec_init();
101 m523x_qspi_init();
102 m523x_i2c_init();
103}
104
105/***************************************************************************/
1// SPDX-License-Identifier: GPL-2.0
2/***************************************************************************/
3
4/*
5 * m523x.c -- platform support for ColdFire 523x based boards
6 *
7 * Sub-architcture dependent initialization code for the Freescale
8 * 523x CPUs.
9 *
10 * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com)
11 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
12 */
13
14/***************************************************************************/
15
16#include <linux/clkdev.h>
17#include <linux/kernel.h>
18#include <linux/param.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <asm/machdep.h>
22#include <asm/coldfire.h>
23#include <asm/mcfsim.h>
24#include <asm/mcfclk.h>
25
26/***************************************************************************/
27
28DEFINE_CLK(pll, "pll.0", MCF_CLK);
29DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
30
31static struct clk_lookup m523x_clk_lookup[] = {
32 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
33 CLKDEV_INIT(NULL, "sys.0", &clk_sys),
34 CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
35 CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
36 CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
37 CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
38 CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
39 CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
40 CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
41 CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
42 CLKDEV_INIT("fec.0", NULL, &clk_sys),
43 CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
44};
45
46/***************************************************************************/
47
48static void __init m523x_qspi_init(void)
49{
50#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
51 u16 par;
52
53 /* setup QSPS pins for QSPI with gpio CS control */
54 writeb(0x1f, MCFGPIO_PAR_QSPI);
55 /* and CS2 & CS3 as gpio */
56 par = readw(MCFGPIO_PAR_TIMER);
57 par &= 0x3f3f;
58 writew(par, MCFGPIO_PAR_TIMER);
59#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
60}
61
62/***************************************************************************/
63
64static void __init m523x_i2c_init(void)
65{
66#if IS_ENABLED(CONFIG_I2C_IMX)
67 u8 par;
68
69 /* setup Port AS Pin Assignment Register for I2C */
70 /* set PASPA0 to SCL and PASPA1 to SDA */
71 par = readb(MCFGPIO_PAR_FECI2C);
72 par |= 0x0f;
73 writeb(par, MCFGPIO_PAR_FECI2C);
74#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
75}
76
77/***************************************************************************/
78
79static void __init m523x_fec_init(void)
80{
81 /* Set multi-function pins to ethernet use */
82 writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
83}
84
85/***************************************************************************/
86
87void __init config_BSP(char *commandp, int size)
88{
89 mach_sched_init = hw_timer_init;
90 m523x_fec_init();
91 m523x_qspi_init();
92 m523x_i2c_init();
93
94 clkdev_add_table(m523x_clk_lookup, ARRAY_SIZE(m523x_clk_lookup));
95}
96
97/***************************************************************************/