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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * Abramo Bagnara <abramo@alsa-project.org>
5 * Cirrus Logic, Inc.
6 * Routines for control of Cirrus Logic CS461x chips
7 *
8 * KNOWN BUGS:
9 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
10 * and the SPDIF get somewhat "distorcionated", or/and left right channel
11 * are swapped. To get around this problem when it happens, mute and unmute
12 * the SPDIF input mixer control.
13 * - On the Hercules Game Theater XP the amplifier are sometimes turned
14 * off on inadecuate moments which causes distorcions on sound.
15 *
16 * TODO:
17 * - Secondary CODEC on some soundcards
18 * - SPDIF input support for other sample rates then 48khz
19 * - Posibility to mix the SPDIF output with analog sources.
20 * - PCM channels for Center and LFE on secondary codec
21 *
22 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
23 * is default configuration), no SPDIF, no secondary codec, no
24 * multi channel PCM. But known to work.
25 *
26 * FINALLY: A credit to the developers Tom and Jordan
27 * at Cirrus for have helping me out with the DSP, however we
28 * still don't have sufficient documentation and technical
29 * references to be able to implement all fancy feutures
30 * supported by the cs46xx DSP's.
31 * Benny <benny@hostmobility.com>
32 */
33
34#include <linux/delay.h>
35#include <linux/pci.h>
36#include <linux/pm.h>
37#include <linux/init.h>
38#include <linux/interrupt.h>
39#include <linux/slab.h>
40#include <linux/gameport.h>
41#include <linux/mutex.h>
42#include <linux/export.h>
43#include <linux/module.h>
44#include <linux/firmware.h>
45#include <linux/vmalloc.h>
46#include <linux/io.h>
47
48#include <sound/core.h>
49#include <sound/control.h>
50#include <sound/info.h>
51#include <sound/pcm.h>
52#include <sound/pcm_params.h>
53#include "cs46xx.h"
54
55#include "cs46xx_lib.h"
56#include "dsp_spos.h"
57
58static void amp_voyetra(struct snd_cs46xx *chip, int change);
59
60#ifdef CONFIG_SND_CS46XX_NEW_DSP
61static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
62static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
63static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
64static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
65static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
66static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
67#endif
68
69static const struct snd_pcm_ops snd_cs46xx_playback_ops;
70static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
71static const struct snd_pcm_ops snd_cs46xx_capture_ops;
72static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
73
74static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
75 unsigned short reg,
76 int codec_index)
77{
78 int count;
79 unsigned short result,tmp;
80 u32 offset = 0;
81
82 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
83 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
84 return 0xffff;
85
86 chip->active_ctrl(chip, 1);
87
88 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
89 offset = CS46XX_SECONDARY_CODEC_OFFSET;
90
91 /*
92 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
93 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
94 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
95 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
96 * 5. if DCV not cleared, break and return error
97 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
98 */
99
100 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
101
102 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
103 if ((tmp & ACCTL_VFRM) == 0) {
104 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
105 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
106 msleep(50);
107 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
108 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
109
110 }
111
112 /*
113 * Setup the AC97 control registers on the CS461x to send the
114 * appropriate command to the AC97 to perform the read.
115 * ACCAD = Command Address Register = 46Ch
116 * ACCDA = Command Data Register = 470h
117 * ACCTL = Control Register = 460h
118 * set DCV - will clear when process completed
119 * set CRW - Read command
120 * set VFRM - valid frame enabled
121 * set ESYN - ASYNC generation enabled
122 * set RSTN - ARST# inactive, AC97 codec not reset
123 */
124
125 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
126 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
127 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
128 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
129 ACCTL_VFRM | ACCTL_ESYN |
130 ACCTL_RSTN);
131 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
132 ACCTL_VFRM | ACCTL_ESYN |
133 ACCTL_RSTN);
134 } else {
135 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
136 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
137 ACCTL_RSTN);
138 }
139
140 /*
141 * Wait for the read to occur.
142 */
143 for (count = 0; count < 1000; count++) {
144 /*
145 * First, we want to wait for a short time.
146 */
147 udelay(10);
148 /*
149 * Now, check to see if the read has completed.
150 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
151 */
152 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
153 goto ok1;
154 }
155
156 dev_err(chip->card->dev,
157 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
158 result = 0xffff;
159 goto end;
160
161 ok1:
162 /*
163 * Wait for the valid status bit to go active.
164 */
165 for (count = 0; count < 100; count++) {
166 /*
167 * Read the AC97 status register.
168 * ACSTS = Status Register = 464h
169 * VSTS - Valid Status
170 */
171 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
172 goto ok2;
173 udelay(10);
174 }
175
176 dev_err(chip->card->dev,
177 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
178 codec_index, reg);
179 result = 0xffff;
180 goto end;
181
182 ok2:
183 /*
184 * Read the data returned from the AC97 register.
185 * ACSDA = Status Data Register = 474h
186 */
187#if 0
188 dev_dbg(chip->card->dev,
189 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
190 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
191 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
192#endif
193
194 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
195 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
196 end:
197 chip->active_ctrl(chip, -1);
198 return result;
199}
200
201static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
202 unsigned short reg)
203{
204 struct snd_cs46xx *chip = ac97->private_data;
205 unsigned short val;
206 int codec_index = ac97->num;
207
208 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
209 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
210 return 0xffff;
211
212 val = snd_cs46xx_codec_read(chip, reg, codec_index);
213
214 return val;
215}
216
217
218static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
219 unsigned short reg,
220 unsigned short val,
221 int codec_index)
222{
223 int count;
224
225 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
226 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
227 return;
228
229 chip->active_ctrl(chip, 1);
230
231 /*
232 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
233 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
234 * 3. Write ACCTL = Control Register = 460h for initiating the write
235 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
236 * 5. if DCV not cleared, break and return error
237 */
238
239 /*
240 * Setup the AC97 control registers on the CS461x to send the
241 * appropriate command to the AC97 to perform the read.
242 * ACCAD = Command Address Register = 46Ch
243 * ACCDA = Command Data Register = 470h
244 * ACCTL = Control Register = 460h
245 * set DCV - will clear when process completed
246 * reset CRW - Write command
247 * set VFRM - valid frame enabled
248 * set ESYN - ASYNC generation enabled
249 * set RSTN - ARST# inactive, AC97 codec not reset
250 */
251 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
252 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
253 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
254
255 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
256 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
257 ACCTL_ESYN | ACCTL_RSTN);
258 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
259 ACCTL_ESYN | ACCTL_RSTN);
260 } else {
261 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
262 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
263 }
264
265 for (count = 0; count < 4000; count++) {
266 /*
267 * First, we want to wait for a short time.
268 */
269 udelay(10);
270 /*
271 * Now, check to see if the write has completed.
272 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
273 */
274 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
275 goto end;
276 }
277 }
278 dev_err(chip->card->dev,
279 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
280 codec_index, reg, val);
281 end:
282 chip->active_ctrl(chip, -1);
283}
284
285static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
286 unsigned short reg,
287 unsigned short val)
288{
289 struct snd_cs46xx *chip = ac97->private_data;
290 int codec_index = ac97->num;
291
292 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
293 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
294 return;
295
296 snd_cs46xx_codec_write(chip, reg, val, codec_index);
297}
298
299
300/*
301 * Chip initialization
302 */
303
304int snd_cs46xx_download(struct snd_cs46xx *chip,
305 u32 *src,
306 unsigned long offset,
307 unsigned long len)
308{
309 void __iomem *dst;
310 unsigned int bank = offset >> 16;
311 offset = offset & 0xffff;
312
313 if (snd_BUG_ON((offset & 3) || (len & 3)))
314 return -EINVAL;
315 dst = chip->region.idx[bank+1].remap_addr + offset;
316 len /= sizeof(u32);
317
318 /* writel already converts 32-bit value to right endianess */
319 while (len-- > 0) {
320 writel(*src++, dst);
321 dst += sizeof(u32);
322 }
323 return 0;
324}
325
326static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
327{
328#ifdef __LITTLE_ENDIAN
329 memcpy(dst, src, len);
330#else
331 u32 *_dst = dst;
332 const __le32 *_src = src;
333 len /= 4;
334 while (len-- > 0)
335 *_dst++ = le32_to_cpu(*_src++);
336#endif
337}
338
339#ifdef CONFIG_SND_CS46XX_NEW_DSP
340
341static const char *module_names[CS46XX_DSP_MODULES] = {
342 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
343};
344
345MODULE_FIRMWARE("cs46xx/cwc4630");
346MODULE_FIRMWARE("cs46xx/cwcasync");
347MODULE_FIRMWARE("cs46xx/cwcsnoop");
348MODULE_FIRMWARE("cs46xx/cwcbinhack");
349MODULE_FIRMWARE("cs46xx/cwcdma");
350
351static void free_module_desc(struct dsp_module_desc *module)
352{
353 if (!module)
354 return;
355 kfree(module->module_name);
356 kfree(module->symbol_table.symbols);
357 if (module->segments) {
358 int i;
359 for (i = 0; i < module->nsegments; i++)
360 kfree(module->segments[i].data);
361 kfree(module->segments);
362 }
363 kfree(module);
364}
365
366/* firmware binary format:
367 * le32 nsymbols;
368 * struct {
369 * le32 address;
370 * char symbol_name[DSP_MAX_SYMBOL_NAME];
371 * le32 symbol_type;
372 * } symbols[nsymbols];
373 * le32 nsegments;
374 * struct {
375 * le32 segment_type;
376 * le32 offset;
377 * le32 size;
378 * le32 data[size];
379 * } segments[nsegments];
380 */
381
382static int load_firmware(struct snd_cs46xx *chip,
383 struct dsp_module_desc **module_ret,
384 const char *fw_name)
385{
386 int i, err;
387 unsigned int nums, fwlen, fwsize;
388 const __le32 *fwdat;
389 struct dsp_module_desc *module = NULL;
390 const struct firmware *fw;
391 char fw_path[32];
392
393 sprintf(fw_path, "cs46xx/%s", fw_name);
394 err = request_firmware(&fw, fw_path, &chip->pci->dev);
395 if (err < 0)
396 return err;
397 fwsize = fw->size / 4;
398 if (fwsize < 2) {
399 err = -EINVAL;
400 goto error;
401 }
402
403 err = -ENOMEM;
404 module = kzalloc(sizeof(*module), GFP_KERNEL);
405 if (!module)
406 goto error;
407 module->module_name = kstrdup(fw_name, GFP_KERNEL);
408 if (!module->module_name)
409 goto error;
410
411 fwlen = 0;
412 fwdat = (const __le32 *)fw->data;
413 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
414 if (nums >= 40)
415 goto error_inval;
416 module->symbol_table.symbols =
417 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
418 if (!module->symbol_table.symbols)
419 goto error;
420 for (i = 0; i < nums; i++) {
421 struct dsp_symbol_entry *entry =
422 &module->symbol_table.symbols[i];
423 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
424 goto error_inval;
425 entry->address = le32_to_cpu(fwdat[fwlen++]);
426 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
427 fwlen += DSP_MAX_SYMBOL_NAME / 4;
428 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
429 }
430
431 if (fwlen >= fwsize)
432 goto error_inval;
433 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
434 if (nums > 10)
435 goto error_inval;
436 module->segments =
437 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
438 if (!module->segments)
439 goto error;
440 for (i = 0; i < nums; i++) {
441 struct dsp_segment_desc *entry = &module->segments[i];
442 if (fwlen + 3 > fwsize)
443 goto error_inval;
444 entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
445 entry->offset = le32_to_cpu(fwdat[fwlen++]);
446 entry->size = le32_to_cpu(fwdat[fwlen++]);
447 if (fwlen + entry->size > fwsize)
448 goto error_inval;
449 entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL);
450 if (!entry->data)
451 goto error;
452 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
453 fwlen += entry->size;
454 }
455
456 *module_ret = module;
457 release_firmware(fw);
458 return 0;
459
460 error_inval:
461 err = -EINVAL;
462 error:
463 free_module_desc(module);
464 release_firmware(fw);
465 return err;
466}
467
468int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
469 unsigned long offset,
470 unsigned long len)
471{
472 void __iomem *dst;
473 unsigned int bank = offset >> 16;
474 offset = offset & 0xffff;
475
476 if (snd_BUG_ON((offset & 3) || (len & 3)))
477 return -EINVAL;
478 dst = chip->region.idx[bank+1].remap_addr + offset;
479 len /= sizeof(u32);
480
481 /* writel already converts 32-bit value to right endianess */
482 while (len-- > 0) {
483 writel(0, dst);
484 dst += sizeof(u32);
485 }
486 return 0;
487}
488
489#else /* old DSP image */
490
491struct ba1_struct {
492 struct {
493 u32 offset;
494 u32 size;
495 } memory[BA1_MEMORY_COUNT];
496 u32 map[BA1_DWORD_SIZE];
497};
498
499MODULE_FIRMWARE("cs46xx/ba1");
500
501static int load_firmware(struct snd_cs46xx *chip)
502{
503 const struct firmware *fw;
504 int i, size, err;
505
506 err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
507 if (err < 0)
508 return err;
509 if (fw->size != sizeof(*chip->ba1)) {
510 err = -EINVAL;
511 goto error;
512 }
513
514 chip->ba1 = vmalloc(sizeof(*chip->ba1));
515 if (!chip->ba1) {
516 err = -ENOMEM;
517 goto error;
518 }
519
520 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
521
522 /* sanity check */
523 size = 0;
524 for (i = 0; i < BA1_MEMORY_COUNT; i++)
525 size += chip->ba1->memory[i].size;
526 if (size > BA1_DWORD_SIZE * 4)
527 err = -EINVAL;
528
529 error:
530 release_firmware(fw);
531 return err;
532}
533
534int snd_cs46xx_download_image(struct snd_cs46xx *chip)
535{
536 int idx, err;
537 unsigned int offset = 0;
538 struct ba1_struct *ba1 = chip->ba1;
539
540 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
541 err = snd_cs46xx_download(chip,
542 &ba1->map[offset],
543 ba1->memory[idx].offset,
544 ba1->memory[idx].size);
545 if (err < 0)
546 return err;
547 offset += ba1->memory[idx].size >> 2;
548 }
549 return 0;
550}
551#endif /* CONFIG_SND_CS46XX_NEW_DSP */
552
553/*
554 * Chip reset
555 */
556
557static void snd_cs46xx_reset(struct snd_cs46xx *chip)
558{
559 int idx;
560
561 /*
562 * Write the reset bit of the SP control register.
563 */
564 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
565
566 /*
567 * Write the control register.
568 */
569 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
570
571 /*
572 * Clear the trap registers.
573 */
574 for (idx = 0; idx < 8; idx++) {
575 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
576 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
577 }
578 snd_cs46xx_poke(chip, BA1_DREG, 0);
579
580 /*
581 * Set the frame timer to reflect the number of cycles per frame.
582 */
583 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
584}
585
586static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
587{
588 u32 i, status = 0;
589 /*
590 * Make sure the previous FIFO write operation has completed.
591 */
592 for(i = 0; i < 50; i++){
593 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
594
595 if( !(status & SERBST_WBSY) )
596 break;
597
598 mdelay(retry_timeout);
599 }
600
601 if(status & SERBST_WBSY) {
602 dev_err(chip->card->dev,
603 "failure waiting for FIFO command to complete\n");
604 return -EINVAL;
605 }
606
607 return 0;
608}
609
610static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
611{
612 int idx, powerdown = 0;
613 unsigned int tmp;
614
615 /*
616 * See if the devices are powered down. If so, we must power them up first
617 * or they will not respond.
618 */
619 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
620 if (!(tmp & CLKCR1_SWCE)) {
621 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
622 powerdown = 1;
623 }
624
625 /*
626 * We want to clear out the serial port FIFOs so we don't end up playing
627 * whatever random garbage happens to be in them. We fill the sample FIFOS
628 * with zero (silence).
629 */
630 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
631
632 /*
633 * Fill all 256 sample FIFO locations.
634 */
635 for (idx = 0; idx < 0xFF; idx++) {
636 /*
637 * Make sure the previous FIFO write operation has completed.
638 */
639 if (cs46xx_wait_for_fifo(chip,1)) {
640 dev_dbg(chip->card->dev,
641 "failed waiting for FIFO at addr (%02X)\n",
642 idx);
643
644 if (powerdown)
645 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
646
647 break;
648 }
649 /*
650 * Write the serial port FIFO index.
651 */
652 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
653 /*
654 * Tell the serial port to load the new value into the FIFO location.
655 */
656 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
657 }
658 /*
659 * Now, if we powered up the devices, then power them back down again.
660 * This is kinda ugly, but should never happen.
661 */
662 if (powerdown)
663 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
664}
665
666static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
667{
668 int cnt;
669
670 /*
671 * Set the frame timer to reflect the number of cycles per frame.
672 */
673 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
674 /*
675 * Turn on the run, run at frame, and DMA enable bits in the local copy of
676 * the SP control register.
677 */
678 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
679 /*
680 * Wait until the run at frame bit resets itself in the SP control
681 * register.
682 */
683 for (cnt = 0; cnt < 25; cnt++) {
684 udelay(50);
685 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
686 break;
687 }
688
689 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
690 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
691}
692
693static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
694{
695 /*
696 * Turn off the run, run at frame, and DMA enable bits in the local copy of
697 * the SP control register.
698 */
699 snd_cs46xx_poke(chip, BA1_SPCR, 0);
700}
701
702/*
703 * Sample rate routines
704 */
705
706#define GOF_PER_SEC 200
707
708static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
709{
710 unsigned long flags;
711 unsigned int tmp1, tmp2;
712 unsigned int phiIncr;
713 unsigned int correctionPerGOF, correctionPerSec;
714
715 /*
716 * Compute the values used to drive the actual sample rate conversion.
717 * The following formulas are being computed, using inline assembly
718 * since we need to use 64 bit arithmetic to compute the values:
719 *
720 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
721 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
722 * GOF_PER_SEC)
723 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
724 * GOF_PER_SEC * correctionPerGOF
725 *
726 * i.e.
727 *
728 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
729 * correctionPerGOF:correctionPerSec =
730 * dividend:remainder(ulOther / GOF_PER_SEC)
731 */
732 tmp1 = rate << 16;
733 phiIncr = tmp1 / 48000;
734 tmp1 -= phiIncr * 48000;
735 tmp1 <<= 10;
736 phiIncr <<= 10;
737 tmp2 = tmp1 / 48000;
738 phiIncr += tmp2;
739 tmp1 -= tmp2 * 48000;
740 correctionPerGOF = tmp1 / GOF_PER_SEC;
741 tmp1 -= correctionPerGOF * GOF_PER_SEC;
742 correctionPerSec = tmp1;
743
744 /*
745 * Fill in the SampleRateConverter control block.
746 */
747 spin_lock_irqsave(&chip->reg_lock, flags);
748 snd_cs46xx_poke(chip, BA1_PSRC,
749 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
750 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
751 spin_unlock_irqrestore(&chip->reg_lock, flags);
752}
753
754static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
755{
756 unsigned long flags;
757 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
758 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
759 unsigned int frameGroupLength, cnt;
760
761 /*
762 * We can only decimate by up to a factor of 1/9th the hardware rate.
763 * Correct the value if an attempt is made to stray outside that limit.
764 */
765 if ((rate * 9) < 48000)
766 rate = 48000 / 9;
767
768 /*
769 * We can not capture at a rate greater than the Input Rate (48000).
770 * Return an error if an attempt is made to stray outside that limit.
771 */
772 if (rate > 48000)
773 rate = 48000;
774
775 /*
776 * Compute the values used to drive the actual sample rate conversion.
777 * The following formulas are being computed, using inline assembly
778 * since we need to use 64 bit arithmetic to compute the values:
779 *
780 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
781 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
782 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
783 * GOF_PER_SEC)
784 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
785 * GOF_PER_SEC * correctionPerGOF
786 * initialDelay = ceil((24 * Fs,in) / Fs,out)
787 *
788 * i.e.
789 *
790 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
791 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
792 * correctionPerGOF:correctionPerSec =
793 * dividend:remainder(ulOther / GOF_PER_SEC)
794 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
795 */
796
797 tmp1 = rate << 16;
798 coeffIncr = tmp1 / 48000;
799 tmp1 -= coeffIncr * 48000;
800 tmp1 <<= 7;
801 coeffIncr <<= 7;
802 coeffIncr += tmp1 / 48000;
803 coeffIncr ^= 0xFFFFFFFF;
804 coeffIncr++;
805 tmp1 = 48000 << 16;
806 phiIncr = tmp1 / rate;
807 tmp1 -= phiIncr * rate;
808 tmp1 <<= 10;
809 phiIncr <<= 10;
810 tmp2 = tmp1 / rate;
811 phiIncr += tmp2;
812 tmp1 -= tmp2 * rate;
813 correctionPerGOF = tmp1 / GOF_PER_SEC;
814 tmp1 -= correctionPerGOF * GOF_PER_SEC;
815 correctionPerSec = tmp1;
816 initialDelay = ((48000 * 24) + rate - 1) / rate;
817
818 /*
819 * Fill in the VariDecimate control block.
820 */
821 spin_lock_irqsave(&chip->reg_lock, flags);
822 snd_cs46xx_poke(chip, BA1_CSRC,
823 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
824 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
825 snd_cs46xx_poke(chip, BA1_CD,
826 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
827 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
828 spin_unlock_irqrestore(&chip->reg_lock, flags);
829
830 /*
831 * Figure out the frame group length for the write back task. Basically,
832 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
833 * the output sample rate.
834 */
835 frameGroupLength = 1;
836 for (cnt = 2; cnt <= 64; cnt *= 2) {
837 if (((rate / cnt) * cnt) != rate)
838 frameGroupLength *= 2;
839 }
840 if (((rate / 3) * 3) != rate) {
841 frameGroupLength *= 3;
842 }
843 for (cnt = 5; cnt <= 125; cnt *= 5) {
844 if (((rate / cnt) * cnt) != rate)
845 frameGroupLength *= 5;
846 }
847
848 /*
849 * Fill in the WriteBack control block.
850 */
851 spin_lock_irqsave(&chip->reg_lock, flags);
852 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
853 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
854 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
855 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
856 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
857 spin_unlock_irqrestore(&chip->reg_lock, flags);
858}
859
860/*
861 * PCM part
862 */
863
864static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
865 struct snd_pcm_indirect *rec, size_t bytes)
866{
867 struct snd_pcm_runtime *runtime = substream->runtime;
868 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
869 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
870}
871
872static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
873{
874 struct snd_pcm_runtime *runtime = substream->runtime;
875 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
876 return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec,
877 snd_cs46xx_pb_trans_copy);
878}
879
880static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
881 struct snd_pcm_indirect *rec, size_t bytes)
882{
883 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
884 struct snd_pcm_runtime *runtime = substream->runtime;
885 memcpy(runtime->dma_area + rec->sw_data,
886 chip->capt.hw_buf.area + rec->hw_data, bytes);
887}
888
889static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
890{
891 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
892 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
893 snd_cs46xx_cp_trans_copy);
894}
895
896static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
897{
898 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
899 size_t ptr;
900 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
901
902 if (snd_BUG_ON(!cpcm->pcm_channel))
903 return -ENXIO;
904
905#ifdef CONFIG_SND_CS46XX_NEW_DSP
906 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
907#else
908 ptr = snd_cs46xx_peek(chip, BA1_PBA);
909#endif
910 ptr -= cpcm->hw_buf.addr;
911 return ptr >> cpcm->shift;
912}
913
914static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
915{
916 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
917 size_t ptr;
918 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
919
920#ifdef CONFIG_SND_CS46XX_NEW_DSP
921 if (snd_BUG_ON(!cpcm->pcm_channel))
922 return -ENXIO;
923 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
924#else
925 ptr = snd_cs46xx_peek(chip, BA1_PBA);
926#endif
927 ptr -= cpcm->hw_buf.addr;
928 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
929}
930
931static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
932{
933 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
934 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
935 return ptr >> chip->capt.shift;
936}
937
938static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
939{
940 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
941 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
942 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
943}
944
945static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
946 int cmd)
947{
948 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
949 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
950 int result = 0;
951
952#ifdef CONFIG_SND_CS46XX_NEW_DSP
953 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
954 if (! cpcm->pcm_channel) {
955 return -ENXIO;
956 }
957#endif
958 switch (cmd) {
959 case SNDRV_PCM_TRIGGER_START:
960 case SNDRV_PCM_TRIGGER_RESUME:
961#ifdef CONFIG_SND_CS46XX_NEW_DSP
962 /* magic value to unmute PCM stream playback volume */
963 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
964 SCBVolumeCtrl) << 2, 0x80008000);
965
966 if (cpcm->pcm_channel->unlinked)
967 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
968
969 if (substream->runtime->periods != CS46XX_FRAGS)
970 snd_cs46xx_playback_transfer(substream);
971#else
972 spin_lock(&chip->reg_lock);
973 if (substream->runtime->periods != CS46XX_FRAGS)
974 snd_cs46xx_playback_transfer(substream);
975 { unsigned int tmp;
976 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
977 tmp &= 0x0000ffff;
978 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
979 }
980 spin_unlock(&chip->reg_lock);
981#endif
982 break;
983 case SNDRV_PCM_TRIGGER_STOP:
984 case SNDRV_PCM_TRIGGER_SUSPEND:
985#ifdef CONFIG_SND_CS46XX_NEW_DSP
986 /* magic mute channel */
987 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
988 SCBVolumeCtrl) << 2, 0xffffffff);
989
990 if (!cpcm->pcm_channel->unlinked)
991 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
992#else
993 spin_lock(&chip->reg_lock);
994 { unsigned int tmp;
995 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
996 tmp &= 0x0000ffff;
997 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
998 }
999 spin_unlock(&chip->reg_lock);
1000#endif
1001 break;
1002 default:
1003 result = -EINVAL;
1004 break;
1005 }
1006
1007 return result;
1008}
1009
1010static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1011 int cmd)
1012{
1013 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1014 unsigned int tmp;
1015 int result = 0;
1016
1017 spin_lock(&chip->reg_lock);
1018 switch (cmd) {
1019 case SNDRV_PCM_TRIGGER_START:
1020 case SNDRV_PCM_TRIGGER_RESUME:
1021 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1022 tmp &= 0xffff0000;
1023 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1024 break;
1025 case SNDRV_PCM_TRIGGER_STOP:
1026 case SNDRV_PCM_TRIGGER_SUSPEND:
1027 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1028 tmp &= 0xffff0000;
1029 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1030 break;
1031 default:
1032 result = -EINVAL;
1033 break;
1034 }
1035 spin_unlock(&chip->reg_lock);
1036
1037 return result;
1038}
1039
1040#ifdef CONFIG_SND_CS46XX_NEW_DSP
1041static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1042 int sample_rate)
1043{
1044
1045 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1046 if ( cpcm->pcm_channel == NULL) {
1047 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1048 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1049 if (cpcm->pcm_channel == NULL) {
1050 dev_err(chip->card->dev,
1051 "failed to create virtual PCM channel\n");
1052 return -ENOMEM;
1053 }
1054 cpcm->pcm_channel->sample_rate = sample_rate;
1055 } else
1056 /* if sample rate is changed */
1057 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1058 int unlinked = cpcm->pcm_channel->unlinked;
1059 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1060
1061 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
1062 cpcm->hw_buf.addr,
1063 cpcm->pcm_channel_id)) == NULL) {
1064 dev_err(chip->card->dev,
1065 "failed to re-create virtual PCM channel\n");
1066 return -ENOMEM;
1067 }
1068
1069 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1070 cpcm->pcm_channel->sample_rate = sample_rate;
1071 }
1072
1073 return 0;
1074}
1075#endif
1076
1077
1078static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1079 struct snd_pcm_hw_params *hw_params)
1080{
1081 struct snd_pcm_runtime *runtime = substream->runtime;
1082 struct snd_cs46xx_pcm *cpcm;
1083 int err;
1084#ifdef CONFIG_SND_CS46XX_NEW_DSP
1085 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1086 int sample_rate = params_rate(hw_params);
1087 int period_size = params_period_bytes(hw_params);
1088#endif
1089 cpcm = runtime->private_data;
1090
1091#ifdef CONFIG_SND_CS46XX_NEW_DSP
1092 if (snd_BUG_ON(!sample_rate))
1093 return -ENXIO;
1094
1095 mutex_lock(&chip->spos_mutex);
1096
1097 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
1098 mutex_unlock(&chip->spos_mutex);
1099 return -ENXIO;
1100 }
1101
1102 snd_BUG_ON(!cpcm->pcm_channel);
1103 if (!cpcm->pcm_channel) {
1104 mutex_unlock(&chip->spos_mutex);
1105 return -ENXIO;
1106 }
1107
1108
1109 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1110 mutex_unlock(&chip->spos_mutex);
1111 return -EINVAL;
1112 }
1113
1114 dev_dbg(chip->card->dev,
1115 "period_size (%d), periods (%d) buffer_size(%d)\n",
1116 period_size, params_periods(hw_params),
1117 params_buffer_bytes(hw_params));
1118#endif
1119
1120 if (params_periods(hw_params) == CS46XX_FRAGS) {
1121 if (runtime->dma_area != cpcm->hw_buf.area)
1122 snd_pcm_lib_free_pages(substream);
1123 runtime->dma_area = cpcm->hw_buf.area;
1124 runtime->dma_addr = cpcm->hw_buf.addr;
1125 runtime->dma_bytes = cpcm->hw_buf.bytes;
1126
1127
1128#ifdef CONFIG_SND_CS46XX_NEW_DSP
1129 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1130 substream->ops = &snd_cs46xx_playback_ops;
1131 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1132 substream->ops = &snd_cs46xx_playback_rear_ops;
1133 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1134 substream->ops = &snd_cs46xx_playback_clfe_ops;
1135 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1136 substream->ops = &snd_cs46xx_playback_iec958_ops;
1137 } else {
1138 snd_BUG();
1139 }
1140#else
1141 substream->ops = &snd_cs46xx_playback_ops;
1142#endif
1143
1144 } else {
1145 if (runtime->dma_area == cpcm->hw_buf.area) {
1146 runtime->dma_area = NULL;
1147 runtime->dma_addr = 0;
1148 runtime->dma_bytes = 0;
1149 }
1150 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
1151#ifdef CONFIG_SND_CS46XX_NEW_DSP
1152 mutex_unlock(&chip->spos_mutex);
1153#endif
1154 return err;
1155 }
1156
1157#ifdef CONFIG_SND_CS46XX_NEW_DSP
1158 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1159 substream->ops = &snd_cs46xx_playback_indirect_ops;
1160 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1161 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1162 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1163 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1164 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1165 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1166 } else {
1167 snd_BUG();
1168 }
1169#else
1170 substream->ops = &snd_cs46xx_playback_indirect_ops;
1171#endif
1172
1173 }
1174
1175#ifdef CONFIG_SND_CS46XX_NEW_DSP
1176 mutex_unlock(&chip->spos_mutex);
1177#endif
1178
1179 return 0;
1180}
1181
1182static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1183{
1184 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1185 struct snd_pcm_runtime *runtime = substream->runtime;
1186 struct snd_cs46xx_pcm *cpcm;
1187
1188 cpcm = runtime->private_data;
1189
1190 /* if play_back open fails, then this function
1191 is called and cpcm can actually be NULL here */
1192 if (!cpcm) return -ENXIO;
1193
1194 if (runtime->dma_area != cpcm->hw_buf.area)
1195 snd_pcm_lib_free_pages(substream);
1196
1197 runtime->dma_area = NULL;
1198 runtime->dma_addr = 0;
1199 runtime->dma_bytes = 0;
1200
1201 return 0;
1202}
1203
1204static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1205{
1206 unsigned int tmp;
1207 unsigned int pfie;
1208 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1209 struct snd_pcm_runtime *runtime = substream->runtime;
1210 struct snd_cs46xx_pcm *cpcm;
1211
1212 cpcm = runtime->private_data;
1213
1214#ifdef CONFIG_SND_CS46XX_NEW_DSP
1215 if (snd_BUG_ON(!cpcm->pcm_channel))
1216 return -ENXIO;
1217
1218 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1219 pfie &= ~0x0000f03f;
1220#else
1221 /* old dsp */
1222 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1223 pfie &= ~0x0000f03f;
1224#endif
1225
1226 cpcm->shift = 2;
1227 /* if to convert from stereo to mono */
1228 if (runtime->channels == 1) {
1229 cpcm->shift--;
1230 pfie |= 0x00002000;
1231 }
1232 /* if to convert from 8 bit to 16 bit */
1233 if (snd_pcm_format_width(runtime->format) == 8) {
1234 cpcm->shift--;
1235 pfie |= 0x00001000;
1236 }
1237 /* if to convert to unsigned */
1238 if (snd_pcm_format_unsigned(runtime->format))
1239 pfie |= 0x00008000;
1240
1241 /* Never convert byte order when sample stream is 8 bit */
1242 if (snd_pcm_format_width(runtime->format) != 8) {
1243 /* convert from big endian to little endian */
1244 if (snd_pcm_format_big_endian(runtime->format))
1245 pfie |= 0x00004000;
1246 }
1247
1248 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1249 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1250 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1251
1252#ifdef CONFIG_SND_CS46XX_NEW_DSP
1253
1254 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1255 tmp &= ~0x000003ff;
1256 tmp |= (4 << cpcm->shift) - 1;
1257 /* playback transaction count register */
1258 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1259
1260 /* playback format && interrupt enable */
1261 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1262#else
1263 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1264 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1265 tmp &= ~0x000003ff;
1266 tmp |= (4 << cpcm->shift) - 1;
1267 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1268 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1269 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1270#endif
1271
1272 return 0;
1273}
1274
1275static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1276 struct snd_pcm_hw_params *hw_params)
1277{
1278 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1279 struct snd_pcm_runtime *runtime = substream->runtime;
1280 int err;
1281
1282#ifdef CONFIG_SND_CS46XX_NEW_DSP
1283 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1284#endif
1285 if (runtime->periods == CS46XX_FRAGS) {
1286 if (runtime->dma_area != chip->capt.hw_buf.area)
1287 snd_pcm_lib_free_pages(substream);
1288 runtime->dma_area = chip->capt.hw_buf.area;
1289 runtime->dma_addr = chip->capt.hw_buf.addr;
1290 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1291 substream->ops = &snd_cs46xx_capture_ops;
1292 } else {
1293 if (runtime->dma_area == chip->capt.hw_buf.area) {
1294 runtime->dma_area = NULL;
1295 runtime->dma_addr = 0;
1296 runtime->dma_bytes = 0;
1297 }
1298 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1299 return err;
1300 substream->ops = &snd_cs46xx_capture_indirect_ops;
1301 }
1302
1303 return 0;
1304}
1305
1306static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1307{
1308 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1309 struct snd_pcm_runtime *runtime = substream->runtime;
1310
1311 if (runtime->dma_area != chip->capt.hw_buf.area)
1312 snd_pcm_lib_free_pages(substream);
1313 runtime->dma_area = NULL;
1314 runtime->dma_addr = 0;
1315 runtime->dma_bytes = 0;
1316
1317 return 0;
1318}
1319
1320static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1321{
1322 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1323 struct snd_pcm_runtime *runtime = substream->runtime;
1324
1325 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1326 chip->capt.shift = 2;
1327 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1328 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1329 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1330 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1331
1332 return 0;
1333}
1334
1335static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1336{
1337 struct snd_cs46xx *chip = dev_id;
1338 u32 status1;
1339#ifdef CONFIG_SND_CS46XX_NEW_DSP
1340 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1341 u32 status2;
1342 int i;
1343 struct snd_cs46xx_pcm *cpcm = NULL;
1344#endif
1345
1346 /*
1347 * Read the Interrupt Status Register to clear the interrupt
1348 */
1349 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1350 if ((status1 & 0x7fffffff) == 0) {
1351 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1352 return IRQ_NONE;
1353 }
1354
1355#ifdef CONFIG_SND_CS46XX_NEW_DSP
1356 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1357
1358 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1359 if (i <= 15) {
1360 if ( status1 & (1 << i) ) {
1361 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1362 if (chip->capt.substream)
1363 snd_pcm_period_elapsed(chip->capt.substream);
1364 } else {
1365 if (ins->pcm_channels[i].active &&
1366 ins->pcm_channels[i].private_data &&
1367 !ins->pcm_channels[i].unlinked) {
1368 cpcm = ins->pcm_channels[i].private_data;
1369 snd_pcm_period_elapsed(cpcm->substream);
1370 }
1371 }
1372 }
1373 } else {
1374 if ( status2 & (1 << (i - 16))) {
1375 if (ins->pcm_channels[i].active &&
1376 ins->pcm_channels[i].private_data &&
1377 !ins->pcm_channels[i].unlinked) {
1378 cpcm = ins->pcm_channels[i].private_data;
1379 snd_pcm_period_elapsed(cpcm->substream);
1380 }
1381 }
1382 }
1383 }
1384
1385#else
1386 /* old dsp */
1387 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1388 if (chip->playback_pcm->substream)
1389 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1390 }
1391 if ((status1 & HISR_VC1) && chip->pcm) {
1392 if (chip->capt.substream)
1393 snd_pcm_period_elapsed(chip->capt.substream);
1394 }
1395#endif
1396
1397 if ((status1 & HISR_MIDI) && chip->rmidi) {
1398 unsigned char c;
1399
1400 spin_lock(&chip->reg_lock);
1401 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1402 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1403 if ((chip->midcr & MIDCR_RIE) == 0)
1404 continue;
1405 snd_rawmidi_receive(chip->midi_input, &c, 1);
1406 }
1407 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1408 if ((chip->midcr & MIDCR_TIE) == 0)
1409 break;
1410 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1411 chip->midcr &= ~MIDCR_TIE;
1412 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1413 break;
1414 }
1415 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1416 }
1417 spin_unlock(&chip->reg_lock);
1418 }
1419 /*
1420 * EOI to the PCI part....reenables interrupts
1421 */
1422 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1423
1424 return IRQ_HANDLED;
1425}
1426
1427static const struct snd_pcm_hardware snd_cs46xx_playback =
1428{
1429 .info = (SNDRV_PCM_INFO_MMAP |
1430 SNDRV_PCM_INFO_INTERLEAVED |
1431 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1432 /*SNDRV_PCM_INFO_RESUME*/ |
1433 SNDRV_PCM_INFO_SYNC_APPLPTR),
1434 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1435 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1436 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1437 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1438 .rate_min = 5500,
1439 .rate_max = 48000,
1440 .channels_min = 1,
1441 .channels_max = 2,
1442 .buffer_bytes_max = (256 * 1024),
1443 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1444 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1445 .periods_min = CS46XX_FRAGS,
1446 .periods_max = 1024,
1447 .fifo_size = 0,
1448};
1449
1450static const struct snd_pcm_hardware snd_cs46xx_capture =
1451{
1452 .info = (SNDRV_PCM_INFO_MMAP |
1453 SNDRV_PCM_INFO_INTERLEAVED |
1454 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1455 /*SNDRV_PCM_INFO_RESUME*/ |
1456 SNDRV_PCM_INFO_SYNC_APPLPTR),
1457 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1458 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1459 .rate_min = 5500,
1460 .rate_max = 48000,
1461 .channels_min = 2,
1462 .channels_max = 2,
1463 .buffer_bytes_max = (256 * 1024),
1464 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1465 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1466 .periods_min = CS46XX_FRAGS,
1467 .periods_max = 1024,
1468 .fifo_size = 0,
1469};
1470
1471#ifdef CONFIG_SND_CS46XX_NEW_DSP
1472
1473static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1474
1475static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1476 .count = ARRAY_SIZE(period_sizes),
1477 .list = period_sizes,
1478 .mask = 0
1479};
1480
1481#endif
1482
1483static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1484{
1485 kfree(runtime->private_data);
1486}
1487
1488static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1489{
1490 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1491 struct snd_cs46xx_pcm * cpcm;
1492 struct snd_pcm_runtime *runtime = substream->runtime;
1493
1494 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1495 if (cpcm == NULL)
1496 return -ENOMEM;
1497 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1498 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1499 kfree(cpcm);
1500 return -ENOMEM;
1501 }
1502
1503 runtime->hw = snd_cs46xx_playback;
1504 runtime->private_data = cpcm;
1505 runtime->private_free = snd_cs46xx_pcm_free_substream;
1506
1507 cpcm->substream = substream;
1508#ifdef CONFIG_SND_CS46XX_NEW_DSP
1509 mutex_lock(&chip->spos_mutex);
1510 cpcm->pcm_channel = NULL;
1511 cpcm->pcm_channel_id = pcm_channel_id;
1512
1513
1514 snd_pcm_hw_constraint_list(runtime, 0,
1515 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1516 &hw_constraints_period_sizes);
1517
1518 mutex_unlock(&chip->spos_mutex);
1519#else
1520 chip->playback_pcm = cpcm; /* HACK */
1521#endif
1522
1523 if (chip->accept_valid)
1524 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1525 chip->active_ctrl(chip, 1);
1526
1527 return 0;
1528}
1529
1530static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1531{
1532 dev_dbg(substream->pcm->card->dev, "open front channel\n");
1533 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1534}
1535
1536#ifdef CONFIG_SND_CS46XX_NEW_DSP
1537static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1538{
1539 dev_dbg(substream->pcm->card->dev, "open rear channel\n");
1540 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1541}
1542
1543static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1544{
1545 dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n");
1546 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1547}
1548
1549static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1550{
1551 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1552
1553 dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1554
1555 mutex_lock(&chip->spos_mutex);
1556 cs46xx_iec958_pre_open (chip);
1557 mutex_unlock(&chip->spos_mutex);
1558
1559 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1560}
1561
1562static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1563
1564static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1565{
1566 int err;
1567 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1568
1569 dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1570
1571 err = snd_cs46xx_playback_close(substream);
1572
1573 mutex_lock(&chip->spos_mutex);
1574 cs46xx_iec958_post_close (chip);
1575 mutex_unlock(&chip->spos_mutex);
1576
1577 return err;
1578}
1579#endif
1580
1581static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1582{
1583 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1584
1585 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1586 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1587 return -ENOMEM;
1588 chip->capt.substream = substream;
1589 substream->runtime->hw = snd_cs46xx_capture;
1590
1591 if (chip->accept_valid)
1592 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1593
1594 chip->active_ctrl(chip, 1);
1595
1596#ifdef CONFIG_SND_CS46XX_NEW_DSP
1597 snd_pcm_hw_constraint_list(substream->runtime, 0,
1598 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1599 &hw_constraints_period_sizes);
1600#endif
1601 return 0;
1602}
1603
1604static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1605{
1606 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1607 struct snd_pcm_runtime *runtime = substream->runtime;
1608 struct snd_cs46xx_pcm * cpcm;
1609
1610 cpcm = runtime->private_data;
1611
1612 /* when playback_open fails, then cpcm can be NULL */
1613 if (!cpcm) return -ENXIO;
1614
1615#ifdef CONFIG_SND_CS46XX_NEW_DSP
1616 mutex_lock(&chip->spos_mutex);
1617 if (cpcm->pcm_channel) {
1618 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1619 cpcm->pcm_channel = NULL;
1620 }
1621 mutex_unlock(&chip->spos_mutex);
1622#else
1623 chip->playback_pcm = NULL;
1624#endif
1625
1626 cpcm->substream = NULL;
1627 snd_dma_free_pages(&cpcm->hw_buf);
1628 chip->active_ctrl(chip, -1);
1629
1630 return 0;
1631}
1632
1633static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1634{
1635 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1636
1637 chip->capt.substream = NULL;
1638 snd_dma_free_pages(&chip->capt.hw_buf);
1639 chip->active_ctrl(chip, -1);
1640
1641 return 0;
1642}
1643
1644#ifdef CONFIG_SND_CS46XX_NEW_DSP
1645static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1646 .open = snd_cs46xx_playback_open_rear,
1647 .close = snd_cs46xx_playback_close,
1648 .hw_params = snd_cs46xx_playback_hw_params,
1649 .hw_free = snd_cs46xx_playback_hw_free,
1650 .prepare = snd_cs46xx_playback_prepare,
1651 .trigger = snd_cs46xx_playback_trigger,
1652 .pointer = snd_cs46xx_playback_direct_pointer,
1653};
1654
1655static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1656 .open = snd_cs46xx_playback_open_rear,
1657 .close = snd_cs46xx_playback_close,
1658 .hw_params = snd_cs46xx_playback_hw_params,
1659 .hw_free = snd_cs46xx_playback_hw_free,
1660 .prepare = snd_cs46xx_playback_prepare,
1661 .trigger = snd_cs46xx_playback_trigger,
1662 .pointer = snd_cs46xx_playback_indirect_pointer,
1663 .ack = snd_cs46xx_playback_transfer,
1664};
1665
1666static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1667 .open = snd_cs46xx_playback_open_clfe,
1668 .close = snd_cs46xx_playback_close,
1669 .hw_params = snd_cs46xx_playback_hw_params,
1670 .hw_free = snd_cs46xx_playback_hw_free,
1671 .prepare = snd_cs46xx_playback_prepare,
1672 .trigger = snd_cs46xx_playback_trigger,
1673 .pointer = snd_cs46xx_playback_direct_pointer,
1674};
1675
1676static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1677 .open = snd_cs46xx_playback_open_clfe,
1678 .close = snd_cs46xx_playback_close,
1679 .hw_params = snd_cs46xx_playback_hw_params,
1680 .hw_free = snd_cs46xx_playback_hw_free,
1681 .prepare = snd_cs46xx_playback_prepare,
1682 .trigger = snd_cs46xx_playback_trigger,
1683 .pointer = snd_cs46xx_playback_indirect_pointer,
1684 .ack = snd_cs46xx_playback_transfer,
1685};
1686
1687static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1688 .open = snd_cs46xx_playback_open_iec958,
1689 .close = snd_cs46xx_playback_close_iec958,
1690 .hw_params = snd_cs46xx_playback_hw_params,
1691 .hw_free = snd_cs46xx_playback_hw_free,
1692 .prepare = snd_cs46xx_playback_prepare,
1693 .trigger = snd_cs46xx_playback_trigger,
1694 .pointer = snd_cs46xx_playback_direct_pointer,
1695};
1696
1697static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1698 .open = snd_cs46xx_playback_open_iec958,
1699 .close = snd_cs46xx_playback_close_iec958,
1700 .hw_params = snd_cs46xx_playback_hw_params,
1701 .hw_free = snd_cs46xx_playback_hw_free,
1702 .prepare = snd_cs46xx_playback_prepare,
1703 .trigger = snd_cs46xx_playback_trigger,
1704 .pointer = snd_cs46xx_playback_indirect_pointer,
1705 .ack = snd_cs46xx_playback_transfer,
1706};
1707
1708#endif
1709
1710static const struct snd_pcm_ops snd_cs46xx_playback_ops = {
1711 .open = snd_cs46xx_playback_open,
1712 .close = snd_cs46xx_playback_close,
1713 .hw_params = snd_cs46xx_playback_hw_params,
1714 .hw_free = snd_cs46xx_playback_hw_free,
1715 .prepare = snd_cs46xx_playback_prepare,
1716 .trigger = snd_cs46xx_playback_trigger,
1717 .pointer = snd_cs46xx_playback_direct_pointer,
1718};
1719
1720static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1721 .open = snd_cs46xx_playback_open,
1722 .close = snd_cs46xx_playback_close,
1723 .hw_params = snd_cs46xx_playback_hw_params,
1724 .hw_free = snd_cs46xx_playback_hw_free,
1725 .prepare = snd_cs46xx_playback_prepare,
1726 .trigger = snd_cs46xx_playback_trigger,
1727 .pointer = snd_cs46xx_playback_indirect_pointer,
1728 .ack = snd_cs46xx_playback_transfer,
1729};
1730
1731static const struct snd_pcm_ops snd_cs46xx_capture_ops = {
1732 .open = snd_cs46xx_capture_open,
1733 .close = snd_cs46xx_capture_close,
1734 .hw_params = snd_cs46xx_capture_hw_params,
1735 .hw_free = snd_cs46xx_capture_hw_free,
1736 .prepare = snd_cs46xx_capture_prepare,
1737 .trigger = snd_cs46xx_capture_trigger,
1738 .pointer = snd_cs46xx_capture_direct_pointer,
1739};
1740
1741static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1742 .open = snd_cs46xx_capture_open,
1743 .close = snd_cs46xx_capture_close,
1744 .hw_params = snd_cs46xx_capture_hw_params,
1745 .hw_free = snd_cs46xx_capture_hw_free,
1746 .prepare = snd_cs46xx_capture_prepare,
1747 .trigger = snd_cs46xx_capture_trigger,
1748 .pointer = snd_cs46xx_capture_indirect_pointer,
1749 .ack = snd_cs46xx_capture_transfer,
1750};
1751
1752#ifdef CONFIG_SND_CS46XX_NEW_DSP
1753#define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1754#else
1755#define MAX_PLAYBACK_CHANNELS 1
1756#endif
1757
1758int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1759{
1760 struct snd_pcm *pcm;
1761 int err;
1762
1763 if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1764 return err;
1765
1766 pcm->private_data = chip;
1767
1768 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1769 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1770
1771 /* global setup */
1772 pcm->info_flags = 0;
1773 strcpy(pcm->name, "CS46xx");
1774 chip->pcm = pcm;
1775
1776 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1777 &chip->pci->dev,
1778 64*1024, 256*1024);
1779
1780 return 0;
1781}
1782
1783
1784#ifdef CONFIG_SND_CS46XX_NEW_DSP
1785int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1786{
1787 struct snd_pcm *pcm;
1788 int err;
1789
1790 if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1791 return err;
1792
1793 pcm->private_data = chip;
1794
1795 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1796
1797 /* global setup */
1798 pcm->info_flags = 0;
1799 strcpy(pcm->name, "CS46xx - Rear");
1800 chip->pcm_rear = pcm;
1801
1802 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1803 &chip->pci->dev,
1804 64*1024, 256*1024);
1805
1806 return 0;
1807}
1808
1809int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1810{
1811 struct snd_pcm *pcm;
1812 int err;
1813
1814 if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1815 return err;
1816
1817 pcm->private_data = chip;
1818
1819 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1820
1821 /* global setup */
1822 pcm->info_flags = 0;
1823 strcpy(pcm->name, "CS46xx - Center LFE");
1824 chip->pcm_center_lfe = pcm;
1825
1826 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1827 &chip->pci->dev,
1828 64*1024, 256*1024);
1829
1830 return 0;
1831}
1832
1833int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1834{
1835 struct snd_pcm *pcm;
1836 int err;
1837
1838 if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1839 return err;
1840
1841 pcm->private_data = chip;
1842
1843 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1844
1845 /* global setup */
1846 pcm->info_flags = 0;
1847 strcpy(pcm->name, "CS46xx - IEC958");
1848 chip->pcm_iec958 = pcm;
1849
1850 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1851 &chip->pci->dev,
1852 64*1024, 256*1024);
1853
1854 return 0;
1855}
1856#endif
1857
1858/*
1859 * Mixer routines
1860 */
1861static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1862{
1863 struct snd_cs46xx *chip = bus->private_data;
1864
1865 chip->ac97_bus = NULL;
1866}
1867
1868static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1869{
1870 struct snd_cs46xx *chip = ac97->private_data;
1871
1872 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1873 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1874 return;
1875
1876 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1877 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1878 chip->eapd_switch = NULL;
1879 }
1880 else
1881 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1882}
1883
1884static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1885 struct snd_ctl_elem_info *uinfo)
1886{
1887 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1888 uinfo->count = 2;
1889 uinfo->value.integer.min = 0;
1890 uinfo->value.integer.max = 0x7fff;
1891 return 0;
1892}
1893
1894static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1895{
1896 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1897 int reg = kcontrol->private_value;
1898 unsigned int val = snd_cs46xx_peek(chip, reg);
1899 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1900 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1901 return 0;
1902}
1903
1904static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1905{
1906 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1907 int reg = kcontrol->private_value;
1908 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1909 (0xffff - ucontrol->value.integer.value[1]));
1910 unsigned int old = snd_cs46xx_peek(chip, reg);
1911 int change = (old != val);
1912
1913 if (change) {
1914 snd_cs46xx_poke(chip, reg, val);
1915 }
1916
1917 return change;
1918}
1919
1920#ifdef CONFIG_SND_CS46XX_NEW_DSP
1921
1922static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1923{
1924 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1925
1926 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1927 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1928
1929 return 0;
1930}
1931
1932static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1933{
1934 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1935 int change = 0;
1936
1937 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1938 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1939 cs46xx_dsp_set_dac_volume(chip,
1940 ucontrol->value.integer.value[0],
1941 ucontrol->value.integer.value[1]);
1942 change = 1;
1943 }
1944
1945 return change;
1946}
1947
1948#if 0
1949static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1950{
1951 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1952
1953 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1954 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1955 return 0;
1956}
1957
1958static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1959{
1960 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1961 int change = 0;
1962
1963 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1964 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1965 cs46xx_dsp_set_iec958_volume (chip,
1966 ucontrol->value.integer.value[0],
1967 ucontrol->value.integer.value[1]);
1968 change = 1;
1969 }
1970
1971 return change;
1972}
1973#endif
1974
1975#define snd_mixer_boolean_info snd_ctl_boolean_mono_info
1976
1977static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1978 struct snd_ctl_elem_value *ucontrol)
1979{
1980 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1981 int reg = kcontrol->private_value;
1982
1983 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1984 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1985 else
1986 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1987
1988 return 0;
1989}
1990
1991static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
1992 struct snd_ctl_elem_value *ucontrol)
1993{
1994 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1995 int change, res;
1996
1997 switch (kcontrol->private_value) {
1998 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1999 mutex_lock(&chip->spos_mutex);
2000 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
2001 if (ucontrol->value.integer.value[0] && !change)
2002 cs46xx_dsp_enable_spdif_out(chip);
2003 else if (change && !ucontrol->value.integer.value[0])
2004 cs46xx_dsp_disable_spdif_out(chip);
2005
2006 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
2007 mutex_unlock(&chip->spos_mutex);
2008 break;
2009 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
2010 change = chip->dsp_spos_instance->spdif_status_in;
2011 if (ucontrol->value.integer.value[0] && !change) {
2012 cs46xx_dsp_enable_spdif_in(chip);
2013 /* restore volume */
2014 }
2015 else if (change && !ucontrol->value.integer.value[0])
2016 cs46xx_dsp_disable_spdif_in(chip);
2017
2018 res = (change != chip->dsp_spos_instance->spdif_status_in);
2019 break;
2020 default:
2021 res = -EINVAL;
2022 snd_BUG(); /* should never happen ... */
2023 }
2024
2025 return res;
2026}
2027
2028static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
2029 struct snd_ctl_elem_value *ucontrol)
2030{
2031 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2032 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2033
2034 if (ins->adc_input != NULL)
2035 ucontrol->value.integer.value[0] = 1;
2036 else
2037 ucontrol->value.integer.value[0] = 0;
2038
2039 return 0;
2040}
2041
2042static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
2043 struct snd_ctl_elem_value *ucontrol)
2044{
2045 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2046 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2047 int change = 0;
2048
2049 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2050 cs46xx_dsp_enable_adc_capture(chip);
2051 change = 1;
2052 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2053 cs46xx_dsp_disable_adc_capture(chip);
2054 change = 1;
2055 }
2056 return change;
2057}
2058
2059static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
2060 struct snd_ctl_elem_value *ucontrol)
2061{
2062 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2063 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2064
2065 if (ins->pcm_input != NULL)
2066 ucontrol->value.integer.value[0] = 1;
2067 else
2068 ucontrol->value.integer.value[0] = 0;
2069
2070 return 0;
2071}
2072
2073
2074static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
2075 struct snd_ctl_elem_value *ucontrol)
2076{
2077 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2078 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2079 int change = 0;
2080
2081 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2082 cs46xx_dsp_enable_pcm_capture(chip);
2083 change = 1;
2084 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2085 cs46xx_dsp_disable_pcm_capture(chip);
2086 change = 1;
2087 }
2088
2089 return change;
2090}
2091
2092static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
2093 struct snd_ctl_elem_value *ucontrol)
2094{
2095 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2096
2097 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2098
2099 if (val1 & EGPIODR_GPOE0)
2100 ucontrol->value.integer.value[0] = 1;
2101 else
2102 ucontrol->value.integer.value[0] = 0;
2103
2104 return 0;
2105}
2106
2107/*
2108 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2109 */
2110static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
2111 struct snd_ctl_elem_value *ucontrol)
2112{
2113 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2114 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2115 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2116
2117 if (ucontrol->value.integer.value[0]) {
2118 /* optical is default */
2119 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2120 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
2121 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2122 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2123 } else {
2124 /* coaxial */
2125 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
2126 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2127 }
2128
2129 /* checking diff from the EGPIO direction register
2130 should be enough */
2131 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2132}
2133
2134
2135static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2136{
2137 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2138 uinfo->count = 1;
2139 return 0;
2140}
2141
2142static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2143 struct snd_ctl_elem_value *ucontrol)
2144{
2145 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2146 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2147
2148 mutex_lock(&chip->spos_mutex);
2149 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2150 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2151 ucontrol->value.iec958.status[2] = 0;
2152 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2153 mutex_unlock(&chip->spos_mutex);
2154
2155 return 0;
2156}
2157
2158static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2159 struct snd_ctl_elem_value *ucontrol)
2160{
2161 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2162 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2163 unsigned int val;
2164 int change;
2165
2166 mutex_lock(&chip->spos_mutex);
2167 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2168 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2169 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2170 /* left and right validity bit */
2171 (1 << 13) | (1 << 12);
2172
2173
2174 change = (unsigned int)ins->spdif_csuv_default != val;
2175 ins->spdif_csuv_default = val;
2176
2177 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2178 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2179
2180 mutex_unlock(&chip->spos_mutex);
2181
2182 return change;
2183}
2184
2185static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2186 struct snd_ctl_elem_value *ucontrol)
2187{
2188 ucontrol->value.iec958.status[0] = 0xff;
2189 ucontrol->value.iec958.status[1] = 0xff;
2190 ucontrol->value.iec958.status[2] = 0x00;
2191 ucontrol->value.iec958.status[3] = 0xff;
2192 return 0;
2193}
2194
2195static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2196 struct snd_ctl_elem_value *ucontrol)
2197{
2198 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2199 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2200
2201 mutex_lock(&chip->spos_mutex);
2202 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2203 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2204 ucontrol->value.iec958.status[2] = 0;
2205 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2206 mutex_unlock(&chip->spos_mutex);
2207
2208 return 0;
2209}
2210
2211static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2212 struct snd_ctl_elem_value *ucontrol)
2213{
2214 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2215 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2216 unsigned int val;
2217 int change;
2218
2219 mutex_lock(&chip->spos_mutex);
2220 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2221 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2222 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2223 /* left and right validity bit */
2224 (1 << 13) | (1 << 12);
2225
2226
2227 change = ins->spdif_csuv_stream != val;
2228 ins->spdif_csuv_stream = val;
2229
2230 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2231 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2232
2233 mutex_unlock(&chip->spos_mutex);
2234
2235 return change;
2236}
2237
2238#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2239
2240
2241static const struct snd_kcontrol_new snd_cs46xx_controls[] = {
2242{
2243 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2244 .name = "DAC Volume",
2245 .info = snd_cs46xx_vol_info,
2246#ifndef CONFIG_SND_CS46XX_NEW_DSP
2247 .get = snd_cs46xx_vol_get,
2248 .put = snd_cs46xx_vol_put,
2249 .private_value = BA1_PVOL,
2250#else
2251 .get = snd_cs46xx_vol_dac_get,
2252 .put = snd_cs46xx_vol_dac_put,
2253#endif
2254},
2255
2256{
2257 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2258 .name = "ADC Volume",
2259 .info = snd_cs46xx_vol_info,
2260 .get = snd_cs46xx_vol_get,
2261 .put = snd_cs46xx_vol_put,
2262#ifndef CONFIG_SND_CS46XX_NEW_DSP
2263 .private_value = BA1_CVOL,
2264#else
2265 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2266#endif
2267},
2268#ifdef CONFIG_SND_CS46XX_NEW_DSP
2269{
2270 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2271 .name = "ADC Capture Switch",
2272 .info = snd_mixer_boolean_info,
2273 .get = snd_cs46xx_adc_capture_get,
2274 .put = snd_cs46xx_adc_capture_put
2275},
2276{
2277 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2278 .name = "DAC Capture Switch",
2279 .info = snd_mixer_boolean_info,
2280 .get = snd_cs46xx_pcm_capture_get,
2281 .put = snd_cs46xx_pcm_capture_put
2282},
2283{
2284 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2285 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2286 .info = snd_mixer_boolean_info,
2287 .get = snd_cs46xx_iec958_get,
2288 .put = snd_cs46xx_iec958_put,
2289 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2290},
2291{
2292 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2293 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2294 .info = snd_mixer_boolean_info,
2295 .get = snd_cs46xx_iec958_get,
2296 .put = snd_cs46xx_iec958_put,
2297 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2298},
2299#if 0
2300/* Input IEC958 volume does not work for the moment. (Benny) */
2301{
2302 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2303 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2304 .info = snd_cs46xx_vol_info,
2305 .get = snd_cs46xx_vol_iec958_get,
2306 .put = snd_cs46xx_vol_iec958_put,
2307 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2308},
2309#endif
2310{
2311 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2312 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2313 .info = snd_cs46xx_spdif_info,
2314 .get = snd_cs46xx_spdif_default_get,
2315 .put = snd_cs46xx_spdif_default_put,
2316},
2317{
2318 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2319 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2320 .info = snd_cs46xx_spdif_info,
2321 .get = snd_cs46xx_spdif_mask_get,
2322 .access = SNDRV_CTL_ELEM_ACCESS_READ
2323},
2324{
2325 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2326 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2327 .info = snd_cs46xx_spdif_info,
2328 .get = snd_cs46xx_spdif_stream_get,
2329 .put = snd_cs46xx_spdif_stream_put
2330},
2331
2332#endif
2333};
2334
2335#ifdef CONFIG_SND_CS46XX_NEW_DSP
2336/* set primary cs4294 codec into Extended Audio Mode */
2337static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2338 struct snd_ctl_elem_value *ucontrol)
2339{
2340 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2341 unsigned short val;
2342 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2343 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2344 return 0;
2345}
2346
2347static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2348 struct snd_ctl_elem_value *ucontrol)
2349{
2350 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2351 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2352 AC97_CSR_ACMODE, 0x200,
2353 ucontrol->value.integer.value[0] ? 0 : 0x200);
2354}
2355
2356static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2357 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2358 .name = "Duplicate Front",
2359 .info = snd_mixer_boolean_info,
2360 .get = snd_cs46xx_front_dup_get,
2361 .put = snd_cs46xx_front_dup_put,
2362};
2363#endif
2364
2365#ifdef CONFIG_SND_CS46XX_NEW_DSP
2366/* Only available on the Hercules Game Theater XP soundcard */
2367static const struct snd_kcontrol_new snd_hercules_controls[] = {
2368{
2369 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2370 .name = "Optical/Coaxial SPDIF Input Switch",
2371 .info = snd_mixer_boolean_info,
2372 .get = snd_herc_spdif_select_get,
2373 .put = snd_herc_spdif_select_put,
2374},
2375};
2376
2377
2378static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2379{
2380 unsigned long end_time;
2381 int err;
2382
2383 /* reset to defaults */
2384 snd_ac97_write(ac97, AC97_RESET, 0);
2385
2386 /* set the desired CODEC mode */
2387 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2388 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0);
2389 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
2390 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2391 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3);
2392 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
2393 } else {
2394 snd_BUG(); /* should never happen ... */
2395 }
2396
2397 udelay(50);
2398
2399 /* it's necessary to wait awhile until registers are accessible after RESET */
2400 /* because the PCM or MASTER volume registers can be modified, */
2401 /* the REC_GAIN register is used for tests */
2402 end_time = jiffies + HZ;
2403 do {
2404 unsigned short ext_mid;
2405
2406 /* use preliminary reads to settle the communication */
2407 snd_ac97_read(ac97, AC97_RESET);
2408 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2409 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2410 /* modem? */
2411 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2412 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2413 return;
2414
2415 /* test if we can write to the record gain volume register */
2416 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
2417 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2418 return;
2419
2420 msleep(10);
2421 } while (time_after_eq(end_time, jiffies));
2422
2423 dev_err(ac97->bus->card->dev,
2424 "CS46xx secondary codec doesn't respond!\n");
2425}
2426#endif
2427
2428static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2429{
2430 int idx, err;
2431 struct snd_ac97_template ac97;
2432
2433 memset(&ac97, 0, sizeof(ac97));
2434 ac97.private_data = chip;
2435 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2436 ac97.num = codec;
2437 if (chip->amplifier_ctrl == amp_voyetra)
2438 ac97.scaps = AC97_SCAP_INV_EAPD;
2439
2440 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2441 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2442 udelay(10);
2443 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2444 dev_dbg(chip->card->dev,
2445 "secondary codec not present\n");
2446 return -ENXIO;
2447 }
2448 }
2449
2450 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2451 for (idx = 0; idx < 100; ++idx) {
2452 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2453 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2454 return err;
2455 }
2456 msleep(10);
2457 }
2458 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
2459 return -ENXIO;
2460}
2461
2462int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2463{
2464 struct snd_card *card = chip->card;
2465 struct snd_ctl_elem_id id;
2466 int err;
2467 unsigned int idx;
2468 static const struct snd_ac97_bus_ops ops = {
2469#ifdef CONFIG_SND_CS46XX_NEW_DSP
2470 .reset = snd_cs46xx_codec_reset,
2471#endif
2472 .write = snd_cs46xx_ac97_write,
2473 .read = snd_cs46xx_ac97_read,
2474 };
2475
2476 /* detect primary codec */
2477 chip->nr_ac97_codecs = 0;
2478 dev_dbg(chip->card->dev, "detecting primary codec\n");
2479 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2480 return err;
2481 chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2482
2483 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2484 return -ENXIO;
2485 chip->nr_ac97_codecs = 1;
2486
2487#ifdef CONFIG_SND_CS46XX_NEW_DSP
2488 dev_dbg(chip->card->dev, "detecting secondary codec\n");
2489 /* try detect a secondary codec */
2490 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2491 chip->nr_ac97_codecs = 2;
2492#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2493
2494 /* add cs4630 mixer controls */
2495 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2496 struct snd_kcontrol *kctl;
2497 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2498 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2499 kctl->id.device = spdif_device;
2500 if ((err = snd_ctl_add(card, kctl)) < 0)
2501 return err;
2502 }
2503
2504 /* get EAPD mixer switch (for voyetra hack) */
2505 memset(&id, 0, sizeof(id));
2506 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2507 strcpy(id.name, "External Amplifier");
2508 chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2509
2510#ifdef CONFIG_SND_CS46XX_NEW_DSP
2511 if (chip->nr_ac97_codecs == 1) {
2512 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2513 if ((id2 & 0xfff0) == 0x5920) { /* CS4294 and CS4298 */
2514 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2515 if (err < 0)
2516 return err;
2517 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2518 AC97_CSR_ACMODE, 0x200);
2519 }
2520 }
2521 /* do soundcard specific mixer setup */
2522 if (chip->mixer_init) {
2523 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
2524 chip->mixer_init(chip);
2525 }
2526#endif
2527
2528 /* turn on amplifier */
2529 chip->amplifier_ctrl(chip, 1);
2530
2531 return 0;
2532}
2533
2534/*
2535 * RawMIDI interface
2536 */
2537
2538static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2539{
2540 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2541 udelay(100);
2542 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2543}
2544
2545static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2546{
2547 struct snd_cs46xx *chip = substream->rmidi->private_data;
2548
2549 chip->active_ctrl(chip, 1);
2550 spin_lock_irq(&chip->reg_lock);
2551 chip->uartm |= CS46XX_MODE_INPUT;
2552 chip->midcr |= MIDCR_RXE;
2553 chip->midi_input = substream;
2554 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2555 snd_cs46xx_midi_reset(chip);
2556 } else {
2557 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2558 }
2559 spin_unlock_irq(&chip->reg_lock);
2560 return 0;
2561}
2562
2563static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2564{
2565 struct snd_cs46xx *chip = substream->rmidi->private_data;
2566
2567 spin_lock_irq(&chip->reg_lock);
2568 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2569 chip->midi_input = NULL;
2570 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2571 snd_cs46xx_midi_reset(chip);
2572 } else {
2573 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2574 }
2575 chip->uartm &= ~CS46XX_MODE_INPUT;
2576 spin_unlock_irq(&chip->reg_lock);
2577 chip->active_ctrl(chip, -1);
2578 return 0;
2579}
2580
2581static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2582{
2583 struct snd_cs46xx *chip = substream->rmidi->private_data;
2584
2585 chip->active_ctrl(chip, 1);
2586
2587 spin_lock_irq(&chip->reg_lock);
2588 chip->uartm |= CS46XX_MODE_OUTPUT;
2589 chip->midcr |= MIDCR_TXE;
2590 chip->midi_output = substream;
2591 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2592 snd_cs46xx_midi_reset(chip);
2593 } else {
2594 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2595 }
2596 spin_unlock_irq(&chip->reg_lock);
2597 return 0;
2598}
2599
2600static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2601{
2602 struct snd_cs46xx *chip = substream->rmidi->private_data;
2603
2604 spin_lock_irq(&chip->reg_lock);
2605 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2606 chip->midi_output = NULL;
2607 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2608 snd_cs46xx_midi_reset(chip);
2609 } else {
2610 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2611 }
2612 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2613 spin_unlock_irq(&chip->reg_lock);
2614 chip->active_ctrl(chip, -1);
2615 return 0;
2616}
2617
2618static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2619{
2620 unsigned long flags;
2621 struct snd_cs46xx *chip = substream->rmidi->private_data;
2622
2623 spin_lock_irqsave(&chip->reg_lock, flags);
2624 if (up) {
2625 if ((chip->midcr & MIDCR_RIE) == 0) {
2626 chip->midcr |= MIDCR_RIE;
2627 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2628 }
2629 } else {
2630 if (chip->midcr & MIDCR_RIE) {
2631 chip->midcr &= ~MIDCR_RIE;
2632 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2633 }
2634 }
2635 spin_unlock_irqrestore(&chip->reg_lock, flags);
2636}
2637
2638static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2639{
2640 unsigned long flags;
2641 struct snd_cs46xx *chip = substream->rmidi->private_data;
2642 unsigned char byte;
2643
2644 spin_lock_irqsave(&chip->reg_lock, flags);
2645 if (up) {
2646 if ((chip->midcr & MIDCR_TIE) == 0) {
2647 chip->midcr |= MIDCR_TIE;
2648 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2649 while ((chip->midcr & MIDCR_TIE) &&
2650 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2651 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2652 chip->midcr &= ~MIDCR_TIE;
2653 } else {
2654 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2655 }
2656 }
2657 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2658 }
2659 } else {
2660 if (chip->midcr & MIDCR_TIE) {
2661 chip->midcr &= ~MIDCR_TIE;
2662 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2663 }
2664 }
2665 spin_unlock_irqrestore(&chip->reg_lock, flags);
2666}
2667
2668static const struct snd_rawmidi_ops snd_cs46xx_midi_output =
2669{
2670 .open = snd_cs46xx_midi_output_open,
2671 .close = snd_cs46xx_midi_output_close,
2672 .trigger = snd_cs46xx_midi_output_trigger,
2673};
2674
2675static const struct snd_rawmidi_ops snd_cs46xx_midi_input =
2676{
2677 .open = snd_cs46xx_midi_input_open,
2678 .close = snd_cs46xx_midi_input_close,
2679 .trigger = snd_cs46xx_midi_input_trigger,
2680};
2681
2682int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
2683{
2684 struct snd_rawmidi *rmidi;
2685 int err;
2686
2687 if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2688 return err;
2689 strcpy(rmidi->name, "CS46XX");
2690 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2691 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2692 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2693 rmidi->private_data = chip;
2694 chip->rmidi = rmidi;
2695 return 0;
2696}
2697
2698
2699/*
2700 * gameport interface
2701 */
2702
2703#if IS_REACHABLE(CONFIG_GAMEPORT)
2704
2705static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2706{
2707 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2708
2709 if (snd_BUG_ON(!chip))
2710 return;
2711 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2712}
2713
2714static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2715{
2716 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2717
2718 if (snd_BUG_ON(!chip))
2719 return 0;
2720 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2721}
2722
2723static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2724{
2725 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2726 unsigned js1, js2, jst;
2727
2728 if (snd_BUG_ON(!chip))
2729 return 0;
2730
2731 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2732 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2733 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2734
2735 *buttons = (~jst >> 4) & 0x0F;
2736
2737 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2738 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2739 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2740 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2741
2742 for(jst=0;jst<4;++jst)
2743 if(axes[jst]==0xFFFF) axes[jst] = -1;
2744 return 0;
2745}
2746
2747static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2748{
2749 switch (mode) {
2750 case GAMEPORT_MODE_COOKED:
2751 return 0;
2752 case GAMEPORT_MODE_RAW:
2753 return 0;
2754 default:
2755 return -1;
2756 }
2757 return 0;
2758}
2759
2760int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2761{
2762 struct gameport *gp;
2763
2764 chip->gameport = gp = gameport_allocate_port();
2765 if (!gp) {
2766 dev_err(chip->card->dev,
2767 "cannot allocate memory for gameport\n");
2768 return -ENOMEM;
2769 }
2770
2771 gameport_set_name(gp, "CS46xx Gameport");
2772 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2773 gameport_set_dev_parent(gp, &chip->pci->dev);
2774 gameport_set_port_data(gp, chip);
2775
2776 gp->open = snd_cs46xx_gameport_open;
2777 gp->read = snd_cs46xx_gameport_read;
2778 gp->trigger = snd_cs46xx_gameport_trigger;
2779 gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2780
2781 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2782 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2783
2784 gameport_register_port(gp);
2785
2786 return 0;
2787}
2788
2789static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2790{
2791 if (chip->gameport) {
2792 gameport_unregister_port(chip->gameport);
2793 chip->gameport = NULL;
2794 }
2795}
2796#else
2797int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2798static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2799#endif /* CONFIG_GAMEPORT */
2800
2801#ifdef CONFIG_SND_PROC_FS
2802/*
2803 * proc interface
2804 */
2805
2806static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2807 void *file_private_data,
2808 struct file *file, char __user *buf,
2809 size_t count, loff_t pos)
2810{
2811 struct snd_cs46xx_region *region = entry->private_data;
2812
2813 if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2814 return -EFAULT;
2815 return count;
2816}
2817
2818static const struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2819 .read = snd_cs46xx_io_read,
2820};
2821
2822static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2823{
2824 struct snd_info_entry *entry;
2825 int idx;
2826
2827 for (idx = 0; idx < 5; idx++) {
2828 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2829 if (! snd_card_proc_new(card, region->name, &entry)) {
2830 entry->content = SNDRV_INFO_CONTENT_DATA;
2831 entry->private_data = chip;
2832 entry->c.ops = &snd_cs46xx_proc_io_ops;
2833 entry->size = region->size;
2834 entry->mode = S_IFREG | 0400;
2835 }
2836 }
2837#ifdef CONFIG_SND_CS46XX_NEW_DSP
2838 cs46xx_dsp_proc_init(card, chip);
2839#endif
2840 return 0;
2841}
2842
2843static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2844{
2845#ifdef CONFIG_SND_CS46XX_NEW_DSP
2846 cs46xx_dsp_proc_done(chip);
2847#endif
2848 return 0;
2849}
2850#else /* !CONFIG_SND_PROC_FS */
2851#define snd_cs46xx_proc_init(card, chip)
2852#define snd_cs46xx_proc_done(chip)
2853#endif
2854
2855/*
2856 * stop the h/w
2857 */
2858static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2859{
2860 unsigned int tmp;
2861
2862 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2863 tmp &= ~0x0000f03f;
2864 tmp |= 0x00000010;
2865 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2866
2867 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2868 tmp &= ~0x0000003f;
2869 tmp |= 0x00000011;
2870 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2871
2872 /*
2873 * Stop playback DMA.
2874 */
2875 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2876 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2877
2878 /*
2879 * Stop capture DMA.
2880 */
2881 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2882 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2883
2884 /*
2885 * Reset the processor.
2886 */
2887 snd_cs46xx_reset(chip);
2888
2889 snd_cs46xx_proc_stop(chip);
2890
2891 /*
2892 * Power down the PLL.
2893 */
2894 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2895
2896 /*
2897 * Turn off the Processor by turning off the software clock enable flag in
2898 * the clock control register.
2899 */
2900 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2901 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2902}
2903
2904
2905static int snd_cs46xx_free(struct snd_cs46xx *chip)
2906{
2907 int idx;
2908
2909 if (snd_BUG_ON(!chip))
2910 return -EINVAL;
2911
2912 if (chip->active_ctrl)
2913 chip->active_ctrl(chip, 1);
2914
2915 snd_cs46xx_remove_gameport(chip);
2916
2917 if (chip->amplifier_ctrl)
2918 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2919
2920 snd_cs46xx_proc_done(chip);
2921
2922 if (chip->region.idx[0].resource)
2923 snd_cs46xx_hw_stop(chip);
2924
2925 if (chip->irq >= 0)
2926 free_irq(chip->irq, chip);
2927
2928 if (chip->active_ctrl)
2929 chip->active_ctrl(chip, -chip->amplifier);
2930
2931 for (idx = 0; idx < 5; idx++) {
2932 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2933
2934 iounmap(region->remap_addr);
2935 release_and_free_resource(region->resource);
2936 }
2937
2938#ifdef CONFIG_SND_CS46XX_NEW_DSP
2939 if (chip->dsp_spos_instance) {
2940 cs46xx_dsp_spos_destroy(chip);
2941 chip->dsp_spos_instance = NULL;
2942 }
2943 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2944 free_module_desc(chip->modules[idx]);
2945#else
2946 vfree(chip->ba1);
2947#endif
2948
2949#ifdef CONFIG_PM_SLEEP
2950 kfree(chip->saved_regs);
2951#endif
2952
2953 pci_disable_device(chip->pci);
2954 kfree(chip);
2955 return 0;
2956}
2957
2958static int snd_cs46xx_dev_free(struct snd_device *device)
2959{
2960 struct snd_cs46xx *chip = device->device_data;
2961 return snd_cs46xx_free(chip);
2962}
2963
2964/*
2965 * initialize chip
2966 */
2967static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2968{
2969 int timeout;
2970
2971 /*
2972 * First, blast the clock control register to zero so that the PLL starts
2973 * out in a known state, and blast the master serial port control register
2974 * to zero so that the serial ports also start out in a known state.
2975 */
2976 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2977 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2978
2979 /*
2980 * If we are in AC97 mode, then we must set the part to a host controlled
2981 * AC-link. Otherwise, we won't be able to bring up the link.
2982 */
2983#ifdef CONFIG_SND_CS46XX_NEW_DSP
2984 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2985 SERACC_TWO_CODECS); /* 2.00 dual codecs */
2986 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2987#else
2988 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2989#endif
2990
2991 /*
2992 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2993 * spec) and then drive it high. This is done for non AC97 modes since
2994 * there might be logic external to the CS461x that uses the ARST# line
2995 * for a reset.
2996 */
2997 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2998#ifdef CONFIG_SND_CS46XX_NEW_DSP
2999 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
3000#endif
3001 udelay(50);
3002 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
3003#ifdef CONFIG_SND_CS46XX_NEW_DSP
3004 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
3005#endif
3006
3007 /*
3008 * The first thing we do here is to enable sync generation. As soon
3009 * as we start receiving bit clock, we'll start producing the SYNC
3010 * signal.
3011 */
3012 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
3013#ifdef CONFIG_SND_CS46XX_NEW_DSP
3014 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
3015#endif
3016
3017 /*
3018 * Now wait for a short while to allow the AC97 part to start
3019 * generating bit clock (so we don't try to start the PLL without an
3020 * input clock).
3021 */
3022 mdelay(10);
3023
3024 /*
3025 * Set the serial port timing configuration, so that
3026 * the clock control circuit gets its clock from the correct place.
3027 */
3028 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
3029
3030 /*
3031 * Write the selected clock control setup to the hardware. Do not turn on
3032 * SWCE yet (if requested), so that the devices clocked by the output of
3033 * PLL are not clocked until the PLL is stable.
3034 */
3035 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3036 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3037 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3038
3039 /*
3040 * Power up the PLL.
3041 */
3042 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3043
3044 /*
3045 * Wait until the PLL has stabilized.
3046 */
3047 msleep(100);
3048
3049 /*
3050 * Turn on clocking of the core so that we can setup the serial ports.
3051 */
3052 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3053
3054 /*
3055 * Enable FIFO Host Bypass
3056 */
3057 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3058
3059 /*
3060 * Fill the serial port FIFOs with silence.
3061 */
3062 snd_cs46xx_clear_serial_FIFOs(chip);
3063
3064 /*
3065 * Set the serial port FIFO pointer to the first sample in the FIFO.
3066 */
3067 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3068
3069 /*
3070 * Write the serial port configuration to the part. The master
3071 * enable bit is not set until all other values have been written.
3072 */
3073 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3074 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3075 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3076
3077
3078#ifdef CONFIG_SND_CS46XX_NEW_DSP
3079 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3080 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3081 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3082 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3083 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3084#endif
3085
3086 mdelay(5);
3087
3088
3089 /*
3090 * Wait for the codec ready signal from the AC97 codec.
3091 */
3092 timeout = 150;
3093 while (timeout-- > 0) {
3094 /*
3095 * Read the AC97 status register to see if we've seen a CODEC READY
3096 * signal from the AC97 codec.
3097 */
3098 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3099 goto ok1;
3100 msleep(10);
3101 }
3102
3103
3104 dev_err(chip->card->dev,
3105 "create - never read codec ready from AC'97\n");
3106 dev_err(chip->card->dev,
3107 "it is not probably bug, try to use CS4236 driver\n");
3108 return -EIO;
3109 ok1:
3110#ifdef CONFIG_SND_CS46XX_NEW_DSP
3111 {
3112 int count;
3113 for (count = 0; count < 150; count++) {
3114 /* First, we want to wait for a short time. */
3115 udelay(25);
3116
3117 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3118 break;
3119 }
3120
3121 /*
3122 * Make sure CODEC is READY.
3123 */
3124 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3125 dev_dbg(chip->card->dev,
3126 "never read card ready from secondary AC'97\n");
3127 }
3128#endif
3129
3130 /*
3131 * Assert the vaid frame signal so that we can start sending commands
3132 * to the AC97 codec.
3133 */
3134 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3135#ifdef CONFIG_SND_CS46XX_NEW_DSP
3136 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3137#endif
3138
3139
3140 /*
3141 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3142 * the codec is pumping ADC data across the AC-link.
3143 */
3144 timeout = 150;
3145 while (timeout-- > 0) {
3146 /*
3147 * Read the input slot valid register and see if input slots 3 and
3148 * 4 are valid yet.
3149 */
3150 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3151 goto ok2;
3152 msleep(10);
3153 }
3154
3155#ifndef CONFIG_SND_CS46XX_NEW_DSP
3156 dev_err(chip->card->dev,
3157 "create - never read ISV3 & ISV4 from AC'97\n");
3158 return -EIO;
3159#else
3160 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3161 Reloading the driver may help, if there's other soundcards
3162 with the same problem I would like to know. (Benny) */
3163
3164 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3165 dev_err(chip->card->dev,
3166 "Try reloading the ALSA driver, if you find something\n");
3167 dev_err(chip->card->dev,
3168 "broken or not working on your soundcard upon\n");
3169 dev_err(chip->card->dev,
3170 "this message please report to alsa-devel@alsa-project.org\n");
3171
3172 return -EIO;
3173#endif
3174 ok2:
3175
3176 /*
3177 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3178 * commense the transfer of digital audio data to the AC97 codec.
3179 */
3180
3181 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3182
3183
3184 /*
3185 * Power down the DAC and ADC. We will power them up (if) when we need
3186 * them.
3187 */
3188 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3189
3190 /*
3191 * Turn off the Processor by turning off the software clock enable flag in
3192 * the clock control register.
3193 */
3194 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3195 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3196
3197 return 0;
3198}
3199
3200/*
3201 * start and load DSP
3202 */
3203
3204static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3205{
3206 unsigned int tmp;
3207
3208 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3209
3210 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3211 tmp &= ~0x0000f03f;
3212 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3213
3214 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3215 tmp &= ~0x0000003f;
3216 tmp |= 0x00000001;
3217 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3218}
3219
3220int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3221{
3222 unsigned int tmp;
3223#ifdef CONFIG_SND_CS46XX_NEW_DSP
3224 int i;
3225#endif
3226 int err;
3227
3228 /*
3229 * Reset the processor.
3230 */
3231 snd_cs46xx_reset(chip);
3232 /*
3233 * Download the image to the processor.
3234 */
3235#ifdef CONFIG_SND_CS46XX_NEW_DSP
3236 for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3237 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3238 if (err < 0) {
3239 dev_err(chip->card->dev, "firmware load error [%s]\n",
3240 module_names[i]);
3241 return err;
3242 }
3243 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3244 if (err < 0) {
3245 dev_err(chip->card->dev, "image download error [%s]\n",
3246 module_names[i]);
3247 return err;
3248 }
3249 }
3250
3251 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3252 return -EIO;
3253#else
3254 err = load_firmware(chip);
3255 if (err < 0)
3256 return err;
3257
3258 /* old image */
3259 err = snd_cs46xx_download_image(chip);
3260 if (err < 0) {
3261 dev_err(chip->card->dev, "image download error\n");
3262 return err;
3263 }
3264
3265 /*
3266 * Stop playback DMA.
3267 */
3268 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3269 chip->play_ctl = tmp & 0xffff0000;
3270 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3271#endif
3272
3273 /*
3274 * Stop capture DMA.
3275 */
3276 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3277 chip->capt.ctl = tmp & 0x0000ffff;
3278 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3279
3280 mdelay(5);
3281
3282 snd_cs46xx_set_play_sample_rate(chip, 8000);
3283 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3284
3285 snd_cs46xx_proc_start(chip);
3286
3287 cs46xx_enable_stream_irqs(chip);
3288
3289#ifndef CONFIG_SND_CS46XX_NEW_DSP
3290 /* set the attenuation to 0dB */
3291 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3292 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3293#endif
3294
3295 return 0;
3296}
3297
3298
3299/*
3300 * AMP control - null AMP
3301 */
3302
3303static void amp_none(struct snd_cs46xx *chip, int change)
3304{
3305}
3306
3307#ifdef CONFIG_SND_CS46XX_NEW_DSP
3308static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3309{
3310
3311 u32 idx, valid_slots,tmp,powerdown = 0;
3312 u16 modem_power,pin_config,logic_type;
3313
3314 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
3315
3316 /*
3317 * See if the devices are powered down. If so, we must power them up first
3318 * or they will not respond.
3319 */
3320 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3321
3322 if (!(tmp & CLKCR1_SWCE)) {
3323 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3324 powerdown = 1;
3325 }
3326
3327 /*
3328 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3329 * stuff.
3330 */
3331 if(chip->nr_ac97_codecs != 2) {
3332 dev_err(chip->card->dev,
3333 "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3334 return -EINVAL;
3335 }
3336
3337 modem_power = snd_cs46xx_codec_read (chip,
3338 AC97_EXTENDED_MSTATUS,
3339 CS46XX_SECONDARY_CODEC_INDEX);
3340 modem_power &=0xFEFF;
3341
3342 snd_cs46xx_codec_write(chip,
3343 AC97_EXTENDED_MSTATUS, modem_power,
3344 CS46XX_SECONDARY_CODEC_INDEX);
3345
3346 /*
3347 * Set GPIO pin's 7 and 8 so that they are configured for output.
3348 */
3349 pin_config = snd_cs46xx_codec_read (chip,
3350 AC97_GPIO_CFG,
3351 CS46XX_SECONDARY_CODEC_INDEX);
3352 pin_config &=0x27F;
3353
3354 snd_cs46xx_codec_write(chip,
3355 AC97_GPIO_CFG, pin_config,
3356 CS46XX_SECONDARY_CODEC_INDEX);
3357
3358 /*
3359 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3360 */
3361
3362 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3363 CS46XX_SECONDARY_CODEC_INDEX);
3364 logic_type &=0x27F;
3365
3366 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3367 CS46XX_SECONDARY_CODEC_INDEX);
3368
3369 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3370 valid_slots |= 0x200;
3371 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3372
3373 if ( cs46xx_wait_for_fifo(chip,1) ) {
3374 dev_dbg(chip->card->dev, "FIFO is busy\n");
3375
3376 return -EINVAL;
3377 }
3378
3379 /*
3380 * Fill slots 12 with the correct value for the GPIO pins.
3381 */
3382 for(idx = 0x90; idx <= 0x9F; idx++) {
3383 /*
3384 * Initialize the fifo so that bits 7 and 8 are on.
3385 *
3386 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3387 * the left. 0x1800 corresponds to bits 7 and 8.
3388 */
3389 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3390
3391 /*
3392 * Wait for command to complete
3393 */
3394 if ( cs46xx_wait_for_fifo(chip,200) ) {
3395 dev_dbg(chip->card->dev,
3396 "failed waiting for FIFO at addr (%02X)\n",
3397 idx);
3398
3399 return -EINVAL;
3400 }
3401
3402 /*
3403 * Write the serial port FIFO index.
3404 */
3405 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3406
3407 /*
3408 * Tell the serial port to load the new value into the FIFO location.
3409 */
3410 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3411 }
3412
3413 /* wait for last command to complete */
3414 cs46xx_wait_for_fifo(chip,200);
3415
3416 /*
3417 * Now, if we powered up the devices, then power them back down again.
3418 * This is kinda ugly, but should never happen.
3419 */
3420 if (powerdown)
3421 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3422
3423 return 0;
3424}
3425#endif
3426
3427/*
3428 * Crystal EAPD mode
3429 */
3430
3431static void amp_voyetra(struct snd_cs46xx *chip, int change)
3432{
3433 /* Manage the EAPD bit on the Crystal 4297
3434 and the Analog AD1885 */
3435
3436#ifdef CONFIG_SND_CS46XX_NEW_DSP
3437 int old = chip->amplifier;
3438#endif
3439 int oval, val;
3440
3441 chip->amplifier += change;
3442 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3443 CS46XX_PRIMARY_CODEC_INDEX);
3444 val = oval;
3445 if (chip->amplifier) {
3446 /* Turn the EAPD amp on */
3447 val |= 0x8000;
3448 } else {
3449 /* Turn the EAPD amp off */
3450 val &= ~0x8000;
3451 }
3452 if (val != oval) {
3453 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3454 CS46XX_PRIMARY_CODEC_INDEX);
3455 if (chip->eapd_switch)
3456 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3457 &chip->eapd_switch->id);
3458 }
3459
3460#ifdef CONFIG_SND_CS46XX_NEW_DSP
3461 if (chip->amplifier && !old) {
3462 voyetra_setup_eapd_slot(chip);
3463 }
3464#endif
3465}
3466
3467static void hercules_init(struct snd_cs46xx *chip)
3468{
3469 /* default: AMP off, and SPDIF input optical */
3470 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3471 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3472}
3473
3474
3475/*
3476 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3477 */
3478static void amp_hercules(struct snd_cs46xx *chip, int change)
3479{
3480 int old = chip->amplifier;
3481 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3482 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3483
3484 chip->amplifier += change;
3485 if (chip->amplifier && !old) {
3486 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
3487
3488 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3489 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3490 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3491 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3492 } else if (old && !chip->amplifier) {
3493 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
3494 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3495 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3496 }
3497}
3498
3499static void voyetra_mixer_init (struct snd_cs46xx *chip)
3500{
3501 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
3502
3503 /* Enable SPDIF out */
3504 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3505 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3506}
3507
3508static void hercules_mixer_init (struct snd_cs46xx *chip)
3509{
3510#ifdef CONFIG_SND_CS46XX_NEW_DSP
3511 unsigned int idx;
3512 int err;
3513 struct snd_card *card = chip->card;
3514#endif
3515
3516 /* set EGPIO to default */
3517 hercules_init(chip);
3518
3519 dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
3520
3521#ifdef CONFIG_SND_CS46XX_NEW_DSP
3522 if (chip->in_suspend)
3523 return;
3524
3525 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3526 struct snd_kcontrol *kctl;
3527
3528 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3529 if ((err = snd_ctl_add(card, kctl)) < 0) {
3530 dev_err(card->dev,
3531 "failed to initialize Hercules mixer (%d)\n",
3532 err);
3533 break;
3534 }
3535 }
3536#endif
3537}
3538
3539
3540#if 0
3541/*
3542 * Untested
3543 */
3544
3545static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3546{
3547 chip->amplifier += change;
3548
3549 if (chip->amplifier) {
3550 /* Switch the GPIO pins 7 and 8 to open drain */
3551 snd_cs46xx_codec_write(chip, 0x4C,
3552 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3553 snd_cs46xx_codec_write(chip, 0x4E,
3554 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3555 /* Now wake the AMP (this might be backwards) */
3556 snd_cs46xx_codec_write(chip, 0x54,
3557 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3558 } else {
3559 snd_cs46xx_codec_write(chip, 0x54,
3560 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3561 }
3562}
3563#endif
3564
3565
3566/*
3567 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3568 * whenever we need to beat on the chip.
3569 *
3570 * The original idea and code for this hack comes from David Kaiser at
3571 * Linuxcare. Perhaps one day Crystal will document their chips well
3572 * enough to make them useful.
3573 */
3574
3575static void clkrun_hack(struct snd_cs46xx *chip, int change)
3576{
3577 u16 control, nval;
3578
3579 if (!chip->acpi_port)
3580 return;
3581
3582 chip->amplifier += change;
3583
3584 /* Read ACPI port */
3585 nval = control = inw(chip->acpi_port + 0x10);
3586
3587 /* Flip CLKRUN off while running */
3588 if (! chip->amplifier)
3589 nval |= 0x2000;
3590 else
3591 nval &= ~0x2000;
3592 if (nval != control)
3593 outw(nval, chip->acpi_port + 0x10);
3594}
3595
3596
3597/*
3598 * detect intel piix4
3599 */
3600static void clkrun_init(struct snd_cs46xx *chip)
3601{
3602 struct pci_dev *pdev;
3603 u8 pp;
3604
3605 chip->acpi_port = 0;
3606
3607 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3608 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3609 if (pdev == NULL)
3610 return; /* Not a thinkpad thats for sure */
3611
3612 /* Find the control port */
3613 pci_read_config_byte(pdev, 0x41, &pp);
3614 chip->acpi_port = pp << 8;
3615 pci_dev_put(pdev);
3616}
3617
3618
3619/*
3620 * Card subid table
3621 */
3622
3623struct cs_card_type
3624{
3625 u16 vendor;
3626 u16 id;
3627 char *name;
3628 void (*init)(struct snd_cs46xx *);
3629 void (*amp)(struct snd_cs46xx *, int);
3630 void (*active)(struct snd_cs46xx *, int);
3631 void (*mixer_init)(struct snd_cs46xx *);
3632};
3633
3634static struct cs_card_type cards[] = {
3635 {
3636 .vendor = 0x1489,
3637 .id = 0x7001,
3638 .name = "Genius Soundmaker 128 value",
3639 /* nothing special */
3640 },
3641 {
3642 .vendor = 0x5053,
3643 .id = 0x3357,
3644 .name = "Voyetra",
3645 .amp = amp_voyetra,
3646 .mixer_init = voyetra_mixer_init,
3647 },
3648 {
3649 .vendor = 0x1071,
3650 .id = 0x6003,
3651 .name = "Mitac MI6020/21",
3652 .amp = amp_voyetra,
3653 },
3654 /* Hercules Game Theatre XP */
3655 {
3656 .vendor = 0x14af, /* Guillemot Corporation */
3657 .id = 0x0050,
3658 .name = "Hercules Game Theatre XP",
3659 .amp = amp_hercules,
3660 .mixer_init = hercules_mixer_init,
3661 },
3662 {
3663 .vendor = 0x1681,
3664 .id = 0x0050,
3665 .name = "Hercules Game Theatre XP",
3666 .amp = amp_hercules,
3667 .mixer_init = hercules_mixer_init,
3668 },
3669 {
3670 .vendor = 0x1681,
3671 .id = 0x0051,
3672 .name = "Hercules Game Theatre XP",
3673 .amp = amp_hercules,
3674 .mixer_init = hercules_mixer_init,
3675
3676 },
3677 {
3678 .vendor = 0x1681,
3679 .id = 0x0052,
3680 .name = "Hercules Game Theatre XP",
3681 .amp = amp_hercules,
3682 .mixer_init = hercules_mixer_init,
3683 },
3684 {
3685 .vendor = 0x1681,
3686 .id = 0x0053,
3687 .name = "Hercules Game Theatre XP",
3688 .amp = amp_hercules,
3689 .mixer_init = hercules_mixer_init,
3690 },
3691 {
3692 .vendor = 0x1681,
3693 .id = 0x0054,
3694 .name = "Hercules Game Theatre XP",
3695 .amp = amp_hercules,
3696 .mixer_init = hercules_mixer_init,
3697 },
3698 /* Herculess Fortissimo */
3699 {
3700 .vendor = 0x1681,
3701 .id = 0xa010,
3702 .name = "Hercules Gamesurround Fortissimo II",
3703 },
3704 {
3705 .vendor = 0x1681,
3706 .id = 0xa011,
3707 .name = "Hercules Gamesurround Fortissimo III 7.1",
3708 },
3709 /* Teratec */
3710 {
3711 .vendor = 0x153b,
3712 .id = 0x112e,
3713 .name = "Terratec DMX XFire 1024",
3714 },
3715 {
3716 .vendor = 0x153b,
3717 .id = 0x1136,
3718 .name = "Terratec SiXPack 5.1",
3719 },
3720 /* Not sure if the 570 needs the clkrun hack */
3721 {
3722 .vendor = PCI_VENDOR_ID_IBM,
3723 .id = 0x0132,
3724 .name = "Thinkpad 570",
3725 .init = clkrun_init,
3726 .active = clkrun_hack,
3727 },
3728 {
3729 .vendor = PCI_VENDOR_ID_IBM,
3730 .id = 0x0153,
3731 .name = "Thinkpad 600X/A20/T20",
3732 .init = clkrun_init,
3733 .active = clkrun_hack,
3734 },
3735 {
3736 .vendor = PCI_VENDOR_ID_IBM,
3737 .id = 0x1010,
3738 .name = "Thinkpad 600E (unsupported)",
3739 },
3740 {} /* terminator */
3741};
3742
3743
3744/*
3745 * APM support
3746 */
3747#ifdef CONFIG_PM_SLEEP
3748static const unsigned int saved_regs[] = {
3749 BA0_ACOSV,
3750 /*BA0_ASER_FADDR,*/
3751 BA0_ASER_MASTER,
3752 BA1_PVOL,
3753 BA1_CVOL,
3754};
3755
3756static int snd_cs46xx_suspend(struct device *dev)
3757{
3758 struct snd_card *card = dev_get_drvdata(dev);
3759 struct snd_cs46xx *chip = card->private_data;
3760 int i, amp_saved;
3761
3762 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3763 chip->in_suspend = 1;
3764 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3765 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3766
3767 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3768 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3769
3770 /* save some registers */
3771 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3772 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3773
3774 amp_saved = chip->amplifier;
3775 /* turn off amp */
3776 chip->amplifier_ctrl(chip, -chip->amplifier);
3777 snd_cs46xx_hw_stop(chip);
3778 /* disable CLKRUN */
3779 chip->active_ctrl(chip, -chip->amplifier);
3780 chip->amplifier = amp_saved; /* restore the status */
3781 return 0;
3782}
3783
3784static int snd_cs46xx_resume(struct device *dev)
3785{
3786 struct snd_card *card = dev_get_drvdata(dev);
3787 struct snd_cs46xx *chip = card->private_data;
3788 int amp_saved;
3789#ifdef CONFIG_SND_CS46XX_NEW_DSP
3790 int i;
3791#endif
3792 unsigned int tmp;
3793
3794 amp_saved = chip->amplifier;
3795 chip->amplifier = 0;
3796 chip->active_ctrl(chip, 1); /* force to on */
3797
3798 snd_cs46xx_chip_init(chip);
3799
3800 snd_cs46xx_reset(chip);
3801#ifdef CONFIG_SND_CS46XX_NEW_DSP
3802 cs46xx_dsp_resume(chip);
3803 /* restore some registers */
3804 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3805 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3806#else
3807 snd_cs46xx_download_image(chip);
3808#endif
3809
3810#if 0
3811 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3812 chip->ac97_general_purpose);
3813 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3814 chip->ac97_powerdown);
3815 mdelay(10);
3816 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3817 chip->ac97_powerdown);
3818 mdelay(5);
3819#endif
3820
3821 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3822 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3823
3824 /*
3825 * Stop capture DMA.
3826 */
3827 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3828 chip->capt.ctl = tmp & 0x0000ffff;
3829 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3830
3831 mdelay(5);
3832
3833 /* reset playback/capture */
3834 snd_cs46xx_set_play_sample_rate(chip, 8000);
3835 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3836 snd_cs46xx_proc_start(chip);
3837
3838 cs46xx_enable_stream_irqs(chip);
3839
3840 if (amp_saved)
3841 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3842 else
3843 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3844 chip->amplifier = amp_saved;
3845 chip->in_suspend = 0;
3846 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3847 return 0;
3848}
3849
3850SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
3851#endif /* CONFIG_PM_SLEEP */
3852
3853
3854/*
3855 */
3856
3857int snd_cs46xx_create(struct snd_card *card,
3858 struct pci_dev *pci,
3859 int external_amp, int thinkpad,
3860 struct snd_cs46xx **rchip)
3861{
3862 struct snd_cs46xx *chip;
3863 int err, idx;
3864 struct snd_cs46xx_region *region;
3865 struct cs_card_type *cp;
3866 u16 ss_card, ss_vendor;
3867 static const struct snd_device_ops ops = {
3868 .dev_free = snd_cs46xx_dev_free,
3869 };
3870
3871 *rchip = NULL;
3872
3873 /* enable PCI device */
3874 if ((err = pci_enable_device(pci)) < 0)
3875 return err;
3876
3877 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3878 if (chip == NULL) {
3879 pci_disable_device(pci);
3880 return -ENOMEM;
3881 }
3882 spin_lock_init(&chip->reg_lock);
3883#ifdef CONFIG_SND_CS46XX_NEW_DSP
3884 mutex_init(&chip->spos_mutex);
3885#endif
3886 chip->card = card;
3887 chip->pci = pci;
3888 chip->irq = -1;
3889 chip->ba0_addr = pci_resource_start(pci, 0);
3890 chip->ba1_addr = pci_resource_start(pci, 1);
3891 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3892 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3893 dev_err(chip->card->dev,
3894 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3895 chip->ba0_addr, chip->ba1_addr);
3896 snd_cs46xx_free(chip);
3897 return -ENOMEM;
3898 }
3899
3900 region = &chip->region.name.ba0;
3901 strcpy(region->name, "CS46xx_BA0");
3902 region->base = chip->ba0_addr;
3903 region->size = CS46XX_BA0_SIZE;
3904
3905 region = &chip->region.name.data0;
3906 strcpy(region->name, "CS46xx_BA1_data0");
3907 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3908 region->size = CS46XX_BA1_DATA0_SIZE;
3909
3910 region = &chip->region.name.data1;
3911 strcpy(region->name, "CS46xx_BA1_data1");
3912 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3913 region->size = CS46XX_BA1_DATA1_SIZE;
3914
3915 region = &chip->region.name.pmem;
3916 strcpy(region->name, "CS46xx_BA1_pmem");
3917 region->base = chip->ba1_addr + BA1_SP_PMEM;
3918 region->size = CS46XX_BA1_PRG_SIZE;
3919
3920 region = &chip->region.name.reg;
3921 strcpy(region->name, "CS46xx_BA1_reg");
3922 region->base = chip->ba1_addr + BA1_SP_REG;
3923 region->size = CS46XX_BA1_REG_SIZE;
3924
3925 /* set up amp and clkrun hack */
3926 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3927 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3928
3929 for (cp = &cards[0]; cp->name; cp++) {
3930 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3931 dev_dbg(chip->card->dev, "hack for %s enabled\n",
3932 cp->name);
3933
3934 chip->amplifier_ctrl = cp->amp;
3935 chip->active_ctrl = cp->active;
3936 chip->mixer_init = cp->mixer_init;
3937
3938 if (cp->init)
3939 cp->init(chip);
3940 break;
3941 }
3942 }
3943
3944 if (external_amp) {
3945 dev_info(chip->card->dev,
3946 "Crystal EAPD support forced on.\n");
3947 chip->amplifier_ctrl = amp_voyetra;
3948 }
3949
3950 if (thinkpad) {
3951 dev_info(chip->card->dev,
3952 "Activating CLKRUN hack for Thinkpad.\n");
3953 chip->active_ctrl = clkrun_hack;
3954 clkrun_init(chip);
3955 }
3956
3957 if (chip->amplifier_ctrl == NULL)
3958 chip->amplifier_ctrl = amp_none;
3959 if (chip->active_ctrl == NULL)
3960 chip->active_ctrl = amp_none;
3961
3962 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3963
3964 pci_set_master(pci);
3965
3966 for (idx = 0; idx < 5; idx++) {
3967 region = &chip->region.idx[idx];
3968 if ((region->resource = request_mem_region(region->base, region->size,
3969 region->name)) == NULL) {
3970 dev_err(chip->card->dev,
3971 "unable to request memory region 0x%lx-0x%lx\n",
3972 region->base, region->base + region->size - 1);
3973 snd_cs46xx_free(chip);
3974 return -EBUSY;
3975 }
3976 region->remap_addr = ioremap(region->base, region->size);
3977 if (region->remap_addr == NULL) {
3978 dev_err(chip->card->dev,
3979 "%s ioremap problem\n", region->name);
3980 snd_cs46xx_free(chip);
3981 return -ENOMEM;
3982 }
3983 }
3984
3985 if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED,
3986 KBUILD_MODNAME, chip)) {
3987 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
3988 snd_cs46xx_free(chip);
3989 return -EBUSY;
3990 }
3991 chip->irq = pci->irq;
3992 card->sync_irq = chip->irq;
3993
3994#ifdef CONFIG_SND_CS46XX_NEW_DSP
3995 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3996 if (chip->dsp_spos_instance == NULL) {
3997 snd_cs46xx_free(chip);
3998 return -ENOMEM;
3999 }
4000#endif
4001
4002 err = snd_cs46xx_chip_init(chip);
4003 if (err < 0) {
4004 snd_cs46xx_free(chip);
4005 return err;
4006 }
4007
4008 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
4009 snd_cs46xx_free(chip);
4010 return err;
4011 }
4012
4013 snd_cs46xx_proc_init(card, chip);
4014
4015#ifdef CONFIG_PM_SLEEP
4016 chip->saved_regs = kmalloc_array(ARRAY_SIZE(saved_regs),
4017 sizeof(*chip->saved_regs),
4018 GFP_KERNEL);
4019 if (!chip->saved_regs) {
4020 snd_cs46xx_free(chip);
4021 return -ENOMEM;
4022 }
4023#endif
4024
4025 chip->active_ctrl(chip, -1); /* disable CLKRUN */
4026
4027 *rchip = chip;
4028 return 0;
4029}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * Abramo Bagnara <abramo@alsa-project.org>
5 * Cirrus Logic, Inc.
6 * Routines for control of Cirrus Logic CS461x chips
7 *
8 * KNOWN BUGS:
9 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
10 * and the SPDIF get somewhat "distorcionated", or/and left right channel
11 * are swapped. To get around this problem when it happens, mute and unmute
12 * the SPDIF input mixer control.
13 * - On the Hercules Game Theater XP the amplifier are sometimes turned
14 * off on inadecuate moments which causes distorcions on sound.
15 *
16 * TODO:
17 * - Secondary CODEC on some soundcards
18 * - SPDIF input support for other sample rates then 48khz
19 * - Posibility to mix the SPDIF output with analog sources.
20 * - PCM channels for Center and LFE on secondary codec
21 *
22 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
23 * is default configuration), no SPDIF, no secondary codec, no
24 * multi channel PCM. But known to work.
25 *
26 * FINALLY: A credit to the developers Tom and Jordan
27 * at Cirrus for have helping me out with the DSP, however we
28 * still don't have sufficient documentation and technical
29 * references to be able to implement all fancy feutures
30 * supported by the cs46xx DSP's.
31 * Benny <benny@hostmobility.com>
32 */
33
34#include <linux/delay.h>
35#include <linux/pci.h>
36#include <linux/pm.h>
37#include <linux/init.h>
38#include <linux/interrupt.h>
39#include <linux/slab.h>
40#include <linux/gameport.h>
41#include <linux/mutex.h>
42#include <linux/export.h>
43#include <linux/module.h>
44#include <linux/firmware.h>
45#include <linux/vmalloc.h>
46#include <linux/io.h>
47
48#include <sound/core.h>
49#include <sound/control.h>
50#include <sound/info.h>
51#include <sound/pcm.h>
52#include <sound/pcm_params.h>
53#include "cs46xx.h"
54
55#include "cs46xx_lib.h"
56#include "dsp_spos.h"
57
58static void amp_voyetra(struct snd_cs46xx *chip, int change);
59
60#ifdef CONFIG_SND_CS46XX_NEW_DSP
61static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
62static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
63static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
64static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
65static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
66static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
67#endif
68
69static const struct snd_pcm_ops snd_cs46xx_playback_ops;
70static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
71static const struct snd_pcm_ops snd_cs46xx_capture_ops;
72static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
73
74static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
75 unsigned short reg,
76 int codec_index)
77{
78 int count;
79 unsigned short result,tmp;
80 u32 offset = 0;
81
82 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
83 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
84 return 0xffff;
85
86 chip->active_ctrl(chip, 1);
87
88 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
89 offset = CS46XX_SECONDARY_CODEC_OFFSET;
90
91 /*
92 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
93 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
94 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
95 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
96 * 5. if DCV not cleared, break and return error
97 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
98 */
99
100 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
101
102 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
103 if ((tmp & ACCTL_VFRM) == 0) {
104 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
105 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
106 msleep(50);
107 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
108 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
109
110 }
111
112 /*
113 * Setup the AC97 control registers on the CS461x to send the
114 * appropriate command to the AC97 to perform the read.
115 * ACCAD = Command Address Register = 46Ch
116 * ACCDA = Command Data Register = 470h
117 * ACCTL = Control Register = 460h
118 * set DCV - will clear when process completed
119 * set CRW - Read command
120 * set VFRM - valid frame enabled
121 * set ESYN - ASYNC generation enabled
122 * set RSTN - ARST# inactive, AC97 codec not reset
123 */
124
125 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
126 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
127 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
128 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
129 ACCTL_VFRM | ACCTL_ESYN |
130 ACCTL_RSTN);
131 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
132 ACCTL_VFRM | ACCTL_ESYN |
133 ACCTL_RSTN);
134 } else {
135 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
136 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
137 ACCTL_RSTN);
138 }
139
140 /*
141 * Wait for the read to occur.
142 */
143 for (count = 0; count < 1000; count++) {
144 /*
145 * First, we want to wait for a short time.
146 */
147 udelay(10);
148 /*
149 * Now, check to see if the read has completed.
150 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
151 */
152 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
153 goto ok1;
154 }
155
156 dev_err(chip->card->dev,
157 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
158 result = 0xffff;
159 goto end;
160
161 ok1:
162 /*
163 * Wait for the valid status bit to go active.
164 */
165 for (count = 0; count < 100; count++) {
166 /*
167 * Read the AC97 status register.
168 * ACSTS = Status Register = 464h
169 * VSTS - Valid Status
170 */
171 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
172 goto ok2;
173 udelay(10);
174 }
175
176 dev_err(chip->card->dev,
177 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
178 codec_index, reg);
179 result = 0xffff;
180 goto end;
181
182 ok2:
183 /*
184 * Read the data returned from the AC97 register.
185 * ACSDA = Status Data Register = 474h
186 */
187#if 0
188 dev_dbg(chip->card->dev,
189 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
190 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
191 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
192#endif
193
194 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
195 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
196 end:
197 chip->active_ctrl(chip, -1);
198 return result;
199}
200
201static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
202 unsigned short reg)
203{
204 struct snd_cs46xx *chip = ac97->private_data;
205 unsigned short val;
206 int codec_index = ac97->num;
207
208 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
209 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
210 return 0xffff;
211
212 val = snd_cs46xx_codec_read(chip, reg, codec_index);
213
214 return val;
215}
216
217
218static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
219 unsigned short reg,
220 unsigned short val,
221 int codec_index)
222{
223 int count;
224
225 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
226 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
227 return;
228
229 chip->active_ctrl(chip, 1);
230
231 /*
232 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
233 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
234 * 3. Write ACCTL = Control Register = 460h for initiating the write
235 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
236 * 5. if DCV not cleared, break and return error
237 */
238
239 /*
240 * Setup the AC97 control registers on the CS461x to send the
241 * appropriate command to the AC97 to perform the read.
242 * ACCAD = Command Address Register = 46Ch
243 * ACCDA = Command Data Register = 470h
244 * ACCTL = Control Register = 460h
245 * set DCV - will clear when process completed
246 * reset CRW - Write command
247 * set VFRM - valid frame enabled
248 * set ESYN - ASYNC generation enabled
249 * set RSTN - ARST# inactive, AC97 codec not reset
250 */
251 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
252 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
253 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
254
255 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
256 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
257 ACCTL_ESYN | ACCTL_RSTN);
258 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
259 ACCTL_ESYN | ACCTL_RSTN);
260 } else {
261 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
262 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
263 }
264
265 for (count = 0; count < 4000; count++) {
266 /*
267 * First, we want to wait for a short time.
268 */
269 udelay(10);
270 /*
271 * Now, check to see if the write has completed.
272 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
273 */
274 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
275 goto end;
276 }
277 }
278 dev_err(chip->card->dev,
279 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
280 codec_index, reg, val);
281 end:
282 chip->active_ctrl(chip, -1);
283}
284
285static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
286 unsigned short reg,
287 unsigned short val)
288{
289 struct snd_cs46xx *chip = ac97->private_data;
290 int codec_index = ac97->num;
291
292 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
293 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
294 return;
295
296 snd_cs46xx_codec_write(chip, reg, val, codec_index);
297}
298
299
300/*
301 * Chip initialization
302 */
303
304int snd_cs46xx_download(struct snd_cs46xx *chip,
305 u32 *src,
306 unsigned long offset,
307 unsigned long len)
308{
309 void __iomem *dst;
310 unsigned int bank = offset >> 16;
311 offset = offset & 0xffff;
312
313 if (snd_BUG_ON((offset & 3) || (len & 3)))
314 return -EINVAL;
315 dst = chip->region.idx[bank+1].remap_addr + offset;
316 len /= sizeof(u32);
317
318 /* writel already converts 32-bit value to right endianess */
319 while (len-- > 0) {
320 writel(*src++, dst);
321 dst += sizeof(u32);
322 }
323 return 0;
324}
325
326static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
327{
328#ifdef __LITTLE_ENDIAN
329 memcpy(dst, src, len);
330#else
331 u32 *_dst = dst;
332 const __le32 *_src = src;
333 len /= 4;
334 while (len-- > 0)
335 *_dst++ = le32_to_cpu(*_src++);
336#endif
337}
338
339#ifdef CONFIG_SND_CS46XX_NEW_DSP
340
341static const char *module_names[CS46XX_DSP_MODULES] = {
342 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
343};
344
345MODULE_FIRMWARE("cs46xx/cwc4630");
346MODULE_FIRMWARE("cs46xx/cwcasync");
347MODULE_FIRMWARE("cs46xx/cwcsnoop");
348MODULE_FIRMWARE("cs46xx/cwcbinhack");
349MODULE_FIRMWARE("cs46xx/cwcdma");
350
351static void free_module_desc(struct dsp_module_desc *module)
352{
353 if (!module)
354 return;
355 kfree(module->module_name);
356 kfree(module->symbol_table.symbols);
357 if (module->segments) {
358 int i;
359 for (i = 0; i < module->nsegments; i++)
360 kfree(module->segments[i].data);
361 kfree(module->segments);
362 }
363 kfree(module);
364}
365
366/* firmware binary format:
367 * le32 nsymbols;
368 * struct {
369 * le32 address;
370 * char symbol_name[DSP_MAX_SYMBOL_NAME];
371 * le32 symbol_type;
372 * } symbols[nsymbols];
373 * le32 nsegments;
374 * struct {
375 * le32 segment_type;
376 * le32 offset;
377 * le32 size;
378 * le32 data[size];
379 * } segments[nsegments];
380 */
381
382static int load_firmware(struct snd_cs46xx *chip,
383 struct dsp_module_desc **module_ret,
384 const char *fw_name)
385{
386 int i, err;
387 unsigned int nums, fwlen, fwsize;
388 const __le32 *fwdat;
389 struct dsp_module_desc *module = NULL;
390 const struct firmware *fw;
391 char fw_path[32];
392
393 sprintf(fw_path, "cs46xx/%s", fw_name);
394 err = request_firmware(&fw, fw_path, &chip->pci->dev);
395 if (err < 0)
396 return err;
397 fwsize = fw->size / 4;
398 if (fwsize < 2) {
399 err = -EINVAL;
400 goto error;
401 }
402
403 err = -ENOMEM;
404 module = kzalloc(sizeof(*module), GFP_KERNEL);
405 if (!module)
406 goto error;
407 module->module_name = kstrdup(fw_name, GFP_KERNEL);
408 if (!module->module_name)
409 goto error;
410
411 fwlen = 0;
412 fwdat = (const __le32 *)fw->data;
413 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
414 if (nums >= 40)
415 goto error_inval;
416 module->symbol_table.symbols =
417 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
418 if (!module->symbol_table.symbols)
419 goto error;
420 for (i = 0; i < nums; i++) {
421 struct dsp_symbol_entry *entry =
422 &module->symbol_table.symbols[i];
423 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
424 goto error_inval;
425 entry->address = le32_to_cpu(fwdat[fwlen++]);
426 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
427 fwlen += DSP_MAX_SYMBOL_NAME / 4;
428 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
429 }
430
431 if (fwlen >= fwsize)
432 goto error_inval;
433 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
434 if (nums > 10)
435 goto error_inval;
436 module->segments =
437 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
438 if (!module->segments)
439 goto error;
440 for (i = 0; i < nums; i++) {
441 struct dsp_segment_desc *entry = &module->segments[i];
442 if (fwlen + 3 > fwsize)
443 goto error_inval;
444 entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
445 entry->offset = le32_to_cpu(fwdat[fwlen++]);
446 entry->size = le32_to_cpu(fwdat[fwlen++]);
447 if (fwlen + entry->size > fwsize)
448 goto error_inval;
449 entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL);
450 if (!entry->data)
451 goto error;
452 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
453 fwlen += entry->size;
454 }
455
456 *module_ret = module;
457 release_firmware(fw);
458 return 0;
459
460 error_inval:
461 err = -EINVAL;
462 error:
463 free_module_desc(module);
464 release_firmware(fw);
465 return err;
466}
467
468int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
469 unsigned long offset,
470 unsigned long len)
471{
472 void __iomem *dst;
473 unsigned int bank = offset >> 16;
474 offset = offset & 0xffff;
475
476 if (snd_BUG_ON((offset & 3) || (len & 3)))
477 return -EINVAL;
478 dst = chip->region.idx[bank+1].remap_addr + offset;
479 len /= sizeof(u32);
480
481 /* writel already converts 32-bit value to right endianess */
482 while (len-- > 0) {
483 writel(0, dst);
484 dst += sizeof(u32);
485 }
486 return 0;
487}
488
489#else /* old DSP image */
490
491struct ba1_struct {
492 struct {
493 u32 offset;
494 u32 size;
495 } memory[BA1_MEMORY_COUNT];
496 u32 map[BA1_DWORD_SIZE];
497};
498
499MODULE_FIRMWARE("cs46xx/ba1");
500
501static int load_firmware(struct snd_cs46xx *chip)
502{
503 const struct firmware *fw;
504 int i, size, err;
505
506 err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
507 if (err < 0)
508 return err;
509 if (fw->size != sizeof(*chip->ba1)) {
510 err = -EINVAL;
511 goto error;
512 }
513
514 chip->ba1 = vmalloc(sizeof(*chip->ba1));
515 if (!chip->ba1) {
516 err = -ENOMEM;
517 goto error;
518 }
519
520 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
521
522 /* sanity check */
523 size = 0;
524 for (i = 0; i < BA1_MEMORY_COUNT; i++)
525 size += chip->ba1->memory[i].size;
526 if (size > BA1_DWORD_SIZE * 4)
527 err = -EINVAL;
528
529 error:
530 release_firmware(fw);
531 return err;
532}
533
534static __maybe_unused int snd_cs46xx_download_image(struct snd_cs46xx *chip)
535{
536 int idx, err;
537 unsigned int offset = 0;
538 struct ba1_struct *ba1 = chip->ba1;
539
540 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
541 err = snd_cs46xx_download(chip,
542 &ba1->map[offset],
543 ba1->memory[idx].offset,
544 ba1->memory[idx].size);
545 if (err < 0)
546 return err;
547 offset += ba1->memory[idx].size >> 2;
548 }
549 return 0;
550}
551#endif /* CONFIG_SND_CS46XX_NEW_DSP */
552
553/*
554 * Chip reset
555 */
556
557static void snd_cs46xx_reset(struct snd_cs46xx *chip)
558{
559 int idx;
560
561 /*
562 * Write the reset bit of the SP control register.
563 */
564 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
565
566 /*
567 * Write the control register.
568 */
569 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
570
571 /*
572 * Clear the trap registers.
573 */
574 for (idx = 0; idx < 8; idx++) {
575 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
576 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
577 }
578 snd_cs46xx_poke(chip, BA1_DREG, 0);
579
580 /*
581 * Set the frame timer to reflect the number of cycles per frame.
582 */
583 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
584}
585
586static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
587{
588 u32 i, status = 0;
589 /*
590 * Make sure the previous FIFO write operation has completed.
591 */
592 for(i = 0; i < 50; i++){
593 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
594
595 if( !(status & SERBST_WBSY) )
596 break;
597
598 mdelay(retry_timeout);
599 }
600
601 if(status & SERBST_WBSY) {
602 dev_err(chip->card->dev,
603 "failure waiting for FIFO command to complete\n");
604 return -EINVAL;
605 }
606
607 return 0;
608}
609
610static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
611{
612 int idx, powerdown = 0;
613 unsigned int tmp;
614
615 /*
616 * See if the devices are powered down. If so, we must power them up first
617 * or they will not respond.
618 */
619 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
620 if (!(tmp & CLKCR1_SWCE)) {
621 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
622 powerdown = 1;
623 }
624
625 /*
626 * We want to clear out the serial port FIFOs so we don't end up playing
627 * whatever random garbage happens to be in them. We fill the sample FIFOS
628 * with zero (silence).
629 */
630 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
631
632 /*
633 * Fill all 256 sample FIFO locations.
634 */
635 for (idx = 0; idx < 0xFF; idx++) {
636 /*
637 * Make sure the previous FIFO write operation has completed.
638 */
639 if (cs46xx_wait_for_fifo(chip,1)) {
640 dev_dbg(chip->card->dev,
641 "failed waiting for FIFO at addr (%02X)\n",
642 idx);
643
644 if (powerdown)
645 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
646
647 break;
648 }
649 /*
650 * Write the serial port FIFO index.
651 */
652 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
653 /*
654 * Tell the serial port to load the new value into the FIFO location.
655 */
656 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
657 }
658 /*
659 * Now, if we powered up the devices, then power them back down again.
660 * This is kinda ugly, but should never happen.
661 */
662 if (powerdown)
663 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
664}
665
666static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
667{
668 int cnt;
669
670 /*
671 * Set the frame timer to reflect the number of cycles per frame.
672 */
673 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
674 /*
675 * Turn on the run, run at frame, and DMA enable bits in the local copy of
676 * the SP control register.
677 */
678 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
679 /*
680 * Wait until the run at frame bit resets itself in the SP control
681 * register.
682 */
683 for (cnt = 0; cnt < 25; cnt++) {
684 udelay(50);
685 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
686 break;
687 }
688
689 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
690 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
691}
692
693static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
694{
695 /*
696 * Turn off the run, run at frame, and DMA enable bits in the local copy of
697 * the SP control register.
698 */
699 snd_cs46xx_poke(chip, BA1_SPCR, 0);
700}
701
702/*
703 * Sample rate routines
704 */
705
706#define GOF_PER_SEC 200
707
708static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
709{
710 unsigned long flags;
711 unsigned int tmp1, tmp2;
712 unsigned int phiIncr;
713 unsigned int correctionPerGOF, correctionPerSec;
714
715 /*
716 * Compute the values used to drive the actual sample rate conversion.
717 * The following formulas are being computed, using inline assembly
718 * since we need to use 64 bit arithmetic to compute the values:
719 *
720 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
721 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
722 * GOF_PER_SEC)
723 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
724 * GOF_PER_SEC * correctionPerGOF
725 *
726 * i.e.
727 *
728 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
729 * correctionPerGOF:correctionPerSec =
730 * dividend:remainder(ulOther / GOF_PER_SEC)
731 */
732 tmp1 = rate << 16;
733 phiIncr = tmp1 / 48000;
734 tmp1 -= phiIncr * 48000;
735 tmp1 <<= 10;
736 phiIncr <<= 10;
737 tmp2 = tmp1 / 48000;
738 phiIncr += tmp2;
739 tmp1 -= tmp2 * 48000;
740 correctionPerGOF = tmp1 / GOF_PER_SEC;
741 tmp1 -= correctionPerGOF * GOF_PER_SEC;
742 correctionPerSec = tmp1;
743
744 /*
745 * Fill in the SampleRateConverter control block.
746 */
747 spin_lock_irqsave(&chip->reg_lock, flags);
748 snd_cs46xx_poke(chip, BA1_PSRC,
749 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
750 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
751 spin_unlock_irqrestore(&chip->reg_lock, flags);
752}
753
754static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
755{
756 unsigned long flags;
757 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
758 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
759 unsigned int frameGroupLength, cnt;
760
761 /*
762 * We can only decimate by up to a factor of 1/9th the hardware rate.
763 * Correct the value if an attempt is made to stray outside that limit.
764 */
765 if ((rate * 9) < 48000)
766 rate = 48000 / 9;
767
768 /*
769 * We can not capture at a rate greater than the Input Rate (48000).
770 * Return an error if an attempt is made to stray outside that limit.
771 */
772 if (rate > 48000)
773 rate = 48000;
774
775 /*
776 * Compute the values used to drive the actual sample rate conversion.
777 * The following formulas are being computed, using inline assembly
778 * since we need to use 64 bit arithmetic to compute the values:
779 *
780 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
781 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
782 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
783 * GOF_PER_SEC)
784 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
785 * GOF_PER_SEC * correctionPerGOF
786 * initialDelay = ceil((24 * Fs,in) / Fs,out)
787 *
788 * i.e.
789 *
790 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
791 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
792 * correctionPerGOF:correctionPerSec =
793 * dividend:remainder(ulOther / GOF_PER_SEC)
794 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
795 */
796
797 tmp1 = rate << 16;
798 coeffIncr = tmp1 / 48000;
799 tmp1 -= coeffIncr * 48000;
800 tmp1 <<= 7;
801 coeffIncr <<= 7;
802 coeffIncr += tmp1 / 48000;
803 coeffIncr ^= 0xFFFFFFFF;
804 coeffIncr++;
805 tmp1 = 48000 << 16;
806 phiIncr = tmp1 / rate;
807 tmp1 -= phiIncr * rate;
808 tmp1 <<= 10;
809 phiIncr <<= 10;
810 tmp2 = tmp1 / rate;
811 phiIncr += tmp2;
812 tmp1 -= tmp2 * rate;
813 correctionPerGOF = tmp1 / GOF_PER_SEC;
814 tmp1 -= correctionPerGOF * GOF_PER_SEC;
815 correctionPerSec = tmp1;
816 initialDelay = DIV_ROUND_UP(48000 * 24, rate);
817
818 /*
819 * Fill in the VariDecimate control block.
820 */
821 spin_lock_irqsave(&chip->reg_lock, flags);
822 snd_cs46xx_poke(chip, BA1_CSRC,
823 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
824 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
825 snd_cs46xx_poke(chip, BA1_CD,
826 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
827 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
828 spin_unlock_irqrestore(&chip->reg_lock, flags);
829
830 /*
831 * Figure out the frame group length for the write back task. Basically,
832 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
833 * the output sample rate.
834 */
835 frameGroupLength = 1;
836 for (cnt = 2; cnt <= 64; cnt *= 2) {
837 if (((rate / cnt) * cnt) != rate)
838 frameGroupLength *= 2;
839 }
840 if (((rate / 3) * 3) != rate) {
841 frameGroupLength *= 3;
842 }
843 for (cnt = 5; cnt <= 125; cnt *= 5) {
844 if (((rate / cnt) * cnt) != rate)
845 frameGroupLength *= 5;
846 }
847
848 /*
849 * Fill in the WriteBack control block.
850 */
851 spin_lock_irqsave(&chip->reg_lock, flags);
852 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
853 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
854 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
855 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
856 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
857 spin_unlock_irqrestore(&chip->reg_lock, flags);
858}
859
860/*
861 * PCM part
862 */
863
864static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
865 struct snd_pcm_indirect *rec, size_t bytes)
866{
867 struct snd_pcm_runtime *runtime = substream->runtime;
868 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
869 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
870}
871
872static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
873{
874 struct snd_pcm_runtime *runtime = substream->runtime;
875 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
876 return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec,
877 snd_cs46xx_pb_trans_copy);
878}
879
880static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
881 struct snd_pcm_indirect *rec, size_t bytes)
882{
883 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
884 struct snd_pcm_runtime *runtime = substream->runtime;
885 memcpy(runtime->dma_area + rec->sw_data,
886 chip->capt.hw_buf.area + rec->hw_data, bytes);
887}
888
889static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
890{
891 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
892 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
893 snd_cs46xx_cp_trans_copy);
894}
895
896static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
897{
898 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
899 size_t ptr;
900 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
901
902 if (snd_BUG_ON(!cpcm->pcm_channel))
903 return -ENXIO;
904
905#ifdef CONFIG_SND_CS46XX_NEW_DSP
906 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
907#else
908 ptr = snd_cs46xx_peek(chip, BA1_PBA);
909#endif
910 ptr -= cpcm->hw_buf.addr;
911 return ptr >> cpcm->shift;
912}
913
914static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
915{
916 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
917 size_t ptr;
918 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
919
920#ifdef CONFIG_SND_CS46XX_NEW_DSP
921 if (snd_BUG_ON(!cpcm->pcm_channel))
922 return -ENXIO;
923 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
924#else
925 ptr = snd_cs46xx_peek(chip, BA1_PBA);
926#endif
927 ptr -= cpcm->hw_buf.addr;
928 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
929}
930
931static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
932{
933 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
934 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
935 return ptr >> chip->capt.shift;
936}
937
938static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
939{
940 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
941 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
942 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
943}
944
945static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
946 int cmd)
947{
948 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
949 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
950 int result = 0;
951
952#ifdef CONFIG_SND_CS46XX_NEW_DSP
953 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
954 if (! cpcm->pcm_channel) {
955 return -ENXIO;
956 }
957#endif
958 switch (cmd) {
959 case SNDRV_PCM_TRIGGER_START:
960 case SNDRV_PCM_TRIGGER_RESUME:
961#ifdef CONFIG_SND_CS46XX_NEW_DSP
962 /* magic value to unmute PCM stream playback volume */
963 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
964 SCBVolumeCtrl) << 2, 0x80008000);
965
966 if (cpcm->pcm_channel->unlinked)
967 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
968
969 if (substream->runtime->periods != CS46XX_FRAGS)
970 snd_cs46xx_playback_transfer(substream);
971#else
972 spin_lock(&chip->reg_lock);
973 if (substream->runtime->periods != CS46XX_FRAGS)
974 snd_cs46xx_playback_transfer(substream);
975 { unsigned int tmp;
976 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
977 tmp &= 0x0000ffff;
978 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
979 }
980 spin_unlock(&chip->reg_lock);
981#endif
982 break;
983 case SNDRV_PCM_TRIGGER_STOP:
984 case SNDRV_PCM_TRIGGER_SUSPEND:
985#ifdef CONFIG_SND_CS46XX_NEW_DSP
986 /* magic mute channel */
987 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
988 SCBVolumeCtrl) << 2, 0xffffffff);
989
990 if (!cpcm->pcm_channel->unlinked)
991 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
992#else
993 spin_lock(&chip->reg_lock);
994 { unsigned int tmp;
995 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
996 tmp &= 0x0000ffff;
997 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
998 }
999 spin_unlock(&chip->reg_lock);
1000#endif
1001 break;
1002 default:
1003 result = -EINVAL;
1004 break;
1005 }
1006
1007 return result;
1008}
1009
1010static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1011 int cmd)
1012{
1013 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1014 unsigned int tmp;
1015 int result = 0;
1016
1017 spin_lock(&chip->reg_lock);
1018 switch (cmd) {
1019 case SNDRV_PCM_TRIGGER_START:
1020 case SNDRV_PCM_TRIGGER_RESUME:
1021 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1022 tmp &= 0xffff0000;
1023 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1024 break;
1025 case SNDRV_PCM_TRIGGER_STOP:
1026 case SNDRV_PCM_TRIGGER_SUSPEND:
1027 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1028 tmp &= 0xffff0000;
1029 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1030 break;
1031 default:
1032 result = -EINVAL;
1033 break;
1034 }
1035 spin_unlock(&chip->reg_lock);
1036
1037 return result;
1038}
1039
1040#ifdef CONFIG_SND_CS46XX_NEW_DSP
1041static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1042 int sample_rate)
1043{
1044
1045 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1046 if ( cpcm->pcm_channel == NULL) {
1047 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1048 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1049 if (cpcm->pcm_channel == NULL) {
1050 dev_err(chip->card->dev,
1051 "failed to create virtual PCM channel\n");
1052 return -ENOMEM;
1053 }
1054 cpcm->pcm_channel->sample_rate = sample_rate;
1055 } else
1056 /* if sample rate is changed */
1057 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1058 int unlinked = cpcm->pcm_channel->unlinked;
1059 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1060
1061 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel(chip, sample_rate, cpcm,
1062 cpcm->hw_buf.addr,
1063 cpcm->pcm_channel_id);
1064 if (!cpcm->pcm_channel) {
1065 dev_err(chip->card->dev,
1066 "failed to re-create virtual PCM channel\n");
1067 return -ENOMEM;
1068 }
1069
1070 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1071 cpcm->pcm_channel->sample_rate = sample_rate;
1072 }
1073
1074 return 0;
1075}
1076#endif
1077
1078
1079static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1080 struct snd_pcm_hw_params *hw_params)
1081{
1082 struct snd_pcm_runtime *runtime = substream->runtime;
1083 struct snd_cs46xx_pcm *cpcm;
1084 int err;
1085#ifdef CONFIG_SND_CS46XX_NEW_DSP
1086 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1087 int sample_rate = params_rate(hw_params);
1088 int period_size = params_period_bytes(hw_params);
1089#endif
1090 cpcm = runtime->private_data;
1091
1092#ifdef CONFIG_SND_CS46XX_NEW_DSP
1093 if (snd_BUG_ON(!sample_rate))
1094 return -ENXIO;
1095
1096 mutex_lock(&chip->spos_mutex);
1097
1098 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
1099 mutex_unlock(&chip->spos_mutex);
1100 return -ENXIO;
1101 }
1102
1103 snd_BUG_ON(!cpcm->pcm_channel);
1104 if (!cpcm->pcm_channel) {
1105 mutex_unlock(&chip->spos_mutex);
1106 return -ENXIO;
1107 }
1108
1109
1110 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1111 mutex_unlock(&chip->spos_mutex);
1112 return -EINVAL;
1113 }
1114
1115 dev_dbg(chip->card->dev,
1116 "period_size (%d), periods (%d) buffer_size(%d)\n",
1117 period_size, params_periods(hw_params),
1118 params_buffer_bytes(hw_params));
1119#endif
1120
1121 if (params_periods(hw_params) == CS46XX_FRAGS) {
1122 if (runtime->dma_area != cpcm->hw_buf.area)
1123 snd_pcm_lib_free_pages(substream);
1124 snd_pcm_set_runtime_buffer(substream, &cpcm->hw_buf);
1125
1126
1127#ifdef CONFIG_SND_CS46XX_NEW_DSP
1128 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1129 substream->ops = &snd_cs46xx_playback_ops;
1130 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1131 substream->ops = &snd_cs46xx_playback_rear_ops;
1132 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1133 substream->ops = &snd_cs46xx_playback_clfe_ops;
1134 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1135 substream->ops = &snd_cs46xx_playback_iec958_ops;
1136 } else {
1137 snd_BUG();
1138 }
1139#else
1140 substream->ops = &snd_cs46xx_playback_ops;
1141#endif
1142
1143 } else {
1144 if (runtime->dma_area == cpcm->hw_buf.area)
1145 snd_pcm_set_runtime_buffer(substream, NULL);
1146 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1147 if (err < 0) {
1148#ifdef CONFIG_SND_CS46XX_NEW_DSP
1149 mutex_unlock(&chip->spos_mutex);
1150#endif
1151 return err;
1152 }
1153
1154#ifdef CONFIG_SND_CS46XX_NEW_DSP
1155 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1156 substream->ops = &snd_cs46xx_playback_indirect_ops;
1157 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1158 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1159 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1160 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1161 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1162 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1163 } else {
1164 snd_BUG();
1165 }
1166#else
1167 substream->ops = &snd_cs46xx_playback_indirect_ops;
1168#endif
1169
1170 }
1171
1172#ifdef CONFIG_SND_CS46XX_NEW_DSP
1173 mutex_unlock(&chip->spos_mutex);
1174#endif
1175
1176 return 0;
1177}
1178
1179static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1180{
1181 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1182 struct snd_pcm_runtime *runtime = substream->runtime;
1183 struct snd_cs46xx_pcm *cpcm;
1184
1185 cpcm = runtime->private_data;
1186
1187 /* if play_back open fails, then this function
1188 is called and cpcm can actually be NULL here */
1189 if (!cpcm) return -ENXIO;
1190
1191 if (runtime->dma_area != cpcm->hw_buf.area)
1192 snd_pcm_lib_free_pages(substream);
1193
1194 snd_pcm_set_runtime_buffer(substream, NULL);
1195
1196 return 0;
1197}
1198
1199static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1200{
1201 unsigned int tmp;
1202 unsigned int pfie;
1203 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1204 struct snd_pcm_runtime *runtime = substream->runtime;
1205 struct snd_cs46xx_pcm *cpcm;
1206
1207 cpcm = runtime->private_data;
1208
1209#ifdef CONFIG_SND_CS46XX_NEW_DSP
1210 if (snd_BUG_ON(!cpcm->pcm_channel))
1211 return -ENXIO;
1212
1213 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1214 pfie &= ~0x0000f03f;
1215#else
1216 /* old dsp */
1217 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1218 pfie &= ~0x0000f03f;
1219#endif
1220
1221 cpcm->shift = 2;
1222 /* if to convert from stereo to mono */
1223 if (runtime->channels == 1) {
1224 cpcm->shift--;
1225 pfie |= 0x00002000;
1226 }
1227 /* if to convert from 8 bit to 16 bit */
1228 if (snd_pcm_format_width(runtime->format) == 8) {
1229 cpcm->shift--;
1230 pfie |= 0x00001000;
1231 }
1232 /* if to convert to unsigned */
1233 if (snd_pcm_format_unsigned(runtime->format))
1234 pfie |= 0x00008000;
1235
1236 /* Never convert byte order when sample stream is 8 bit */
1237 if (snd_pcm_format_width(runtime->format) != 8) {
1238 /* convert from big endian to little endian */
1239 if (snd_pcm_format_big_endian(runtime->format))
1240 pfie |= 0x00004000;
1241 }
1242
1243 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1244 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1245 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1246
1247#ifdef CONFIG_SND_CS46XX_NEW_DSP
1248
1249 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1250 tmp &= ~0x000003ff;
1251 tmp |= (4 << cpcm->shift) - 1;
1252 /* playback transaction count register */
1253 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1254
1255 /* playback format && interrupt enable */
1256 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1257#else
1258 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1259 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1260 tmp &= ~0x000003ff;
1261 tmp |= (4 << cpcm->shift) - 1;
1262 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1263 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1264 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1265#endif
1266
1267 return 0;
1268}
1269
1270static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1271 struct snd_pcm_hw_params *hw_params)
1272{
1273 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1274 struct snd_pcm_runtime *runtime = substream->runtime;
1275 int err;
1276
1277#ifdef CONFIG_SND_CS46XX_NEW_DSP
1278 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1279#endif
1280 if (runtime->periods == CS46XX_FRAGS) {
1281 if (runtime->dma_area != chip->capt.hw_buf.area)
1282 snd_pcm_lib_free_pages(substream);
1283 snd_pcm_set_runtime_buffer(substream, &chip->capt.hw_buf);
1284 substream->ops = &snd_cs46xx_capture_ops;
1285 } else {
1286 if (runtime->dma_area == chip->capt.hw_buf.area)
1287 snd_pcm_set_runtime_buffer(substream, NULL);
1288 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1289 if (err < 0)
1290 return err;
1291 substream->ops = &snd_cs46xx_capture_indirect_ops;
1292 }
1293
1294 return 0;
1295}
1296
1297static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1298{
1299 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1300 struct snd_pcm_runtime *runtime = substream->runtime;
1301
1302 if (runtime->dma_area != chip->capt.hw_buf.area)
1303 snd_pcm_lib_free_pages(substream);
1304 snd_pcm_set_runtime_buffer(substream, NULL);
1305
1306 return 0;
1307}
1308
1309static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1310{
1311 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1312 struct snd_pcm_runtime *runtime = substream->runtime;
1313
1314 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1315 chip->capt.shift = 2;
1316 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1317 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1318 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1319 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1320
1321 return 0;
1322}
1323
1324static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1325{
1326 struct snd_cs46xx *chip = dev_id;
1327 u32 status1;
1328#ifdef CONFIG_SND_CS46XX_NEW_DSP
1329 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1330 u32 status2;
1331 int i;
1332 struct snd_cs46xx_pcm *cpcm = NULL;
1333#endif
1334
1335 /*
1336 * Read the Interrupt Status Register to clear the interrupt
1337 */
1338 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1339 if ((status1 & 0x7fffffff) == 0) {
1340 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1341 return IRQ_NONE;
1342 }
1343
1344#ifdef CONFIG_SND_CS46XX_NEW_DSP
1345 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1346
1347 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1348 if (i <= 15) {
1349 if ( status1 & (1 << i) ) {
1350 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1351 if (chip->capt.substream)
1352 snd_pcm_period_elapsed(chip->capt.substream);
1353 } else {
1354 if (ins->pcm_channels[i].active &&
1355 ins->pcm_channels[i].private_data &&
1356 !ins->pcm_channels[i].unlinked) {
1357 cpcm = ins->pcm_channels[i].private_data;
1358 snd_pcm_period_elapsed(cpcm->substream);
1359 }
1360 }
1361 }
1362 } else {
1363 if ( status2 & (1 << (i - 16))) {
1364 if (ins->pcm_channels[i].active &&
1365 ins->pcm_channels[i].private_data &&
1366 !ins->pcm_channels[i].unlinked) {
1367 cpcm = ins->pcm_channels[i].private_data;
1368 snd_pcm_period_elapsed(cpcm->substream);
1369 }
1370 }
1371 }
1372 }
1373
1374#else
1375 /* old dsp */
1376 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1377 if (chip->playback_pcm->substream)
1378 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1379 }
1380 if ((status1 & HISR_VC1) && chip->pcm) {
1381 if (chip->capt.substream)
1382 snd_pcm_period_elapsed(chip->capt.substream);
1383 }
1384#endif
1385
1386 if ((status1 & HISR_MIDI) && chip->rmidi) {
1387 unsigned char c;
1388
1389 spin_lock(&chip->reg_lock);
1390 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1391 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1392 if ((chip->midcr & MIDCR_RIE) == 0)
1393 continue;
1394 snd_rawmidi_receive(chip->midi_input, &c, 1);
1395 }
1396 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1397 if ((chip->midcr & MIDCR_TIE) == 0)
1398 break;
1399 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1400 chip->midcr &= ~MIDCR_TIE;
1401 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1402 break;
1403 }
1404 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1405 }
1406 spin_unlock(&chip->reg_lock);
1407 }
1408 /*
1409 * EOI to the PCI part....reenables interrupts
1410 */
1411 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1412
1413 return IRQ_HANDLED;
1414}
1415
1416static const struct snd_pcm_hardware snd_cs46xx_playback =
1417{
1418 .info = (SNDRV_PCM_INFO_MMAP |
1419 SNDRV_PCM_INFO_INTERLEAVED |
1420 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1421 /*SNDRV_PCM_INFO_RESUME*/ |
1422 SNDRV_PCM_INFO_SYNC_APPLPTR),
1423 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1424 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1425 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1426 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1427 .rate_min = 5500,
1428 .rate_max = 48000,
1429 .channels_min = 1,
1430 .channels_max = 2,
1431 .buffer_bytes_max = (256 * 1024),
1432 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1433 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1434 .periods_min = CS46XX_FRAGS,
1435 .periods_max = 1024,
1436 .fifo_size = 0,
1437};
1438
1439static const struct snd_pcm_hardware snd_cs46xx_capture =
1440{
1441 .info = (SNDRV_PCM_INFO_MMAP |
1442 SNDRV_PCM_INFO_INTERLEAVED |
1443 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1444 /*SNDRV_PCM_INFO_RESUME*/ |
1445 SNDRV_PCM_INFO_SYNC_APPLPTR),
1446 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1447 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1448 .rate_min = 5500,
1449 .rate_max = 48000,
1450 .channels_min = 2,
1451 .channels_max = 2,
1452 .buffer_bytes_max = (256 * 1024),
1453 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1454 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1455 .periods_min = CS46XX_FRAGS,
1456 .periods_max = 1024,
1457 .fifo_size = 0,
1458};
1459
1460#ifdef CONFIG_SND_CS46XX_NEW_DSP
1461
1462static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1463
1464static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1465 .count = ARRAY_SIZE(period_sizes),
1466 .list = period_sizes,
1467 .mask = 0
1468};
1469
1470#endif
1471
1472static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1473{
1474 kfree(runtime->private_data);
1475}
1476
1477static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1478{
1479 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1480 struct snd_cs46xx_pcm * cpcm;
1481 struct snd_pcm_runtime *runtime = substream->runtime;
1482
1483 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1484 if (cpcm == NULL)
1485 return -ENOMEM;
1486 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1487 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1488 kfree(cpcm);
1489 return -ENOMEM;
1490 }
1491
1492 runtime->hw = snd_cs46xx_playback;
1493 runtime->private_data = cpcm;
1494 runtime->private_free = snd_cs46xx_pcm_free_substream;
1495
1496 cpcm->substream = substream;
1497#ifdef CONFIG_SND_CS46XX_NEW_DSP
1498 mutex_lock(&chip->spos_mutex);
1499 cpcm->pcm_channel = NULL;
1500 cpcm->pcm_channel_id = pcm_channel_id;
1501
1502
1503 snd_pcm_hw_constraint_list(runtime, 0,
1504 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1505 &hw_constraints_period_sizes);
1506
1507 mutex_unlock(&chip->spos_mutex);
1508#else
1509 chip->playback_pcm = cpcm; /* HACK */
1510#endif
1511
1512 if (chip->accept_valid)
1513 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1514 chip->active_ctrl(chip, 1);
1515
1516 return 0;
1517}
1518
1519static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1520{
1521 dev_dbg(substream->pcm->card->dev, "open front channel\n");
1522 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1523}
1524
1525#ifdef CONFIG_SND_CS46XX_NEW_DSP
1526static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1527{
1528 dev_dbg(substream->pcm->card->dev, "open rear channel\n");
1529 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1530}
1531
1532static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1533{
1534 dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n");
1535 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1536}
1537
1538static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1539{
1540 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1541
1542 dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1543
1544 mutex_lock(&chip->spos_mutex);
1545 cs46xx_iec958_pre_open (chip);
1546 mutex_unlock(&chip->spos_mutex);
1547
1548 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1549}
1550
1551static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1552
1553static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1554{
1555 int err;
1556 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1557
1558 dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1559
1560 err = snd_cs46xx_playback_close(substream);
1561
1562 mutex_lock(&chip->spos_mutex);
1563 cs46xx_iec958_post_close (chip);
1564 mutex_unlock(&chip->spos_mutex);
1565
1566 return err;
1567}
1568#endif
1569
1570static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1571{
1572 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1573
1574 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1575 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1576 return -ENOMEM;
1577 chip->capt.substream = substream;
1578 substream->runtime->hw = snd_cs46xx_capture;
1579
1580 if (chip->accept_valid)
1581 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1582
1583 chip->active_ctrl(chip, 1);
1584
1585#ifdef CONFIG_SND_CS46XX_NEW_DSP
1586 snd_pcm_hw_constraint_list(substream->runtime, 0,
1587 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1588 &hw_constraints_period_sizes);
1589#endif
1590 return 0;
1591}
1592
1593static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1594{
1595 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1596 struct snd_pcm_runtime *runtime = substream->runtime;
1597 struct snd_cs46xx_pcm * cpcm;
1598
1599 cpcm = runtime->private_data;
1600
1601 /* when playback_open fails, then cpcm can be NULL */
1602 if (!cpcm) return -ENXIO;
1603
1604#ifdef CONFIG_SND_CS46XX_NEW_DSP
1605 mutex_lock(&chip->spos_mutex);
1606 if (cpcm->pcm_channel) {
1607 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1608 cpcm->pcm_channel = NULL;
1609 }
1610 mutex_unlock(&chip->spos_mutex);
1611#else
1612 chip->playback_pcm = NULL;
1613#endif
1614
1615 cpcm->substream = NULL;
1616 snd_dma_free_pages(&cpcm->hw_buf);
1617 chip->active_ctrl(chip, -1);
1618
1619 return 0;
1620}
1621
1622static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1623{
1624 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1625
1626 chip->capt.substream = NULL;
1627 snd_dma_free_pages(&chip->capt.hw_buf);
1628 chip->active_ctrl(chip, -1);
1629
1630 return 0;
1631}
1632
1633#ifdef CONFIG_SND_CS46XX_NEW_DSP
1634static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1635 .open = snd_cs46xx_playback_open_rear,
1636 .close = snd_cs46xx_playback_close,
1637 .hw_params = snd_cs46xx_playback_hw_params,
1638 .hw_free = snd_cs46xx_playback_hw_free,
1639 .prepare = snd_cs46xx_playback_prepare,
1640 .trigger = snd_cs46xx_playback_trigger,
1641 .pointer = snd_cs46xx_playback_direct_pointer,
1642};
1643
1644static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1645 .open = snd_cs46xx_playback_open_rear,
1646 .close = snd_cs46xx_playback_close,
1647 .hw_params = snd_cs46xx_playback_hw_params,
1648 .hw_free = snd_cs46xx_playback_hw_free,
1649 .prepare = snd_cs46xx_playback_prepare,
1650 .trigger = snd_cs46xx_playback_trigger,
1651 .pointer = snd_cs46xx_playback_indirect_pointer,
1652 .ack = snd_cs46xx_playback_transfer,
1653};
1654
1655static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1656 .open = snd_cs46xx_playback_open_clfe,
1657 .close = snd_cs46xx_playback_close,
1658 .hw_params = snd_cs46xx_playback_hw_params,
1659 .hw_free = snd_cs46xx_playback_hw_free,
1660 .prepare = snd_cs46xx_playback_prepare,
1661 .trigger = snd_cs46xx_playback_trigger,
1662 .pointer = snd_cs46xx_playback_direct_pointer,
1663};
1664
1665static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1666 .open = snd_cs46xx_playback_open_clfe,
1667 .close = snd_cs46xx_playback_close,
1668 .hw_params = snd_cs46xx_playback_hw_params,
1669 .hw_free = snd_cs46xx_playback_hw_free,
1670 .prepare = snd_cs46xx_playback_prepare,
1671 .trigger = snd_cs46xx_playback_trigger,
1672 .pointer = snd_cs46xx_playback_indirect_pointer,
1673 .ack = snd_cs46xx_playback_transfer,
1674};
1675
1676static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1677 .open = snd_cs46xx_playback_open_iec958,
1678 .close = snd_cs46xx_playback_close_iec958,
1679 .hw_params = snd_cs46xx_playback_hw_params,
1680 .hw_free = snd_cs46xx_playback_hw_free,
1681 .prepare = snd_cs46xx_playback_prepare,
1682 .trigger = snd_cs46xx_playback_trigger,
1683 .pointer = snd_cs46xx_playback_direct_pointer,
1684};
1685
1686static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1687 .open = snd_cs46xx_playback_open_iec958,
1688 .close = snd_cs46xx_playback_close_iec958,
1689 .hw_params = snd_cs46xx_playback_hw_params,
1690 .hw_free = snd_cs46xx_playback_hw_free,
1691 .prepare = snd_cs46xx_playback_prepare,
1692 .trigger = snd_cs46xx_playback_trigger,
1693 .pointer = snd_cs46xx_playback_indirect_pointer,
1694 .ack = snd_cs46xx_playback_transfer,
1695};
1696
1697#endif
1698
1699static const struct snd_pcm_ops snd_cs46xx_playback_ops = {
1700 .open = snd_cs46xx_playback_open,
1701 .close = snd_cs46xx_playback_close,
1702 .hw_params = snd_cs46xx_playback_hw_params,
1703 .hw_free = snd_cs46xx_playback_hw_free,
1704 .prepare = snd_cs46xx_playback_prepare,
1705 .trigger = snd_cs46xx_playback_trigger,
1706 .pointer = snd_cs46xx_playback_direct_pointer,
1707};
1708
1709static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1710 .open = snd_cs46xx_playback_open,
1711 .close = snd_cs46xx_playback_close,
1712 .hw_params = snd_cs46xx_playback_hw_params,
1713 .hw_free = snd_cs46xx_playback_hw_free,
1714 .prepare = snd_cs46xx_playback_prepare,
1715 .trigger = snd_cs46xx_playback_trigger,
1716 .pointer = snd_cs46xx_playback_indirect_pointer,
1717 .ack = snd_cs46xx_playback_transfer,
1718};
1719
1720static const struct snd_pcm_ops snd_cs46xx_capture_ops = {
1721 .open = snd_cs46xx_capture_open,
1722 .close = snd_cs46xx_capture_close,
1723 .hw_params = snd_cs46xx_capture_hw_params,
1724 .hw_free = snd_cs46xx_capture_hw_free,
1725 .prepare = snd_cs46xx_capture_prepare,
1726 .trigger = snd_cs46xx_capture_trigger,
1727 .pointer = snd_cs46xx_capture_direct_pointer,
1728};
1729
1730static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1731 .open = snd_cs46xx_capture_open,
1732 .close = snd_cs46xx_capture_close,
1733 .hw_params = snd_cs46xx_capture_hw_params,
1734 .hw_free = snd_cs46xx_capture_hw_free,
1735 .prepare = snd_cs46xx_capture_prepare,
1736 .trigger = snd_cs46xx_capture_trigger,
1737 .pointer = snd_cs46xx_capture_indirect_pointer,
1738 .ack = snd_cs46xx_capture_transfer,
1739};
1740
1741#ifdef CONFIG_SND_CS46XX_NEW_DSP
1742#define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1743#else
1744#define MAX_PLAYBACK_CHANNELS 1
1745#endif
1746
1747int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1748{
1749 struct snd_pcm *pcm;
1750 int err;
1751
1752 err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm);
1753 if (err < 0)
1754 return err;
1755
1756 pcm->private_data = chip;
1757
1758 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1759 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1760
1761 /* global setup */
1762 pcm->info_flags = 0;
1763 strcpy(pcm->name, "CS46xx");
1764 chip->pcm = pcm;
1765
1766 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1767 &chip->pci->dev,
1768 64*1024, 256*1024);
1769
1770 return 0;
1771}
1772
1773
1774#ifdef CONFIG_SND_CS46XX_NEW_DSP
1775int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1776{
1777 struct snd_pcm *pcm;
1778 int err;
1779
1780 err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1781 if (err < 0)
1782 return err;
1783
1784 pcm->private_data = chip;
1785
1786 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1787
1788 /* global setup */
1789 pcm->info_flags = 0;
1790 strcpy(pcm->name, "CS46xx - Rear");
1791 chip->pcm_rear = pcm;
1792
1793 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1794 &chip->pci->dev,
1795 64*1024, 256*1024);
1796
1797 return 0;
1798}
1799
1800int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1801{
1802 struct snd_pcm *pcm;
1803 int err;
1804
1805 err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1806 if (err < 0)
1807 return err;
1808
1809 pcm->private_data = chip;
1810
1811 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1812
1813 /* global setup */
1814 pcm->info_flags = 0;
1815 strcpy(pcm->name, "CS46xx - Center LFE");
1816 chip->pcm_center_lfe = pcm;
1817
1818 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1819 &chip->pci->dev,
1820 64*1024, 256*1024);
1821
1822 return 0;
1823}
1824
1825int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1826{
1827 struct snd_pcm *pcm;
1828 int err;
1829
1830 err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm);
1831 if (err < 0)
1832 return err;
1833
1834 pcm->private_data = chip;
1835
1836 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1837
1838 /* global setup */
1839 pcm->info_flags = 0;
1840 strcpy(pcm->name, "CS46xx - IEC958");
1841 chip->pcm_iec958 = pcm;
1842
1843 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1844 &chip->pci->dev,
1845 64*1024, 256*1024);
1846
1847 return 0;
1848}
1849#endif
1850
1851/*
1852 * Mixer routines
1853 */
1854static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1855{
1856 struct snd_cs46xx *chip = ac97->private_data;
1857
1858 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1859 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1860 return;
1861
1862 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1863 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1864 chip->eapd_switch = NULL;
1865 }
1866 else
1867 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1868}
1869
1870static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1871 struct snd_ctl_elem_info *uinfo)
1872{
1873 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1874 uinfo->count = 2;
1875 uinfo->value.integer.min = 0;
1876 uinfo->value.integer.max = 0x7fff;
1877 return 0;
1878}
1879
1880static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1881{
1882 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1883 int reg = kcontrol->private_value;
1884 unsigned int val = snd_cs46xx_peek(chip, reg);
1885 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1886 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1887 return 0;
1888}
1889
1890static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1891{
1892 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1893 int reg = kcontrol->private_value;
1894 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1895 (0xffff - ucontrol->value.integer.value[1]));
1896 unsigned int old = snd_cs46xx_peek(chip, reg);
1897 int change = (old != val);
1898
1899 if (change) {
1900 snd_cs46xx_poke(chip, reg, val);
1901 }
1902
1903 return change;
1904}
1905
1906#ifdef CONFIG_SND_CS46XX_NEW_DSP
1907
1908static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1909{
1910 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1911
1912 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1913 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1914
1915 return 0;
1916}
1917
1918static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1919{
1920 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1921 int change = 0;
1922
1923 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1924 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1925 cs46xx_dsp_set_dac_volume(chip,
1926 ucontrol->value.integer.value[0],
1927 ucontrol->value.integer.value[1]);
1928 change = 1;
1929 }
1930
1931 return change;
1932}
1933
1934#if 0
1935static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1936{
1937 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1938
1939 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1940 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1941 return 0;
1942}
1943
1944static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1945{
1946 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1947 int change = 0;
1948
1949 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1950 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1951 cs46xx_dsp_set_iec958_volume (chip,
1952 ucontrol->value.integer.value[0],
1953 ucontrol->value.integer.value[1]);
1954 change = 1;
1955 }
1956
1957 return change;
1958}
1959#endif
1960
1961#define snd_mixer_boolean_info snd_ctl_boolean_mono_info
1962
1963static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1964 struct snd_ctl_elem_value *ucontrol)
1965{
1966 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1967 int reg = kcontrol->private_value;
1968
1969 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1970 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1971 else
1972 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1973
1974 return 0;
1975}
1976
1977static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
1978 struct snd_ctl_elem_value *ucontrol)
1979{
1980 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1981 int change, res;
1982
1983 switch (kcontrol->private_value) {
1984 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1985 mutex_lock(&chip->spos_mutex);
1986 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1987 if (ucontrol->value.integer.value[0] && !change)
1988 cs46xx_dsp_enable_spdif_out(chip);
1989 else if (change && !ucontrol->value.integer.value[0])
1990 cs46xx_dsp_disable_spdif_out(chip);
1991
1992 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1993 mutex_unlock(&chip->spos_mutex);
1994 break;
1995 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
1996 change = chip->dsp_spos_instance->spdif_status_in;
1997 if (ucontrol->value.integer.value[0] && !change) {
1998 cs46xx_dsp_enable_spdif_in(chip);
1999 /* restore volume */
2000 }
2001 else if (change && !ucontrol->value.integer.value[0])
2002 cs46xx_dsp_disable_spdif_in(chip);
2003
2004 res = (change != chip->dsp_spos_instance->spdif_status_in);
2005 break;
2006 default:
2007 res = -EINVAL;
2008 snd_BUG(); /* should never happen ... */
2009 }
2010
2011 return res;
2012}
2013
2014static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
2015 struct snd_ctl_elem_value *ucontrol)
2016{
2017 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2018 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2019
2020 if (ins->adc_input != NULL)
2021 ucontrol->value.integer.value[0] = 1;
2022 else
2023 ucontrol->value.integer.value[0] = 0;
2024
2025 return 0;
2026}
2027
2028static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
2029 struct snd_ctl_elem_value *ucontrol)
2030{
2031 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2032 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2033 int change = 0;
2034
2035 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2036 cs46xx_dsp_enable_adc_capture(chip);
2037 change = 1;
2038 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2039 cs46xx_dsp_disable_adc_capture(chip);
2040 change = 1;
2041 }
2042 return change;
2043}
2044
2045static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
2046 struct snd_ctl_elem_value *ucontrol)
2047{
2048 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2049 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2050
2051 if (ins->pcm_input != NULL)
2052 ucontrol->value.integer.value[0] = 1;
2053 else
2054 ucontrol->value.integer.value[0] = 0;
2055
2056 return 0;
2057}
2058
2059
2060static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
2061 struct snd_ctl_elem_value *ucontrol)
2062{
2063 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2064 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2065 int change = 0;
2066
2067 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2068 cs46xx_dsp_enable_pcm_capture(chip);
2069 change = 1;
2070 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2071 cs46xx_dsp_disable_pcm_capture(chip);
2072 change = 1;
2073 }
2074
2075 return change;
2076}
2077
2078static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
2079 struct snd_ctl_elem_value *ucontrol)
2080{
2081 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2082
2083 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2084
2085 if (val1 & EGPIODR_GPOE0)
2086 ucontrol->value.integer.value[0] = 1;
2087 else
2088 ucontrol->value.integer.value[0] = 0;
2089
2090 return 0;
2091}
2092
2093/*
2094 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2095 */
2096static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
2097 struct snd_ctl_elem_value *ucontrol)
2098{
2099 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2100 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2101 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2102
2103 if (ucontrol->value.integer.value[0]) {
2104 /* optical is default */
2105 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2106 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
2107 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2108 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2109 } else {
2110 /* coaxial */
2111 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
2112 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2113 }
2114
2115 /* checking diff from the EGPIO direction register
2116 should be enough */
2117 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2118}
2119
2120
2121static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2122{
2123 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2124 uinfo->count = 1;
2125 return 0;
2126}
2127
2128static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2129 struct snd_ctl_elem_value *ucontrol)
2130{
2131 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2132 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2133
2134 mutex_lock(&chip->spos_mutex);
2135 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2136 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2137 ucontrol->value.iec958.status[2] = 0;
2138 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2139 mutex_unlock(&chip->spos_mutex);
2140
2141 return 0;
2142}
2143
2144static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2145 struct snd_ctl_elem_value *ucontrol)
2146{
2147 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2148 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2149 unsigned int val;
2150 int change;
2151
2152 mutex_lock(&chip->spos_mutex);
2153 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2154 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2155 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2156 /* left and right validity bit */
2157 (1 << 13) | (1 << 12);
2158
2159
2160 change = (unsigned int)ins->spdif_csuv_default != val;
2161 ins->spdif_csuv_default = val;
2162
2163 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2164 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2165
2166 mutex_unlock(&chip->spos_mutex);
2167
2168 return change;
2169}
2170
2171static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2172 struct snd_ctl_elem_value *ucontrol)
2173{
2174 ucontrol->value.iec958.status[0] = 0xff;
2175 ucontrol->value.iec958.status[1] = 0xff;
2176 ucontrol->value.iec958.status[2] = 0x00;
2177 ucontrol->value.iec958.status[3] = 0xff;
2178 return 0;
2179}
2180
2181static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2182 struct snd_ctl_elem_value *ucontrol)
2183{
2184 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2185 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2186
2187 mutex_lock(&chip->spos_mutex);
2188 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2189 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2190 ucontrol->value.iec958.status[2] = 0;
2191 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2192 mutex_unlock(&chip->spos_mutex);
2193
2194 return 0;
2195}
2196
2197static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2198 struct snd_ctl_elem_value *ucontrol)
2199{
2200 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2201 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2202 unsigned int val;
2203 int change;
2204
2205 mutex_lock(&chip->spos_mutex);
2206 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2207 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2208 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2209 /* left and right validity bit */
2210 (1 << 13) | (1 << 12);
2211
2212
2213 change = ins->spdif_csuv_stream != val;
2214 ins->spdif_csuv_stream = val;
2215
2216 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2217 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2218
2219 mutex_unlock(&chip->spos_mutex);
2220
2221 return change;
2222}
2223
2224#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2225
2226
2227static const struct snd_kcontrol_new snd_cs46xx_controls[] = {
2228{
2229 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2230 .name = "DAC Volume",
2231 .info = snd_cs46xx_vol_info,
2232#ifndef CONFIG_SND_CS46XX_NEW_DSP
2233 .get = snd_cs46xx_vol_get,
2234 .put = snd_cs46xx_vol_put,
2235 .private_value = BA1_PVOL,
2236#else
2237 .get = snd_cs46xx_vol_dac_get,
2238 .put = snd_cs46xx_vol_dac_put,
2239#endif
2240},
2241
2242{
2243 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2244 .name = "ADC Volume",
2245 .info = snd_cs46xx_vol_info,
2246 .get = snd_cs46xx_vol_get,
2247 .put = snd_cs46xx_vol_put,
2248#ifndef CONFIG_SND_CS46XX_NEW_DSP
2249 .private_value = BA1_CVOL,
2250#else
2251 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2252#endif
2253},
2254#ifdef CONFIG_SND_CS46XX_NEW_DSP
2255{
2256 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2257 .name = "ADC Capture Switch",
2258 .info = snd_mixer_boolean_info,
2259 .get = snd_cs46xx_adc_capture_get,
2260 .put = snd_cs46xx_adc_capture_put
2261},
2262{
2263 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2264 .name = "DAC Capture Switch",
2265 .info = snd_mixer_boolean_info,
2266 .get = snd_cs46xx_pcm_capture_get,
2267 .put = snd_cs46xx_pcm_capture_put
2268},
2269{
2270 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2271 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2272 .info = snd_mixer_boolean_info,
2273 .get = snd_cs46xx_iec958_get,
2274 .put = snd_cs46xx_iec958_put,
2275 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2276},
2277{
2278 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2279 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2280 .info = snd_mixer_boolean_info,
2281 .get = snd_cs46xx_iec958_get,
2282 .put = snd_cs46xx_iec958_put,
2283 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2284},
2285#if 0
2286/* Input IEC958 volume does not work for the moment. (Benny) */
2287{
2288 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2289 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2290 .info = snd_cs46xx_vol_info,
2291 .get = snd_cs46xx_vol_iec958_get,
2292 .put = snd_cs46xx_vol_iec958_put,
2293 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2294},
2295#endif
2296{
2297 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2298 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2299 .info = snd_cs46xx_spdif_info,
2300 .get = snd_cs46xx_spdif_default_get,
2301 .put = snd_cs46xx_spdif_default_put,
2302},
2303{
2304 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2305 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2306 .info = snd_cs46xx_spdif_info,
2307 .get = snd_cs46xx_spdif_mask_get,
2308 .access = SNDRV_CTL_ELEM_ACCESS_READ
2309},
2310{
2311 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2312 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2313 .info = snd_cs46xx_spdif_info,
2314 .get = snd_cs46xx_spdif_stream_get,
2315 .put = snd_cs46xx_spdif_stream_put
2316},
2317
2318#endif
2319};
2320
2321#ifdef CONFIG_SND_CS46XX_NEW_DSP
2322/* set primary cs4294 codec into Extended Audio Mode */
2323static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2324 struct snd_ctl_elem_value *ucontrol)
2325{
2326 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2327 unsigned short val;
2328 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2329 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2330 return 0;
2331}
2332
2333static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2334 struct snd_ctl_elem_value *ucontrol)
2335{
2336 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2337 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2338 AC97_CSR_ACMODE, 0x200,
2339 ucontrol->value.integer.value[0] ? 0 : 0x200);
2340}
2341
2342static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2343 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2344 .name = "Duplicate Front",
2345 .info = snd_mixer_boolean_info,
2346 .get = snd_cs46xx_front_dup_get,
2347 .put = snd_cs46xx_front_dup_put,
2348};
2349#endif
2350
2351#ifdef CONFIG_SND_CS46XX_NEW_DSP
2352/* Only available on the Hercules Game Theater XP soundcard */
2353static const struct snd_kcontrol_new snd_hercules_controls[] = {
2354{
2355 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2356 .name = "Optical/Coaxial SPDIF Input Switch",
2357 .info = snd_mixer_boolean_info,
2358 .get = snd_herc_spdif_select_get,
2359 .put = snd_herc_spdif_select_put,
2360},
2361};
2362
2363
2364static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2365{
2366 unsigned long end_time;
2367 int err;
2368
2369 /* reset to defaults */
2370 snd_ac97_write(ac97, AC97_RESET, 0);
2371
2372 /* set the desired CODEC mode */
2373 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2374 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0);
2375 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
2376 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2377 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3);
2378 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
2379 } else {
2380 snd_BUG(); /* should never happen ... */
2381 }
2382
2383 udelay(50);
2384
2385 /* it's necessary to wait awhile until registers are accessible after RESET */
2386 /* because the PCM or MASTER volume registers can be modified, */
2387 /* the REC_GAIN register is used for tests */
2388 end_time = jiffies + HZ;
2389 do {
2390 unsigned short ext_mid;
2391
2392 /* use preliminary reads to settle the communication */
2393 snd_ac97_read(ac97, AC97_RESET);
2394 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2395 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2396 /* modem? */
2397 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2398 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2399 return;
2400
2401 /* test if we can write to the record gain volume register */
2402 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
2403 err = snd_ac97_read(ac97, AC97_REC_GAIN);
2404 if (err == 0x8a05)
2405 return;
2406
2407 msleep(10);
2408 } while (time_after_eq(end_time, jiffies));
2409
2410 dev_err(ac97->bus->card->dev,
2411 "CS46xx secondary codec doesn't respond!\n");
2412}
2413#endif
2414
2415static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2416{
2417 int idx, err;
2418 struct snd_ac97_template ac97;
2419
2420 memset(&ac97, 0, sizeof(ac97));
2421 ac97.private_data = chip;
2422 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2423 ac97.num = codec;
2424 if (chip->amplifier_ctrl == amp_voyetra)
2425 ac97.scaps = AC97_SCAP_INV_EAPD;
2426
2427 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2428 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2429 udelay(10);
2430 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2431 dev_dbg(chip->card->dev,
2432 "secondary codec not present\n");
2433 return -ENXIO;
2434 }
2435 }
2436
2437 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2438 for (idx = 0; idx < 100; ++idx) {
2439 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2440 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2441 return err;
2442 }
2443 msleep(10);
2444 }
2445 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
2446 return -ENXIO;
2447}
2448
2449int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2450{
2451 struct snd_card *card = chip->card;
2452 int err;
2453 unsigned int idx;
2454 static const struct snd_ac97_bus_ops ops = {
2455#ifdef CONFIG_SND_CS46XX_NEW_DSP
2456 .reset = snd_cs46xx_codec_reset,
2457#endif
2458 .write = snd_cs46xx_ac97_write,
2459 .read = snd_cs46xx_ac97_read,
2460 };
2461
2462 /* detect primary codec */
2463 chip->nr_ac97_codecs = 0;
2464 dev_dbg(chip->card->dev, "detecting primary codec\n");
2465 err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
2466 if (err < 0)
2467 return err;
2468
2469 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2470 return -ENXIO;
2471 chip->nr_ac97_codecs = 1;
2472
2473#ifdef CONFIG_SND_CS46XX_NEW_DSP
2474 dev_dbg(chip->card->dev, "detecting secondary codec\n");
2475 /* try detect a secondary codec */
2476 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2477 chip->nr_ac97_codecs = 2;
2478#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2479
2480 /* add cs4630 mixer controls */
2481 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2482 struct snd_kcontrol *kctl;
2483 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2484 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2485 kctl->id.device = spdif_device;
2486 err = snd_ctl_add(card, kctl);
2487 if (err < 0)
2488 return err;
2489 }
2490
2491 /* get EAPD mixer switch (for voyetra hack) */
2492 chip->eapd_switch = snd_ctl_find_id_mixer(chip->card,
2493 "External Amplifier");
2494
2495#ifdef CONFIG_SND_CS46XX_NEW_DSP
2496 if (chip->nr_ac97_codecs == 1) {
2497 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2498 if ((id2 & 0xfff0) == 0x5920) { /* CS4294 and CS4298 */
2499 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2500 if (err < 0)
2501 return err;
2502 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2503 AC97_CSR_ACMODE, 0x200);
2504 }
2505 }
2506 /* do soundcard specific mixer setup */
2507 if (chip->mixer_init) {
2508 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
2509 chip->mixer_init(chip);
2510 }
2511#endif
2512
2513 /* turn on amplifier */
2514 chip->amplifier_ctrl(chip, 1);
2515
2516 return 0;
2517}
2518
2519/*
2520 * RawMIDI interface
2521 */
2522
2523static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2524{
2525 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2526 udelay(100);
2527 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2528}
2529
2530static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2531{
2532 struct snd_cs46xx *chip = substream->rmidi->private_data;
2533
2534 chip->active_ctrl(chip, 1);
2535 spin_lock_irq(&chip->reg_lock);
2536 chip->uartm |= CS46XX_MODE_INPUT;
2537 chip->midcr |= MIDCR_RXE;
2538 chip->midi_input = substream;
2539 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2540 snd_cs46xx_midi_reset(chip);
2541 } else {
2542 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2543 }
2544 spin_unlock_irq(&chip->reg_lock);
2545 return 0;
2546}
2547
2548static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2549{
2550 struct snd_cs46xx *chip = substream->rmidi->private_data;
2551
2552 spin_lock_irq(&chip->reg_lock);
2553 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2554 chip->midi_input = NULL;
2555 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2556 snd_cs46xx_midi_reset(chip);
2557 } else {
2558 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2559 }
2560 chip->uartm &= ~CS46XX_MODE_INPUT;
2561 spin_unlock_irq(&chip->reg_lock);
2562 chip->active_ctrl(chip, -1);
2563 return 0;
2564}
2565
2566static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2567{
2568 struct snd_cs46xx *chip = substream->rmidi->private_data;
2569
2570 chip->active_ctrl(chip, 1);
2571
2572 spin_lock_irq(&chip->reg_lock);
2573 chip->uartm |= CS46XX_MODE_OUTPUT;
2574 chip->midcr |= MIDCR_TXE;
2575 chip->midi_output = substream;
2576 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2577 snd_cs46xx_midi_reset(chip);
2578 } else {
2579 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2580 }
2581 spin_unlock_irq(&chip->reg_lock);
2582 return 0;
2583}
2584
2585static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2586{
2587 struct snd_cs46xx *chip = substream->rmidi->private_data;
2588
2589 spin_lock_irq(&chip->reg_lock);
2590 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2591 chip->midi_output = NULL;
2592 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2593 snd_cs46xx_midi_reset(chip);
2594 } else {
2595 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2596 }
2597 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2598 spin_unlock_irq(&chip->reg_lock);
2599 chip->active_ctrl(chip, -1);
2600 return 0;
2601}
2602
2603static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2604{
2605 unsigned long flags;
2606 struct snd_cs46xx *chip = substream->rmidi->private_data;
2607
2608 spin_lock_irqsave(&chip->reg_lock, flags);
2609 if (up) {
2610 if ((chip->midcr & MIDCR_RIE) == 0) {
2611 chip->midcr |= MIDCR_RIE;
2612 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2613 }
2614 } else {
2615 if (chip->midcr & MIDCR_RIE) {
2616 chip->midcr &= ~MIDCR_RIE;
2617 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2618 }
2619 }
2620 spin_unlock_irqrestore(&chip->reg_lock, flags);
2621}
2622
2623static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2624{
2625 unsigned long flags;
2626 struct snd_cs46xx *chip = substream->rmidi->private_data;
2627 unsigned char byte;
2628
2629 spin_lock_irqsave(&chip->reg_lock, flags);
2630 if (up) {
2631 if ((chip->midcr & MIDCR_TIE) == 0) {
2632 chip->midcr |= MIDCR_TIE;
2633 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2634 while ((chip->midcr & MIDCR_TIE) &&
2635 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2636 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2637 chip->midcr &= ~MIDCR_TIE;
2638 } else {
2639 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2640 }
2641 }
2642 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2643 }
2644 } else {
2645 if (chip->midcr & MIDCR_TIE) {
2646 chip->midcr &= ~MIDCR_TIE;
2647 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2648 }
2649 }
2650 spin_unlock_irqrestore(&chip->reg_lock, flags);
2651}
2652
2653static const struct snd_rawmidi_ops snd_cs46xx_midi_output =
2654{
2655 .open = snd_cs46xx_midi_output_open,
2656 .close = snd_cs46xx_midi_output_close,
2657 .trigger = snd_cs46xx_midi_output_trigger,
2658};
2659
2660static const struct snd_rawmidi_ops snd_cs46xx_midi_input =
2661{
2662 .open = snd_cs46xx_midi_input_open,
2663 .close = snd_cs46xx_midi_input_close,
2664 .trigger = snd_cs46xx_midi_input_trigger,
2665};
2666
2667int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
2668{
2669 struct snd_rawmidi *rmidi;
2670 int err;
2671
2672 err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi);
2673 if (err < 0)
2674 return err;
2675 strcpy(rmidi->name, "CS46XX");
2676 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2677 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2678 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2679 rmidi->private_data = chip;
2680 chip->rmidi = rmidi;
2681 return 0;
2682}
2683
2684
2685/*
2686 * gameport interface
2687 */
2688
2689#if IS_REACHABLE(CONFIG_GAMEPORT)
2690
2691static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2692{
2693 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2694
2695 if (snd_BUG_ON(!chip))
2696 return;
2697 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2698}
2699
2700static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2701{
2702 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2703
2704 if (snd_BUG_ON(!chip))
2705 return 0;
2706 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2707}
2708
2709static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2710{
2711 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2712 unsigned js1, js2, jst;
2713
2714 if (snd_BUG_ON(!chip))
2715 return 0;
2716
2717 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2718 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2719 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2720
2721 *buttons = (~jst >> 4) & 0x0F;
2722
2723 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2724 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2725 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2726 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2727
2728 for(jst=0;jst<4;++jst)
2729 if(axes[jst]==0xFFFF) axes[jst] = -1;
2730 return 0;
2731}
2732
2733static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2734{
2735 switch (mode) {
2736 case GAMEPORT_MODE_COOKED:
2737 return 0;
2738 case GAMEPORT_MODE_RAW:
2739 return 0;
2740 default:
2741 return -1;
2742 }
2743 return 0;
2744}
2745
2746int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2747{
2748 struct gameport *gp;
2749
2750 chip->gameport = gp = gameport_allocate_port();
2751 if (!gp) {
2752 dev_err(chip->card->dev,
2753 "cannot allocate memory for gameport\n");
2754 return -ENOMEM;
2755 }
2756
2757 gameport_set_name(gp, "CS46xx Gameport");
2758 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2759 gameport_set_dev_parent(gp, &chip->pci->dev);
2760 gameport_set_port_data(gp, chip);
2761
2762 gp->open = snd_cs46xx_gameport_open;
2763 gp->read = snd_cs46xx_gameport_read;
2764 gp->trigger = snd_cs46xx_gameport_trigger;
2765 gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2766
2767 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2768 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2769
2770 gameport_register_port(gp);
2771
2772 return 0;
2773}
2774
2775static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2776{
2777 if (chip->gameport) {
2778 gameport_unregister_port(chip->gameport);
2779 chip->gameport = NULL;
2780 }
2781}
2782#else
2783int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2784static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2785#endif /* CONFIG_GAMEPORT */
2786
2787#ifdef CONFIG_SND_PROC_FS
2788/*
2789 * proc interface
2790 */
2791
2792static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2793 void *file_private_data,
2794 struct file *file, char __user *buf,
2795 size_t count, loff_t pos)
2796{
2797 struct snd_cs46xx_region *region = entry->private_data;
2798
2799 if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2800 return -EFAULT;
2801 return count;
2802}
2803
2804static const struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2805 .read = snd_cs46xx_io_read,
2806};
2807
2808static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2809{
2810 struct snd_info_entry *entry;
2811 int idx;
2812
2813 for (idx = 0; idx < 5; idx++) {
2814 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2815 if (! snd_card_proc_new(card, region->name, &entry)) {
2816 entry->content = SNDRV_INFO_CONTENT_DATA;
2817 entry->private_data = chip;
2818 entry->c.ops = &snd_cs46xx_proc_io_ops;
2819 entry->size = region->size;
2820 entry->mode = S_IFREG | 0400;
2821 }
2822 }
2823#ifdef CONFIG_SND_CS46XX_NEW_DSP
2824 cs46xx_dsp_proc_init(card, chip);
2825#endif
2826 return 0;
2827}
2828
2829static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2830{
2831#ifdef CONFIG_SND_CS46XX_NEW_DSP
2832 cs46xx_dsp_proc_done(chip);
2833#endif
2834 return 0;
2835}
2836#else /* !CONFIG_SND_PROC_FS */
2837#define snd_cs46xx_proc_init(card, chip)
2838#define snd_cs46xx_proc_done(chip)
2839#endif
2840
2841/*
2842 * stop the h/w
2843 */
2844static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2845{
2846 unsigned int tmp;
2847
2848 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2849 tmp &= ~0x0000f03f;
2850 tmp |= 0x00000010;
2851 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2852
2853 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2854 tmp &= ~0x0000003f;
2855 tmp |= 0x00000011;
2856 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2857
2858 /*
2859 * Stop playback DMA.
2860 */
2861 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2862 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2863
2864 /*
2865 * Stop capture DMA.
2866 */
2867 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2868 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2869
2870 /*
2871 * Reset the processor.
2872 */
2873 snd_cs46xx_reset(chip);
2874
2875 snd_cs46xx_proc_stop(chip);
2876
2877 /*
2878 * Power down the PLL.
2879 */
2880 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2881
2882 /*
2883 * Turn off the Processor by turning off the software clock enable flag in
2884 * the clock control register.
2885 */
2886 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2887 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2888}
2889
2890
2891static void snd_cs46xx_free(struct snd_card *card)
2892{
2893 struct snd_cs46xx *chip = card->private_data;
2894#ifdef CONFIG_SND_CS46XX_NEW_DSP
2895 int idx;
2896#endif
2897
2898 if (chip->active_ctrl)
2899 chip->active_ctrl(chip, 1);
2900
2901 snd_cs46xx_remove_gameport(chip);
2902
2903 if (chip->amplifier_ctrl)
2904 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2905
2906 snd_cs46xx_proc_done(chip);
2907
2908 snd_cs46xx_hw_stop(chip);
2909
2910 if (chip->active_ctrl)
2911 chip->active_ctrl(chip, -chip->amplifier);
2912
2913#ifdef CONFIG_SND_CS46XX_NEW_DSP
2914 if (chip->dsp_spos_instance) {
2915 cs46xx_dsp_spos_destroy(chip);
2916 chip->dsp_spos_instance = NULL;
2917 }
2918 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2919 free_module_desc(chip->modules[idx]);
2920#else
2921 vfree(chip->ba1);
2922#endif
2923}
2924
2925/*
2926 * initialize chip
2927 */
2928static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2929{
2930 int timeout;
2931
2932 /*
2933 * First, blast the clock control register to zero so that the PLL starts
2934 * out in a known state, and blast the master serial port control register
2935 * to zero so that the serial ports also start out in a known state.
2936 */
2937 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2938 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2939
2940 /*
2941 * If we are in AC97 mode, then we must set the part to a host controlled
2942 * AC-link. Otherwise, we won't be able to bring up the link.
2943 */
2944#ifdef CONFIG_SND_CS46XX_NEW_DSP
2945 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2946 SERACC_TWO_CODECS); /* 2.00 dual codecs */
2947 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2948#else
2949 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2950#endif
2951
2952 /*
2953 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2954 * spec) and then drive it high. This is done for non AC97 modes since
2955 * there might be logic external to the CS461x that uses the ARST# line
2956 * for a reset.
2957 */
2958 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2959#ifdef CONFIG_SND_CS46XX_NEW_DSP
2960 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2961#endif
2962 udelay(50);
2963 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2964#ifdef CONFIG_SND_CS46XX_NEW_DSP
2965 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2966#endif
2967
2968 /*
2969 * The first thing we do here is to enable sync generation. As soon
2970 * as we start receiving bit clock, we'll start producing the SYNC
2971 * signal.
2972 */
2973 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2974#ifdef CONFIG_SND_CS46XX_NEW_DSP
2975 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2976#endif
2977
2978 /*
2979 * Now wait for a short while to allow the AC97 part to start
2980 * generating bit clock (so we don't try to start the PLL without an
2981 * input clock).
2982 */
2983 mdelay(10);
2984
2985 /*
2986 * Set the serial port timing configuration, so that
2987 * the clock control circuit gets its clock from the correct place.
2988 */
2989 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
2990
2991 /*
2992 * Write the selected clock control setup to the hardware. Do not turn on
2993 * SWCE yet (if requested), so that the devices clocked by the output of
2994 * PLL are not clocked until the PLL is stable.
2995 */
2996 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
2997 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
2998 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
2999
3000 /*
3001 * Power up the PLL.
3002 */
3003 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3004
3005 /*
3006 * Wait until the PLL has stabilized.
3007 */
3008 msleep(100);
3009
3010 /*
3011 * Turn on clocking of the core so that we can setup the serial ports.
3012 */
3013 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3014
3015 /*
3016 * Enable FIFO Host Bypass
3017 */
3018 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3019
3020 /*
3021 * Fill the serial port FIFOs with silence.
3022 */
3023 snd_cs46xx_clear_serial_FIFOs(chip);
3024
3025 /*
3026 * Set the serial port FIFO pointer to the first sample in the FIFO.
3027 */
3028 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3029
3030 /*
3031 * Write the serial port configuration to the part. The master
3032 * enable bit is not set until all other values have been written.
3033 */
3034 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3035 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3036 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3037
3038
3039#ifdef CONFIG_SND_CS46XX_NEW_DSP
3040 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3041 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3042 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3043 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3044 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3045#endif
3046
3047 mdelay(5);
3048
3049
3050 /*
3051 * Wait for the codec ready signal from the AC97 codec.
3052 */
3053 timeout = 150;
3054 while (timeout-- > 0) {
3055 /*
3056 * Read the AC97 status register to see if we've seen a CODEC READY
3057 * signal from the AC97 codec.
3058 */
3059 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3060 goto ok1;
3061 msleep(10);
3062 }
3063
3064
3065 dev_err(chip->card->dev,
3066 "create - never read codec ready from AC'97\n");
3067 dev_err(chip->card->dev,
3068 "it is not probably bug, try to use CS4236 driver\n");
3069 return -EIO;
3070 ok1:
3071#ifdef CONFIG_SND_CS46XX_NEW_DSP
3072 {
3073 int count;
3074 for (count = 0; count < 150; count++) {
3075 /* First, we want to wait for a short time. */
3076 udelay(25);
3077
3078 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3079 break;
3080 }
3081
3082 /*
3083 * Make sure CODEC is READY.
3084 */
3085 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3086 dev_dbg(chip->card->dev,
3087 "never read card ready from secondary AC'97\n");
3088 }
3089#endif
3090
3091 /*
3092 * Assert the vaid frame signal so that we can start sending commands
3093 * to the AC97 codec.
3094 */
3095 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3096#ifdef CONFIG_SND_CS46XX_NEW_DSP
3097 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3098#endif
3099
3100
3101 /*
3102 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3103 * the codec is pumping ADC data across the AC-link.
3104 */
3105 timeout = 150;
3106 while (timeout-- > 0) {
3107 /*
3108 * Read the input slot valid register and see if input slots 3 and
3109 * 4 are valid yet.
3110 */
3111 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3112 goto ok2;
3113 msleep(10);
3114 }
3115
3116#ifndef CONFIG_SND_CS46XX_NEW_DSP
3117 dev_err(chip->card->dev,
3118 "create - never read ISV3 & ISV4 from AC'97\n");
3119 return -EIO;
3120#else
3121 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3122 Reloading the driver may help, if there's other soundcards
3123 with the same problem I would like to know. (Benny) */
3124
3125 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3126 dev_err(chip->card->dev,
3127 "Try reloading the ALSA driver, if you find something\n");
3128 dev_err(chip->card->dev,
3129 "broken or not working on your soundcard upon\n");
3130 dev_err(chip->card->dev,
3131 "this message please report to alsa-devel@alsa-project.org\n");
3132
3133 return -EIO;
3134#endif
3135 ok2:
3136
3137 /*
3138 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3139 * commense the transfer of digital audio data to the AC97 codec.
3140 */
3141
3142 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3143
3144
3145 /*
3146 * Power down the DAC and ADC. We will power them up (if) when we need
3147 * them.
3148 */
3149 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3150
3151 /*
3152 * Turn off the Processor by turning off the software clock enable flag in
3153 * the clock control register.
3154 */
3155 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3156 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3157
3158 return 0;
3159}
3160
3161/*
3162 * start and load DSP
3163 */
3164
3165static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3166{
3167 unsigned int tmp;
3168
3169 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3170
3171 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3172 tmp &= ~0x0000f03f;
3173 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3174
3175 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3176 tmp &= ~0x0000003f;
3177 tmp |= 0x00000001;
3178 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3179}
3180
3181int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3182{
3183 unsigned int tmp;
3184#ifdef CONFIG_SND_CS46XX_NEW_DSP
3185 int i;
3186#endif
3187 int err;
3188
3189 /*
3190 * Reset the processor.
3191 */
3192 snd_cs46xx_reset(chip);
3193 /*
3194 * Download the image to the processor.
3195 */
3196#ifdef CONFIG_SND_CS46XX_NEW_DSP
3197 for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3198 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3199 if (err < 0) {
3200 dev_err(chip->card->dev, "firmware load error [%s]\n",
3201 module_names[i]);
3202 return err;
3203 }
3204 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3205 if (err < 0) {
3206 dev_err(chip->card->dev, "image download error [%s]\n",
3207 module_names[i]);
3208 return err;
3209 }
3210 }
3211
3212 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3213 return -EIO;
3214#else
3215 err = load_firmware(chip);
3216 if (err < 0)
3217 return err;
3218
3219 /* old image */
3220 err = snd_cs46xx_download_image(chip);
3221 if (err < 0) {
3222 dev_err(chip->card->dev, "image download error\n");
3223 return err;
3224 }
3225
3226 /*
3227 * Stop playback DMA.
3228 */
3229 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3230 chip->play_ctl = tmp & 0xffff0000;
3231 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3232#endif
3233
3234 /*
3235 * Stop capture DMA.
3236 */
3237 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3238 chip->capt.ctl = tmp & 0x0000ffff;
3239 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3240
3241 mdelay(5);
3242
3243 snd_cs46xx_set_play_sample_rate(chip, 8000);
3244 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3245
3246 snd_cs46xx_proc_start(chip);
3247
3248 cs46xx_enable_stream_irqs(chip);
3249
3250#ifndef CONFIG_SND_CS46XX_NEW_DSP
3251 /* set the attenuation to 0dB */
3252 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3253 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3254#endif
3255
3256 return 0;
3257}
3258
3259
3260/*
3261 * AMP control - null AMP
3262 */
3263
3264static void amp_none(struct snd_cs46xx *chip, int change)
3265{
3266}
3267
3268#ifdef CONFIG_SND_CS46XX_NEW_DSP
3269static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3270{
3271
3272 u32 idx, valid_slots,tmp,powerdown = 0;
3273 u16 modem_power,pin_config,logic_type;
3274
3275 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
3276
3277 /*
3278 * See if the devices are powered down. If so, we must power them up first
3279 * or they will not respond.
3280 */
3281 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3282
3283 if (!(tmp & CLKCR1_SWCE)) {
3284 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3285 powerdown = 1;
3286 }
3287
3288 /*
3289 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3290 * stuff.
3291 */
3292 if(chip->nr_ac97_codecs != 2) {
3293 dev_err(chip->card->dev,
3294 "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3295 return -EINVAL;
3296 }
3297
3298 modem_power = snd_cs46xx_codec_read (chip,
3299 AC97_EXTENDED_MSTATUS,
3300 CS46XX_SECONDARY_CODEC_INDEX);
3301 modem_power &=0xFEFF;
3302
3303 snd_cs46xx_codec_write(chip,
3304 AC97_EXTENDED_MSTATUS, modem_power,
3305 CS46XX_SECONDARY_CODEC_INDEX);
3306
3307 /*
3308 * Set GPIO pin's 7 and 8 so that they are configured for output.
3309 */
3310 pin_config = snd_cs46xx_codec_read (chip,
3311 AC97_GPIO_CFG,
3312 CS46XX_SECONDARY_CODEC_INDEX);
3313 pin_config &=0x27F;
3314
3315 snd_cs46xx_codec_write(chip,
3316 AC97_GPIO_CFG, pin_config,
3317 CS46XX_SECONDARY_CODEC_INDEX);
3318
3319 /*
3320 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3321 */
3322
3323 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3324 CS46XX_SECONDARY_CODEC_INDEX);
3325 logic_type &=0x27F;
3326
3327 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3328 CS46XX_SECONDARY_CODEC_INDEX);
3329
3330 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3331 valid_slots |= 0x200;
3332 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3333
3334 if ( cs46xx_wait_for_fifo(chip,1) ) {
3335 dev_dbg(chip->card->dev, "FIFO is busy\n");
3336
3337 return -EINVAL;
3338 }
3339
3340 /*
3341 * Fill slots 12 with the correct value for the GPIO pins.
3342 */
3343 for(idx = 0x90; idx <= 0x9F; idx++) {
3344 /*
3345 * Initialize the fifo so that bits 7 and 8 are on.
3346 *
3347 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3348 * the left. 0x1800 corresponds to bits 7 and 8.
3349 */
3350 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3351
3352 /*
3353 * Wait for command to complete
3354 */
3355 if ( cs46xx_wait_for_fifo(chip,200) ) {
3356 dev_dbg(chip->card->dev,
3357 "failed waiting for FIFO at addr (%02X)\n",
3358 idx);
3359
3360 return -EINVAL;
3361 }
3362
3363 /*
3364 * Write the serial port FIFO index.
3365 */
3366 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3367
3368 /*
3369 * Tell the serial port to load the new value into the FIFO location.
3370 */
3371 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3372 }
3373
3374 /* wait for last command to complete */
3375 cs46xx_wait_for_fifo(chip,200);
3376
3377 /*
3378 * Now, if we powered up the devices, then power them back down again.
3379 * This is kinda ugly, but should never happen.
3380 */
3381 if (powerdown)
3382 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3383
3384 return 0;
3385}
3386#endif
3387
3388/*
3389 * Crystal EAPD mode
3390 */
3391
3392static void amp_voyetra(struct snd_cs46xx *chip, int change)
3393{
3394 /* Manage the EAPD bit on the Crystal 4297
3395 and the Analog AD1885 */
3396
3397#ifdef CONFIG_SND_CS46XX_NEW_DSP
3398 int old = chip->amplifier;
3399#endif
3400 int oval, val;
3401
3402 chip->amplifier += change;
3403 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3404 CS46XX_PRIMARY_CODEC_INDEX);
3405 val = oval;
3406 if (chip->amplifier) {
3407 /* Turn the EAPD amp on */
3408 val |= 0x8000;
3409 } else {
3410 /* Turn the EAPD amp off */
3411 val &= ~0x8000;
3412 }
3413 if (val != oval) {
3414 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3415 CS46XX_PRIMARY_CODEC_INDEX);
3416 if (chip->eapd_switch)
3417 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3418 &chip->eapd_switch->id);
3419 }
3420
3421#ifdef CONFIG_SND_CS46XX_NEW_DSP
3422 if (chip->amplifier && !old) {
3423 voyetra_setup_eapd_slot(chip);
3424 }
3425#endif
3426}
3427
3428static void hercules_init(struct snd_cs46xx *chip)
3429{
3430 /* default: AMP off, and SPDIF input optical */
3431 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3432 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3433}
3434
3435
3436/*
3437 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3438 */
3439static void amp_hercules(struct snd_cs46xx *chip, int change)
3440{
3441 int old = chip->amplifier;
3442 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3443 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3444
3445 chip->amplifier += change;
3446 if (chip->amplifier && !old) {
3447 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
3448
3449 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3450 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3451 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3452 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3453 } else if (old && !chip->amplifier) {
3454 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
3455 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3456 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3457 }
3458}
3459
3460static void voyetra_mixer_init (struct snd_cs46xx *chip)
3461{
3462 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
3463
3464 /* Enable SPDIF out */
3465 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3466 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3467}
3468
3469static void hercules_mixer_init (struct snd_cs46xx *chip)
3470{
3471#ifdef CONFIG_SND_CS46XX_NEW_DSP
3472 unsigned int idx;
3473 int err;
3474 struct snd_card *card = chip->card;
3475#endif
3476
3477 /* set EGPIO to default */
3478 hercules_init(chip);
3479
3480 dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
3481
3482#ifdef CONFIG_SND_CS46XX_NEW_DSP
3483 if (chip->in_suspend)
3484 return;
3485
3486 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3487 struct snd_kcontrol *kctl;
3488
3489 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3490 err = snd_ctl_add(card, kctl);
3491 if (err < 0) {
3492 dev_err(card->dev,
3493 "failed to initialize Hercules mixer (%d)\n",
3494 err);
3495 break;
3496 }
3497 }
3498#endif
3499}
3500
3501
3502#if 0
3503/*
3504 * Untested
3505 */
3506
3507static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3508{
3509 chip->amplifier += change;
3510
3511 if (chip->amplifier) {
3512 /* Switch the GPIO pins 7 and 8 to open drain */
3513 snd_cs46xx_codec_write(chip, 0x4C,
3514 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3515 snd_cs46xx_codec_write(chip, 0x4E,
3516 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3517 /* Now wake the AMP (this might be backwards) */
3518 snd_cs46xx_codec_write(chip, 0x54,
3519 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3520 } else {
3521 snd_cs46xx_codec_write(chip, 0x54,
3522 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3523 }
3524}
3525#endif
3526
3527
3528/*
3529 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3530 * whenever we need to beat on the chip.
3531 *
3532 * The original idea and code for this hack comes from David Kaiser at
3533 * Linuxcare. Perhaps one day Crystal will document their chips well
3534 * enough to make them useful.
3535 */
3536
3537static void clkrun_hack(struct snd_cs46xx *chip, int change)
3538{
3539 u16 control, nval;
3540
3541 if (!chip->acpi_port)
3542 return;
3543
3544 chip->amplifier += change;
3545
3546 /* Read ACPI port */
3547 nval = control = inw(chip->acpi_port + 0x10);
3548
3549 /* Flip CLKRUN off while running */
3550 if (! chip->amplifier)
3551 nval |= 0x2000;
3552 else
3553 nval &= ~0x2000;
3554 if (nval != control)
3555 outw(nval, chip->acpi_port + 0x10);
3556}
3557
3558
3559/*
3560 * detect intel piix4
3561 */
3562static void clkrun_init(struct snd_cs46xx *chip)
3563{
3564 struct pci_dev *pdev;
3565 u8 pp;
3566
3567 chip->acpi_port = 0;
3568
3569 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3570 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3571 if (pdev == NULL)
3572 return; /* Not a thinkpad thats for sure */
3573
3574 /* Find the control port */
3575 pci_read_config_byte(pdev, 0x41, &pp);
3576 chip->acpi_port = pp << 8;
3577 pci_dev_put(pdev);
3578}
3579
3580
3581/*
3582 * Card subid table
3583 */
3584
3585struct cs_card_type
3586{
3587 u16 vendor;
3588 u16 id;
3589 char *name;
3590 void (*init)(struct snd_cs46xx *);
3591 void (*amp)(struct snd_cs46xx *, int);
3592 void (*active)(struct snd_cs46xx *, int);
3593 void (*mixer_init)(struct snd_cs46xx *);
3594};
3595
3596static struct cs_card_type cards[] = {
3597 {
3598 .vendor = 0x1489,
3599 .id = 0x7001,
3600 .name = "Genius Soundmaker 128 value",
3601 /* nothing special */
3602 },
3603 {
3604 .vendor = 0x5053,
3605 .id = 0x3357,
3606 .name = "Voyetra",
3607 .amp = amp_voyetra,
3608 .mixer_init = voyetra_mixer_init,
3609 },
3610 {
3611 .vendor = 0x1071,
3612 .id = 0x6003,
3613 .name = "Mitac MI6020/21",
3614 .amp = amp_voyetra,
3615 },
3616 /* Hercules Game Theatre XP */
3617 {
3618 .vendor = 0x14af, /* Guillemot Corporation */
3619 .id = 0x0050,
3620 .name = "Hercules Game Theatre XP",
3621 .amp = amp_hercules,
3622 .mixer_init = hercules_mixer_init,
3623 },
3624 {
3625 .vendor = 0x1681,
3626 .id = 0x0050,
3627 .name = "Hercules Game Theatre XP",
3628 .amp = amp_hercules,
3629 .mixer_init = hercules_mixer_init,
3630 },
3631 {
3632 .vendor = 0x1681,
3633 .id = 0x0051,
3634 .name = "Hercules Game Theatre XP",
3635 .amp = amp_hercules,
3636 .mixer_init = hercules_mixer_init,
3637
3638 },
3639 {
3640 .vendor = 0x1681,
3641 .id = 0x0052,
3642 .name = "Hercules Game Theatre XP",
3643 .amp = amp_hercules,
3644 .mixer_init = hercules_mixer_init,
3645 },
3646 {
3647 .vendor = 0x1681,
3648 .id = 0x0053,
3649 .name = "Hercules Game Theatre XP",
3650 .amp = amp_hercules,
3651 .mixer_init = hercules_mixer_init,
3652 },
3653 {
3654 .vendor = 0x1681,
3655 .id = 0x0054,
3656 .name = "Hercules Game Theatre XP",
3657 .amp = amp_hercules,
3658 .mixer_init = hercules_mixer_init,
3659 },
3660 /* Herculess Fortissimo */
3661 {
3662 .vendor = 0x1681,
3663 .id = 0xa010,
3664 .name = "Hercules Gamesurround Fortissimo II",
3665 },
3666 {
3667 .vendor = 0x1681,
3668 .id = 0xa011,
3669 .name = "Hercules Gamesurround Fortissimo III 7.1",
3670 },
3671 /* Teratec */
3672 {
3673 .vendor = 0x153b,
3674 .id = 0x112e,
3675 .name = "Terratec DMX XFire 1024",
3676 },
3677 {
3678 .vendor = 0x153b,
3679 .id = 0x1136,
3680 .name = "Terratec SiXPack 5.1",
3681 },
3682 /* Not sure if the 570 needs the clkrun hack */
3683 {
3684 .vendor = PCI_VENDOR_ID_IBM,
3685 .id = 0x0132,
3686 .name = "Thinkpad 570",
3687 .init = clkrun_init,
3688 .active = clkrun_hack,
3689 },
3690 {
3691 .vendor = PCI_VENDOR_ID_IBM,
3692 .id = 0x0153,
3693 .name = "Thinkpad 600X/A20/T20",
3694 .init = clkrun_init,
3695 .active = clkrun_hack,
3696 },
3697 {
3698 .vendor = PCI_VENDOR_ID_IBM,
3699 .id = 0x1010,
3700 .name = "Thinkpad 600E (unsupported)",
3701 },
3702 {} /* terminator */
3703};
3704
3705
3706/*
3707 * APM support
3708 */
3709#ifdef CONFIG_PM_SLEEP
3710static const unsigned int saved_regs[] = {
3711 BA0_ACOSV,
3712 /*BA0_ASER_FADDR,*/
3713 BA0_ASER_MASTER,
3714 BA1_PVOL,
3715 BA1_CVOL,
3716};
3717
3718static int snd_cs46xx_suspend(struct device *dev)
3719{
3720 struct snd_card *card = dev_get_drvdata(dev);
3721 struct snd_cs46xx *chip = card->private_data;
3722 int i, amp_saved;
3723
3724 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3725 chip->in_suspend = 1;
3726 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3727 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3728
3729 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3730 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3731
3732 /* save some registers */
3733 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3734 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3735
3736 amp_saved = chip->amplifier;
3737 /* turn off amp */
3738 chip->amplifier_ctrl(chip, -chip->amplifier);
3739 snd_cs46xx_hw_stop(chip);
3740 /* disable CLKRUN */
3741 chip->active_ctrl(chip, -chip->amplifier);
3742 chip->amplifier = amp_saved; /* restore the status */
3743 return 0;
3744}
3745
3746static int snd_cs46xx_resume(struct device *dev)
3747{
3748 struct snd_card *card = dev_get_drvdata(dev);
3749 struct snd_cs46xx *chip = card->private_data;
3750 int amp_saved;
3751#ifdef CONFIG_SND_CS46XX_NEW_DSP
3752 int i;
3753#endif
3754 unsigned int tmp;
3755
3756 amp_saved = chip->amplifier;
3757 chip->amplifier = 0;
3758 chip->active_ctrl(chip, 1); /* force to on */
3759
3760 snd_cs46xx_chip_init(chip);
3761
3762 snd_cs46xx_reset(chip);
3763#ifdef CONFIG_SND_CS46XX_NEW_DSP
3764 cs46xx_dsp_resume(chip);
3765 /* restore some registers */
3766 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3767 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3768#else
3769 snd_cs46xx_download_image(chip);
3770#endif
3771
3772#if 0
3773 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3774 chip->ac97_general_purpose);
3775 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3776 chip->ac97_powerdown);
3777 mdelay(10);
3778 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3779 chip->ac97_powerdown);
3780 mdelay(5);
3781#endif
3782
3783 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3784 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3785
3786 /*
3787 * Stop capture DMA.
3788 */
3789 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3790 chip->capt.ctl = tmp & 0x0000ffff;
3791 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3792
3793 mdelay(5);
3794
3795 /* reset playback/capture */
3796 snd_cs46xx_set_play_sample_rate(chip, 8000);
3797 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3798 snd_cs46xx_proc_start(chip);
3799
3800 cs46xx_enable_stream_irqs(chip);
3801
3802 if (amp_saved)
3803 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3804 else
3805 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3806 chip->amplifier = amp_saved;
3807 chip->in_suspend = 0;
3808 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3809 return 0;
3810}
3811
3812SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
3813#endif /* CONFIG_PM_SLEEP */
3814
3815
3816/*
3817 */
3818
3819int snd_cs46xx_create(struct snd_card *card,
3820 struct pci_dev *pci,
3821 int external_amp, int thinkpad)
3822{
3823 struct snd_cs46xx *chip = card->private_data;
3824 int err, idx;
3825 struct snd_cs46xx_region *region;
3826 struct cs_card_type *cp;
3827 u16 ss_card, ss_vendor;
3828
3829 /* enable PCI device */
3830 err = pcim_enable_device(pci);
3831 if (err < 0)
3832 return err;
3833
3834 spin_lock_init(&chip->reg_lock);
3835#ifdef CONFIG_SND_CS46XX_NEW_DSP
3836 mutex_init(&chip->spos_mutex);
3837#endif
3838 chip->card = card;
3839 chip->pci = pci;
3840 chip->irq = -1;
3841
3842 err = pci_request_regions(pci, "CS46xx");
3843 if (err < 0)
3844 return err;
3845 chip->ba0_addr = pci_resource_start(pci, 0);
3846 chip->ba1_addr = pci_resource_start(pci, 1);
3847 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3848 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3849 dev_err(chip->card->dev,
3850 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3851 chip->ba0_addr, chip->ba1_addr);
3852 return -ENOMEM;
3853 }
3854
3855 region = &chip->region.name.ba0;
3856 strcpy(region->name, "CS46xx_BA0");
3857 region->base = chip->ba0_addr;
3858 region->size = CS46XX_BA0_SIZE;
3859
3860 region = &chip->region.name.data0;
3861 strcpy(region->name, "CS46xx_BA1_data0");
3862 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3863 region->size = CS46XX_BA1_DATA0_SIZE;
3864
3865 region = &chip->region.name.data1;
3866 strcpy(region->name, "CS46xx_BA1_data1");
3867 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3868 region->size = CS46XX_BA1_DATA1_SIZE;
3869
3870 region = &chip->region.name.pmem;
3871 strcpy(region->name, "CS46xx_BA1_pmem");
3872 region->base = chip->ba1_addr + BA1_SP_PMEM;
3873 region->size = CS46XX_BA1_PRG_SIZE;
3874
3875 region = &chip->region.name.reg;
3876 strcpy(region->name, "CS46xx_BA1_reg");
3877 region->base = chip->ba1_addr + BA1_SP_REG;
3878 region->size = CS46XX_BA1_REG_SIZE;
3879
3880 /* set up amp and clkrun hack */
3881 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3882 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3883
3884 for (cp = &cards[0]; cp->name; cp++) {
3885 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3886 dev_dbg(chip->card->dev, "hack for %s enabled\n",
3887 cp->name);
3888
3889 chip->amplifier_ctrl = cp->amp;
3890 chip->active_ctrl = cp->active;
3891 chip->mixer_init = cp->mixer_init;
3892
3893 if (cp->init)
3894 cp->init(chip);
3895 break;
3896 }
3897 }
3898
3899 if (external_amp) {
3900 dev_info(chip->card->dev,
3901 "Crystal EAPD support forced on.\n");
3902 chip->amplifier_ctrl = amp_voyetra;
3903 }
3904
3905 if (thinkpad) {
3906 dev_info(chip->card->dev,
3907 "Activating CLKRUN hack for Thinkpad.\n");
3908 chip->active_ctrl = clkrun_hack;
3909 clkrun_init(chip);
3910 }
3911
3912 if (chip->amplifier_ctrl == NULL)
3913 chip->amplifier_ctrl = amp_none;
3914 if (chip->active_ctrl == NULL)
3915 chip->active_ctrl = amp_none;
3916
3917 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3918
3919 pci_set_master(pci);
3920
3921 for (idx = 0; idx < 5; idx++) {
3922 region = &chip->region.idx[idx];
3923 region->remap_addr = devm_ioremap(&pci->dev, region->base,
3924 region->size);
3925 if (region->remap_addr == NULL) {
3926 dev_err(chip->card->dev,
3927 "%s ioremap problem\n", region->name);
3928 return -ENOMEM;
3929 }
3930 }
3931
3932 if (devm_request_irq(&pci->dev, pci->irq, snd_cs46xx_interrupt,
3933 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3934 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
3935 return -EBUSY;
3936 }
3937 chip->irq = pci->irq;
3938 card->sync_irq = chip->irq;
3939 card->private_free = snd_cs46xx_free;
3940
3941#ifdef CONFIG_SND_CS46XX_NEW_DSP
3942 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3943 if (!chip->dsp_spos_instance)
3944 return -ENOMEM;
3945#endif
3946
3947 err = snd_cs46xx_chip_init(chip);
3948 if (err < 0)
3949 return err;
3950
3951 snd_cs46xx_proc_init(card, chip);
3952
3953#ifdef CONFIG_PM_SLEEP
3954 chip->saved_regs = devm_kmalloc_array(&pci->dev,
3955 ARRAY_SIZE(saved_regs),
3956 sizeof(*chip->saved_regs),
3957 GFP_KERNEL);
3958 if (!chip->saved_regs)
3959 return -ENOMEM;
3960#endif
3961
3962 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3963 return 0;
3964}