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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * ca91c042.h
4 *
5 * Support for the Tundra Universe 1 and Universe II VME bridge chips
6 *
7 * Author: Tom Armistead
8 * Updated by Ajit Prem
9 * Copyright 2004 Motorola Inc.
10 *
11 * Further updated by Martyn Welch <martyn.welch@ge.com>
12 * Copyright 2009 GE Intelligent Platforms Embedded Systems, Inc.
13 *
14 * Derived from ca91c042.h by Michael Wyrick
15 */
16
17#ifndef _CA91CX42_H
18#define _CA91CX42_H
19
20#ifndef PCI_VENDOR_ID_TUNDRA
21#define PCI_VENDOR_ID_TUNDRA 0x10e3
22#endif
23
24#ifndef PCI_DEVICE_ID_TUNDRA_CA91C142
25#define PCI_DEVICE_ID_TUNDRA_CA91C142 0x0000
26#endif
27
28/*
29 * Define the number of each that the CA91C142 supports.
30 */
31#define CA91C142_MAX_MASTER 8 /* Max Master Windows */
32#define CA91C142_MAX_SLAVE 8 /* Max Slave Windows */
33#define CA91C142_MAX_DMA 1 /* Max DMA Controllers */
34#define CA91C142_MAX_MAILBOX 4 /* Max Mail Box registers */
35
36/* Structure used to hold driver specific information */
37struct ca91cx42_driver {
38 void __iomem *base; /* Base Address of device registers */
39 wait_queue_head_t dma_queue;
40 wait_queue_head_t iack_queue;
41 wait_queue_head_t mbox_queue;
42 void (*lm_callback[4])(void *); /* Called in interrupt handler */
43 void *lm_data[4];
44 void *crcsr_kernel;
45 dma_addr_t crcsr_bus;
46 struct mutex vme_rmw; /* Only one RMW cycle at a time */
47 struct mutex vme_int; /*
48 * Only one VME interrupt can be
49 * generated at a time, provide locking
50 */
51};
52
53/* See Page 2-77 in the Universe User Manual */
54struct ca91cx42_dma_descriptor {
55 unsigned int dctl; /* DMA Control */
56 unsigned int dtbc; /* Transfer Byte Count */
57 unsigned int dla; /* PCI Address */
58 unsigned int res1; /* Reserved */
59 unsigned int dva; /* Vme Address */
60 unsigned int res2; /* Reserved */
61 unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */
62 unsigned int res3; /* Reserved */
63};
64
65struct ca91cx42_dma_entry {
66 struct ca91cx42_dma_descriptor descriptor;
67 struct list_head list;
68};
69
70/* Universe Register Offsets */
71/* general PCI configuration registers */
72#define CA91CX42_PCI_ID 0x000
73#define CA91CX42_PCI_CSR 0x004
74#define CA91CX42_PCI_CLASS 0x008
75#define CA91CX42_PCI_MISC0 0x00C
76#define CA91CX42_PCI_BS 0x010
77#define CA91CX42_PCI_MISC1 0x03C
78
79#define LSI0_CTL 0x0100
80#define LSI0_BS 0x0104
81#define LSI0_BD 0x0108
82#define LSI0_TO 0x010C
83
84#define LSI1_CTL 0x0114
85#define LSI1_BS 0x0118
86#define LSI1_BD 0x011C
87#define LSI1_TO 0x0120
88
89#define LSI2_CTL 0x0128
90#define LSI2_BS 0x012C
91#define LSI2_BD 0x0130
92#define LSI2_TO 0x0134
93
94#define LSI3_CTL 0x013C
95#define LSI3_BS 0x0140
96#define LSI3_BD 0x0144
97#define LSI3_TO 0x0148
98
99#define LSI4_CTL 0x01A0
100#define LSI4_BS 0x01A4
101#define LSI4_BD 0x01A8
102#define LSI4_TO 0x01AC
103
104#define LSI5_CTL 0x01B4
105#define LSI5_BS 0x01B8
106#define LSI5_BD 0x01BC
107#define LSI5_TO 0x01C0
108
109#define LSI6_CTL 0x01C8
110#define LSI6_BS 0x01CC
111#define LSI6_BD 0x01D0
112#define LSI6_TO 0x01D4
113
114#define LSI7_CTL 0x01DC
115#define LSI7_BS 0x01E0
116#define LSI7_BD 0x01E4
117#define LSI7_TO 0x01E8
118
119static const int CA91CX42_LSI_CTL[] = { LSI0_CTL, LSI1_CTL, LSI2_CTL, LSI3_CTL,
120 LSI4_CTL, LSI5_CTL, LSI6_CTL, LSI7_CTL };
121
122static const int CA91CX42_LSI_BS[] = { LSI0_BS, LSI1_BS, LSI2_BS, LSI3_BS,
123 LSI4_BS, LSI5_BS, LSI6_BS, LSI7_BS };
124
125static const int CA91CX42_LSI_BD[] = { LSI0_BD, LSI1_BD, LSI2_BD, LSI3_BD,
126 LSI4_BD, LSI5_BD, LSI6_BD, LSI7_BD };
127
128static const int CA91CX42_LSI_TO[] = { LSI0_TO, LSI1_TO, LSI2_TO, LSI3_TO,
129 LSI4_TO, LSI5_TO, LSI6_TO, LSI7_TO };
130
131#define SCYC_CTL 0x0170
132#define SCYC_ADDR 0x0174
133#define SCYC_EN 0x0178
134#define SCYC_CMP 0x017C
135#define SCYC_SWP 0x0180
136#define LMISC 0x0184
137#define SLSI 0x0188
138#define L_CMDERR 0x018C
139#define LAERR 0x0190
140
141#define DCTL 0x0200
142#define DTBC 0x0204
143#define DLA 0x0208
144#define DVA 0x0210
145#define DCPP 0x0218
146#define DGCS 0x0220
147#define D_LLUE 0x0224
148
149#define LINT_EN 0x0300
150#define LINT_STAT 0x0304
151#define LINT_MAP0 0x0308
152#define LINT_MAP1 0x030C
153#define VINT_EN 0x0310
154#define VINT_STAT 0x0314
155#define VINT_MAP0 0x0318
156#define VINT_MAP1 0x031C
157#define STATID 0x0320
158
159#define V1_STATID 0x0324
160#define V2_STATID 0x0328
161#define V3_STATID 0x032C
162#define V4_STATID 0x0330
163#define V5_STATID 0x0334
164#define V6_STATID 0x0338
165#define V7_STATID 0x033C
166
167static const int CA91CX42_V_STATID[8] = { 0, V1_STATID, V2_STATID, V3_STATID,
168 V4_STATID, V5_STATID, V6_STATID,
169 V7_STATID };
170
171#define LINT_MAP2 0x0340
172#define VINT_MAP2 0x0344
173
174#define MBOX0 0x0348
175#define MBOX1 0x034C
176#define MBOX2 0x0350
177#define MBOX3 0x0354
178#define SEMA0 0x0358
179#define SEMA1 0x035C
180
181#define MAST_CTL 0x0400
182#define MISC_CTL 0x0404
183#define MISC_STAT 0x0408
184#define USER_AM 0x040C
185
186#define VSI0_CTL 0x0F00
187#define VSI0_BS 0x0F04
188#define VSI0_BD 0x0F08
189#define VSI0_TO 0x0F0C
190
191#define VSI1_CTL 0x0F14
192#define VSI1_BS 0x0F18
193#define VSI1_BD 0x0F1C
194#define VSI1_TO 0x0F20
195
196#define VSI2_CTL 0x0F28
197#define VSI2_BS 0x0F2C
198#define VSI2_BD 0x0F30
199#define VSI2_TO 0x0F34
200
201#define VSI3_CTL 0x0F3C
202#define VSI3_BS 0x0F40
203#define VSI3_BD 0x0F44
204#define VSI3_TO 0x0F48
205
206#define LM_CTL 0x0F64
207#define LM_BS 0x0F68
208
209#define VRAI_CTL 0x0F70
210
211#define VRAI_BS 0x0F74
212#define VCSR_CTL 0x0F80
213#define VCSR_TO 0x0F84
214#define V_AMERR 0x0F88
215#define VAERR 0x0F8C
216
217#define VSI4_CTL 0x0F90
218#define VSI4_BS 0x0F94
219#define VSI4_BD 0x0F98
220#define VSI4_TO 0x0F9C
221
222#define VSI5_CTL 0x0FA4
223#define VSI5_BS 0x0FA8
224#define VSI5_BD 0x0FAC
225#define VSI5_TO 0x0FB0
226
227#define VSI6_CTL 0x0FB8
228#define VSI6_BS 0x0FBC
229#define VSI6_BD 0x0FC0
230#define VSI6_TO 0x0FC4
231
232#define VSI7_CTL 0x0FCC
233#define VSI7_BS 0x0FD0
234#define VSI7_BD 0x0FD4
235#define VSI7_TO 0x0FD8
236
237static const int CA91CX42_VSI_CTL[] = { VSI0_CTL, VSI1_CTL, VSI2_CTL, VSI3_CTL,
238 VSI4_CTL, VSI5_CTL, VSI6_CTL, VSI7_CTL };
239
240static const int CA91CX42_VSI_BS[] = { VSI0_BS, VSI1_BS, VSI2_BS, VSI3_BS,
241 VSI4_BS, VSI5_BS, VSI6_BS, VSI7_BS };
242
243static const int CA91CX42_VSI_BD[] = { VSI0_BD, VSI1_BD, VSI2_BD, VSI3_BD,
244 VSI4_BD, VSI5_BD, VSI6_BD, VSI7_BD };
245
246static const int CA91CX42_VSI_TO[] = { VSI0_TO, VSI1_TO, VSI2_TO, VSI3_TO,
247 VSI4_TO, VSI5_TO, VSI6_TO, VSI7_TO };
248
249#define VCSR_CLR 0x0FF4
250#define VCSR_SET 0x0FF8
251#define VCSR_BS 0x0FFC
252
253/*
254 * PCI Class Register
255 * offset 008
256 */
257#define CA91CX42_BM_PCI_CLASS_BASE 0xFF000000
258#define CA91CX42_OF_PCI_CLASS_BASE 24
259#define CA91CX42_BM_PCI_CLASS_SUB 0x00FF0000
260#define CA91CX42_OF_PCI_CLASS_SUB 16
261#define CA91CX42_BM_PCI_CLASS_PROG 0x0000FF00
262#define CA91CX42_OF_PCI_CLASS_PROG 8
263#define CA91CX42_BM_PCI_CLASS_RID 0x000000FF
264#define CA91CX42_OF_PCI_CLASS_RID 0
265
266#define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_I 0
267#define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_II 1
268
269/*
270 * PCI Misc Register
271 * offset 00C
272 */
273#define CA91CX42_BM_PCI_MISC0_BISTC 0x80000000
274#define CA91CX42_BM_PCI_MISC0_SBIST 0x60000000
275#define CA91CX42_BM_PCI_MISC0_CCODE 0x0F000000
276#define CA91CX42_BM_PCI_MISC0_MFUNCT 0x00800000
277#define CA91CX42_BM_PCI_MISC0_LAYOUT 0x007F0000
278#define CA91CX42_BM_PCI_MISC0_LTIMER 0x0000FF00
279#define CA91CX42_OF_PCI_MISC0_LTIMER 8
280
281
282/*
283 * LSI Control Register
284 * offset 100
285 */
286#define CA91CX42_LSI_CTL_EN (1<<31)
287#define CA91CX42_LSI_CTL_PWEN (1<<30)
288
289#define CA91CX42_LSI_CTL_VDW_M (3<<22)
290#define CA91CX42_LSI_CTL_VDW_D8 0
291#define CA91CX42_LSI_CTL_VDW_D16 (1<<22)
292#define CA91CX42_LSI_CTL_VDW_D32 (1<<23)
293#define CA91CX42_LSI_CTL_VDW_D64 (3<<22)
294
295#define CA91CX42_LSI_CTL_VAS_M (7<<16)
296#define CA91CX42_LSI_CTL_VAS_A16 0
297#define CA91CX42_LSI_CTL_VAS_A24 (1<<16)
298#define CA91CX42_LSI_CTL_VAS_A32 (1<<17)
299#define CA91CX42_LSI_CTL_VAS_CRCSR (5<<16)
300#define CA91CX42_LSI_CTL_VAS_USER1 (3<<17)
301#define CA91CX42_LSI_CTL_VAS_USER2 (7<<16)
302
303#define CA91CX42_LSI_CTL_PGM_M (1<<14)
304#define CA91CX42_LSI_CTL_PGM_DATA 0
305#define CA91CX42_LSI_CTL_PGM_PGM (1<<14)
306
307#define CA91CX42_LSI_CTL_SUPER_M (1<<12)
308#define CA91CX42_LSI_CTL_SUPER_NPRIV 0
309#define CA91CX42_LSI_CTL_SUPER_SUPR (1<<12)
310
311#define CA91CX42_LSI_CTL_VCT_M (1<<8)
312#define CA91CX42_LSI_CTL_VCT_BLT (1<<8)
313#define CA91CX42_LSI_CTL_VCT_MBLT (1<<8)
314#define CA91CX42_LSI_CTL_LAS (1<<0)
315
316/*
317 * SCYC_CTL Register
318 * offset 178
319 */
320#define CA91CX42_SCYC_CTL_LAS_PCIMEM 0
321#define CA91CX42_SCYC_CTL_LAS_PCIIO (1<<2)
322
323#define CA91CX42_SCYC_CTL_CYC_M (3<<0)
324#define CA91CX42_SCYC_CTL_CYC_RMW (1<<0)
325#define CA91CX42_SCYC_CTL_CYC_ADOH (1<<1)
326
327/*
328 * LMISC Register
329 * offset 184
330 */
331#define CA91CX42_BM_LMISC_CRT 0xF0000000
332#define CA91CX42_OF_LMISC_CRT 28
333#define CA91CX42_BM_LMISC_CWT 0x0F000000
334#define CA91CX42_OF_LMISC_CWT 24
335
336/*
337 * SLSI Register
338 * offset 188
339 */
340#define CA91CX42_BM_SLSI_EN 0x80000000
341#define CA91CX42_BM_SLSI_PWEN 0x40000000
342#define CA91CX42_BM_SLSI_VDW 0x00F00000
343#define CA91CX42_OF_SLSI_VDW 20
344#define CA91CX42_BM_SLSI_PGM 0x0000F000
345#define CA91CX42_OF_SLSI_PGM 12
346#define CA91CX42_BM_SLSI_SUPER 0x00000F00
347#define CA91CX42_OF_SLSI_SUPER 8
348#define CA91CX42_BM_SLSI_BS 0x000000F6
349#define CA91CX42_OF_SLSI_BS 2
350#define CA91CX42_BM_SLSI_LAS 0x00000003
351#define CA91CX42_OF_SLSI_LAS 0
352#define CA91CX42_BM_SLSI_RESERVED 0x3F0F0000
353
354/*
355 * DCTL Register
356 * offset 200
357 */
358#define CA91CX42_DCTL_L2V (1<<31)
359#define CA91CX42_DCTL_VDW_M (3<<22)
360#define CA91CX42_DCTL_VDW_D8 0
361#define CA91CX42_DCTL_VDW_D16 (1<<22)
362#define CA91CX42_DCTL_VDW_D32 (1<<23)
363#define CA91CX42_DCTL_VDW_D64 (3<<22)
364
365#define CA91CX42_DCTL_VAS_M (7<<16)
366#define CA91CX42_DCTL_VAS_A16 0
367#define CA91CX42_DCTL_VAS_A24 (1<<16)
368#define CA91CX42_DCTL_VAS_A32 (1<<17)
369#define CA91CX42_DCTL_VAS_USER1 (3<<17)
370#define CA91CX42_DCTL_VAS_USER2 (7<<16)
371
372#define CA91CX42_DCTL_PGM_M (1<<14)
373#define CA91CX42_DCTL_PGM_DATA 0
374#define CA91CX42_DCTL_PGM_PGM (1<<14)
375
376#define CA91CX42_DCTL_SUPER_M (1<<12)
377#define CA91CX42_DCTL_SUPER_NPRIV 0
378#define CA91CX42_DCTL_SUPER_SUPR (1<<12)
379
380#define CA91CX42_DCTL_VCT_M (1<<8)
381#define CA91CX42_DCTL_VCT_BLT (1<<8)
382#define CA91CX42_DCTL_LD64EN (1<<7)
383
384/*
385 * DCPP Register
386 * offset 218
387 */
388#define CA91CX42_DCPP_M 0xf
389#define CA91CX42_DCPP_NULL (1<<0)
390
391/*
392 * DMA General Control/Status Register (DGCS)
393 * offset 220
394 */
395#define CA91CX42_DGCS_GO (1<<31)
396#define CA91CX42_DGCS_STOP_REQ (1<<30)
397#define CA91CX42_DGCS_HALT_REQ (1<<29)
398#define CA91CX42_DGCS_CHAIN (1<<27)
399
400#define CA91CX42_DGCS_VON_M (7<<20)
401
402#define CA91CX42_DGCS_VOFF_M (0xf<<16)
403
404#define CA91CX42_DGCS_ACT (1<<15)
405#define CA91CX42_DGCS_STOP (1<<14)
406#define CA91CX42_DGCS_HALT (1<<13)
407#define CA91CX42_DGCS_DONE (1<<11)
408#define CA91CX42_DGCS_LERR (1<<10)
409#define CA91CX42_DGCS_VERR (1<<9)
410#define CA91CX42_DGCS_PERR (1<<8)
411#define CA91CX42_DGCS_INT_STOP (1<<6)
412#define CA91CX42_DGCS_INT_HALT (1<<5)
413#define CA91CX42_DGCS_INT_DONE (1<<3)
414#define CA91CX42_DGCS_INT_LERR (1<<2)
415#define CA91CX42_DGCS_INT_VERR (1<<1)
416#define CA91CX42_DGCS_INT_PERR (1<<0)
417
418/*
419 * PCI Interrupt Enable Register
420 * offset 300
421 */
422#define CA91CX42_LINT_LM3 0x00800000
423#define CA91CX42_LINT_LM2 0x00400000
424#define CA91CX42_LINT_LM1 0x00200000
425#define CA91CX42_LINT_LM0 0x00100000
426#define CA91CX42_LINT_MBOX3 0x00080000
427#define CA91CX42_LINT_MBOX2 0x00040000
428#define CA91CX42_LINT_MBOX1 0x00020000
429#define CA91CX42_LINT_MBOX0 0x00010000
430#define CA91CX42_LINT_ACFAIL 0x00008000
431#define CA91CX42_LINT_SYSFAIL 0x00004000
432#define CA91CX42_LINT_SW_INT 0x00002000
433#define CA91CX42_LINT_SW_IACK 0x00001000
434
435#define CA91CX42_LINT_VERR 0x00000400
436#define CA91CX42_LINT_LERR 0x00000200
437#define CA91CX42_LINT_DMA 0x00000100
438#define CA91CX42_LINT_VIRQ7 0x00000080
439#define CA91CX42_LINT_VIRQ6 0x00000040
440#define CA91CX42_LINT_VIRQ5 0x00000020
441#define CA91CX42_LINT_VIRQ4 0x00000010
442#define CA91CX42_LINT_VIRQ3 0x00000008
443#define CA91CX42_LINT_VIRQ2 0x00000004
444#define CA91CX42_LINT_VIRQ1 0x00000002
445#define CA91CX42_LINT_VOWN 0x00000001
446
447static const int CA91CX42_LINT_VIRQ[] = { 0, CA91CX42_LINT_VIRQ1,
448 CA91CX42_LINT_VIRQ2, CA91CX42_LINT_VIRQ3,
449 CA91CX42_LINT_VIRQ4, CA91CX42_LINT_VIRQ5,
450 CA91CX42_LINT_VIRQ6, CA91CX42_LINT_VIRQ7 };
451
452#define CA91CX42_LINT_MBOX 0x000F0000
453
454static const int CA91CX42_LINT_LM[] = { CA91CX42_LINT_LM0, CA91CX42_LINT_LM1,
455 CA91CX42_LINT_LM2, CA91CX42_LINT_LM3 };
456
457/*
458 * MAST_CTL Register
459 * offset 400
460 */
461#define CA91CX42_BM_MAST_CTL_MAXRTRY 0xF0000000
462#define CA91CX42_OF_MAST_CTL_MAXRTRY 28
463#define CA91CX42_BM_MAST_CTL_PWON 0x0F000000
464#define CA91CX42_OF_MAST_CTL_PWON 24
465#define CA91CX42_BM_MAST_CTL_VRL 0x00C00000
466#define CA91CX42_OF_MAST_CTL_VRL 22
467#define CA91CX42_BM_MAST_CTL_VRM 0x00200000
468#define CA91CX42_BM_MAST_CTL_VREL 0x00100000
469#define CA91CX42_BM_MAST_CTL_VOWN 0x00080000
470#define CA91CX42_BM_MAST_CTL_VOWN_ACK 0x00040000
471#define CA91CX42_BM_MAST_CTL_PABS 0x00001000
472#define CA91CX42_BM_MAST_CTL_BUS_NO 0x0000000F
473#define CA91CX42_OF_MAST_CTL_BUS_NO 0
474
475/*
476 * MISC_CTL Register
477 * offset 404
478 */
479#define CA91CX42_MISC_CTL_VBTO 0xF0000000
480#define CA91CX42_MISC_CTL_VARB 0x04000000
481#define CA91CX42_MISC_CTL_VARBTO 0x03000000
482#define CA91CX42_MISC_CTL_SW_LRST 0x00800000
483#define CA91CX42_MISC_CTL_SW_SRST 0x00400000
484#define CA91CX42_MISC_CTL_BI 0x00100000
485#define CA91CX42_MISC_CTL_ENGBI 0x00080000
486#define CA91CX42_MISC_CTL_RESCIND 0x00040000
487#define CA91CX42_MISC_CTL_SYSCON 0x00020000
488#define CA91CX42_MISC_CTL_V64AUTO 0x00010000
489#define CA91CX42_MISC_CTL_RESERVED 0x0820FFFF
490
491#define CA91CX42_OF_MISC_CTL_VARBTO 24
492#define CA91CX42_OF_MISC_CTL_VBTO 28
493
494/*
495 * MISC_STAT Register
496 * offset 408
497 */
498#define CA91CX42_BM_MISC_STAT_ENDIAN 0x80000000
499#define CA91CX42_BM_MISC_STAT_LCLSIZE 0x40000000
500#define CA91CX42_BM_MISC_STAT_DY4AUTO 0x08000000
501#define CA91CX42_BM_MISC_STAT_MYBBSY 0x00200000
502#define CA91CX42_BM_MISC_STAT_DY4DONE 0x00080000
503#define CA91CX42_BM_MISC_STAT_TXFE 0x00040000
504#define CA91CX42_BM_MISC_STAT_RXFE 0x00020000
505#define CA91CX42_BM_MISC_STAT_DY4AUTOID 0x0000FF00
506#define CA91CX42_OF_MISC_STAT_DY4AUTOID 8
507
508/*
509 * VSI Control Register
510 * offset F00
511 */
512#define CA91CX42_VSI_CTL_EN (1<<31)
513#define CA91CX42_VSI_CTL_PWEN (1<<30)
514#define CA91CX42_VSI_CTL_PREN (1<<29)
515
516#define CA91CX42_VSI_CTL_PGM_M (3<<22)
517#define CA91CX42_VSI_CTL_PGM_DATA (1<<22)
518#define CA91CX42_VSI_CTL_PGM_PGM (1<<23)
519
520#define CA91CX42_VSI_CTL_SUPER_M (3<<20)
521#define CA91CX42_VSI_CTL_SUPER_NPRIV (1<<20)
522#define CA91CX42_VSI_CTL_SUPER_SUPR (1<<21)
523
524#define CA91CX42_VSI_CTL_VAS_M (7<<16)
525#define CA91CX42_VSI_CTL_VAS_A16 0
526#define CA91CX42_VSI_CTL_VAS_A24 (1<<16)
527#define CA91CX42_VSI_CTL_VAS_A32 (1<<17)
528#define CA91CX42_VSI_CTL_VAS_USER1 (3<<17)
529#define CA91CX42_VSI_CTL_VAS_USER2 (7<<16)
530
531#define CA91CX42_VSI_CTL_LD64EN (1<<7)
532#define CA91CX42_VSI_CTL_LLRMW (1<<6)
533
534#define CA91CX42_VSI_CTL_LAS_M (3<<0)
535#define CA91CX42_VSI_CTL_LAS_PCI_MS 0
536#define CA91CX42_VSI_CTL_LAS_PCI_IO (1<<0)
537#define CA91CX42_VSI_CTL_LAS_PCI_CONF (1<<1)
538
539/* LM_CTL Register
540 * offset F64
541 */
542#define CA91CX42_LM_CTL_EN (1<<31)
543#define CA91CX42_LM_CTL_PGM (1<<23)
544#define CA91CX42_LM_CTL_DATA (1<<22)
545#define CA91CX42_LM_CTL_SUPR (1<<21)
546#define CA91CX42_LM_CTL_NPRIV (1<<20)
547#define CA91CX42_LM_CTL_AS_M (7<<16)
548#define CA91CX42_LM_CTL_AS_A16 0
549#define CA91CX42_LM_CTL_AS_A24 (1<<16)
550#define CA91CX42_LM_CTL_AS_A32 (1<<17)
551
552/*
553 * VRAI_CTL Register
554 * offset F70
555 */
556#define CA91CX42_BM_VRAI_CTL_EN 0x80000000
557#define CA91CX42_BM_VRAI_CTL_PGM 0x00C00000
558#define CA91CX42_OF_VRAI_CTL_PGM 22
559#define CA91CX42_BM_VRAI_CTL_SUPER 0x00300000
560#define CA91CX42_OF_VRAI_CTL_SUPER 20
561#define CA91CX42_BM_VRAI_CTL_VAS 0x00030000
562#define CA91CX42_OF_VRAI_CTL_VAS 16
563
564/* VCSR_CTL Register
565 * offset F80
566 */
567#define CA91CX42_VCSR_CTL_EN (1<<31)
568
569#define CA91CX42_VCSR_CTL_LAS_M (3<<0)
570#define CA91CX42_VCSR_CTL_LAS_PCI_MS 0
571#define CA91CX42_VCSR_CTL_LAS_PCI_IO (1<<0)
572#define CA91CX42_VCSR_CTL_LAS_PCI_CONF (1<<1)
573
574/* VCSR_BS Register
575 * offset FFC
576 */
577#define CA91CX42_VCSR_BS_SLOT_M (0x1F<<27)
578
579#endif /* _CA91CX42_H */