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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * drivers/pwm/pwm-tegra.c
4 *
5 * Tegra pulse-width-modulation controller driver
6 *
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
9 *
10 * Overview of Tegra Pulse Width Modulator Register:
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
14 *
15 * The PWM clock frequency is divided by 256 before subdividing it based
16 * on the programmable frequency division value to generate the required
17 * frequency for PWM output. The maximum output frequency that can be
18 * achieved is (max rate of source clock) / 256.
19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
20 * 408 MHz/256 = 1.6 MHz.
21 * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
22 *
23 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
24 * To achieve 100% duty cycle, program Bit [24] of this register to
25 * 1’b1. In which case the other bits [23:16] are set to don't care.
26 *
27 * Limitations:
28 * - When PWM is disabled, the output is driven to inactive.
29 * - It does not allow the current PWM period to complete and
30 * stops abruptly.
31 *
32 * - If the register is reconfigured while PWM is running,
33 * it does not complete the currently running period.
34 *
35 * - If the user input duty is beyond acceptible limits,
36 * -EINVAL is returned.
37 */
38
39#include <linux/clk.h>
40#include <linux/err.h>
41#include <linux/io.h>
42#include <linux/module.h>
43#include <linux/of.h>
44#include <linux/of_device.h>
45#include <linux/pwm.h>
46#include <linux/platform_device.h>
47#include <linux/pinctrl/consumer.h>
48#include <linux/slab.h>
49#include <linux/reset.h>
50
51#define PWM_ENABLE (1 << 31)
52#define PWM_DUTY_WIDTH 8
53#define PWM_DUTY_SHIFT 16
54#define PWM_SCALE_WIDTH 13
55#define PWM_SCALE_SHIFT 0
56
57struct tegra_pwm_soc {
58 unsigned int num_channels;
59
60 /* Maximum IP frequency for given SoCs */
61 unsigned long max_frequency;
62};
63
64struct tegra_pwm_chip {
65 struct pwm_chip chip;
66 struct device *dev;
67
68 struct clk *clk;
69 struct reset_control*rst;
70
71 unsigned long clk_rate;
72 unsigned long min_period_ns;
73
74 void __iomem *regs;
75
76 const struct tegra_pwm_soc *soc;
77};
78
79static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
80{
81 return container_of(chip, struct tegra_pwm_chip, chip);
82}
83
84static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
85{
86 return readl(chip->regs + (num << 4));
87}
88
89static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
90 unsigned long val)
91{
92 writel(val, chip->regs + (num << 4));
93}
94
95static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
96 int duty_ns, int period_ns)
97{
98 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
99 unsigned long long c = duty_ns, hz;
100 unsigned long rate, required_clk_rate;
101 u32 val = 0;
102 int err;
103
104 /*
105 * Convert from duty_ns / period_ns to a fixed number of duty ticks
106 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
107 * nearest integer during division.
108 */
109 c *= (1 << PWM_DUTY_WIDTH);
110 c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
111
112 val = (u32)c << PWM_DUTY_SHIFT;
113
114 /*
115 * min period = max clock limit >> PWM_DUTY_WIDTH
116 */
117 if (period_ns < pc->min_period_ns)
118 return -EINVAL;
119
120 /*
121 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
122 * cycles at the PWM clock rate will take period_ns nanoseconds.
123 *
124 * num_channels: If single instance of PWM controller has multiple
125 * channels (e.g. Tegra210 or older) then it is not possible to
126 * configure separate clock rates to each of the channels, in such
127 * case the value stored during probe will be referred.
128 *
129 * If every PWM controller instance has one channel respectively, i.e.
130 * nums_channels == 1 then only the clock rate can be modified
131 * dynamically (e.g. Tegra186 or Tegra194).
132 */
133 if (pc->soc->num_channels == 1) {
134 /*
135 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
136 * with the maximum possible rate that the controller can
137 * provide. Any further lower value can be derived by setting
138 * PFM bits[0:12].
139 *
140 * required_clk_rate is a reference rate for source clock and
141 * it is derived based on user requested period. By setting the
142 * source clock rate as required_clk_rate, PWM controller will
143 * be able to configure the requested period.
144 */
145 required_clk_rate =
146 (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
147
148 err = clk_set_rate(pc->clk, required_clk_rate);
149 if (err < 0)
150 return -EINVAL;
151
152 /* Store the new rate for further references */
153 pc->clk_rate = clk_get_rate(pc->clk);
154 }
155
156 rate = pc->clk_rate >> PWM_DUTY_WIDTH;
157
158 /* Consider precision in PWM_SCALE_WIDTH rate calculation */
159 hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns);
160 rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz);
161
162 /*
163 * Since the actual PWM divider is the register's frequency divider
164 * field plus 1, we need to decrement to get the correct value to
165 * write to the register.
166 */
167 if (rate > 0)
168 rate--;
169
170 /*
171 * Make sure that the rate will fit in the register's frequency
172 * divider field.
173 */
174 if (rate >> PWM_SCALE_WIDTH)
175 return -EINVAL;
176
177 val |= rate << PWM_SCALE_SHIFT;
178
179 /*
180 * If the PWM channel is disabled, make sure to turn on the clock
181 * before writing the register. Otherwise, keep it enabled.
182 */
183 if (!pwm_is_enabled(pwm)) {
184 err = clk_prepare_enable(pc->clk);
185 if (err < 0)
186 return err;
187 } else
188 val |= PWM_ENABLE;
189
190 pwm_writel(pc, pwm->hwpwm, val);
191
192 /*
193 * If the PWM is not enabled, turn the clock off again to save power.
194 */
195 if (!pwm_is_enabled(pwm))
196 clk_disable_unprepare(pc->clk);
197
198 return 0;
199}
200
201static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
202{
203 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
204 int rc = 0;
205 u32 val;
206
207 rc = clk_prepare_enable(pc->clk);
208 if (rc < 0)
209 return rc;
210
211 val = pwm_readl(pc, pwm->hwpwm);
212 val |= PWM_ENABLE;
213 pwm_writel(pc, pwm->hwpwm, val);
214
215 return 0;
216}
217
218static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
219{
220 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
221 u32 val;
222
223 val = pwm_readl(pc, pwm->hwpwm);
224 val &= ~PWM_ENABLE;
225 pwm_writel(pc, pwm->hwpwm, val);
226
227 clk_disable_unprepare(pc->clk);
228}
229
230static const struct pwm_ops tegra_pwm_ops = {
231 .config = tegra_pwm_config,
232 .enable = tegra_pwm_enable,
233 .disable = tegra_pwm_disable,
234 .owner = THIS_MODULE,
235};
236
237static int tegra_pwm_probe(struct platform_device *pdev)
238{
239 struct tegra_pwm_chip *pwm;
240 struct resource *r;
241 int ret;
242
243 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
244 if (!pwm)
245 return -ENOMEM;
246
247 pwm->soc = of_device_get_match_data(&pdev->dev);
248 pwm->dev = &pdev->dev;
249
250 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
251 pwm->regs = devm_ioremap_resource(&pdev->dev, r);
252 if (IS_ERR(pwm->regs))
253 return PTR_ERR(pwm->regs);
254
255 platform_set_drvdata(pdev, pwm);
256
257 pwm->clk = devm_clk_get(&pdev->dev, NULL);
258 if (IS_ERR(pwm->clk))
259 return PTR_ERR(pwm->clk);
260
261 /* Set maximum frequency of the IP */
262 ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
263 if (ret < 0) {
264 dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
265 return ret;
266 }
267
268 /*
269 * The requested and configured frequency may differ due to
270 * clock register resolutions. Get the configured frequency
271 * so that PWM period can be calculated more accurately.
272 */
273 pwm->clk_rate = clk_get_rate(pwm->clk);
274
275 /* Set minimum limit of PWM period for the IP */
276 pwm->min_period_ns =
277 (NSEC_PER_SEC / (pwm->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
278
279 pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
280 if (IS_ERR(pwm->rst)) {
281 ret = PTR_ERR(pwm->rst);
282 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
283 return ret;
284 }
285
286 reset_control_deassert(pwm->rst);
287
288 pwm->chip.dev = &pdev->dev;
289 pwm->chip.ops = &tegra_pwm_ops;
290 pwm->chip.base = -1;
291 pwm->chip.npwm = pwm->soc->num_channels;
292
293 ret = pwmchip_add(&pwm->chip);
294 if (ret < 0) {
295 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
296 reset_control_assert(pwm->rst);
297 return ret;
298 }
299
300 return 0;
301}
302
303static int tegra_pwm_remove(struct platform_device *pdev)
304{
305 struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
306 unsigned int i;
307 int err;
308
309 if (WARN_ON(!pc))
310 return -ENODEV;
311
312 err = clk_prepare_enable(pc->clk);
313 if (err < 0)
314 return err;
315
316 for (i = 0; i < pc->chip.npwm; i++) {
317 struct pwm_device *pwm = &pc->chip.pwms[i];
318
319 if (!pwm_is_enabled(pwm))
320 if (clk_prepare_enable(pc->clk) < 0)
321 continue;
322
323 pwm_writel(pc, i, 0);
324
325 clk_disable_unprepare(pc->clk);
326 }
327
328 reset_control_assert(pc->rst);
329 clk_disable_unprepare(pc->clk);
330
331 return pwmchip_remove(&pc->chip);
332}
333
334#ifdef CONFIG_PM_SLEEP
335static int tegra_pwm_suspend(struct device *dev)
336{
337 return pinctrl_pm_select_sleep_state(dev);
338}
339
340static int tegra_pwm_resume(struct device *dev)
341{
342 return pinctrl_pm_select_default_state(dev);
343}
344#endif
345
346static const struct tegra_pwm_soc tegra20_pwm_soc = {
347 .num_channels = 4,
348 .max_frequency = 48000000UL,
349};
350
351static const struct tegra_pwm_soc tegra186_pwm_soc = {
352 .num_channels = 1,
353 .max_frequency = 102000000UL,
354};
355
356static const struct tegra_pwm_soc tegra194_pwm_soc = {
357 .num_channels = 1,
358 .max_frequency = 408000000UL,
359};
360
361static const struct of_device_id tegra_pwm_of_match[] = {
362 { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
363 { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
364 { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
365 { }
366};
367MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
368
369static const struct dev_pm_ops tegra_pwm_pm_ops = {
370 SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume)
371};
372
373static struct platform_driver tegra_pwm_driver = {
374 .driver = {
375 .name = "tegra-pwm",
376 .of_match_table = tegra_pwm_of_match,
377 .pm = &tegra_pwm_pm_ops,
378 },
379 .probe = tegra_pwm_probe,
380 .remove = tegra_pwm_remove,
381};
382
383module_platform_driver(tegra_pwm_driver);
384
385MODULE_LICENSE("GPL");
386MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
387MODULE_DESCRIPTION("Tegra PWM controller driver");
388MODULE_ALIAS("platform:tegra-pwm");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * drivers/pwm/pwm-tegra.c
4 *
5 * Tegra pulse-width-modulation controller driver
6 *
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
9 *
10 * Overview of Tegra Pulse Width Modulator Register:
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
14 *
15 * The PWM clock frequency is divided by 256 before subdividing it based
16 * on the programmable frequency division value to generate the required
17 * frequency for PWM output. The maximum output frequency that can be
18 * achieved is (max rate of source clock) / 256.
19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
20 * 408 MHz/256 = 1.6 MHz.
21 * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
22 *
23 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
24 * To achieve 100% duty cycle, program Bit [24] of this register to
25 * 1’b1. In which case the other bits [23:16] are set to don't care.
26 *
27 * Limitations:
28 * - When PWM is disabled, the output is driven to inactive.
29 * - It does not allow the current PWM period to complete and
30 * stops abruptly.
31 *
32 * - If the register is reconfigured while PWM is running,
33 * it does not complete the currently running period.
34 *
35 * - If the user input duty is beyond acceptible limits,
36 * -EINVAL is returned.
37 */
38
39#include <linux/clk.h>
40#include <linux/err.h>
41#include <linux/io.h>
42#include <linux/module.h>
43#include <linux/of.h>
44#include <linux/pm_opp.h>
45#include <linux/pwm.h>
46#include <linux/platform_device.h>
47#include <linux/pinctrl/consumer.h>
48#include <linux/pm_runtime.h>
49#include <linux/slab.h>
50#include <linux/reset.h>
51
52#include <soc/tegra/common.h>
53
54#define PWM_ENABLE (1 << 31)
55#define PWM_DUTY_WIDTH 8
56#define PWM_DUTY_SHIFT 16
57#define PWM_SCALE_WIDTH 13
58#define PWM_SCALE_SHIFT 0
59
60struct tegra_pwm_soc {
61 unsigned int num_channels;
62
63 /* Maximum IP frequency for given SoCs */
64 unsigned long max_frequency;
65};
66
67struct tegra_pwm_chip {
68 struct pwm_chip chip;
69 struct device *dev;
70
71 struct clk *clk;
72 struct reset_control*rst;
73
74 unsigned long clk_rate;
75 unsigned long min_period_ns;
76
77 void __iomem *regs;
78
79 const struct tegra_pwm_soc *soc;
80};
81
82static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
83{
84 return container_of(chip, struct tegra_pwm_chip, chip);
85}
86
87static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset)
88{
89 return readl(pc->regs + (offset << 4));
90}
91
92static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value)
93{
94 writel(value, pc->regs + (offset << 4));
95}
96
97static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
98 int duty_ns, int period_ns)
99{
100 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
101 unsigned long long c = duty_ns;
102 unsigned long rate, required_clk_rate;
103 u32 val = 0;
104 int err;
105
106 /*
107 * Convert from duty_ns / period_ns to a fixed number of duty ticks
108 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
109 * nearest integer during division.
110 */
111 c *= (1 << PWM_DUTY_WIDTH);
112 c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
113
114 val = (u32)c << PWM_DUTY_SHIFT;
115
116 /*
117 * min period = max clock limit >> PWM_DUTY_WIDTH
118 */
119 if (period_ns < pc->min_period_ns)
120 return -EINVAL;
121
122 /*
123 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
124 * cycles at the PWM clock rate will take period_ns nanoseconds.
125 *
126 * num_channels: If single instance of PWM controller has multiple
127 * channels (e.g. Tegra210 or older) then it is not possible to
128 * configure separate clock rates to each of the channels, in such
129 * case the value stored during probe will be referred.
130 *
131 * If every PWM controller instance has one channel respectively, i.e.
132 * nums_channels == 1 then only the clock rate can be modified
133 * dynamically (e.g. Tegra186 or Tegra194).
134 */
135 if (pc->soc->num_channels == 1) {
136 /*
137 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
138 * with the maximum possible rate that the controller can
139 * provide. Any further lower value can be derived by setting
140 * PFM bits[0:12].
141 *
142 * required_clk_rate is a reference rate for source clock and
143 * it is derived based on user requested period. By setting the
144 * source clock rate as required_clk_rate, PWM controller will
145 * be able to configure the requested period.
146 */
147 required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
148 period_ns);
149
150 if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))
151 /*
152 * required_clk_rate is a lower bound for the input
153 * rate; for lower rates there is no value for PWM_SCALE
154 * that yields a period less than or equal to the
155 * requested period. Hence, for lower rates, double the
156 * required_clk_rate to get a clock rate that can meet
157 * the requested period.
158 */
159 required_clk_rate *= 2;
160
161 err = dev_pm_opp_set_rate(pc->dev, required_clk_rate);
162 if (err < 0)
163 return -EINVAL;
164
165 /* Store the new rate for further references */
166 pc->clk_rate = clk_get_rate(pc->clk);
167 }
168
169 /* Consider precision in PWM_SCALE_WIDTH rate calculation */
170 rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns,
171 (u64)NSEC_PER_SEC << PWM_DUTY_WIDTH);
172
173 /*
174 * Since the actual PWM divider is the register's frequency divider
175 * field plus 1, we need to decrement to get the correct value to
176 * write to the register.
177 */
178 if (rate > 0)
179 rate--;
180 else
181 return -EINVAL;
182
183 /*
184 * Make sure that the rate will fit in the register's frequency
185 * divider field.
186 */
187 if (rate >> PWM_SCALE_WIDTH)
188 return -EINVAL;
189
190 val |= rate << PWM_SCALE_SHIFT;
191
192 /*
193 * If the PWM channel is disabled, make sure to turn on the clock
194 * before writing the register. Otherwise, keep it enabled.
195 */
196 if (!pwm_is_enabled(pwm)) {
197 err = pm_runtime_resume_and_get(pc->dev);
198 if (err)
199 return err;
200 } else
201 val |= PWM_ENABLE;
202
203 pwm_writel(pc, pwm->hwpwm, val);
204
205 /*
206 * If the PWM is not enabled, turn the clock off again to save power.
207 */
208 if (!pwm_is_enabled(pwm))
209 pm_runtime_put(pc->dev);
210
211 return 0;
212}
213
214static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
215{
216 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
217 int rc = 0;
218 u32 val;
219
220 rc = pm_runtime_resume_and_get(pc->dev);
221 if (rc)
222 return rc;
223
224 val = pwm_readl(pc, pwm->hwpwm);
225 val |= PWM_ENABLE;
226 pwm_writel(pc, pwm->hwpwm, val);
227
228 return 0;
229}
230
231static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
232{
233 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
234 u32 val;
235
236 val = pwm_readl(pc, pwm->hwpwm);
237 val &= ~PWM_ENABLE;
238 pwm_writel(pc, pwm->hwpwm, val);
239
240 pm_runtime_put_sync(pc->dev);
241}
242
243static int tegra_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
244 const struct pwm_state *state)
245{
246 int err;
247 bool enabled = pwm->state.enabled;
248
249 if (state->polarity != PWM_POLARITY_NORMAL)
250 return -EINVAL;
251
252 if (!state->enabled) {
253 if (enabled)
254 tegra_pwm_disable(chip, pwm);
255
256 return 0;
257 }
258
259 err = tegra_pwm_config(chip, pwm, state->duty_cycle, state->period);
260 if (err)
261 return err;
262
263 if (!enabled)
264 err = tegra_pwm_enable(chip, pwm);
265
266 return err;
267}
268
269static const struct pwm_ops tegra_pwm_ops = {
270 .apply = tegra_pwm_apply,
271};
272
273static int tegra_pwm_probe(struct platform_device *pdev)
274{
275 struct tegra_pwm_chip *pc;
276 int ret;
277
278 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
279 if (!pc)
280 return -ENOMEM;
281
282 pc->soc = of_device_get_match_data(&pdev->dev);
283 pc->dev = &pdev->dev;
284
285 pc->regs = devm_platform_ioremap_resource(pdev, 0);
286 if (IS_ERR(pc->regs))
287 return PTR_ERR(pc->regs);
288
289 platform_set_drvdata(pdev, pc);
290
291 pc->clk = devm_clk_get(&pdev->dev, NULL);
292 if (IS_ERR(pc->clk))
293 return PTR_ERR(pc->clk);
294
295 ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
296 if (ret)
297 return ret;
298
299 pm_runtime_enable(&pdev->dev);
300 ret = pm_runtime_resume_and_get(&pdev->dev);
301 if (ret)
302 return ret;
303
304 /* Set maximum frequency of the IP */
305 ret = dev_pm_opp_set_rate(pc->dev, pc->soc->max_frequency);
306 if (ret < 0) {
307 dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
308 goto put_pm;
309 }
310
311 /*
312 * The requested and configured frequency may differ due to
313 * clock register resolutions. Get the configured frequency
314 * so that PWM period can be calculated more accurately.
315 */
316 pc->clk_rate = clk_get_rate(pc->clk);
317
318 /* Set minimum limit of PWM period for the IP */
319 pc->min_period_ns =
320 (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
321
322 pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
323 if (IS_ERR(pc->rst)) {
324 ret = PTR_ERR(pc->rst);
325 dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
326 goto put_pm;
327 }
328
329 reset_control_deassert(pc->rst);
330
331 pc->chip.dev = &pdev->dev;
332 pc->chip.ops = &tegra_pwm_ops;
333 pc->chip.npwm = pc->soc->num_channels;
334
335 ret = pwmchip_add(&pc->chip);
336 if (ret < 0) {
337 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
338 reset_control_assert(pc->rst);
339 goto put_pm;
340 }
341
342 pm_runtime_put(&pdev->dev);
343
344 return 0;
345put_pm:
346 pm_runtime_put_sync_suspend(&pdev->dev);
347 pm_runtime_force_suspend(&pdev->dev);
348 return ret;
349}
350
351static void tegra_pwm_remove(struct platform_device *pdev)
352{
353 struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
354
355 pwmchip_remove(&pc->chip);
356
357 reset_control_assert(pc->rst);
358
359 pm_runtime_force_suspend(&pdev->dev);
360}
361
362static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev)
363{
364 struct tegra_pwm_chip *pc = dev_get_drvdata(dev);
365 int err;
366
367 clk_disable_unprepare(pc->clk);
368
369 err = pinctrl_pm_select_sleep_state(dev);
370 if (err) {
371 clk_prepare_enable(pc->clk);
372 return err;
373 }
374
375 return 0;
376}
377
378static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)
379{
380 struct tegra_pwm_chip *pc = dev_get_drvdata(dev);
381 int err;
382
383 err = pinctrl_pm_select_default_state(dev);
384 if (err)
385 return err;
386
387 err = clk_prepare_enable(pc->clk);
388 if (err) {
389 pinctrl_pm_select_sleep_state(dev);
390 return err;
391 }
392
393 return 0;
394}
395
396static const struct tegra_pwm_soc tegra20_pwm_soc = {
397 .num_channels = 4,
398 .max_frequency = 48000000UL,
399};
400
401static const struct tegra_pwm_soc tegra186_pwm_soc = {
402 .num_channels = 1,
403 .max_frequency = 102000000UL,
404};
405
406static const struct tegra_pwm_soc tegra194_pwm_soc = {
407 .num_channels = 1,
408 .max_frequency = 408000000UL,
409};
410
411static const struct of_device_id tegra_pwm_of_match[] = {
412 { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
413 { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
414 { .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
415 { }
416};
417MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
418
419static const struct dev_pm_ops tegra_pwm_pm_ops = {
420 SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume,
421 NULL)
422 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
423 pm_runtime_force_resume)
424};
425
426static struct platform_driver tegra_pwm_driver = {
427 .driver = {
428 .name = "tegra-pwm",
429 .of_match_table = tegra_pwm_of_match,
430 .pm = &tegra_pwm_pm_ops,
431 },
432 .probe = tegra_pwm_probe,
433 .remove_new = tegra_pwm_remove,
434};
435
436module_platform_driver(tegra_pwm_driver);
437
438MODULE_LICENSE("GPL");
439MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
440MODULE_DESCRIPTION("Tegra PWM controller driver");
441MODULE_ALIAS("platform:tegra-pwm");