1// SPDX-License-Identifier: GPL-2.0
 2/*
 3 * Renesas R-Car V3U System Controller
 4 *
 5 * Copyright (C) 2020 Renesas Electronics Corp.
 6 */
 7
 8#include <linux/bits.h>
 9#include <linux/clk/renesas.h>
10#include <linux/delay.h>
11#include <linux/err.h>
12#include <linux/io.h>
13#include <linux/iopoll.h>
14#include <linux/kernel.h>
15#include <linux/mm.h>
16#include <linux/of_address.h>
17#include <linux/pm_domain.h>
18#include <linux/slab.h>
19#include <linux/spinlock.h>
20#include <linux/types.h>
21
22#include <dt-bindings/power/r8a779a0-sysc.h>
23
24#include "rcar-gen4-sysc.h"
25
26static struct rcar_gen4_sysc_area r8a779a0_areas[] __initdata = {
27	{ "always-on",	R8A779A0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
28	{ "a3e0",	R8A779A0_PD_A3E0, R8A779A0_PD_ALWAYS_ON, PD_SCU },
29	{ "a3e1",	R8A779A0_PD_A3E1, R8A779A0_PD_ALWAYS_ON, PD_SCU },
30	{ "a2e0d0",	R8A779A0_PD_A2E0D0, R8A779A0_PD_A3E0, PD_SCU },
31	{ "a2e0d1",	R8A779A0_PD_A2E0D1, R8A779A0_PD_A3E0, PD_SCU },
32	{ "a2e1d0",	R8A779A0_PD_A2E1D0, R8A779A0_PD_A3E1, PD_SCU },
33	{ "a2e1d1",	R8A779A0_PD_A2E1D1, R8A779A0_PD_A3E1, PD_SCU },
34	{ "a1e0d0c0",	R8A779A0_PD_A1E0D0C0, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
35	{ "a1e0d0c1",	R8A779A0_PD_A1E0D0C1, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
36	{ "a1e0d1c0",	R8A779A0_PD_A1E0D1C0, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
37	{ "a1e0d1c1",	R8A779A0_PD_A1E0D1C1, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
38	{ "a1e1d0c0",	R8A779A0_PD_A1E1D0C0, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
39	{ "a1e1d0c1",	R8A779A0_PD_A1E1D0C1, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
40	{ "a1e1d1c0",	R8A779A0_PD_A1E1D1C0, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
41	{ "a1e1d1c1",	R8A779A0_PD_A1E1D1C1, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
42	{ "3dg-a",	R8A779A0_PD_3DG_A, R8A779A0_PD_ALWAYS_ON },
43	{ "3dg-b",	R8A779A0_PD_3DG_B, R8A779A0_PD_3DG_A },
44	{ "a3vip0",	R8A779A0_PD_A3VIP0, R8A779A0_PD_ALWAYS_ON },
45	{ "a3vip1",	R8A779A0_PD_A3VIP1, R8A779A0_PD_ALWAYS_ON },
46	{ "a3vip3",	R8A779A0_PD_A3VIP3, R8A779A0_PD_ALWAYS_ON },
47	{ "a3vip2",	R8A779A0_PD_A3VIP2, R8A779A0_PD_ALWAYS_ON },
48	{ "a3isp01",	R8A779A0_PD_A3ISP01, R8A779A0_PD_ALWAYS_ON },
49	{ "a3isp23",	R8A779A0_PD_A3ISP23, R8A779A0_PD_ALWAYS_ON },
50	{ "a3ir",	R8A779A0_PD_A3IR, R8A779A0_PD_ALWAYS_ON },
51	{ "a2cn0",	R8A779A0_PD_A2CN0, R8A779A0_PD_A3IR },
52	{ "a2imp01",	R8A779A0_PD_A2IMP01, R8A779A0_PD_A3IR },
53	{ "a2dp0",	R8A779A0_PD_A2DP0, R8A779A0_PD_A3IR },
54	{ "a2cv0",	R8A779A0_PD_A2CV0, R8A779A0_PD_A3IR },
55	{ "a2cv1",	R8A779A0_PD_A2CV1, R8A779A0_PD_A3IR },
56	{ "a2cv4",	R8A779A0_PD_A2CV4, R8A779A0_PD_A3IR },
57	{ "a2cv6",	R8A779A0_PD_A2CV6, R8A779A0_PD_A3IR },
58	{ "a2cn2",	R8A779A0_PD_A2CN2, R8A779A0_PD_A3IR },
59	{ "a2imp23",	R8A779A0_PD_A2IMP23, R8A779A0_PD_A3IR },
60	{ "a2dp1",	R8A779A0_PD_A2DP1, R8A779A0_PD_A3IR },
61	{ "a2cv2",	R8A779A0_PD_A2CV2, R8A779A0_PD_A3IR },
62	{ "a2cv3",	R8A779A0_PD_A2CV3, R8A779A0_PD_A3IR },
63	{ "a2cv5",	R8A779A0_PD_A2CV5, R8A779A0_PD_A3IR },
64	{ "a2cv7",	R8A779A0_PD_A2CV7, R8A779A0_PD_A3IR },
65	{ "a2cn1",	R8A779A0_PD_A2CN1, R8A779A0_PD_A3IR },
66	{ "a1cnn0",	R8A779A0_PD_A1CNN0, R8A779A0_PD_A2CN0 },
67	{ "a1cnn2",	R8A779A0_PD_A1CNN2, R8A779A0_PD_A2CN2 },
68	{ "a1dsp0",	R8A779A0_PD_A1DSP0, R8A779A0_PD_A2CN2 },
69	{ "a1cnn1",	R8A779A0_PD_A1CNN1, R8A779A0_PD_A2CN1 },
70	{ "a1dsp1",	R8A779A0_PD_A1DSP1, R8A779A0_PD_A2CN1 },
71};
72
73const struct rcar_gen4_sysc_info r8a779a0_sysc_info __initconst = {
74	.areas = r8a779a0_areas,
75	.num_areas = ARRAY_SIZE(r8a779a0_areas),
76};