Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas R-Car H3 System Controller
4 *
5 * Copyright (C) 2016-2017 Glider bvba
6 */
7
8#include <linux/bits.h>
9#include <linux/kernel.h>
10#include <linux/sys_soc.h>
11
12#include <dt-bindings/power/r8a7795-sysc.h>
13
14#include "rcar-sysc.h"
15
16static struct rcar_sysc_area r8a7795_areas[] __initdata = {
17 { "always-on", 0, 0, R8A7795_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18 { "ca57-scu", 0x1c0, 0, R8A7795_PD_CA57_SCU, R8A7795_PD_ALWAYS_ON,
19 PD_SCU },
20 { "ca57-cpu0", 0x80, 0, R8A7795_PD_CA57_CPU0, R8A7795_PD_CA57_SCU,
21 PD_CPU_NOCR },
22 { "ca57-cpu1", 0x80, 1, R8A7795_PD_CA57_CPU1, R8A7795_PD_CA57_SCU,
23 PD_CPU_NOCR },
24 { "ca57-cpu2", 0x80, 2, R8A7795_PD_CA57_CPU2, R8A7795_PD_CA57_SCU,
25 PD_CPU_NOCR },
26 { "ca57-cpu3", 0x80, 3, R8A7795_PD_CA57_CPU3, R8A7795_PD_CA57_SCU,
27 PD_CPU_NOCR },
28 { "ca53-scu", 0x140, 0, R8A7795_PD_CA53_SCU, R8A7795_PD_ALWAYS_ON,
29 PD_SCU },
30 { "ca53-cpu0", 0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU,
31 PD_CPU_NOCR },
32 { "ca53-cpu1", 0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU,
33 PD_CPU_NOCR },
34 { "ca53-cpu2", 0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU,
35 PD_CPU_NOCR },
36 { "ca53-cpu3", 0x200, 3, R8A7795_PD_CA53_CPU3, R8A7795_PD_CA53_SCU,
37 PD_CPU_NOCR },
38 { "a3vp", 0x340, 0, R8A7795_PD_A3VP, R8A7795_PD_ALWAYS_ON },
39 { "cr7", 0x240, 0, R8A7795_PD_CR7, R8A7795_PD_ALWAYS_ON },
40 { "a3vc", 0x380, 0, R8A7795_PD_A3VC, R8A7795_PD_ALWAYS_ON },
41 /* A2VC0 exists on ES1.x only */
42 { "a2vc0", 0x3c0, 0, R8A7795_PD_A2VC0, R8A7795_PD_A3VC },
43 { "a2vc1", 0x3c0, 1, R8A7795_PD_A2VC1, R8A7795_PD_A3VC },
44 { "3dg-a", 0x100, 0, R8A7795_PD_3DG_A, R8A7795_PD_ALWAYS_ON },
45 { "3dg-b", 0x100, 1, R8A7795_PD_3DG_B, R8A7795_PD_3DG_A },
46 { "3dg-c", 0x100, 2, R8A7795_PD_3DG_C, R8A7795_PD_3DG_B },
47 { "3dg-d", 0x100, 3, R8A7795_PD_3DG_D, R8A7795_PD_3DG_C },
48 { "3dg-e", 0x100, 4, R8A7795_PD_3DG_E, R8A7795_PD_3DG_D },
49 { "a3ir", 0x180, 0, R8A7795_PD_A3IR, R8A7795_PD_ALWAYS_ON },
50};
51
52
53 /*
54 * Fixups for R-Car H3 revisions
55 */
56
57#define HAS_A2VC0 BIT(0) /* Power domain A2VC0 is present */
58#define NO_EXTMASK BIT(1) /* Missing SYSCEXTMASK register */
59
60static const struct soc_device_attribute r8a7795_quirks_match[] __initconst = {
61 {
62 .soc_id = "r8a7795", .revision = "ES1.*",
63 .data = (void *)(HAS_A2VC0 | NO_EXTMASK),
64 }, {
65 .soc_id = "r8a7795", .revision = "ES2.*",
66 .data = (void *)(NO_EXTMASK),
67 },
68 { /* sentinel */ }
69};
70
71static int __init r8a7795_sysc_init(void)
72{
73 const struct soc_device_attribute *attr;
74 u32 quirks = 0;
75
76 attr = soc_device_match(r8a7795_quirks_match);
77 if (attr)
78 quirks = (uintptr_t)attr->data;
79
80 if (!(quirks & HAS_A2VC0))
81 rcar_sysc_nullify(r8a7795_areas, ARRAY_SIZE(r8a7795_areas),
82 R8A7795_PD_A2VC0);
83
84 if (quirks & NO_EXTMASK)
85 r8a7795_sysc_info.extmask_val = 0;
86
87 return 0;
88}
89
90struct rcar_sysc_info r8a7795_sysc_info __initdata = {
91 .init = r8a7795_sysc_init,
92 .areas = r8a7795_areas,
93 .num_areas = ARRAY_SIZE(r8a7795_areas),
94 .extmask_offs = 0x2f8,
95 .extmask_val = BIT(0),
96};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas R-Car H3 System Controller
4 *
5 * Copyright (C) 2016-2017 Glider bvba
6 */
7
8#include <linux/bits.h>
9#include <linux/kernel.h>
10#include <linux/sys_soc.h>
11
12#include <dt-bindings/power/r8a7795-sysc.h>
13
14#include "rcar-sysc.h"
15
16static struct rcar_sysc_area r8a7795_areas[] __initdata = {
17 { "always-on", 0, 0, R8A7795_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
18 { "ca57-scu", 0x1c0, 0, R8A7795_PD_CA57_SCU, R8A7795_PD_ALWAYS_ON,
19 PD_SCU },
20 { "ca57-cpu0", 0x80, 0, R8A7795_PD_CA57_CPU0, R8A7795_PD_CA57_SCU,
21 PD_CPU_NOCR },
22 { "ca57-cpu1", 0x80, 1, R8A7795_PD_CA57_CPU1, R8A7795_PD_CA57_SCU,
23 PD_CPU_NOCR },
24 { "ca57-cpu2", 0x80, 2, R8A7795_PD_CA57_CPU2, R8A7795_PD_CA57_SCU,
25 PD_CPU_NOCR },
26 { "ca57-cpu3", 0x80, 3, R8A7795_PD_CA57_CPU3, R8A7795_PD_CA57_SCU,
27 PD_CPU_NOCR },
28 { "ca53-scu", 0x140, 0, R8A7795_PD_CA53_SCU, R8A7795_PD_ALWAYS_ON,
29 PD_SCU },
30 { "ca53-cpu0", 0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU,
31 PD_CPU_NOCR },
32 { "ca53-cpu1", 0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU,
33 PD_CPU_NOCR },
34 { "ca53-cpu2", 0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU,
35 PD_CPU_NOCR },
36 { "ca53-cpu3", 0x200, 3, R8A7795_PD_CA53_CPU3, R8A7795_PD_CA53_SCU,
37 PD_CPU_NOCR },
38 { "a3vp", 0x340, 0, R8A7795_PD_A3VP, R8A7795_PD_ALWAYS_ON },
39 { "cr7", 0x240, 0, R8A7795_PD_CR7, R8A7795_PD_ALWAYS_ON },
40 { "a3vc", 0x380, 0, R8A7795_PD_A3VC, R8A7795_PD_ALWAYS_ON },
41 /* A2VC0 exists on ES1.x only */
42 { "a2vc0", 0x3c0, 0, R8A7795_PD_A2VC0, R8A7795_PD_A3VC },
43 { "a2vc1", 0x3c0, 1, R8A7795_PD_A2VC1, R8A7795_PD_A3VC },
44 { "3dg-a", 0x100, 0, R8A7795_PD_3DG_A, R8A7795_PD_ALWAYS_ON },
45 { "3dg-b", 0x100, 1, R8A7795_PD_3DG_B, R8A7795_PD_3DG_A },
46 { "3dg-c", 0x100, 2, R8A7795_PD_3DG_C, R8A7795_PD_3DG_B },
47 { "3dg-d", 0x100, 3, R8A7795_PD_3DG_D, R8A7795_PD_3DG_C },
48 { "3dg-e", 0x100, 4, R8A7795_PD_3DG_E, R8A7795_PD_3DG_D },
49 { "a3ir", 0x180, 0, R8A7795_PD_A3IR, R8A7795_PD_ALWAYS_ON },
50};
51
52
53 /*
54 * Fixups for R-Car H3 revisions
55 */
56
57#define HAS_A2VC0 BIT(0) /* Power domain A2VC0 is present */
58#define NO_EXTMASK BIT(1) /* Missing SYSCEXTMASK register */
59
60static const struct soc_device_attribute r8a7795_quirks_match[] __initconst = {
61 {
62 .soc_id = "r8a7795", .revision = "ES1.*",
63 .data = (void *)(HAS_A2VC0 | NO_EXTMASK),
64 }, {
65 .soc_id = "r8a7795", .revision = "ES2.*",
66 .data = (void *)(NO_EXTMASK),
67 },
68 { /* sentinel */ }
69};
70
71static int __init r8a7795_sysc_init(void)
72{
73 const struct soc_device_attribute *attr;
74 u32 quirks = 0;
75
76 attr = soc_device_match(r8a7795_quirks_match);
77 if (attr)
78 quirks = (uintptr_t)attr->data;
79
80 if (!(quirks & HAS_A2VC0))
81 rcar_sysc_nullify(r8a7795_areas, ARRAY_SIZE(r8a7795_areas),
82 R8A7795_PD_A2VC0);
83
84 if (quirks & NO_EXTMASK)
85 r8a7795_sysc_info.extmask_val = 0;
86
87 return 0;
88}
89
90struct rcar_sysc_info r8a7795_sysc_info __initdata = {
91 .init = r8a7795_sysc_init,
92 .areas = r8a7795_areas,
93 .num_areas = ARRAY_SIZE(r8a7795_areas),
94 .extmask_offs = 0x2f8,
95 .extmask_val = BIT(0),
96};