1// SPDX-License-Identifier: GPL-2.0-only
   2/* Copyright (c) 2020 Facebook */
   3
   4#include <linux/bits.h>
   5#include <linux/err.h>
   6#include <linux/kernel.h>
   7#include <linux/module.h>
   8#include <linux/debugfs.h>
   9#include <linux/init.h>
  10#include <linux/pci.h>
  11#include <linux/serial_8250.h>
  12#include <linux/clkdev.h>
  13#include <linux/clk-provider.h>
  14#include <linux/platform_device.h>
  15#include <linux/platform_data/i2c-xiic.h>
  16#include <linux/platform_data/i2c-ocores.h>
  17#include <linux/ptp_clock_kernel.h>
  18#include <linux/spi/spi.h>
  19#include <linux/spi/xilinx_spi.h>
  20#include <linux/spi/altera.h>
  21#include <net/devlink.h>
  22#include <linux/i2c.h>
  23#include <linux/mtd/mtd.h>
  24#include <linux/nvmem-consumer.h>
  25#include <linux/crc16.h>
  26
  27#define PCI_VENDOR_ID_FACEBOOK			0x1d9b
  28#define PCI_DEVICE_ID_FACEBOOK_TIMECARD		0x0400
  29
  30#define PCI_VENDOR_ID_CELESTICA			0x18d4
  31#define PCI_DEVICE_ID_CELESTICA_TIMECARD	0x1008
  32
  33#define PCI_VENDOR_ID_OROLIA			0x1ad7
  34#define PCI_DEVICE_ID_OROLIA_ARTCARD		0xa000
  35
  36static struct class timecard_class = {
  37	.owner		= THIS_MODULE,
  38	.name		= "timecard",
  39};
  40
  41struct ocp_reg {
  42	u32	ctrl;
  43	u32	status;
  44	u32	select;
  45	u32	version;
  46	u32	time_ns;
  47	u32	time_sec;
  48	u32	__pad0[2];
  49	u32	adjust_ns;
  50	u32	adjust_sec;
  51	u32	__pad1[2];
  52	u32	offset_ns;
  53	u32	offset_window_ns;
  54	u32	__pad2[2];
  55	u32	drift_ns;
  56	u32	drift_window_ns;
  57	u32	__pad3[6];
  58	u32	servo_offset_p;
  59	u32	servo_offset_i;
  60	u32	servo_drift_p;
  61	u32	servo_drift_i;
  62	u32	status_offset;
  63	u32	status_drift;
  64};
  65
  66#define OCP_CTRL_ENABLE		BIT(0)
  67#define OCP_CTRL_ADJUST_TIME	BIT(1)
  68#define OCP_CTRL_ADJUST_OFFSET	BIT(2)
  69#define OCP_CTRL_ADJUST_DRIFT	BIT(3)
  70#define OCP_CTRL_ADJUST_SERVO	BIT(8)
  71#define OCP_CTRL_READ_TIME_REQ	BIT(30)
  72#define OCP_CTRL_READ_TIME_DONE	BIT(31)
  73
  74#define OCP_STATUS_IN_SYNC	BIT(0)
  75#define OCP_STATUS_IN_HOLDOVER	BIT(1)
  76
  77#define OCP_SELECT_CLK_NONE	0
  78#define OCP_SELECT_CLK_REG	0xfe
  79
  80struct tod_reg {
  81	u32	ctrl;
  82	u32	status;
  83	u32	uart_polarity;
  84	u32	version;
  85	u32	adj_sec;
  86	u32	__pad0[3];
  87	u32	uart_baud;
  88	u32	__pad1[3];
  89	u32	utc_status;
  90	u32	leap;
  91};
  92
  93#define TOD_CTRL_PROTOCOL	BIT(28)
  94#define TOD_CTRL_DISABLE_FMT_A	BIT(17)
  95#define TOD_CTRL_DISABLE_FMT_B	BIT(16)
  96#define TOD_CTRL_ENABLE		BIT(0)
  97#define TOD_CTRL_GNSS_MASK	GENMASK(3, 0)
  98#define TOD_CTRL_GNSS_SHIFT	24
  99
 100#define TOD_STATUS_UTC_MASK		GENMASK(7, 0)
 101#define TOD_STATUS_UTC_VALID		BIT(8)
 102#define TOD_STATUS_LEAP_ANNOUNCE	BIT(12)
 103#define TOD_STATUS_LEAP_VALID		BIT(16)
 104
 105struct ts_reg {
 106	u32	enable;
 107	u32	error;
 108	u32	polarity;
 109	u32	version;
 110	u32	__pad0[4];
 111	u32	cable_delay;
 112	u32	__pad1[3];
 113	u32	intr;
 114	u32	intr_mask;
 115	u32	event_count;
 116	u32	__pad2[1];
 117	u32	ts_count;
 118	u32	time_ns;
 119	u32	time_sec;
 120	u32	data_width;
 121	u32	data;
 122};
 123
 124struct pps_reg {
 125	u32	ctrl;
 126	u32	status;
 127	u32	__pad0[6];
 128	u32	cable_delay;
 129};
 130
 131#define PPS_STATUS_FILTER_ERR	BIT(0)
 132#define PPS_STATUS_SUPERV_ERR	BIT(1)
 133
 134struct img_reg {
 135	u32	version;
 136};
 137
 138struct gpio_reg {
 139	u32	gpio1;
 140	u32	__pad0;
 141	u32	gpio2;
 142	u32	__pad1;
 143};
 144
 145struct irig_master_reg {
 146	u32	ctrl;
 147	u32	status;
 148	u32	__pad0;
 149	u32	version;
 150	u32	adj_sec;
 151	u32	mode_ctrl;
 152};
 153
 154#define IRIG_M_CTRL_ENABLE	BIT(0)
 155
 156struct irig_slave_reg {
 157	u32	ctrl;
 158	u32	status;
 159	u32	__pad0;
 160	u32	version;
 161	u32	adj_sec;
 162	u32	mode_ctrl;
 163};
 164
 165#define IRIG_S_CTRL_ENABLE	BIT(0)
 166
 167struct dcf_master_reg {
 168	u32	ctrl;
 169	u32	status;
 170	u32	__pad0;
 171	u32	version;
 172	u32	adj_sec;
 173};
 174
 175#define DCF_M_CTRL_ENABLE	BIT(0)
 176
 177struct dcf_slave_reg {
 178	u32	ctrl;
 179	u32	status;
 180	u32	__pad0;
 181	u32	version;
 182	u32	adj_sec;
 183};
 184
 185#define DCF_S_CTRL_ENABLE	BIT(0)
 186
 187struct signal_reg {
 188	u32	enable;
 189	u32	status;
 190	u32	polarity;
 191	u32	version;
 192	u32	__pad0[4];
 193	u32	cable_delay;
 194	u32	__pad1[3];
 195	u32	intr;
 196	u32	intr_mask;
 197	u32	__pad2[2];
 198	u32	start_ns;
 199	u32	start_sec;
 200	u32	pulse_ns;
 201	u32	pulse_sec;
 202	u32	period_ns;
 203	u32	period_sec;
 204	u32	repeat_count;
 205};
 206
 207struct frequency_reg {
 208	u32	ctrl;
 209	u32	status;
 210};
 211
 212struct board_config_reg {
 213	u32 mro50_serial_activate;
 214};
 215
 216#define FREQ_STATUS_VALID	BIT(31)
 217#define FREQ_STATUS_ERROR	BIT(30)
 218#define FREQ_STATUS_OVERRUN	BIT(29)
 219#define FREQ_STATUS_MASK	GENMASK(23, 0)
 220
 221struct ptp_ocp_flash_info {
 222	const char *name;
 223	int pci_offset;
 224	int data_size;
 225	void *data;
 226};
 227
 228struct ptp_ocp_firmware_header {
 229	char magic[4];
 230	__be16 pci_vendor_id;
 231	__be16 pci_device_id;
 232	__be32 image_size;
 233	__be16 hw_revision;
 234	__be16 crc;
 235};
 236
 237#define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
 238
 239struct ptp_ocp_i2c_info {
 240	const char *name;
 241	unsigned long fixed_rate;
 242	size_t data_size;
 243	void *data;
 244};
 245
 246struct ptp_ocp_ext_info {
 247	int index;
 248	irqreturn_t (*irq_fcn)(int irq, void *priv);
 249	int (*enable)(void *priv, u32 req, bool enable);
 250};
 251
 252struct ptp_ocp_ext_src {
 253	void __iomem		*mem;
 254	struct ptp_ocp		*bp;
 255	struct ptp_ocp_ext_info	*info;
 256	int			irq_vec;
 257};
 258
 259enum ptp_ocp_sma_mode {
 260	SMA_MODE_IN,
 261	SMA_MODE_OUT,
 262};
 263
 264struct ptp_ocp_sma_connector {
 265	enum	ptp_ocp_sma_mode mode;
 266	bool	fixed_fcn;
 267	bool	fixed_dir;
 268	bool	disabled;
 269	u8	default_fcn;
 270};
 271
 272struct ocp_attr_group {
 273	u64 cap;
 274	const struct attribute_group *group;
 275};
 276
 277#define OCP_CAP_BASIC	BIT(0)
 278#define OCP_CAP_SIGNAL	BIT(1)
 279#define OCP_CAP_FREQ	BIT(2)
 280
 281struct ptp_ocp_signal {
 282	ktime_t		period;
 283	ktime_t		pulse;
 284	ktime_t		phase;
 285	ktime_t		start;
 286	int		duty;
 287	bool		polarity;
 288	bool		running;
 289};
 290
 291struct ptp_ocp_serial_port {
 292	int line;
 293	int baud;
 294};
 295
 296#define OCP_BOARD_ID_LEN		13
 297#define OCP_SERIAL_LEN			6
 298
 299struct ptp_ocp {
 300	struct pci_dev		*pdev;
 301	struct device		dev;
 302	spinlock_t		lock;
 303	struct ocp_reg __iomem	*reg;
 304	struct tod_reg __iomem	*tod;
 305	struct pps_reg __iomem	*pps_to_ext;
 306	struct pps_reg __iomem	*pps_to_clk;
 307	struct board_config_reg __iomem	*board_config;
 308	struct gpio_reg __iomem	*pps_select;
 309	struct gpio_reg __iomem	*sma_map1;
 310	struct gpio_reg __iomem	*sma_map2;
 311	struct irig_master_reg	__iomem *irig_out;
 312	struct irig_slave_reg	__iomem *irig_in;
 313	struct dcf_master_reg	__iomem *dcf_out;
 314	struct dcf_slave_reg	__iomem *dcf_in;
 315	struct tod_reg		__iomem *nmea_out;
 316	struct frequency_reg	__iomem *freq_in[4];
 317	struct ptp_ocp_ext_src	*signal_out[4];
 318	struct ptp_ocp_ext_src	*pps;
 319	struct ptp_ocp_ext_src	*ts0;
 320	struct ptp_ocp_ext_src	*ts1;
 321	struct ptp_ocp_ext_src	*ts2;
 322	struct ptp_ocp_ext_src	*ts3;
 323	struct ptp_ocp_ext_src	*ts4;
 324	struct ocp_art_gpio_reg __iomem *art_sma;
 325	struct img_reg __iomem	*image;
 326	struct ptp_clock	*ptp;
 327	struct ptp_clock_info	ptp_info;
 328	struct platform_device	*i2c_ctrl;
 329	struct platform_device	*spi_flash;
 330	struct clk_hw		*i2c_clk;
 331	struct timer_list	watchdog;
 332	const struct attribute_group **attr_group;
 333	const struct ptp_ocp_eeprom_map *eeprom_map;
 334	struct dentry		*debug_root;
 335	time64_t		gnss_lost;
 336	int			id;
 337	int			n_irqs;
 338	struct ptp_ocp_serial_port	gnss_port;
 339	struct ptp_ocp_serial_port	gnss2_port;
 340	struct ptp_ocp_serial_port	mac_port;   /* miniature atomic clock */
 341	struct ptp_ocp_serial_port	nmea_port;
 342	bool			fw_loader;
 343	u8			fw_tag;
 344	u16			fw_version;
 345	u8			board_id[OCP_BOARD_ID_LEN];
 346	u8			serial[OCP_SERIAL_LEN];
 347	bool			has_eeprom_data;
 348	u32			pps_req_map;
 349	int			flash_start;
 350	u32			utc_tai_offset;
 351	u32			ts_window_adjust;
 352	u64			fw_cap;
 353	struct ptp_ocp_signal	signal[4];
 354	struct ptp_ocp_sma_connector sma[4];
 355	const struct ocp_sma_op *sma_op;
 356};
 357
 358#define OCP_REQ_TIMESTAMP	BIT(0)
 359#define OCP_REQ_PPS		BIT(1)
 360
 361struct ocp_resource {
 362	unsigned long offset;
 363	int size;
 364	int irq_vec;
 365	int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
 366	void *extra;
 367	unsigned long bp_offset;
 368	const char * const name;
 369};
 370
 371static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
 372static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
 373static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
 374static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
 375static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
 376static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
 377static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
 378static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
 379static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
 380static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
 381				      struct ptp_perout_request *req);
 382static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
 383static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
 384
 385static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
 386
 387static const struct ocp_attr_group fb_timecard_groups[];
 388
 389static const struct ocp_attr_group art_timecard_groups[];
 390
 391struct ptp_ocp_eeprom_map {
 392	u16	off;
 393	u16	len;
 394	u32	bp_offset;
 395	const void * const tag;
 396};
 397
 398#define EEPROM_ENTRY(addr, member)				\
 399	.off = addr,						\
 400	.len = sizeof_field(struct ptp_ocp, member),		\
 401	.bp_offset = offsetof(struct ptp_ocp, member)
 402
 403#define BP_MAP_ENTRY_ADDR(bp, map) ({				\
 404	(void *)((uintptr_t)(bp) + (map)->bp_offset);		\
 405})
 406
 407static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
 408	{ EEPROM_ENTRY(0x43, board_id) },
 409	{ EEPROM_ENTRY(0x00, serial), .tag = "mac" },
 410	{ }
 411};
 412
 413static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
 414	{ EEPROM_ENTRY(0x200 + 0x43, board_id) },
 415	{ EEPROM_ENTRY(0x200 + 0x63, serial) },
 416	{ }
 417};
 418
 419#define bp_assign_entry(bp, res, val) ({				\
 420	uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset;		\
 421	*(typeof(val) *)addr = val;					\
 422})
 423
 424#define OCP_RES_LOCATION(member) \
 425	.name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
 426
 427#define OCP_MEM_RESOURCE(member) \
 428	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
 429
 430#define OCP_SERIAL_RESOURCE(member) \
 431	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
 432
 433#define OCP_I2C_RESOURCE(member) \
 434	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
 435
 436#define OCP_SPI_RESOURCE(member) \
 437	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
 438
 439#define OCP_EXT_RESOURCE(member) \
 440	OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
 441
 442/* This is the MSI vector mapping used.
 443 * 0: PPS (TS5)
 444 * 1: TS0
 445 * 2: TS1
 446 * 3: GNSS1
 447 * 4: GNSS2
 448 * 5: MAC
 449 * 6: TS2
 450 * 7: I2C controller
 451 * 8: HWICAP (notused)
 452 * 9: SPI Flash
 453 * 10: NMEA
 454 * 11: Signal Generator 1
 455 * 12: Signal Generator 2
 456 * 13: Signal Generator 3
 457 * 14: Signal Generator 4
 458 * 15: TS3
 459 * 16: TS4
 460 --
 461 * 8: Orolia TS1
 462 * 10: Orolia TS2
 463 * 11: Orolia TS0 (GNSS)
 464 * 12: Orolia PPS
 465 * 14: Orolia TS3
 466 * 15: Orolia TS4
 467 */
 468
 469static struct ocp_resource ocp_fb_resource[] = {
 470	{
 471		OCP_MEM_RESOURCE(reg),
 472		.offset = 0x01000000, .size = 0x10000,
 473	},
 474	{
 475		OCP_EXT_RESOURCE(ts0),
 476		.offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
 477		.extra = &(struct ptp_ocp_ext_info) {
 478			.index = 0,
 479			.irq_fcn = ptp_ocp_ts_irq,
 480			.enable = ptp_ocp_ts_enable,
 481		},
 482	},
 483	{
 484		OCP_EXT_RESOURCE(ts1),
 485		.offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
 486		.extra = &(struct ptp_ocp_ext_info) {
 487			.index = 1,
 488			.irq_fcn = ptp_ocp_ts_irq,
 489			.enable = ptp_ocp_ts_enable,
 490		},
 491	},
 492	{
 493		OCP_EXT_RESOURCE(ts2),
 494		.offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
 495		.extra = &(struct ptp_ocp_ext_info) {
 496			.index = 2,
 497			.irq_fcn = ptp_ocp_ts_irq,
 498			.enable = ptp_ocp_ts_enable,
 499		},
 500	},
 501	{
 502		OCP_EXT_RESOURCE(ts3),
 503		.offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
 504		.extra = &(struct ptp_ocp_ext_info) {
 505			.index = 3,
 506			.irq_fcn = ptp_ocp_ts_irq,
 507			.enable = ptp_ocp_ts_enable,
 508		},
 509	},
 510	{
 511		OCP_EXT_RESOURCE(ts4),
 512		.offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
 513		.extra = &(struct ptp_ocp_ext_info) {
 514			.index = 4,
 515			.irq_fcn = ptp_ocp_ts_irq,
 516			.enable = ptp_ocp_ts_enable,
 517		},
 518	},
 519	/* Timestamp for PHC and/or PPS generator */
 520	{
 521		OCP_EXT_RESOURCE(pps),
 522		.offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
 523		.extra = &(struct ptp_ocp_ext_info) {
 524			.index = 5,
 525			.irq_fcn = ptp_ocp_ts_irq,
 526			.enable = ptp_ocp_ts_enable,
 527		},
 528	},
 529	{
 530		OCP_EXT_RESOURCE(signal_out[0]),
 531		.offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
 532		.extra = &(struct ptp_ocp_ext_info) {
 533			.index = 1,
 534			.irq_fcn = ptp_ocp_signal_irq,
 535			.enable = ptp_ocp_signal_enable,
 536		},
 537	},
 538	{
 539		OCP_EXT_RESOURCE(signal_out[1]),
 540		.offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
 541		.extra = &(struct ptp_ocp_ext_info) {
 542			.index = 2,
 543			.irq_fcn = ptp_ocp_signal_irq,
 544			.enable = ptp_ocp_signal_enable,
 545		},
 546	},
 547	{
 548		OCP_EXT_RESOURCE(signal_out[2]),
 549		.offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
 550		.extra = &(struct ptp_ocp_ext_info) {
 551			.index = 3,
 552			.irq_fcn = ptp_ocp_signal_irq,
 553			.enable = ptp_ocp_signal_enable,
 554		},
 555	},
 556	{
 557		OCP_EXT_RESOURCE(signal_out[3]),
 558		.offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
 559		.extra = &(struct ptp_ocp_ext_info) {
 560			.index = 4,
 561			.irq_fcn = ptp_ocp_signal_irq,
 562			.enable = ptp_ocp_signal_enable,
 563		},
 564	},
 565	{
 566		OCP_MEM_RESOURCE(pps_to_ext),
 567		.offset = 0x01030000, .size = 0x10000,
 568	},
 569	{
 570		OCP_MEM_RESOURCE(pps_to_clk),
 571		.offset = 0x01040000, .size = 0x10000,
 572	},
 573	{
 574		OCP_MEM_RESOURCE(tod),
 575		.offset = 0x01050000, .size = 0x10000,
 576	},
 577	{
 578		OCP_MEM_RESOURCE(irig_in),
 579		.offset = 0x01070000, .size = 0x10000,
 580	},
 581	{
 582		OCP_MEM_RESOURCE(irig_out),
 583		.offset = 0x01080000, .size = 0x10000,
 584	},
 585	{
 586		OCP_MEM_RESOURCE(dcf_in),
 587		.offset = 0x01090000, .size = 0x10000,
 588	},
 589	{
 590		OCP_MEM_RESOURCE(dcf_out),
 591		.offset = 0x010A0000, .size = 0x10000,
 592	},
 593	{
 594		OCP_MEM_RESOURCE(nmea_out),
 595		.offset = 0x010B0000, .size = 0x10000,
 596	},
 597	{
 598		OCP_MEM_RESOURCE(image),
 599		.offset = 0x00020000, .size = 0x1000,
 600	},
 601	{
 602		OCP_MEM_RESOURCE(pps_select),
 603		.offset = 0x00130000, .size = 0x1000,
 604	},
 605	{
 606		OCP_MEM_RESOURCE(sma_map1),
 607		.offset = 0x00140000, .size = 0x1000,
 608	},
 609	{
 610		OCP_MEM_RESOURCE(sma_map2),
 611		.offset = 0x00220000, .size = 0x1000,
 612	},
 613	{
 614		OCP_I2C_RESOURCE(i2c_ctrl),
 615		.offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
 616		.extra = &(struct ptp_ocp_i2c_info) {
 617			.name = "xiic-i2c",
 618			.fixed_rate = 50000000,
 619			.data_size = sizeof(struct xiic_i2c_platform_data),
 620			.data = &(struct xiic_i2c_platform_data) {
 621				.num_devices = 2,
 622				.devices = (struct i2c_board_info[]) {
 623					{ I2C_BOARD_INFO("24c02", 0x50) },
 624					{ I2C_BOARD_INFO("24mac402", 0x58),
 625					  .platform_data = "mac" },
 626				},
 627			},
 628		},
 629	},
 630	{
 631		OCP_SERIAL_RESOURCE(gnss_port),
 632		.offset = 0x00160000 + 0x1000, .irq_vec = 3,
 633		.extra = &(struct ptp_ocp_serial_port) {
 634			.baud = 115200,
 635		},
 636	},
 637	{
 638		OCP_SERIAL_RESOURCE(gnss2_port),
 639		.offset = 0x00170000 + 0x1000, .irq_vec = 4,
 640		.extra = &(struct ptp_ocp_serial_port) {
 641			.baud = 115200,
 642		},
 643	},
 644	{
 645		OCP_SERIAL_RESOURCE(mac_port),
 646		.offset = 0x00180000 + 0x1000, .irq_vec = 5,
 647		.extra = &(struct ptp_ocp_serial_port) {
 648			.baud = 57600,
 649		},
 650	},
 651	{
 652		OCP_SERIAL_RESOURCE(nmea_port),
 653		.offset = 0x00190000 + 0x1000, .irq_vec = 10,
 654	},
 655	{
 656		OCP_SPI_RESOURCE(spi_flash),
 657		.offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
 658		.extra = &(struct ptp_ocp_flash_info) {
 659			.name = "xilinx_spi", .pci_offset = 0,
 660			.data_size = sizeof(struct xspi_platform_data),
 661			.data = &(struct xspi_platform_data) {
 662				.num_chipselect = 1,
 663				.bits_per_word = 8,
 664				.num_devices = 1,
 665				.devices = &(struct spi_board_info) {
 666					.modalias = "spi-nor",
 667				},
 668			},
 669		},
 670	},
 671	{
 672		OCP_MEM_RESOURCE(freq_in[0]),
 673		.offset = 0x01200000, .size = 0x10000,
 674	},
 675	{
 676		OCP_MEM_RESOURCE(freq_in[1]),
 677		.offset = 0x01210000, .size = 0x10000,
 678	},
 679	{
 680		OCP_MEM_RESOURCE(freq_in[2]),
 681		.offset = 0x01220000, .size = 0x10000,
 682	},
 683	{
 684		OCP_MEM_RESOURCE(freq_in[3]),
 685		.offset = 0x01230000, .size = 0x10000,
 686	},
 687	{
 688		.setup = ptp_ocp_fb_board_init,
 689	},
 690	{ }
 691};
 692
 693#define OCP_ART_CONFIG_SIZE		144
 694#define OCP_ART_TEMP_TABLE_SIZE		368
 695
 696struct ocp_art_gpio_reg {
 697	struct {
 698		u32	gpio;
 699		u32	__pad[3];
 700	} map[4];
 701};
 702
 703static struct ocp_resource ocp_art_resource[] = {
 704	{
 705		OCP_MEM_RESOURCE(reg),
 706		.offset = 0x01000000, .size = 0x10000,
 707	},
 708	{
 709		OCP_SERIAL_RESOURCE(gnss_port),
 710		.offset = 0x00160000 + 0x1000, .irq_vec = 3,
 711		.extra = &(struct ptp_ocp_serial_port) {
 712			.baud = 115200,
 713		},
 714	},
 715	{
 716		OCP_MEM_RESOURCE(art_sma),
 717		.offset = 0x003C0000, .size = 0x1000,
 718	},
 719	/* Timestamp associated with GNSS1 receiver PPS */
 720	{
 721		OCP_EXT_RESOURCE(ts0),
 722		.offset = 0x360000, .size = 0x20, .irq_vec = 12,
 723		.extra = &(struct ptp_ocp_ext_info) {
 724			.index = 0,
 725			.irq_fcn = ptp_ocp_ts_irq,
 726			.enable = ptp_ocp_ts_enable,
 727		},
 728	},
 729	{
 730		OCP_EXT_RESOURCE(ts1),
 731		.offset = 0x380000, .size = 0x20, .irq_vec = 8,
 732		.extra = &(struct ptp_ocp_ext_info) {
 733			.index = 1,
 734			.irq_fcn = ptp_ocp_ts_irq,
 735			.enable = ptp_ocp_ts_enable,
 736		},
 737	},
 738	{
 739		OCP_EXT_RESOURCE(ts2),
 740		.offset = 0x390000, .size = 0x20, .irq_vec = 10,
 741		.extra = &(struct ptp_ocp_ext_info) {
 742			.index = 2,
 743			.irq_fcn = ptp_ocp_ts_irq,
 744			.enable = ptp_ocp_ts_enable,
 745		},
 746	},
 747	{
 748		OCP_EXT_RESOURCE(ts3),
 749		.offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
 750		.extra = &(struct ptp_ocp_ext_info) {
 751			.index = 3,
 752			.irq_fcn = ptp_ocp_ts_irq,
 753			.enable = ptp_ocp_ts_enable,
 754		},
 755	},
 756	{
 757		OCP_EXT_RESOURCE(ts4),
 758		.offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
 759		.extra = &(struct ptp_ocp_ext_info) {
 760			.index = 4,
 761			.irq_fcn = ptp_ocp_ts_irq,
 762			.enable = ptp_ocp_ts_enable,
 763		},
 764	},
 765	/* Timestamp associated with Internal PPS of the card */
 766	{
 767		OCP_EXT_RESOURCE(pps),
 768		.offset = 0x00330000, .size = 0x20, .irq_vec = 11,
 769		.extra = &(struct ptp_ocp_ext_info) {
 770			.index = 5,
 771			.irq_fcn = ptp_ocp_ts_irq,
 772			.enable = ptp_ocp_ts_enable,
 773		},
 774	},
 775	{
 776		OCP_SPI_RESOURCE(spi_flash),
 777		.offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
 778		.extra = &(struct ptp_ocp_flash_info) {
 779			.name = "spi_altera", .pci_offset = 0,
 780			.data_size = sizeof(struct altera_spi_platform_data),
 781			.data = &(struct altera_spi_platform_data) {
 782				.num_chipselect = 1,
 783				.num_devices = 1,
 784				.devices = &(struct spi_board_info) {
 785					.modalias = "spi-nor",
 786				},
 787			},
 788		},
 789	},
 790	{
 791		OCP_I2C_RESOURCE(i2c_ctrl),
 792		.offset = 0x350000, .size = 0x100, .irq_vec = 4,
 793		.extra = &(struct ptp_ocp_i2c_info) {
 794			.name = "ocores-i2c",
 795			.fixed_rate = 400000,
 796			.data_size = sizeof(struct ocores_i2c_platform_data),
 797			.data = &(struct ocores_i2c_platform_data) {
 798				.clock_khz = 125000,
 799				.bus_khz = 400,
 800				.num_devices = 1,
 801				.devices = &(struct i2c_board_info) {
 802					I2C_BOARD_INFO("24c08", 0x50),
 803				},
 804			},
 805		},
 806	},
 807	{
 808		OCP_SERIAL_RESOURCE(mac_port),
 809		.offset = 0x00190000, .irq_vec = 7,
 810		.extra = &(struct ptp_ocp_serial_port) {
 811			.baud = 9600,
 812		},
 813	},
 814	{
 815		OCP_MEM_RESOURCE(board_config),
 816		.offset = 0x210000, .size = 0x1000,
 817	},
 818	{
 819		.setup = ptp_ocp_art_board_init,
 820	},
 821	{ }
 822};
 823
 824static const struct pci_device_id ptp_ocp_pcidev_id[] = {
 825	{ PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
 826	{ PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
 827	{ PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
 828	{ }
 829};
 830MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
 831
 832static DEFINE_MUTEX(ptp_ocp_lock);
 833static DEFINE_IDR(ptp_ocp_idr);
 834
 835struct ocp_selector {
 836	const char *name;
 837	int value;
 838};
 839
 840static const struct ocp_selector ptp_ocp_clock[] = {
 841	{ .name = "NONE",	.value = 0 },
 842	{ .name = "TOD",	.value = 1 },
 843	{ .name = "IRIG",	.value = 2 },
 844	{ .name = "PPS",	.value = 3 },
 845	{ .name = "PTP",	.value = 4 },
 846	{ .name = "RTC",	.value = 5 },
 847	{ .name = "DCF",	.value = 6 },
 848	{ .name = "REGS",	.value = 0xfe },
 849	{ .name = "EXT",	.value = 0xff },
 850	{ }
 851};
 852
 853#define SMA_DISABLE		BIT(16)
 854#define SMA_ENABLE		BIT(15)
 855#define SMA_SELECT_MASK		GENMASK(14, 0)
 856
 857static const struct ocp_selector ptp_ocp_sma_in[] = {
 858	{ .name = "10Mhz",	.value = 0x0000 },
 859	{ .name = "PPS1",	.value = 0x0001 },
 860	{ .name = "PPS2",	.value = 0x0002 },
 861	{ .name = "TS1",	.value = 0x0004 },
 862	{ .name = "TS2",	.value = 0x0008 },
 863	{ .name = "IRIG",	.value = 0x0010 },
 864	{ .name = "DCF",	.value = 0x0020 },
 865	{ .name = "TS3",	.value = 0x0040 },
 866	{ .name = "TS4",	.value = 0x0080 },
 867	{ .name = "FREQ1",	.value = 0x0100 },
 868	{ .name = "FREQ2",	.value = 0x0200 },
 869	{ .name = "FREQ3",	.value = 0x0400 },
 870	{ .name = "FREQ4",	.value = 0x0800 },
 871	{ .name = "None",	.value = SMA_DISABLE },
 872	{ }
 873};
 874
 875static const struct ocp_selector ptp_ocp_sma_out[] = {
 876	{ .name = "10Mhz",	.value = 0x0000 },
 877	{ .name = "PHC",	.value = 0x0001 },
 878	{ .name = "MAC",	.value = 0x0002 },
 879	{ .name = "GNSS1",	.value = 0x0004 },
 880	{ .name = "GNSS2",	.value = 0x0008 },
 881	{ .name = "IRIG",	.value = 0x0010 },
 882	{ .name = "DCF",	.value = 0x0020 },
 883	{ .name = "GEN1",	.value = 0x0040 },
 884	{ .name = "GEN2",	.value = 0x0080 },
 885	{ .name = "GEN3",	.value = 0x0100 },
 886	{ .name = "GEN4",	.value = 0x0200 },
 887	{ .name = "GND",	.value = 0x2000 },
 888	{ .name = "VCC",	.value = 0x4000 },
 889	{ }
 890};
 891
 892static const struct ocp_selector ptp_ocp_art_sma_in[] = {
 893	{ .name = "PPS1",	.value = 0x0001 },
 894	{ .name = "10Mhz",	.value = 0x0008 },
 895	{ }
 896};
 897
 898static const struct ocp_selector ptp_ocp_art_sma_out[] = {
 899	{ .name = "PHC",	.value = 0x0002 },
 900	{ .name = "GNSS",	.value = 0x0004 },
 901	{ .name = "10Mhz",	.value = 0x0010 },
 902	{ }
 903};
 904
 905struct ocp_sma_op {
 906	const struct ocp_selector *tbl[2];
 907	void (*init)(struct ptp_ocp *bp);
 908	u32 (*get)(struct ptp_ocp *bp, int sma_nr);
 909	int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
 910	int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
 911};
 912
 913static void
 914ptp_ocp_sma_init(struct ptp_ocp *bp)
 915{
 916	return bp->sma_op->init(bp);
 917}
 918
 919static u32
 920ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
 921{
 922	return bp->sma_op->get(bp, sma_nr);
 923}
 924
 925static int
 926ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
 927{
 928	return bp->sma_op->set_inputs(bp, sma_nr, val);
 929}
 930
 931static int
 932ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
 933{
 934	return bp->sma_op->set_output(bp, sma_nr, val);
 935}
 936
 937static const char *
 938ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
 939{
 940	int i;
 941
 942	for (i = 0; tbl[i].name; i++)
 943		if (tbl[i].value == val)
 944			return tbl[i].name;
 945	return NULL;
 946}
 947
 948static int
 949ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
 950{
 951	const char *select;
 952	int i;
 953
 954	for (i = 0; tbl[i].name; i++) {
 955		select = tbl[i].name;
 956		if (!strncasecmp(name, select, strlen(select)))
 957			return tbl[i].value;
 958	}
 959	return -EINVAL;
 960}
 961
 962static ssize_t
 963ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
 964{
 965	ssize_t count;
 966	int i;
 967
 968	count = 0;
 969	for (i = 0; tbl[i].name; i++)
 970		count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
 971	if (count)
 972		count--;
 973	count += sysfs_emit_at(buf, count, "\n");
 974	return count;
 975}
 976
 977static int
 978__ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
 979			 struct ptp_system_timestamp *sts)
 980{
 981	u32 ctrl, time_sec, time_ns;
 982	int i;
 983
 984	ptp_read_system_prets(sts);
 985
 986	ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
 987	iowrite32(ctrl, &bp->reg->ctrl);
 988
 989	for (i = 0; i < 100; i++) {
 990		ctrl = ioread32(&bp->reg->ctrl);
 991		if (ctrl & OCP_CTRL_READ_TIME_DONE)
 992			break;
 993	}
 994	ptp_read_system_postts(sts);
 995
 996	if (sts && bp->ts_window_adjust) {
 997		s64 ns = timespec64_to_ns(&sts->post_ts);
 998
 999		sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
1000	}
1001
1002	time_ns = ioread32(&bp->reg->time_ns);
1003	time_sec = ioread32(&bp->reg->time_sec);
1004
1005	ts->tv_sec = time_sec;
1006	ts->tv_nsec = time_ns;
1007
1008	return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1009}
1010
1011static int
1012ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1013		 struct ptp_system_timestamp *sts)
1014{
1015	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1016	unsigned long flags;
1017	int err;
1018
1019	spin_lock_irqsave(&bp->lock, flags);
1020	err = __ptp_ocp_gettime_locked(bp, ts, sts);
1021	spin_unlock_irqrestore(&bp->lock, flags);
1022
1023	return err;
1024}
1025
1026static void
1027__ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1028{
1029	u32 ctrl, time_sec, time_ns;
1030	u32 select;
1031
1032	time_ns = ts->tv_nsec;
1033	time_sec = ts->tv_sec;
1034
1035	select = ioread32(&bp->reg->select);
1036	iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1037
1038	iowrite32(time_ns, &bp->reg->adjust_ns);
1039	iowrite32(time_sec, &bp->reg->adjust_sec);
1040
1041	ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1042	iowrite32(ctrl, &bp->reg->ctrl);
1043
1044	/* restore clock selection */
1045	iowrite32(select >> 16, &bp->reg->select);
1046}
1047
1048static int
1049ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1050{
1051	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1052	unsigned long flags;
1053
1054	spin_lock_irqsave(&bp->lock, flags);
1055	__ptp_ocp_settime_locked(bp, ts);
1056	spin_unlock_irqrestore(&bp->lock, flags);
1057
1058	return 0;
1059}
1060
1061static void
1062__ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1063{
1064	u32 select, ctrl;
1065
1066	select = ioread32(&bp->reg->select);
1067	iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1068
1069	iowrite32(adj_val, &bp->reg->offset_ns);
1070	iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1071
1072	ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1073	iowrite32(ctrl, &bp->reg->ctrl);
1074
1075	/* restore clock selection */
1076	iowrite32(select >> 16, &bp->reg->select);
1077}
1078
1079static void
1080ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1081{
1082	struct timespec64 ts;
1083	unsigned long flags;
1084	int err;
1085
1086	spin_lock_irqsave(&bp->lock, flags);
1087	err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1088	if (likely(!err)) {
1089		set_normalized_timespec64(&ts, ts.tv_sec,
1090					  ts.tv_nsec + delta_ns);
1091		__ptp_ocp_settime_locked(bp, &ts);
1092	}
1093	spin_unlock_irqrestore(&bp->lock, flags);
1094}
1095
1096static int
1097ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1098{
1099	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1100	unsigned long flags;
1101	u32 adj_ns, sign;
1102
1103	if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1104		ptp_ocp_adjtime_coarse(bp, delta_ns);
1105		return 0;
1106	}
1107
1108	sign = delta_ns < 0 ? BIT(31) : 0;
1109	adj_ns = sign ? -delta_ns : delta_ns;
1110
1111	spin_lock_irqsave(&bp->lock, flags);
1112	__ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1113	spin_unlock_irqrestore(&bp->lock, flags);
1114
1115	return 0;
1116}
1117
1118static int
1119ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1120{
1121	if (scaled_ppm == 0)
1122		return 0;
1123
1124	return -EOPNOTSUPP;
1125}
1126
1127static int
1128ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1129{
1130	return -EOPNOTSUPP;
1131}
1132
1133static int
1134ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1135	       int on)
1136{
1137	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1138	struct ptp_ocp_ext_src *ext = NULL;
1139	u32 req;
1140	int err;
1141
1142	switch (rq->type) {
1143	case PTP_CLK_REQ_EXTTS:
1144		req = OCP_REQ_TIMESTAMP;
1145		switch (rq->extts.index) {
1146		case 0:
1147			ext = bp->ts0;
1148			break;
1149		case 1:
1150			ext = bp->ts1;
1151			break;
1152		case 2:
1153			ext = bp->ts2;
1154			break;
1155		case 3:
1156			ext = bp->ts3;
1157			break;
1158		case 4:
1159			ext = bp->ts4;
1160			break;
1161		case 5:
1162			ext = bp->pps;
1163			break;
1164		}
1165		break;
1166	case PTP_CLK_REQ_PPS:
1167		req = OCP_REQ_PPS;
1168		ext = bp->pps;
1169		break;
1170	case PTP_CLK_REQ_PEROUT:
1171		switch (rq->perout.index) {
1172		case 0:
1173			/* This is a request for 1PPS on an output SMA.
1174			 * Allow, but assume manual configuration.
1175			 */
1176			if (on && (rq->perout.period.sec != 1 ||
1177				   rq->perout.period.nsec != 0))
1178				return -EINVAL;
1179			return 0;
1180		case 1:
1181		case 2:
1182		case 3:
1183		case 4:
1184			req = rq->perout.index - 1;
1185			ext = bp->signal_out[req];
1186			err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1187			if (err)
1188				return err;
1189			break;
1190		}
1191		break;
1192	default:
1193		return -EOPNOTSUPP;
1194	}
1195
1196	err = -ENXIO;
1197	if (ext)
1198		err = ext->info->enable(ext, req, on);
1199
1200	return err;
1201}
1202
1203static int
1204ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1205	       enum ptp_pin_function func, unsigned chan)
1206{
1207	struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1208	char buf[16];
1209
1210	switch (func) {
1211	case PTP_PF_NONE:
1212		snprintf(buf, sizeof(buf), "IN: None");
1213		break;
1214	case PTP_PF_EXTTS:
1215		/* Allow timestamps, but require sysfs configuration. */
1216		return 0;
1217	case PTP_PF_PEROUT:
1218		/* channel 0 is 1PPS from PHC.
1219		 * channels 1..4 are the frequency generators.
1220		 */
1221		if (chan)
1222			snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1223		else
1224			snprintf(buf, sizeof(buf), "OUT: PHC");
1225		break;
1226	default:
1227		return -EOPNOTSUPP;
1228	}
1229
1230	return ptp_ocp_sma_store(bp, buf, pin + 1);
1231}
1232
1233static const struct ptp_clock_info ptp_ocp_clock_info = {
1234	.owner		= THIS_MODULE,
1235	.name		= KBUILD_MODNAME,
1236	.max_adj	= 100000000,
1237	.gettimex64	= ptp_ocp_gettimex,
1238	.settime64	= ptp_ocp_settime,
1239	.adjtime	= ptp_ocp_adjtime,
1240	.adjfine	= ptp_ocp_null_adjfine,
1241	.adjphase	= ptp_ocp_null_adjphase,
1242	.enable		= ptp_ocp_enable,
1243	.verify		= ptp_ocp_verify,
1244	.pps		= true,
1245	.n_ext_ts	= 6,
1246	.n_per_out	= 5,
1247};
1248
1249static void
1250__ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1251{
1252	u32 ctrl, select;
1253
1254	select = ioread32(&bp->reg->select);
1255	iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1256
1257	iowrite32(0, &bp->reg->drift_ns);
1258
1259	ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1260	iowrite32(ctrl, &bp->reg->ctrl);
1261
1262	/* restore clock selection */
1263	iowrite32(select >> 16, &bp->reg->select);
1264}
1265
1266static void
1267ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1268{
1269	unsigned long flags;
1270
1271	spin_lock_irqsave(&bp->lock, flags);
1272
1273	bp->utc_tai_offset = val;
1274
1275	if (bp->irig_out)
1276		iowrite32(val, &bp->irig_out->adj_sec);
1277	if (bp->dcf_out)
1278		iowrite32(val, &bp->dcf_out->adj_sec);
1279	if (bp->nmea_out)
1280		iowrite32(val, &bp->nmea_out->adj_sec);
1281
1282	spin_unlock_irqrestore(&bp->lock, flags);
1283}
1284
1285static void
1286ptp_ocp_watchdog(struct timer_list *t)
1287{
1288	struct ptp_ocp *bp = from_timer(bp, t, watchdog);
1289	unsigned long flags;
1290	u32 status, utc_offset;
1291
1292	status = ioread32(&bp->pps_to_clk->status);
1293
1294	if (status & PPS_STATUS_SUPERV_ERR) {
1295		iowrite32(status, &bp->pps_to_clk->status);
1296		if (!bp->gnss_lost) {
1297			spin_lock_irqsave(&bp->lock, flags);
1298			__ptp_ocp_clear_drift_locked(bp);
1299			spin_unlock_irqrestore(&bp->lock, flags);
1300			bp->gnss_lost = ktime_get_real_seconds();
1301		}
1302
1303	} else if (bp->gnss_lost) {
1304		bp->gnss_lost = 0;
1305	}
1306
1307	/* if GNSS provides correct data we can rely on
1308	 * it to get leap second information
1309	 */
1310	if (bp->tod) {
1311		status = ioread32(&bp->tod->utc_status);
1312		utc_offset = status & TOD_STATUS_UTC_MASK;
1313		if (status & TOD_STATUS_UTC_VALID &&
1314		    utc_offset != bp->utc_tai_offset)
1315			ptp_ocp_utc_distribute(bp, utc_offset);
1316	}
1317
1318	mod_timer(&bp->watchdog, jiffies + HZ);
1319}
1320
1321static void
1322ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1323{
1324	ktime_t start, end;
1325	ktime_t delay;
1326	u32 ctrl;
1327
1328	ctrl = ioread32(&bp->reg->ctrl);
1329	ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1330
1331	iowrite32(ctrl, &bp->reg->ctrl);
1332
1333	start = ktime_get_ns();
1334
1335	ctrl = ioread32(&bp->reg->ctrl);
1336
1337	end = ktime_get_ns();
1338
1339	delay = end - start;
1340	bp->ts_window_adjust = (delay >> 5) * 3;
1341}
1342
1343static int
1344ptp_ocp_init_clock(struct ptp_ocp *bp)
1345{
1346	struct timespec64 ts;
1347	bool sync;
1348	u32 ctrl;
1349
1350	ctrl = OCP_CTRL_ENABLE;
1351	iowrite32(ctrl, &bp->reg->ctrl);
1352
1353	/* NO DRIFT Correction */
1354	/* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */
1355	iowrite32(0x2000, &bp->reg->servo_offset_p);
1356	iowrite32(0x1000, &bp->reg->servo_offset_i);
1357	iowrite32(0,	  &bp->reg->servo_drift_p);
1358	iowrite32(0,	  &bp->reg->servo_drift_i);
1359
1360	/* latch servo values */
1361	ctrl |= OCP_CTRL_ADJUST_SERVO;
1362	iowrite32(ctrl, &bp->reg->ctrl);
1363
1364	if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1365		dev_err(&bp->pdev->dev, "clock not enabled\n");
1366		return -ENODEV;
1367	}
1368
1369	ptp_ocp_estimate_pci_timing(bp);
1370
1371	sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1372	if (!sync) {
1373		ktime_get_clocktai_ts64(&ts);
1374		ptp_ocp_settime(&bp->ptp_info, &ts);
1375	}
1376
1377	/* If there is a clock supervisor, then enable the watchdog */
1378	if (bp->pps_to_clk) {
1379		timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1380		mod_timer(&bp->watchdog, jiffies + HZ);
1381	}
1382
1383	return 0;
1384}
1385
1386static void
1387ptp_ocp_tod_init(struct ptp_ocp *bp)
1388{
1389	u32 ctrl, reg;
1390
1391	ctrl = ioread32(&bp->tod->ctrl);
1392	ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1393	ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1394	iowrite32(ctrl, &bp->tod->ctrl);
1395
1396	reg = ioread32(&bp->tod->utc_status);
1397	if (reg & TOD_STATUS_UTC_VALID)
1398		ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1399}
1400
1401static const char *
1402ptp_ocp_tod_proto_name(const int idx)
1403{
1404	static const char * const proto_name[] = {
1405		"NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1406		"UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1407	};
1408	return proto_name[idx];
1409}
1410
1411static const char *
1412ptp_ocp_tod_gnss_name(int idx)
1413{
1414	static const char * const gnss_name[] = {
1415		"ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1416		"Unknown"
1417	};
1418	if (idx >= ARRAY_SIZE(gnss_name))
1419		idx = ARRAY_SIZE(gnss_name) - 1;
1420	return gnss_name[idx];
1421}
1422
1423struct ptp_ocp_nvmem_match_info {
1424	struct ptp_ocp *bp;
1425	const void * const tag;
1426};
1427
1428static int
1429ptp_ocp_nvmem_match(struct device *dev, const void *data)
1430{
1431	const struct ptp_ocp_nvmem_match_info *info = data;
1432
1433	dev = dev->parent;
1434	if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1435		return 0;
1436
1437	while ((dev = dev->parent))
1438		if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1439			return info->bp == dev_get_drvdata(dev);
1440	return 0;
1441}
1442
1443static inline struct nvmem_device *
1444ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1445{
1446	struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1447
1448	return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1449}
1450
1451static inline void
1452ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1453{
1454	if (!IS_ERR_OR_NULL(*nvmemp))
1455		nvmem_device_put(*nvmemp);
1456	*nvmemp = NULL;
1457}
1458
1459static void
1460ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1461{
1462	const struct ptp_ocp_eeprom_map *map;
1463	struct nvmem_device *nvmem;
1464	const void *tag;
1465	int ret;
1466
1467	if (!bp->i2c_ctrl)
1468		return;
1469
1470	tag = NULL;
1471	nvmem = NULL;
1472
1473	for (map = bp->eeprom_map; map->len; map++) {
1474		if (map->tag != tag) {
1475			tag = map->tag;
1476			ptp_ocp_nvmem_device_put(&nvmem);
1477		}
1478		if (!nvmem) {
1479			nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1480			if (IS_ERR(nvmem)) {
1481				ret = PTR_ERR(nvmem);
1482				goto fail;
1483			}
1484		}
1485		ret = nvmem_device_read(nvmem, map->off, map->len,
1486					BP_MAP_ENTRY_ADDR(bp, map));
1487		if (ret != map->len)
1488			goto fail;
1489	}
1490
1491	bp->has_eeprom_data = true;
1492
1493out:
1494	ptp_ocp_nvmem_device_put(&nvmem);
1495	return;
1496
1497fail:
1498	dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
1499	goto out;
1500}
1501
1502static struct device *
1503ptp_ocp_find_flash(struct ptp_ocp *bp)
1504{
1505	struct device *dev, *last;
1506
1507	last = NULL;
1508	dev = &bp->spi_flash->dev;
1509
1510	while ((dev = device_find_any_child(dev))) {
1511		if (!strcmp("mtd", dev_bus_name(dev)))
1512			break;
1513		put_device(last);
1514		last = dev;
1515	}
1516	put_device(last);
1517
1518	return dev;
1519}
1520
1521static int
1522ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
1523			 const u8 **data, size_t *size)
1524{
1525	struct ptp_ocp *bp = devlink_priv(devlink);
1526	const struct ptp_ocp_firmware_header *hdr;
1527	size_t offset, length;
1528	u16 crc;
1529
1530	hdr = (const struct ptp_ocp_firmware_header *)fw->data;
1531	if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
1532		devlink_flash_update_status_notify(devlink,
1533			"No firmware header found, cancel firmware upgrade",
1534			NULL, 0, 0);
1535		return -EINVAL;
1536	}
1537
1538	if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
1539	    be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
1540		devlink_flash_update_status_notify(devlink,
1541			"Firmware image compatibility check failed",
1542			NULL, 0, 0);
1543		return -EINVAL;
1544	}
1545
1546	offset = sizeof(*hdr);
1547	length = be32_to_cpu(hdr->image_size);
1548	if (length != (fw->size - offset)) {
1549		devlink_flash_update_status_notify(devlink,
1550			"Firmware image size check failed",
1551			NULL, 0, 0);
1552		return -EINVAL;
1553	}
1554
1555	crc = crc16(0xffff, &fw->data[offset], length);
1556	if (be16_to_cpu(hdr->crc) != crc) {
1557		devlink_flash_update_status_notify(devlink,
1558			"Firmware image CRC check failed",
1559			NULL, 0, 0);
1560		return -EINVAL;
1561	}
1562
1563	*data = &fw->data[offset];
1564	*size = length;
1565
1566	return 0;
1567}
1568
1569static int
1570ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1571		      const struct firmware *fw)
1572{
1573	struct mtd_info *mtd = dev_get_drvdata(dev);
1574	struct ptp_ocp *bp = devlink_priv(devlink);
1575	size_t off, len, size, resid, wrote;
1576	struct erase_info erase;
1577	size_t base, blksz;
1578	const u8 *data;
1579	int err;
1580
1581	err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
1582	if (err)
1583		goto out;
1584
1585	off = 0;
1586	base = bp->flash_start;
1587	blksz = 4096;
1588	resid = size;
1589
1590	while (resid) {
1591		devlink_flash_update_status_notify(devlink, "Flashing",
1592						   NULL, off, size);
1593
1594		len = min_t(size_t, resid, blksz);
1595		erase.addr = base + off;
1596		erase.len = blksz;
1597
1598		err = mtd_erase(mtd, &erase);
1599		if (err)
1600			goto out;
1601
1602		err = mtd_write(mtd, base + off, len, &wrote, data + off);
1603		if (err)
1604			goto out;
1605
1606		off += blksz;
1607		resid -= len;
1608	}
1609out:
1610	return err;
1611}
1612
1613static int
1614ptp_ocp_devlink_flash_update(struct devlink *devlink,
1615			     struct devlink_flash_update_params *params,
1616			     struct netlink_ext_ack *extack)
1617{
1618	struct ptp_ocp *bp = devlink_priv(devlink);
1619	struct device *dev;
1620	const char *msg;
1621	int err;
1622
1623	dev = ptp_ocp_find_flash(bp);
1624	if (!dev) {
1625		dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1626		return -ENODEV;
1627	}
1628
1629	devlink_flash_update_status_notify(devlink, "Preparing to flash",
1630					   NULL, 0, 0);
1631
1632	err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1633
1634	msg = err ? "Flash error" : "Flash complete";
1635	devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1636
1637	put_device(dev);
1638	return err;
1639}
1640
1641static int
1642ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1643			 struct netlink_ext_ack *extack)
1644{
1645	struct ptp_ocp *bp = devlink_priv(devlink);
1646	const char *fw_image;
1647	char buf[32];
1648	int err;
1649
1650	fw_image = bp->fw_loader ? "loader" : "fw";
1651	sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
1652	err = devlink_info_version_running_put(req, fw_image, buf);
1653	if (err)
1654		return err;
1655
1656	if (!bp->has_eeprom_data) {
1657		ptp_ocp_read_eeprom(bp);
1658		if (!bp->has_eeprom_data)
1659			return 0;
1660	}
1661
1662	sprintf(buf, "%pM", bp->serial);
1663	err = devlink_info_serial_number_put(req, buf);
1664	if (err)
1665		return err;
1666
1667	err = devlink_info_version_fixed_put(req,
1668			DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
1669			bp->board_id);
1670	if (err)
1671		return err;
1672
1673	return 0;
1674}
1675
1676static const struct devlink_ops ptp_ocp_devlink_ops = {
1677	.flash_update = ptp_ocp_devlink_flash_update,
1678	.info_get = ptp_ocp_devlink_info_get,
1679};
1680
1681static void __iomem *
1682__ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
1683{
1684	struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1685
1686	return devm_ioremap_resource(&bp->pdev->dev, &res);
1687}
1688
1689static void __iomem *
1690ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1691{
1692	resource_size_t start;
1693
1694	start = pci_resource_start(bp->pdev, 0) + r->offset;
1695	return __ptp_ocp_get_mem(bp, start, r->size);
1696}
1697
1698static void
1699ptp_ocp_set_irq_resource(struct resource *res, int irq)
1700{
1701	struct resource r = DEFINE_RES_IRQ(irq);
1702	*res = r;
1703}
1704
1705static void
1706ptp_ocp_set_mem_resource(struct resource *res, resource_size_t start, int size)
1707{
1708	struct resource r = DEFINE_RES_MEM(start, size);
1709	*res = r;
1710}
1711
1712static int
1713ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1714{
1715	struct ptp_ocp_flash_info *info;
1716	struct pci_dev *pdev = bp->pdev;
1717	struct platform_device *p;
1718	struct resource res[2];
1719	resource_size_t start;
1720	int id;
1721
1722	start = pci_resource_start(pdev, 0) + r->offset;
1723	ptp_ocp_set_mem_resource(&res[0], start, r->size);
1724	ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1725
1726	info = r->extra;
1727	id = pci_dev_id(pdev) << 1;
1728	id += info->pci_offset;
1729
1730	p = platform_device_register_resndata(&pdev->dev, info->name, id,
1731					      res, 2, info->data,
1732					      info->data_size);
1733	if (IS_ERR(p))
1734		return PTR_ERR(p);
1735
1736	bp_assign_entry(bp, r, p);
1737
1738	return 0;
1739}
1740
1741static struct platform_device *
1742ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1743{
1744	struct ptp_ocp_i2c_info *info;
1745	struct resource res[2];
1746	resource_size_t start;
1747
1748	info = r->extra;
1749	start = pci_resource_start(pdev, 0) + r->offset;
1750	ptp_ocp_set_mem_resource(&res[0], start, r->size);
1751	ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1752
1753	return platform_device_register_resndata(&pdev->dev, info->name,
1754						 id, res, 2,
1755						 info->data, info->data_size);
1756}
1757
1758static int
1759ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1760{
1761	struct pci_dev *pdev = bp->pdev;
1762	struct ptp_ocp_i2c_info *info;
1763	struct platform_device *p;
1764	struct clk_hw *clk;
1765	char buf[32];
1766	int id;
1767
1768	info = r->extra;
1769	id = pci_dev_id(bp->pdev);
1770
1771	sprintf(buf, "AXI.%d", id);
1772	clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
1773					 info->fixed_rate);
1774	if (IS_ERR(clk))
1775		return PTR_ERR(clk);
1776	bp->i2c_clk = clk;
1777
1778	sprintf(buf, "%s.%d", info->name, id);
1779	devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
1780	p = ptp_ocp_i2c_bus(bp->pdev, r, id);
1781	if (IS_ERR(p))
1782		return PTR_ERR(p);
1783
1784	bp_assign_entry(bp, r, p);
1785
1786	return 0;
1787}
1788
1789/* The expectation is that this is triggered only on error. */
1790static irqreturn_t
1791ptp_ocp_signal_irq(int irq, void *priv)
1792{
1793	struct ptp_ocp_ext_src *ext = priv;
1794	struct signal_reg __iomem *reg = ext->mem;
1795	struct ptp_ocp *bp = ext->bp;
1796	u32 enable, status;
1797	int gen;
1798
1799	gen = ext->info->index - 1;
1800
1801	enable = ioread32(&reg->enable);
1802	status = ioread32(&reg->status);
1803
1804	/* disable generator on error */
1805	if (status || !enable) {
1806		iowrite32(0, &reg->intr_mask);
1807		iowrite32(0, &reg->enable);
1808		bp->signal[gen].running = false;
1809	}
1810
1811	iowrite32(0, &reg->intr);	/* ack interrupt */
1812
1813	return IRQ_HANDLED;
1814}
1815
1816static int
1817ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
1818{
1819	struct ptp_system_timestamp sts;
1820	struct timespec64 ts;
1821	ktime_t start_ns;
1822	int err;
1823
1824	if (!s->period)
1825		return 0;
1826
1827	if (!s->pulse)
1828		s->pulse = ktime_divns(s->period * s->duty, 100);
1829
1830	err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
1831	if (err)
1832		return err;
1833
1834	start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
1835	if (!s->start) {
1836		/* roundup() does not work on 32-bit systems */
1837		s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
1838		s->start = ktime_add(s->start, s->phase);
1839	}
1840
1841	if (s->duty < 1 || s->duty > 99)
1842		return -EINVAL;
1843
1844	if (s->pulse < 1 || s->pulse > s->period)
1845		return -EINVAL;
1846
1847	if (s->start < start_ns)
1848		return -EINVAL;
1849
1850	bp->signal[gen] = *s;
1851
1852	return 0;
1853}
1854
1855static int
1856ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
1857			   struct ptp_perout_request *req)
1858{
1859	struct ptp_ocp_signal s = { };
1860
1861	s.polarity = bp->signal[gen].polarity;
1862	s.period = ktime_set(req->period.sec, req->period.nsec);
1863	if (!s.period)
1864		return 0;
1865
1866	if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
1867		s.pulse = ktime_set(req->on.sec, req->on.nsec);
1868		s.duty = ktime_divns(s.pulse * 100, s.period);
1869	}
1870
1871	if (req->flags & PTP_PEROUT_PHASE)
1872		s.phase = ktime_set(req->phase.sec, req->phase.nsec);
1873	else
1874		s.start = ktime_set(req->start.sec, req->start.nsec);
1875
1876	return ptp_ocp_signal_set(bp, gen, &s);
1877}
1878
1879static int
1880ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
1881{
1882	struct ptp_ocp_ext_src *ext = priv;
1883	struct signal_reg __iomem *reg = ext->mem;
1884	struct ptp_ocp *bp = ext->bp;
1885	struct timespec64 ts;
1886	int gen;
1887
1888	gen = ext->info->index - 1;
1889
1890	iowrite32(0, &reg->intr_mask);
1891	iowrite32(0, &reg->enable);
1892	bp->signal[gen].running = false;
1893	if (!enable)
1894		return 0;
1895
1896	ts = ktime_to_timespec64(bp->signal[gen].start);
1897	iowrite32(ts.tv_sec, &reg->start_sec);
1898	iowrite32(ts.tv_nsec, &reg->start_ns);
1899
1900	ts = ktime_to_timespec64(bp->signal[gen].period);
1901	iowrite32(ts.tv_sec, &reg->period_sec);
1902	iowrite32(ts.tv_nsec, &reg->period_ns);
1903
1904	ts = ktime_to_timespec64(bp->signal[gen].pulse);
1905	iowrite32(ts.tv_sec, &reg->pulse_sec);
1906	iowrite32(ts.tv_nsec, &reg->pulse_ns);
1907
1908	iowrite32(bp->signal[gen].polarity, &reg->polarity);
1909	iowrite32(0, &reg->repeat_count);
1910
1911	iowrite32(0, &reg->intr);		/* clear interrupt state */
1912	iowrite32(1, &reg->intr_mask);		/* enable interrupt */
1913	iowrite32(3, &reg->enable);		/* valid & enable */
1914
1915	bp->signal[gen].running = true;
1916
1917	return 0;
1918}
1919
1920static irqreturn_t
1921ptp_ocp_ts_irq(int irq, void *priv)
1922{
1923	struct ptp_ocp_ext_src *ext = priv;
1924	struct ts_reg __iomem *reg = ext->mem;
1925	struct ptp_clock_event ev;
1926	u32 sec, nsec;
1927
1928	if (ext == ext->bp->pps) {
1929		if (ext->bp->pps_req_map & OCP_REQ_PPS) {
1930			ev.type = PTP_CLOCK_PPS;
1931			ptp_clock_event(ext->bp->ptp, &ev);
1932		}
1933
1934		if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
1935			goto out;
1936	}
1937
1938	/* XXX should fix API - this converts s/ns -> ts -> s/ns */
1939	sec = ioread32(&reg->time_sec);
1940	nsec = ioread32(&reg->time_ns);
1941
1942	ev.type = PTP_CLOCK_EXTTS;
1943	ev.index = ext->info->index;
1944	ev.timestamp = sec * NSEC_PER_SEC + nsec;
1945
1946	ptp_clock_event(ext->bp->ptp, &ev);
1947
1948out:
1949	iowrite32(1, &reg->intr);	/* write 1 to ack */
1950
1951	return IRQ_HANDLED;
1952}
1953
1954static int
1955ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
1956{
1957	struct ptp_ocp_ext_src *ext = priv;
1958	struct ts_reg __iomem *reg = ext->mem;
1959	struct ptp_ocp *bp = ext->bp;
1960
1961	if (ext == bp->pps) {
1962		u32 old_map = bp->pps_req_map;
1963
1964		if (enable)
1965			bp->pps_req_map |= req;
1966		else
1967			bp->pps_req_map &= ~req;
1968
1969		/* if no state change, just return */
1970		if ((!!old_map ^ !!bp->pps_req_map) == 0)
1971			return 0;
1972	}
1973
1974	if (enable) {
1975		iowrite32(1, &reg->enable);
1976		iowrite32(1, &reg->intr_mask);
1977		iowrite32(1, &reg->intr);
1978	} else {
1979		iowrite32(0, &reg->intr_mask);
1980		iowrite32(0, &reg->enable);
1981	}
1982
1983	return 0;
1984}
1985
1986static void
1987ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
1988{
1989	ext->info->enable(ext, ~0, false);
1990	pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
1991	kfree(ext);
1992}
1993
1994static int
1995ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
1996{
1997	struct pci_dev *pdev = bp->pdev;
1998	struct ptp_ocp_ext_src *ext;
1999	int err;
2000
2001	ext = kzalloc(sizeof(*ext), GFP_KERNEL);
2002	if (!ext)
2003		return -ENOMEM;
2004
2005	ext->mem = ptp_ocp_get_mem(bp, r);
2006	if (IS_ERR(ext->mem)) {
2007		err = PTR_ERR(ext->mem);
2008		goto out;
2009	}
2010
2011	ext->bp = bp;
2012	ext->info = r->extra;
2013	ext->irq_vec = r->irq_vec;
2014
2015	err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2016			      ext, "ocp%d.%s", bp->id, r->name);
2017	if (err) {
2018		dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2019		goto out;
2020	}
2021
2022	bp_assign_entry(bp, r, ext);
2023
2024	return 0;
2025
2026out:
2027	kfree(ext);
2028	return err;
2029}
2030
2031static int
2032ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2033{
2034	struct pci_dev *pdev = bp->pdev;
2035	struct uart_8250_port uart;
2036
2037	/* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2038	 * the serial port device claim and release the pci resource.
2039	 */
2040	memset(&uart, 0, sizeof(uart));
2041	uart.port.dev = &pdev->dev;
2042	uart.port.iotype = UPIO_MEM;
2043	uart.port.regshift = 2;
2044	uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2045	uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2046	uart.port.uartclk = 50000000;
2047	uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2048	uart.port.type = PORT_16550A;
2049
2050	return serial8250_register_8250_port(&uart);
2051}
2052
2053static int
2054ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2055{
2056	struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2057	struct ptp_ocp_serial_port port = {};
2058
2059	port.line = ptp_ocp_serial_line(bp, r);
2060	if (port.line < 0)
2061		return port.line;
2062
2063	if (p)
2064		port.baud = p->baud;
2065
2066	bp_assign_entry(bp, r, port);
2067
2068	return 0;
2069}
2070
2071static int
2072ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2073{
2074	void __iomem *mem;
2075
2076	mem = ptp_ocp_get_mem(bp, r);
2077	if (IS_ERR(mem))
2078		return PTR_ERR(mem);
2079
2080	bp_assign_entry(bp, r, mem);
2081
2082	return 0;
2083}
2084
2085static void
2086ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2087{
2088	if (!bp->nmea_out)
2089		return;
2090
2091	iowrite32(0, &bp->nmea_out->ctrl);		/* disable */
2092	iowrite32(7, &bp->nmea_out->uart_baud);		/* 115200 */
2093	iowrite32(1, &bp->nmea_out->ctrl);		/* enable */
2094}
2095
2096static void
2097_ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2098{
2099	u32 val;
2100
2101	iowrite32(0, &reg->enable);		/* disable */
2102
2103	val = ioread32(&reg->polarity);
2104	s->polarity = val ? true : false;
2105	s->duty = 50;
2106}
2107
2108static void
2109ptp_ocp_signal_init(struct ptp_ocp *bp)
2110{
2111	int i;
2112
2113	for (i = 0; i < 4; i++)
2114		if (bp->signal_out[i])
2115			_ptp_ocp_signal_init(&bp->signal[i],
2116					     bp->signal_out[i]->mem);
2117}
2118
2119static void
2120ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2121{
2122	sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2123	kfree(bp->attr_group);
2124}
2125
2126static int
2127ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2128		       const struct ocp_attr_group *attr_tbl)
2129{
2130	int count, i;
2131	int err;
2132
2133	count = 0;
2134	for (i = 0; attr_tbl[i].cap; i++)
2135		if (attr_tbl[i].cap & bp->fw_cap)
2136			count++;
2137
2138	bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *),
2139				 GFP_KERNEL);
2140	if (!bp->attr_group)
2141		return -ENOMEM;
2142
2143	count = 0;
2144	for (i = 0; attr_tbl[i].cap; i++)
2145		if (attr_tbl[i].cap & bp->fw_cap)
2146			bp->attr_group[count++] = attr_tbl[i].group;
2147
2148	err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2149	if (err)
2150		bp->attr_group[0] = NULL;
2151
2152	return err;
2153}
2154
2155static void
2156ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2157{
2158	u32 ctrl;
2159	bool on;
2160
2161	ctrl = ioread32(reg);
2162	on = ctrl & bit;
2163	if (on ^ enable) {
2164		ctrl &= ~bit;
2165		ctrl |= enable ? bit : 0;
2166		iowrite32(ctrl, reg);
2167	}
2168}
2169
2170static void
2171ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2172{
2173	return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2174				   IRIG_M_CTRL_ENABLE, enable);
2175}
2176
2177static void
2178ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2179{
2180	return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2181				   IRIG_S_CTRL_ENABLE, enable);
2182}
2183
2184static void
2185ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2186{
2187	return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2188				   DCF_M_CTRL_ENABLE, enable);
2189}
2190
2191static void
2192ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2193{
2194	return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2195				   DCF_S_CTRL_ENABLE, enable);
2196}
2197
2198static void
2199__handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2200{
2201	ptp_ocp_irig_out(bp, val & 0x00100010);
2202	ptp_ocp_dcf_out(bp, val & 0x00200020);
2203}
2204
2205static void
2206__handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2207{
2208	ptp_ocp_irig_in(bp, val & 0x00100010);
2209	ptp_ocp_dcf_in(bp, val & 0x00200020);
2210}
2211
2212static u32
2213ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2214{
2215	u32 __iomem *gpio;
2216	u32 shift;
2217
2218	if (bp->sma[sma_nr - 1].fixed_fcn)
2219		return (sma_nr - 1) & 1;
2220
2221	if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2222		gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2223	else
2224		gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2225	shift = sma_nr & 1 ? 0 : 16;
2226
2227	return (ioread32(gpio) >> shift) & 0xffff;
2228}
2229
2230static int
2231ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2232{
2233	u32 reg, mask, shift;
2234	unsigned long flags;
2235	u32 __iomem *gpio;
2236
2237	gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2238	shift = sma_nr & 1 ? 0 : 16;
2239
2240	mask = 0xffff << (16 - shift);
2241
2242	spin_lock_irqsave(&bp->lock, flags);
2243
2244	reg = ioread32(gpio);
2245	reg = (reg & mask) | (val << shift);
2246
2247	__handle_signal_outputs(bp, reg);
2248
2249	iowrite32(reg, gpio);
2250
2251	spin_unlock_irqrestore(&bp->lock, flags);
2252
2253	return 0;
2254}
2255
2256static int
2257ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2258{
2259	u32 reg, mask, shift;
2260	unsigned long flags;
2261	u32 __iomem *gpio;
2262
2263	gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2264	shift = sma_nr & 1 ? 0 : 16;
2265
2266	mask = 0xffff << (16 - shift);
2267
2268	spin_lock_irqsave(&bp->lock, flags);
2269
2270	reg = ioread32(gpio);
2271	reg = (reg & mask) | (val << shift);
2272
2273	__handle_signal_inputs(bp, reg);
2274
2275	iowrite32(reg, gpio);
2276
2277	spin_unlock_irqrestore(&bp->lock, flags);
2278
2279	return 0;
2280}
2281
2282static void
2283ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2284{
2285	u32 reg;
2286	int i;
2287
2288	/* defaults */
2289	bp->sma[0].mode = SMA_MODE_IN;
2290	bp->sma[1].mode = SMA_MODE_IN;
2291	bp->sma[2].mode = SMA_MODE_OUT;
2292	bp->sma[3].mode = SMA_MODE_OUT;
2293	for (i = 0; i < 4; i++)
2294		bp->sma[i].default_fcn = i & 1;
2295
2296	/* If no SMA1 map, the pin functions and directions are fixed. */
2297	if (!bp->sma_map1) {
2298		for (i = 0; i < 4; i++) {
2299			bp->sma[i].fixed_fcn = true;
2300			bp->sma[i].fixed_dir = true;
2301		}
2302		return;
2303	}
2304
2305	/* If SMA2 GPIO output map is all 1, it is not present.
2306	 * This indicates the firmware has fixed direction SMA pins.
2307	 */
2308	reg = ioread32(&bp->sma_map2->gpio2);
2309	if (reg == 0xffffffff) {
2310		for (i = 0; i < 4; i++)
2311			bp->sma[i].fixed_dir = true;
2312	} else {
2313		reg = ioread32(&bp->sma_map1->gpio1);
2314		bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2315		bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2316
2317		reg = ioread32(&bp->sma_map1->gpio2);
2318		bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2319		bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2320	}
2321}
2322
2323static const struct ocp_sma_op ocp_fb_sma_op = {
2324	.tbl		= { ptp_ocp_sma_in, ptp_ocp_sma_out },
2325	.init		= ptp_ocp_sma_fb_init,
2326	.get		= ptp_ocp_sma_fb_get,
2327	.set_inputs	= ptp_ocp_sma_fb_set_inputs,
2328	.set_output	= ptp_ocp_sma_fb_set_output,
2329};
2330
2331static int
2332ptp_ocp_fb_set_pins(struct ptp_ocp *bp)
2333{
2334	struct ptp_pin_desc *config;
2335	int i;
2336
2337	config = kcalloc(4, sizeof(*config), GFP_KERNEL);
2338	if (!config)
2339		return -ENOMEM;
2340
2341	for (i = 0; i < 4; i++) {
2342		sprintf(config[i].name, "sma%d", i + 1);
2343		config[i].index = i;
2344	}
2345
2346	bp->ptp_info.n_pins = 4;
2347	bp->ptp_info.pin_config = config;
2348
2349	return 0;
2350}
2351
2352static void
2353ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2354{
2355	u64 cap = OCP_CAP_BASIC;
2356	u32 version;
2357
2358	version = ioread32(&bp->image->version);
2359
2360	/* if lower 16 bits are empty, this is the fw loader. */
2361	if ((version & 0xffff) == 0) {
2362		version = version >> 16;
2363		bp->fw_loader = true;
2364	}
2365
2366	bp->fw_tag = version >> 15;
2367	bp->fw_version = version & 0x7fff;
2368
2369	if (bp->fw_tag) {
2370		/* FPGA firmware */
2371		if (version >= 5)
2372			cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2373	} else {
2374		/* SOM firmware */
2375		if (version >= 19)
2376			cap |= OCP_CAP_SIGNAL;
2377		if (version >= 20)
2378			cap |= OCP_CAP_FREQ;
2379	}
2380
2381	bp->fw_cap = cap;
2382}
2383
2384/* FB specific board initializers; last "resource" registered. */
2385static int
2386ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2387{
2388	int err;
2389
2390	bp->flash_start = 1024 * 4096;
2391	bp->eeprom_map = fb_eeprom_map;
2392	bp->fw_version = ioread32(&bp->image->version);
2393	bp->sma_op = &ocp_fb_sma_op;
2394
2395	ptp_ocp_fb_set_version(bp);
2396
2397	ptp_ocp_tod_init(bp);
2398	ptp_ocp_nmea_out_init(bp);
2399	ptp_ocp_sma_init(bp);
2400	ptp_ocp_signal_init(bp);
2401
2402	err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2403	if (err)
2404		return err;
2405
2406	err = ptp_ocp_fb_set_pins(bp);
2407	if (err)
2408		return err;
2409
2410	return ptp_ocp_init_clock(bp);
2411}
2412
2413static bool
2414ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
2415{
2416	bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
2417
2418	if (!allow)
2419		dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
2420			r->irq_vec, r->name);
2421	return allow;
2422}
2423
2424static int
2425ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
2426{
2427	struct ocp_resource *r, *table;
2428	int err = 0;
2429
2430	table = (struct ocp_resource *)driver_data;
2431	for (r = table; r->setup; r++) {
2432		if (!ptp_ocp_allow_irq(bp, r))
2433			continue;
2434		err = r->setup(bp, r);
2435		if (err) {
2436			dev_err(&bp->pdev->dev,
2437				"Could not register %s: err %d\n",
2438				r->name, err);
2439			break;
2440		}
2441	}
2442	return err;
2443}
2444
2445static void
2446ptp_ocp_art_sma_init(struct ptp_ocp *bp)
2447{
2448	u32 reg;
2449	int i;
2450
2451	/* defaults */
2452	bp->sma[0].mode = SMA_MODE_IN;
2453	bp->sma[1].mode = SMA_MODE_IN;
2454	bp->sma[2].mode = SMA_MODE_OUT;
2455	bp->sma[3].mode = SMA_MODE_OUT;
2456
2457	bp->sma[0].default_fcn = 0x08;	/* IN: 10Mhz */
2458	bp->sma[1].default_fcn = 0x01;	/* IN: PPS1 */
2459	bp->sma[2].default_fcn = 0x10;	/* OUT: 10Mhz */
2460	bp->sma[3].default_fcn = 0x02;	/* OUT: PHC */
2461
2462	/* If no SMA map, the pin functions and directions are fixed. */
2463	if (!bp->art_sma) {
2464		for (i = 0; i < 4; i++) {
2465			bp->sma[i].fixed_fcn = true;
2466			bp->sma[i].fixed_dir = true;
2467		}
2468		return;
2469	}
2470
2471	for (i = 0; i < 4; i++) {
2472		reg = ioread32(&bp->art_sma->map[i].gpio);
2473
2474		switch (reg & 0xff) {
2475		case 0:
2476			bp->sma[i].fixed_fcn = true;
2477			bp->sma[i].fixed_dir = true;
2478			break;
2479		case 1:
2480		case 8:
2481			bp->sma[i].mode = SMA_MODE_IN;
2482			break;
2483		default:
2484			bp->sma[i].mode = SMA_MODE_OUT;
2485			break;
2486		}
2487	}
2488}
2489
2490static u32
2491ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
2492{
2493	if (bp->sma[sma_nr - 1].fixed_fcn)
2494		return bp->sma[sma_nr - 1].default_fcn;
2495
2496	return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
2497}
2498
2499/* note: store 0 is considered invalid. */
2500static int
2501ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
2502{
2503	unsigned long flags;
2504	u32 __iomem *gpio;
2505	int err = 0;
2506	u32 reg;
2507
2508	val &= SMA_SELECT_MASK;
2509	if (hweight32(val) > 1)
2510		return -EINVAL;
2511
2512	gpio = &bp->art_sma->map[sma_nr - 1].gpio;
2513
2514	spin_lock_irqsave(&bp->lock, flags);
2515	reg = ioread32(gpio);
2516	if (((reg >> 16) & val) == 0) {
2517		err = -EOPNOTSUPP;
2518	} else {
2519		reg = (reg & 0xff00) | (val & 0xff);
2520		iowrite32(reg, gpio);
2521	}
2522	spin_unlock_irqrestore(&bp->lock, flags);
2523
2524	return err;
2525}
2526
2527static const struct ocp_sma_op ocp_art_sma_op = {
2528	.tbl		= { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
2529	.init		= ptp_ocp_art_sma_init,
2530	.get		= ptp_ocp_art_sma_get,
2531	.set_inputs	= ptp_ocp_art_sma_set,
2532	.set_output	= ptp_ocp_art_sma_set,
2533};
2534
2535/* ART specific board initializers; last "resource" registered. */
2536static int
2537ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2538{
2539	int err;
2540
2541	bp->flash_start = 0x1000000;
2542	bp->eeprom_map = art_eeprom_map;
2543	bp->fw_cap = OCP_CAP_BASIC;
2544	bp->fw_version = ioread32(&bp->reg->version);
2545	bp->fw_tag = 2;
2546	bp->sma_op = &ocp_art_sma_op;
2547
2548	/* Enable MAC serial port during initialisation */
2549	iowrite32(1, &bp->board_config->mro50_serial_activate);
2550
2551	ptp_ocp_sma_init(bp);
2552
2553	err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
2554	if (err)
2555		return err;
2556
2557	return ptp_ocp_init_clock(bp);
2558}
2559
2560static ssize_t
2561ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
2562		    int def_val)
2563{
2564	const char *name;
2565	ssize_t count;
2566
2567	count = sysfs_emit(buf, "OUT: ");
2568	name = ptp_ocp_select_name_from_val(tbl, val);
2569	if (!name)
2570		name = ptp_ocp_select_name_from_val(tbl, def_val);
2571	count += sysfs_emit_at(buf, count, "%s\n", name);
2572	return count;
2573}
2574
2575static ssize_t
2576ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
2577		    int def_val)
2578{
2579	const char *name;
2580	ssize_t count;
2581	int i;
2582
2583	count = sysfs_emit(buf, "IN: ");
2584	for (i = 0; tbl[i].name; i++) {
2585		if (val & tbl[i].value) {
2586			name = tbl[i].name;
2587			count += sysfs_emit_at(buf, count, "%s ", name);
2588		}
2589	}
2590	if (!val && def_val >= 0) {
2591		name = ptp_ocp_select_name_from_val(tbl, def_val);
2592		count += sysfs_emit_at(buf, count, "%s ", name);
2593	}
2594	if (count)
2595		count--;
2596	count += sysfs_emit_at(buf, count, "\n");
2597	return count;
2598}
2599
2600static int
2601sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
2602		 enum ptp_ocp_sma_mode *mode)
2603{
2604	int idx, count, dir;
2605	char **argv;
2606	int ret;
2607
2608	argv = argv_split(GFP_KERNEL, buf, &count);
2609	if (!argv)
2610		return -ENOMEM;
2611
2612	ret = -EINVAL;
2613	if (!count)
2614		goto out;
2615
2616	idx = 0;
2617	dir = *mode == SMA_MODE_IN ? 0 : 1;
2618	if (!strcasecmp("IN:", argv[0])) {
2619		dir = 0;
2620		idx++;
2621	}
2622	if (!strcasecmp("OUT:", argv[0])) {
2623		dir = 1;
2624		idx++;
2625	}
2626	*mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
2627
2628	ret = 0;
2629	for (; idx < count; idx++)
2630		ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
2631	if (ret < 0)
2632		ret = -EINVAL;
2633
2634out:
2635	argv_free(argv);
2636	return ret;
2637}
2638
2639static ssize_t
2640ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
2641		 int default_in_val, int default_out_val)
2642{
2643	struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2644	const struct ocp_selector * const *tbl;
2645	u32 val;
2646
2647	tbl = bp->sma_op->tbl;
2648	val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
2649
2650	if (sma->mode == SMA_MODE_IN) {
2651		if (sma->disabled)
2652			val = SMA_DISABLE;
2653		return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
2654	}
2655
2656	return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
2657}
2658
2659static ssize_t
2660sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
2661{
2662	struct ptp_ocp *bp = dev_get_drvdata(dev);
2663
2664	return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
2665}
2666
2667static ssize_t
2668sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
2669{
2670	struct ptp_ocp *bp = dev_get_drvdata(dev);
2671
2672	return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
2673}
2674
2675static ssize_t
2676sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
2677{
2678	struct ptp_ocp *bp = dev_get_drvdata(dev);
2679
2680	return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
2681}
2682
2683static ssize_t
2684sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
2685{
2686	struct ptp_ocp *bp = dev_get_drvdata(dev);
2687
2688	return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
2689}
2690
2691static int
2692ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
2693{
2694	struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2695	enum ptp_ocp_sma_mode mode;
2696	int val;
2697
2698	mode = sma->mode;
2699	val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
2700	if (val < 0)
2701		return val;
2702
2703	if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
2704		return -EOPNOTSUPP;
2705
2706	if (sma->fixed_fcn) {
2707		if (val != sma->default_fcn)
2708			return -EOPNOTSUPP;
2709		return 0;
2710	}
2711
2712	sma->disabled = !!(val & SMA_DISABLE);
2713
2714	if (mode != sma->mode) {
2715		if (mode == SMA_MODE_IN)
2716			ptp_ocp_sma_set_output(bp, sma_nr, 0);
2717		else
2718			ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
2719		sma->mode = mode;
2720	}
2721
2722	if (!sma->fixed_dir)
2723		val |= SMA_ENABLE;		/* add enable bit */
2724
2725	if (sma->disabled)
2726		val = 0;
2727
2728	if (mode == SMA_MODE_IN)
2729		val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
2730	else
2731		val = ptp_ocp_sma_set_output(bp, sma_nr, val);
2732
2733	return val;
2734}
2735
2736static ssize_t
2737sma1_store(struct device *dev, struct device_attribute *attr,
2738	   const char *buf, size_t count)
2739{
2740	struct ptp_ocp *bp = dev_get_drvdata(dev);
2741	int err;
2742
2743	err = ptp_ocp_sma_store(bp, buf, 1);
2744	return err ? err : count;
2745}
2746
2747static ssize_t
2748sma2_store(struct device *dev, struct device_attribute *attr,
2749	   const char *buf, size_t count)
2750{
2751	struct ptp_ocp *bp = dev_get_drvdata(dev);
2752	int err;
2753
2754	err = ptp_ocp_sma_store(bp, buf, 2);
2755	return err ? err : count;
2756}
2757
2758static ssize_t
2759sma3_store(struct device *dev, struct device_attribute *attr,
2760	   const char *buf, size_t count)
2761{
2762	struct ptp_ocp *bp = dev_get_drvdata(dev);
2763	int err;
2764
2765	err = ptp_ocp_sma_store(bp, buf, 3);
2766	return err ? err : count;
2767}
2768
2769static ssize_t
2770sma4_store(struct device *dev, struct device_attribute *attr,
2771	   const char *buf, size_t count)
2772{
2773	struct ptp_ocp *bp = dev_get_drvdata(dev);
2774	int err;
2775
2776	err = ptp_ocp_sma_store(bp, buf, 4);
2777	return err ? err : count;
2778}
2779static DEVICE_ATTR_RW(sma1);
2780static DEVICE_ATTR_RW(sma2);
2781static DEVICE_ATTR_RW(sma3);
2782static DEVICE_ATTR_RW(sma4);
2783
2784static ssize_t
2785available_sma_inputs_show(struct device *dev,
2786			  struct device_attribute *attr, char *buf)
2787{
2788	struct ptp_ocp *bp = dev_get_drvdata(dev);
2789
2790	return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
2791}
2792static DEVICE_ATTR_RO(available_sma_inputs);
2793
2794static ssize_t
2795available_sma_outputs_show(struct device *dev,
2796			   struct device_attribute *attr, char *buf)
2797{
2798	struct ptp_ocp *bp = dev_get_drvdata(dev);
2799
2800	return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
2801}
2802static DEVICE_ATTR_RO(available_sma_outputs);
2803
2804#define EXT_ATTR_RO(_group, _name, _val)				\
2805	struct dev_ext_attribute dev_attr_##_group##_val##_##_name =	\
2806		{ __ATTR_RO(_name), (void *)_val }
2807#define EXT_ATTR_RW(_group, _name, _val)				\
2808	struct dev_ext_attribute dev_attr_##_group##_val##_##_name =	\
2809		{ __ATTR_RW(_name), (void *)_val }
2810#define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
2811
2812/* period [duty [phase [polarity]]] */
2813static ssize_t
2814signal_store(struct device *dev, struct device_attribute *attr,
2815	     const char *buf, size_t count)
2816{
2817	struct dev_ext_attribute *ea = to_ext_attr(attr);
2818	struct ptp_ocp *bp = dev_get_drvdata(dev);
2819	struct ptp_ocp_signal s = { };
2820	int gen = (uintptr_t)ea->var;
2821	int argc, err;
2822	char **argv;
2823
2824	argv = argv_split(GFP_KERNEL, buf, &argc);
2825	if (!argv)
2826		return -ENOMEM;
2827
2828	err = -EINVAL;
2829	s.duty = bp->signal[gen].duty;
2830	s.phase = bp->signal[gen].phase;
2831	s.period = bp->signal[gen].period;
2832	s.polarity = bp->signal[gen].polarity;
2833
2834	switch (argc) {
2835	case 4:
2836		argc--;
2837		err = kstrtobool(argv[argc], &s.polarity);
2838		if (err)
2839			goto out;
2840		fallthrough;
2841	case 3:
2842		argc--;
2843		err = kstrtou64(argv[argc], 0, &s.phase);
2844		if (err)
2845			goto out;
2846		fallthrough;
2847	case 2:
2848		argc--;
2849		err = kstrtoint(argv[argc], 0, &s.duty);
2850		if (err)
2851			goto out;
2852		fallthrough;
2853	case 1:
2854		argc--;
2855		err = kstrtou64(argv[argc], 0, &s.period);
2856		if (err)
2857			goto out;
2858		break;
2859	default:
2860		goto out;
2861	}
2862
2863	err = ptp_ocp_signal_set(bp, gen, &s);
2864	if (err)
2865		goto out;
2866
2867	err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
2868
2869out:
2870	argv_free(argv);
2871	return err ? err : count;
2872}
2873
2874static ssize_t
2875signal_show(struct device *dev, struct device_attribute *attr, char *buf)
2876{
2877	struct dev_ext_attribute *ea = to_ext_attr(attr);
2878	struct ptp_ocp *bp = dev_get_drvdata(dev);
2879	struct ptp_ocp_signal *signal;
2880	struct timespec64 ts;
2881	ssize_t count;
2882	int i;
2883
2884	i = (uintptr_t)ea->var;
2885	signal = &bp->signal[i];
2886
2887	count = sysfs_emit(buf, "%llu %d %llu %d", signal->period,
2888			   signal->duty, signal->phase, signal->polarity);
2889
2890	ts = ktime_to_timespec64(signal->start);
2891	count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts);
2892
2893	return count;
2894}
2895static EXT_ATTR_RW(signal, signal, 0);
2896static EXT_ATTR_RW(signal, signal, 1);
2897static EXT_ATTR_RW(signal, signal, 2);
2898static EXT_ATTR_RW(signal, signal, 3);
2899
2900static ssize_t
2901duty_show(struct device *dev, struct device_attribute *attr, char *buf)
2902{
2903	struct dev_ext_attribute *ea = to_ext_attr(attr);
2904	struct ptp_ocp *bp = dev_get_drvdata(dev);
2905	int i = (uintptr_t)ea->var;
2906
2907	return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
2908}
2909static EXT_ATTR_RO(signal, duty, 0);
2910static EXT_ATTR_RO(signal, duty, 1);
2911static EXT_ATTR_RO(signal, duty, 2);
2912static EXT_ATTR_RO(signal, duty, 3);
2913
2914static ssize_t
2915period_show(struct device *dev, struct device_attribute *attr, char *buf)
2916{
2917	struct dev_ext_attribute *ea = to_ext_attr(attr);
2918	struct ptp_ocp *bp = dev_get_drvdata(dev);
2919	int i = (uintptr_t)ea->var;
2920
2921	return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
2922}
2923static EXT_ATTR_RO(signal, period, 0);
2924static EXT_ATTR_RO(signal, period, 1);
2925static EXT_ATTR_RO(signal, period, 2);
2926static EXT_ATTR_RO(signal, period, 3);
2927
2928static ssize_t
2929phase_show(struct device *dev, struct device_attribute *attr, char *buf)
2930{
2931	struct dev_ext_attribute *ea = to_ext_attr(attr);
2932	struct ptp_ocp *bp = dev_get_drvdata(dev);
2933	int i = (uintptr_t)ea->var;
2934
2935	return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
2936}
2937static EXT_ATTR_RO(signal, phase, 0);
2938static EXT_ATTR_RO(signal, phase, 1);
2939static EXT_ATTR_RO(signal, phase, 2);
2940static EXT_ATTR_RO(signal, phase, 3);
2941
2942static ssize_t
2943polarity_show(struct device *dev, struct device_attribute *attr,
2944	      char *buf)
2945{
2946	struct dev_ext_attribute *ea = to_ext_attr(attr);
2947	struct ptp_ocp *bp = dev_get_drvdata(dev);
2948	int i = (uintptr_t)ea->var;
2949
2950	return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
2951}
2952static EXT_ATTR_RO(signal, polarity, 0);
2953static EXT_ATTR_RO(signal, polarity, 1);
2954static EXT_ATTR_RO(signal, polarity, 2);
2955static EXT_ATTR_RO(signal, polarity, 3);
2956
2957static ssize_t
2958running_show(struct device *dev, struct device_attribute *attr, char *buf)
2959{
2960	struct dev_ext_attribute *ea = to_ext_attr(attr);
2961	struct ptp_ocp *bp = dev_get_drvdata(dev);
2962	int i = (uintptr_t)ea->var;
2963
2964	return sysfs_emit(buf, "%d\n", bp->signal[i].running);
2965}
2966static EXT_ATTR_RO(signal, running, 0);
2967static EXT_ATTR_RO(signal, running, 1);
2968static EXT_ATTR_RO(signal, running, 2);
2969static EXT_ATTR_RO(signal, running, 3);
2970
2971static ssize_t
2972start_show(struct device *dev, struct device_attribute *attr, char *buf)
2973{
2974	struct dev_ext_attribute *ea = to_ext_attr(attr);
2975	struct ptp_ocp *bp = dev_get_drvdata(dev);
2976	int i = (uintptr_t)ea->var;
2977	struct timespec64 ts;
2978
2979	ts = ktime_to_timespec64(bp->signal[i].start);
2980	return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
2981}
2982static EXT_ATTR_RO(signal, start, 0);
2983static EXT_ATTR_RO(signal, start, 1);
2984static EXT_ATTR_RO(signal, start, 2);
2985static EXT_ATTR_RO(signal, start, 3);
2986
2987static ssize_t
2988seconds_store(struct device *dev, struct device_attribute *attr,
2989	      const char *buf, size_t count)
2990{
2991	struct dev_ext_attribute *ea = to_ext_attr(attr);
2992	struct ptp_ocp *bp = dev_get_drvdata(dev);
2993	int idx = (uintptr_t)ea->var;
2994	u32 val;
2995	int err;
2996
2997	err = kstrtou32(buf, 0, &val);
2998	if (err)
2999		return err;
3000	if (val > 0xff)
3001		return -EINVAL;
3002
3003	if (val)
3004		val = (val << 8) | 0x1;
3005
3006	iowrite32(val, &bp->freq_in[idx]->ctrl);
3007
3008	return count;
3009}
3010
3011static ssize_t
3012seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3013{
3014	struct dev_ext_attribute *ea = to_ext_attr(attr);
3015	struct ptp_ocp *bp = dev_get_drvdata(dev);
3016	int idx = (uintptr_t)ea->var;
3017	u32 val;
3018
3019	val = ioread32(&bp->freq_in[idx]->ctrl);
3020	if (val & 1)
3021		val = (val >> 8) & 0xff;
3022	else
3023		val = 0;
3024
3025	return sysfs_emit(buf, "%u\n", val);
3026}
3027static EXT_ATTR_RW(freq, seconds, 0);
3028static EXT_ATTR_RW(freq, seconds, 1);
3029static EXT_ATTR_RW(freq, seconds, 2);
3030static EXT_ATTR_RW(freq, seconds, 3);
3031
3032static ssize_t
3033frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3034{
3035	struct dev_ext_attribute *ea = to_ext_attr(attr);
3036	struct ptp_ocp *bp = dev_get_drvdata(dev);
3037	int idx = (uintptr_t)ea->var;
3038	u32 val;
3039
3040	val = ioread32(&bp->freq_in[idx]->status);
3041	if (val & FREQ_STATUS_ERROR)
3042		return sysfs_emit(buf, "error\n");
3043	if (val & FREQ_STATUS_OVERRUN)
3044		return sysfs_emit(buf, "overrun\n");
3045	if (val & FREQ_STATUS_VALID)
3046		return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3047	return 0;
3048}
3049static EXT_ATTR_RO(freq, frequency, 0);
3050static EXT_ATTR_RO(freq, frequency, 1);
3051static EXT_ATTR_RO(freq, frequency, 2);
3052static EXT_ATTR_RO(freq, frequency, 3);
3053
3054static ssize_t
3055serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3056{
3057	struct ptp_ocp *bp = dev_get_drvdata(dev);
3058
3059	if (!bp->has_eeprom_data)
3060		ptp_ocp_read_eeprom(bp);
3061
3062	return sysfs_emit(buf, "%pM\n", bp->serial);
3063}
3064static DEVICE_ATTR_RO(serialnum);
3065
3066static ssize_t
3067gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3068{
3069	struct ptp_ocp *bp = dev_get_drvdata(dev);
3070	ssize_t ret;
3071
3072	if (bp->gnss_lost)
3073		ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3074	else
3075		ret = sysfs_emit(buf, "SYNC\n");
3076
3077	return ret;
3078}
3079static DEVICE_ATTR_RO(gnss_sync);
3080
3081static ssize_t
3082utc_tai_offset_show(struct device *dev,
3083		    struct device_attribute *attr, char *buf)
3084{
3085	struct ptp_ocp *bp = dev_get_drvdata(dev);
3086
3087	return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3088}
3089
3090static ssize_t
3091utc_tai_offset_store(struct device *dev,
3092		     struct device_attribute *attr,
3093		     const char *buf, size_t count)
3094{
3095	struct ptp_ocp *bp = dev_get_drvdata(dev);
3096	int err;
3097	u32 val;
3098
3099	err = kstrtou32(buf, 0, &val);
3100	if (err)
3101		return err;
3102
3103	ptp_ocp_utc_distribute(bp, val);
3104
3105	return count;
3106}
3107static DEVICE_ATTR_RW(utc_tai_offset);
3108
3109static ssize_t
3110ts_window_adjust_show(struct device *dev,
3111		      struct device_attribute *attr, char *buf)
3112{
3113	struct ptp_ocp *bp = dev_get_drvdata(dev);
3114
3115	return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3116}
3117
3118static ssize_t
3119ts_window_adjust_store(struct device *dev,
3120		       struct device_attribute *attr,
3121		       const char *buf, size_t count)
3122{
3123	struct ptp_ocp *bp = dev_get_drvdata(dev);
3124	int err;
3125	u32 val;
3126
3127	err = kstrtou32(buf, 0, &val);
3128	if (err)
3129		return err;
3130
3131	bp->ts_window_adjust = val;
3132
3133	return count;
3134}
3135static DEVICE_ATTR_RW(ts_window_adjust);
3136
3137static ssize_t
3138irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3139{
3140	struct ptp_ocp *bp = dev_get_drvdata(dev);
3141	u32 val;
3142
3143	val = ioread32(&bp->irig_out->ctrl);
3144	val = (val >> 16) & 0x07;
3145	return sysfs_emit(buf, "%d\n", val);
3146}
3147
3148static ssize_t
3149irig_b_mode_store(struct device *dev,
3150		  struct device_attribute *attr,
3151		  const char *buf, size_t count)
3152{
3153	struct ptp_ocp *bp = dev_get_drvdata(dev);
3154	unsigned long flags;
3155	int err;
3156	u32 reg;
3157	u8 val;
3158
3159	err = kstrtou8(buf, 0, &val);
3160	if (err)
3161		return err;
3162	if (val > 7)
3163		return -EINVAL;
3164
3165	reg = ((val & 0x7) << 16);
3166
3167	spin_lock_irqsave(&bp->lock, flags);
3168	iowrite32(0, &bp->irig_out->ctrl);		/* disable */
3169	iowrite32(reg, &bp->irig_out->ctrl);		/* change mode */
3170	iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3171	spin_unlock_irqrestore(&bp->lock, flags);
3172
3173	return count;
3174}
3175static DEVICE_ATTR_RW(irig_b_mode);
3176
3177static ssize_t
3178clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3179{
3180	struct ptp_ocp *bp = dev_get_drvdata(dev);
3181	const char *p;
3182	u32 select;
3183
3184	select = ioread32(&bp->reg->select);
3185	p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3186
3187	return sysfs_emit(buf, "%s\n", p);
3188}
3189
3190static ssize_t
3191clock_source_store(struct device *dev, struct device_attribute *attr,
3192		   const char *buf, size_t count)
3193{
3194	struct ptp_ocp *bp = dev_get_drvdata(dev);
3195	unsigned long flags;
3196	int val;
3197
3198	val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3199	if (val < 0)
3200		return val;
3201
3202	spin_lock_irqsave(&bp->lock, flags);
3203	iowrite32(val, &bp->reg->select);
3204	spin_unlock_irqrestore(&bp->lock, flags);
3205
3206	return count;
3207}
3208static DEVICE_ATTR_RW(clock_source);
3209
3210static ssize_t
3211available_clock_sources_show(struct device *dev,
3212			     struct device_attribute *attr, char *buf)
3213{
3214	return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
3215}
3216static DEVICE_ATTR_RO(available_clock_sources);
3217
3218static ssize_t
3219clock_status_drift_show(struct device *dev,
3220			struct device_attribute *attr, char *buf)
3221{
3222	struct ptp_ocp *bp = dev_get_drvdata(dev);
3223	u32 val;
3224	int res;
3225
3226	val = ioread32(&bp->reg->status_drift);
3227	res = (val & ~INT_MAX) ? -1 : 1;
3228	res *= (val & INT_MAX);
3229	return sysfs_emit(buf, "%d\n", res);
3230}
3231static DEVICE_ATTR_RO(clock_status_drift);
3232
3233static ssize_t
3234clock_status_offset_show(struct device *dev,
3235			 struct device_attribute *attr, char *buf)
3236{
3237	struct ptp_ocp *bp = dev_get_drvdata(dev);
3238	u32 val;
3239	int res;
3240
3241	val = ioread32(&bp->reg->status_offset);
3242	res = (val & ~INT_MAX) ? -1 : 1;
3243	res *= (val & INT_MAX);
3244	return sysfs_emit(buf, "%d\n", res);
3245}
3246static DEVICE_ATTR_RO(clock_status_offset);
3247
3248static ssize_t
3249tod_correction_show(struct device *dev,
3250		    struct device_attribute *attr, char *buf)
3251{
3252	struct ptp_ocp *bp = dev_get_drvdata(dev);
3253	u32 val;
3254	int res;
3255
3256	val = ioread32(&bp->tod->adj_sec);
3257	res = (val & ~INT_MAX) ? -1 : 1;
3258	res *= (val & INT_MAX);
3259	return sysfs_emit(buf, "%d\n", res);
3260}
3261
3262static ssize_t
3263tod_correction_store(struct device *dev, struct device_attribute *attr,
3264		     const char *buf, size_t count)
3265{
3266	struct ptp_ocp *bp = dev_get_drvdata(dev);
3267	unsigned long flags;
3268	int err, res;
3269	u32 val = 0;
3270
3271	err = kstrtos32(buf, 0, &res);
3272	if (err)
3273		return err;
3274	if (res < 0) {
3275		res *= -1;
3276		val |= BIT(31);
3277	}
3278	val |= res;
3279
3280	spin_lock_irqsave(&bp->lock, flags);
3281	iowrite32(val, &bp->tod->adj_sec);
3282	spin_unlock_irqrestore(&bp->lock, flags);
3283
3284	return count;
3285}
3286static DEVICE_ATTR_RW(tod_correction);
3287
3288#define _DEVICE_SIGNAL_GROUP_ATTRS(_nr)					\
3289	static struct attribute *fb_timecard_signal##_nr##_attrs[] = {	\
3290		&dev_attr_signal##_nr##_signal.attr.attr,		\
3291		&dev_attr_signal##_nr##_duty.attr.attr,			\
3292		&dev_attr_signal##_nr##_phase.attr.attr,		\
3293		&dev_attr_signal##_nr##_period.attr.attr,		\
3294		&dev_attr_signal##_nr##_polarity.attr.attr,		\
3295		&dev_attr_signal##_nr##_running.attr.attr,		\
3296		&dev_attr_signal##_nr##_start.attr.attr,		\
3297		NULL,							\
3298	}
3299
3300#define DEVICE_SIGNAL_GROUP(_name, _nr)					\
3301	_DEVICE_SIGNAL_GROUP_ATTRS(_nr);				\
3302	static const struct attribute_group				\
3303			fb_timecard_signal##_nr##_group = {		\
3304		.name = #_name,						\
3305		.attrs = fb_timecard_signal##_nr##_attrs,		\
3306}
3307
3308DEVICE_SIGNAL_GROUP(gen1, 0);
3309DEVICE_SIGNAL_GROUP(gen2, 1);
3310DEVICE_SIGNAL_GROUP(gen3, 2);
3311DEVICE_SIGNAL_GROUP(gen4, 3);
3312
3313#define _DEVICE_FREQ_GROUP_ATTRS(_nr)					\
3314	static struct attribute *fb_timecard_freq##_nr##_attrs[] = {	\
3315		&dev_attr_freq##_nr##_seconds.attr.attr,		\
3316		&dev_attr_freq##_nr##_frequency.attr.attr,		\
3317		NULL,							\
3318	}
3319
3320#define DEVICE_FREQ_GROUP(_name, _nr)					\
3321	_DEVICE_FREQ_GROUP_ATTRS(_nr);					\
3322	static const struct attribute_group				\
3323			fb_timecard_freq##_nr##_group = {		\
3324		.name = #_name,						\
3325		.attrs = fb_timecard_freq##_nr##_attrs,			\
3326}
3327
3328DEVICE_FREQ_GROUP(freq1, 0);
3329DEVICE_FREQ_GROUP(freq2, 1);
3330DEVICE_FREQ_GROUP(freq3, 2);
3331DEVICE_FREQ_GROUP(freq4, 3);
3332
3333static ssize_t
3334disciplining_config_read(struct file *filp, struct kobject *kobj,
3335			 struct bin_attribute *bin_attr, char *buf,
3336			 loff_t off, size_t count)
3337{
3338	struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3339	size_t size = OCP_ART_CONFIG_SIZE;
3340	struct nvmem_device *nvmem;
3341	ssize_t err;
3342
3343	nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3344	if (IS_ERR(nvmem))
3345		return PTR_ERR(nvmem);
3346
3347	if (off > size) {
3348		err = 0;
3349		goto out;
3350	}
3351
3352	if (off + count > size)
3353		count = size - off;
3354
3355	// the configuration is in the very beginning of the EEPROM
3356	err = nvmem_device_read(nvmem, off, count, buf);
3357	if (err != count) {
3358		err = -EFAULT;
3359		goto out;
3360	}
3361
3362out:
3363	ptp_ocp_nvmem_device_put(&nvmem);
3364
3365	return err;
3366}
3367
3368static ssize_t
3369disciplining_config_write(struct file *filp, struct kobject *kobj,
3370			  struct bin_attribute *bin_attr, char *buf,
3371			  loff_t off, size_t count)
3372{
3373	struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3374	struct nvmem_device *nvmem;
3375	ssize_t err;
3376
3377	/* Allow write of the whole area only */
3378	if (off || count != OCP_ART_CONFIG_SIZE)
3379		return -EFAULT;
3380
3381	nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3382	if (IS_ERR(nvmem))
3383		return PTR_ERR(nvmem);
3384
3385	err = nvmem_device_write(nvmem, 0x00, count, buf);
3386	if (err != count)
3387		err = -EFAULT;
3388
3389	ptp_ocp_nvmem_device_put(&nvmem);
3390
3391	return err;
3392}
3393static BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
3394
3395static ssize_t
3396temperature_table_read(struct file *filp, struct kobject *kobj,
3397		       struct bin_attribute *bin_attr, char *buf,
3398		       loff_t off, size_t count)
3399{
3400	struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3401	size_t size = OCP_ART_TEMP_TABLE_SIZE;
3402	struct nvmem_device *nvmem;
3403	ssize_t err;
3404
3405	nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3406	if (IS_ERR(nvmem))
3407		return PTR_ERR(nvmem);
3408
3409	if (off > size) {
3410		err = 0;
3411		goto out;
3412	}
3413
3414	if (off + count > size)
3415		count = size - off;
3416
3417	// the configuration is in the very beginning of the EEPROM
3418	err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
3419	if (err != count) {
3420		err = -EFAULT;
3421		goto out;
3422	}
3423
3424out:
3425	ptp_ocp_nvmem_device_put(&nvmem);
3426
3427	return err;
3428}
3429
3430static ssize_t
3431temperature_table_write(struct file *filp, struct kobject *kobj,
3432			struct bin_attribute *bin_attr, char *buf,
3433			loff_t off, size_t count)
3434{
3435	struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3436	struct nvmem_device *nvmem;
3437	ssize_t err;
3438
3439	/* Allow write of the whole area only */
3440	if (off || count != OCP_ART_TEMP_TABLE_SIZE)
3441		return -EFAULT;
3442
3443	nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3444	if (IS_ERR(nvmem))
3445		return PTR_ERR(nvmem);
3446
3447	err = nvmem_device_write(nvmem, 0x90, count, buf);
3448	if (err != count)
3449		err = -EFAULT;
3450
3451	ptp_ocp_nvmem_device_put(&nvmem);
3452
3453	return err;
3454}
3455static BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
3456
3457static struct attribute *fb_timecard_attrs[] = {
3458	&dev_attr_serialnum.attr,
3459	&dev_attr_gnss_sync.attr,
3460	&dev_attr_clock_source.attr,
3461	&dev_attr_available_clock_sources.attr,
3462	&dev_attr_sma1.attr,
3463	&dev_attr_sma2.attr,
3464	&dev_attr_sma3.attr,
3465	&dev_attr_sma4.attr,
3466	&dev_attr_available_sma_inputs.attr,
3467	&dev_attr_available_sma_outputs.attr,
3468	&dev_attr_clock_status_drift.attr,
3469	&dev_attr_clock_status_offset.attr,
3470	&dev_attr_irig_b_mode.attr,
3471	&dev_attr_utc_tai_offset.attr,
3472	&dev_attr_ts_window_adjust.attr,
3473	&dev_attr_tod_correction.attr,
3474	NULL,
3475};
3476
3477static const struct attribute_group fb_timecard_group = {
3478	.attrs = fb_timecard_attrs,
3479};
3480
3481static const struct ocp_attr_group fb_timecard_groups[] = {
3482	{ .cap = OCP_CAP_BASIC,	    .group = &fb_timecard_group },
3483	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal0_group },
3484	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal1_group },
3485	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal2_group },
3486	{ .cap = OCP_CAP_SIGNAL,    .group = &fb_timecard_signal3_group },
3487	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq0_group },
3488	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq1_group },
3489	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq2_group },
3490	{ .cap = OCP_CAP_FREQ,	    .group = &fb_timecard_freq3_group },
3491	{ },
3492};
3493
3494static struct attribute *art_timecard_attrs[] = {
3495	&dev_attr_serialnum.attr,
3496	&dev_attr_clock_source.attr,
3497	&dev_attr_available_clock_sources.attr,
3498	&dev_attr_utc_tai_offset.attr,
3499	&dev_attr_ts_window_adjust.attr,
3500	&dev_attr_sma1.attr,
3501	&dev_attr_sma2.attr,
3502	&dev_attr_sma3.attr,
3503	&dev_attr_sma4.attr,
3504	&dev_attr_available_sma_inputs.attr,
3505	&dev_attr_available_sma_outputs.attr,
3506	NULL,
3507};
3508
3509static struct bin_attribute *bin_art_timecard_attrs[] = {
3510	&bin_attr_disciplining_config,
3511	&bin_attr_temperature_table,
3512	NULL,
3513};
3514
3515static const struct attribute_group art_timecard_group = {
3516	.attrs = art_timecard_attrs,
3517	.bin_attrs = bin_art_timecard_attrs,
3518};
3519
3520static const struct ocp_attr_group art_timecard_groups[] = {
3521	{ .cap = OCP_CAP_BASIC,	    .group = &art_timecard_group },
3522	{ },
3523};
3524
3525static void
3526gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
3527	       const char *def)
3528{
3529	int i;
3530
3531	for (i = 0; i < 4; i++) {
3532		if (bp->sma[i].mode != SMA_MODE_IN)
3533			continue;
3534		if (map[i][0] & (1 << bit)) {
3535			sprintf(buf, "sma%d", i + 1);
3536			return;
3537		}
3538	}
3539	if (!def)
3540		def = "----";
3541	strcpy(buf, def);
3542}
3543
3544static void
3545gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
3546{
3547	char *ans = buf;
3548	int i;
3549
3550	strcpy(ans, "----");
3551	for (i = 0; i < 4; i++) {
3552		if (bp->sma[i].mode != SMA_MODE_OUT)
3553			continue;
3554		if (map[i][1] & (1 << bit))
3555			ans += sprintf(ans, "sma%d ", i + 1);
3556	}
3557}
3558
3559static void
3560_signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
3561{
3562	struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
3563	struct ptp_ocp_signal *signal = &bp->signal[nr];
3564	char label[8];
3565	bool on;
3566	u32 val;
3567
3568	if (!signal)
3569		return;
3570
3571	on = signal->running;
3572	sprintf(label, "GEN%d", nr + 1);
3573	seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
3574		   label, on ? " ON" : "OFF",
3575		   signal->period, signal->duty, signal->phase,
3576		   signal->polarity);
3577
3578	val = ioread32(&reg->enable);
3579	seq_printf(s, " [%x", val);
3580	val = ioread32(&reg->status);
3581	seq_printf(s, " %x]", val);
3582
3583	seq_printf(s, " start:%llu\n", signal->start);
3584}
3585
3586static void
3587_frequency_summary_show(struct seq_file *s, int nr,
3588			struct frequency_reg __iomem *reg)
3589{
3590	char label[8];
3591	bool on;
3592	u32 val;
3593
3594	if (!reg)
3595		return;
3596
3597	sprintf(label, "FREQ%d", nr + 1);
3598	val = ioread32(&reg->ctrl);
3599	on = val & 1;
3600	val = (val >> 8) & 0xff;
3601	seq_printf(s, "%7s: %s, sec:%u",
3602		   label,
3603		   on ? " ON" : "OFF",
3604		   val);
3605
3606	val = ioread32(&reg->status);
3607	if (val & FREQ_STATUS_ERROR)
3608		seq_printf(s, ", error");
3609	if (val & FREQ_STATUS_OVERRUN)
3610		seq_printf(s, ", overrun");
3611	if (val & FREQ_STATUS_VALID)
3612		seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
3613	seq_printf(s, "  reg:%x\n", val);
3614}
3615
3616static int
3617ptp_ocp_summary_show(struct seq_file *s, void *data)
3618{
3619	struct device *dev = s->private;
3620	struct ptp_system_timestamp sts;
3621	struct ts_reg __iomem *ts_reg;
3622	char *buf, *src, *mac_src;
3623	struct timespec64 ts;
3624	struct ptp_ocp *bp;
3625	u16 sma_val[4][2];
3626	u32 ctrl, val;
3627	bool on, map;
3628	int i;
3629
3630	buf = (char *)__get_free_page(GFP_KERNEL);
3631	if (!buf)
3632		return -ENOMEM;
3633
3634	bp = dev_get_drvdata(dev);
3635
3636	seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
3637	if (bp->gnss_port.line != -1)
3638		seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS1",
3639			   bp->gnss_port.line);
3640	if (bp->gnss2_port.line != -1)
3641		seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS2",
3642			   bp->gnss2_port.line);
3643	if (bp->mac_port.line != -1)
3644		seq_printf(s, "%7s: /dev/ttyS%d\n", "MAC", bp->mac_port.line);
3645	if (bp->nmea_port.line != -1)
3646		seq_printf(s, "%7s: /dev/ttyS%d\n", "NMEA", bp->nmea_port.line);
3647
3648	memset(sma_val, 0xff, sizeof(sma_val));
3649	if (bp->sma_map1) {
3650		u32 reg;
3651
3652		reg = ioread32(&bp->sma_map1->gpio1);
3653		sma_val[0][0] = reg & 0xffff;
3654		sma_val[1][0] = reg >> 16;
3655
3656		reg = ioread32(&bp->sma_map1->gpio2);
3657		sma_val[2][1] = reg & 0xffff;
3658		sma_val[3][1] = reg >> 16;
3659
3660		reg = ioread32(&bp->sma_map2->gpio1);
3661		sma_val[2][0] = reg & 0xffff;
3662		sma_val[3][0] = reg >> 16;
3663
3664		reg = ioread32(&bp->sma_map2->gpio2);
3665		sma_val[0][1] = reg & 0xffff;
3666		sma_val[1][1] = reg >> 16;
3667	}
3668
3669	sma1_show(dev, NULL, buf);
3670	seq_printf(s, "   sma1: %04x,%04x %s",
3671		   sma_val[0][0], sma_val[0][1], buf);
3672
3673	sma2_show(dev, NULL, buf);
3674	seq_printf(s, "   sma2: %04x,%04x %s",
3675		   sma_val[1][0], sma_val[1][1], buf);
3676
3677	sma3_show(dev, NULL, buf);
3678	seq_printf(s, "   sma3: %04x,%04x %s",
3679		   sma_val[2][0], sma_val[2][1], buf);
3680
3681	sma4_show(dev, NULL, buf);
3682	seq_printf(s, "   sma4: %04x,%04x %s",
3683		   sma_val[3][0], sma_val[3][1], buf);
3684
3685	if (bp->ts0) {
3686		ts_reg = bp->ts0->mem;
3687		on = ioread32(&ts_reg->enable);
3688		src = "GNSS1";
3689		seq_printf(s, "%7s: %s, src: %s\n", "TS0",
3690			   on ? " ON" : "OFF", src);
3691	}
3692
3693	if (bp->ts1) {
3694		ts_reg = bp->ts1->mem;
3695		on = ioread32(&ts_reg->enable);
3696		gpio_input_map(buf, bp, sma_val, 2, NULL);
3697		seq_printf(s, "%7s: %s, src: %s\n", "TS1",
3698			   on ? " ON" : "OFF", buf);
3699	}
3700
3701	if (bp->ts2) {
3702		ts_reg = bp->ts2->mem;
3703		on = ioread32(&ts_reg->enable);
3704		gpio_input_map(buf, bp, sma_val, 3, NULL);
3705		seq_printf(s, "%7s: %s, src: %s\n", "TS2",
3706			   on ? " ON" : "OFF", buf);
3707	}
3708
3709	if (bp->ts3) {
3710		ts_reg = bp->ts3->mem;
3711		on = ioread32(&ts_reg->enable);
3712		gpio_input_map(buf, bp, sma_val, 6, NULL);
3713		seq_printf(s, "%7s: %s, src: %s\n", "TS3",
3714			   on ? " ON" : "OFF", buf);
3715	}
3716
3717	if (bp->ts4) {
3718		ts_reg = bp->ts4->mem;
3719		on = ioread32(&ts_reg->enable);
3720		gpio_input_map(buf, bp, sma_val, 7, NULL);
3721		seq_printf(s, "%7s: %s, src: %s\n", "TS4",
3722			   on ? " ON" : "OFF", buf);
3723	}
3724
3725	if (bp->pps) {
3726		ts_reg = bp->pps->mem;
3727		src = "PHC";
3728		on = ioread32(&ts_reg->enable);
3729		map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
3730		seq_printf(s, "%7s: %s, src: %s\n", "TS5",
3731			   on && map ? " ON" : "OFF", src);
3732
3733		map = !!(bp->pps_req_map & OCP_REQ_PPS);
3734		seq_printf(s, "%7s: %s, src: %s\n", "PPS",
3735			   on && map ? " ON" : "OFF", src);
3736	}
3737
3738	if (bp->fw_cap & OCP_CAP_SIGNAL)
3739		for (i = 0; i < 4; i++)
3740			_signal_summary_show(s, bp, i);
3741
3742	if (bp->fw_cap & OCP_CAP_FREQ)
3743		for (i = 0; i < 4; i++)
3744			_frequency_summary_show(s, i, bp->freq_in[i]);
3745
3746	if (bp->irig_out) {
3747		ctrl = ioread32(&bp->irig_out->ctrl);
3748		on = ctrl & IRIG_M_CTRL_ENABLE;
3749		val = ioread32(&bp->irig_out->status);
3750		gpio_output_map(buf, bp, sma_val, 4);
3751		seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
3752			   on ? " ON" : "OFF", val, (ctrl >> 16), buf);
3753	}
3754
3755	if (bp->irig_in) {
3756		on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
3757		val = ioread32(&bp->irig_in->status);
3758		gpio_input_map(buf, bp, sma_val, 4, NULL);
3759		seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
3760			   on ? " ON" : "OFF", val, buf);
3761	}
3762
3763	if (bp->dcf_out) {
3764		on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
3765		val = ioread32(&bp->dcf_out->status);
3766		gpio_output_map(buf, bp, sma_val, 5);
3767		seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
3768			   on ? " ON" : "OFF", val, buf);
3769	}
3770
3771	if (bp->dcf_in) {
3772		on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
3773		val = ioread32(&bp->dcf_in->status);
3774		gpio_input_map(buf, bp, sma_val, 5, NULL);
3775		seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
3776			   on ? " ON" : "OFF", val, buf);
3777	}
3778
3779	if (bp->nmea_out) {
3780		on = ioread32(&bp->nmea_out->ctrl) & 1;
3781		val = ioread32(&bp->nmea_out->status);
3782		seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
3783			   on ? " ON" : "OFF", val);
3784	}
3785
3786	/* compute src for PPS1, used below. */
3787	if (bp->pps_select) {
3788		val = ioread32(&bp->pps_select->gpio1);
3789		src = &buf[80];
3790		mac_src = "GNSS1";
3791		if (val & 0x01) {
3792			gpio_input_map(src, bp, sma_val, 0, NULL);
3793			mac_src = src;
3794		} else if (val & 0x02) {
3795			src = "MAC";
3796		} else if (val & 0x04) {
3797			src = "GNSS1";
3798		} else {
3799			src = "----";
3800			mac_src = src;
3801		}
3802	} else {
3803		src = "?";
3804		mac_src = src;
3805	}
3806	seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
3807
3808	gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
3809	seq_printf(s, "MAC PPS2 src: %s\n", buf);
3810
3811	/* assumes automatic switchover/selection */
3812	val = ioread32(&bp->reg->select);
3813	switch (val >> 16) {
3814	case 0:
3815		sprintf(buf, "----");
3816		break;
3817	case 2:
3818		sprintf(buf, "IRIG");
3819		break;
3820	case 3:
3821		sprintf(buf, "%s via PPS1", src);
3822		break;
3823	case 6:
3824		sprintf(buf, "DCF");
3825		break;
3826	default:
3827		strcpy(buf, "unknown");
3828		break;
3829	}
3830	val = ioread32(&bp->reg->status);
3831	seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
3832		   val & OCP_STATUS_IN_SYNC ? "sync" : "unsynced");
3833
3834	if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
3835		struct timespec64 sys_ts;
3836		s64 pre_ns, post_ns, ns;
3837
3838		pre_ns = timespec64_to_ns(&sts.pre_ts);
3839		post_ns = timespec64_to_ns(&sts.post_ts);
3840		ns = (pre_ns + post_ns) / 2;
3841		ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
3842		sys_ts = ns_to_timespec64(ns);
3843
3844		seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
3845			   ts.tv_sec, ts.tv_nsec, &ts);
3846		seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
3847			   sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
3848			   bp->utc_tai_offset);
3849		seq_printf(s, "%7s: PHC:SYS offset: %lld  window: %lld\n", "",
3850			   timespec64_to_ns(&ts) - ns,
3851			   post_ns - pre_ns);
3852	}
3853
3854	free_page((unsigned long)buf);
3855	return 0;
3856}
3857DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
3858
3859static int
3860ptp_ocp_tod_status_show(struct seq_file *s, void *data)
3861{
3862	struct device *dev = s->private;
3863	struct ptp_ocp *bp;
3864	u32 val;
3865	int idx;
3866
3867	bp = dev_get_drvdata(dev);
3868
3869	val = ioread32(&bp->tod->ctrl);
3870	if (!(val & TOD_CTRL_ENABLE)) {
3871		seq_printf(s, "TOD Slave disabled\n");
3872		return 0;
3873	}
3874	seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
3875
3876	idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
3877	idx += (val >> 16) & 3;
3878	seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
3879
3880	idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
3881	seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
3882
3883	val = ioread32(&bp->tod->version);
3884	seq_printf(s, "TOD Version %d.%d.%d\n",
3885		val >> 24, (val >> 16) & 0xff, val & 0xffff);
3886
3887	val = ioread32(&bp->tod->status);
3888	seq_printf(s, "Status register: 0x%08X\n", val);
3889
3890	val = ioread32(&bp->tod->adj_sec);
3891	idx = (val & ~INT_MAX) ? -1 : 1;
3892	idx *= (val & INT_MAX);
3893	seq_printf(s, "Correction seconds: %d\n", idx);
3894
3895	val = ioread32(&bp->tod->utc_status);
3896	seq_printf(s, "UTC status register: 0x%08X\n", val);
3897	seq_printf(s, "UTC offset: %ld  valid:%d\n",
3898		val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
3899	seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
3900		val & TOD_STATUS_LEAP_VALID ? 1 : 0,
3901		val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
3902
3903	val = ioread32(&bp->tod->leap);
3904	seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
3905
3906	return 0;
3907}
3908DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
3909
3910static struct dentry *ptp_ocp_debugfs_root;
3911
3912static void
3913ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
3914{
3915	struct dentry *d;
3916
3917	d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
3918	bp->debug_root = d;
3919	debugfs_create_file("summary", 0444, bp->debug_root,
3920			    &bp->dev, &ptp_ocp_summary_fops);
3921	if (bp->tod)
3922		debugfs_create_file("tod_status", 0444, bp->debug_root,
3923				    &bp->dev, &ptp_ocp_tod_status_fops);
3924}
3925
3926static void
3927ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
3928{
3929	debugfs_remove_recursive(bp->debug_root);
3930}
3931
3932static void
3933ptp_ocp_debugfs_init(void)
3934{
3935	ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
3936}
3937
3938static void
3939ptp_ocp_debugfs_fini(void)
3940{
3941	debugfs_remove_recursive(ptp_ocp_debugfs_root);
3942}
3943
3944static void
3945ptp_ocp_dev_release(struct device *dev)
3946{
3947	struct ptp_ocp *bp = dev_get_drvdata(dev);
3948
3949	mutex_lock(&ptp_ocp_lock);
3950	idr_remove(&ptp_ocp_idr, bp->id);
3951	mutex_unlock(&ptp_ocp_lock);
3952}
3953
3954static int
3955ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
3956{
3957	int err;
3958
3959	mutex_lock(&ptp_ocp_lock);
3960	err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
3961	mutex_unlock(&ptp_ocp_lock);
3962	if (err < 0) {
3963		dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
3964		return err;
3965	}
3966	bp->id = err;
3967
3968	bp->ptp_info = ptp_ocp_clock_info;
3969	spin_lock_init(&bp->lock);
3970	bp->gnss_port.line = -1;
3971	bp->gnss2_port.line = -1;
3972	bp->mac_port.line = -1;
3973	bp->nmea_port.line = -1;
3974	bp->pdev = pdev;
3975
3976	device_initialize(&bp->dev);
3977	dev_set_name(&bp->dev, "ocp%d", bp->id);
3978	bp->dev.class = &timecard_class;
3979	bp->dev.parent = &pdev->dev;
3980	bp->dev.release = ptp_ocp_dev_release;
3981	dev_set_drvdata(&bp->dev, bp);
3982
3983	err = device_add(&bp->dev);
3984	if (err) {
3985		dev_err(&bp->dev, "device add failed: %d\n", err);
3986		goto out;
3987	}
3988
3989	pci_set_drvdata(pdev, bp);
3990
3991	return 0;
3992
3993out:
3994	ptp_ocp_dev_release(&bp->dev);
3995	put_device(&bp->dev);
3996	return err;
3997}
3998
3999static void
4000ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
4001{
4002	struct device *dev = &bp->dev;
4003
4004	if (sysfs_create_link(&dev->kobj, &child->kobj, link))
4005		dev_err(dev, "%s symlink failed\n", link);
4006}
4007
4008static void
4009ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
4010{
4011	struct device *dev, *child;
4012
4013	dev = &bp->pdev->dev;
4014
4015	child = device_find_child_by_name(dev, name);
4016	if (!child) {
4017		dev_err(dev, "Could not find device %s\n", name);
4018		return;
4019	}
4020
4021	ptp_ocp_symlink(bp, child, link);
4022	put_device(child);
4023}
4024
4025static int
4026ptp_ocp_complete(struct ptp_ocp *bp)
4027{
4028	struct pps_device *pps;
4029	char buf[32];
4030
4031	if (bp->gnss_port.line != -1) {
4032		sprintf(buf, "ttyS%d", bp->gnss_port.line);
4033		ptp_ocp_link_child(bp, buf, "ttyGNSS");
4034	}
4035	if (bp->gnss2_port.line != -1) {
4036		sprintf(buf, "ttyS%d", bp->gnss2_port.line);
4037		ptp_ocp_link_child(bp, buf, "ttyGNSS2");
4038	}
4039	if (bp->mac_port.line != -1) {
4040		sprintf(buf, "ttyS%d", bp->mac_port.line);
4041		ptp_ocp_link_child(bp, buf, "ttyMAC");
4042	}
4043	if (bp->nmea_port.line != -1) {
4044		sprintf(buf, "ttyS%d", bp->nmea_port.line);
4045		ptp_ocp_link_child(bp, buf, "ttyNMEA");
4046	}
4047	sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
4048	ptp_ocp_link_child(bp, buf, "ptp");
4049
4050	pps = pps_lookup_dev(bp->ptp);
4051	if (pps)
4052		ptp_ocp_symlink(bp, pps->dev, "pps");
4053
4054	ptp_ocp_debugfs_add_device(bp);
4055
4056	return 0;
4057}
4058
4059static void
4060ptp_ocp_phc_info(struct ptp_ocp *bp)
4061{
4062	struct timespec64 ts;
4063	u32 version, select;
4064	bool sync;
4065
4066	version = ioread32(&bp->reg->version);
4067	select = ioread32(&bp->reg->select);
4068	dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
4069		 version >> 24, (version >> 16) & 0xff, version & 0xffff,
4070		 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
4071		 ptp_clock_index(bp->ptp));
4072
4073	sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
4074	if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
4075		dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
4076			 ts.tv_sec, ts.tv_nsec,
4077			 sync ? "in-sync" : "UNSYNCED");
4078}
4079
4080static void
4081ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
4082{
4083	if (port != -1)
4084		dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
4085}
4086
4087static void
4088ptp_ocp_info(struct ptp_ocp *bp)
4089{
4090	static int nmea_baud[] = {
4091		1200, 2400, 4800, 9600, 19200, 38400,
4092		57600, 115200, 230400, 460800, 921600,
4093		1000000, 2000000
4094	};
4095	struct device *dev = &bp->pdev->dev;
4096	u32 reg;
4097
4098	ptp_ocp_phc_info(bp);
4099
4100	ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port.line,
4101			    bp->gnss_port.baud);
4102	ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port.line,
4103			    bp->gnss2_port.baud);
4104	ptp_ocp_serial_info(dev, "MAC", bp->mac_port.line, bp->mac_port.baud);
4105	if (bp->nmea_out && bp->nmea_port.line != -1) {
4106		bp->nmea_port.baud = -1;
4107
4108		reg = ioread32(&bp->nmea_out->uart_baud);
4109		if (reg < ARRAY_SIZE(nmea_baud))
4110			bp->nmea_port.baud = nmea_baud[reg];
4111
4112		ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port.line,
4113				    bp->nmea_port.baud);
4114	}
4115}
4116
4117static void
4118ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
4119{
4120	struct device *dev = &bp->dev;
4121
4122	sysfs_remove_link(&dev->kobj, "ttyGNSS");
4123	sysfs_remove_link(&dev->kobj, "ttyGNSS2");
4124	sysfs_remove_link(&dev->kobj, "ttyMAC");
4125	sysfs_remove_link(&dev->kobj, "ptp");
4126	sysfs_remove_link(&dev->kobj, "pps");
4127}
4128
4129static void
4130ptp_ocp_detach(struct ptp_ocp *bp)
4131{
4132	int i;
4133
4134	ptp_ocp_debugfs_remove_device(bp);
4135	ptp_ocp_detach_sysfs(bp);
4136	ptp_ocp_attr_group_del(bp);
4137	if (timer_pending(&bp->watchdog))
4138		del_timer_sync(&bp->watchdog);
4139	if (bp->ts0)
4140		ptp_ocp_unregister_ext(bp->ts0);
4141	if (bp->ts1)
4142		ptp_ocp_unregister_ext(bp->ts1);
4143	if (bp->ts2)
4144		ptp_ocp_unregister_ext(bp->ts2);
4145	if (bp->ts3)
4146		ptp_ocp_unregister_ext(bp->ts3);
4147	if (bp->ts4)
4148		ptp_ocp_unregister_ext(bp->ts4);
4149	if (bp->pps)
4150		ptp_ocp_unregister_ext(bp->pps);
4151	for (i = 0; i < 4; i++)
4152		if (bp->signal_out[i])
4153			ptp_ocp_unregister_ext(bp->signal_out[i]);
4154	if (bp->gnss_port.line != -1)
4155		serial8250_unregister_port(bp->gnss_port.line);
4156	if (bp->gnss2_port.line != -1)
4157		serial8250_unregister_port(bp->gnss2_port.line);
4158	if (bp->mac_port.line != -1)
4159		serial8250_unregister_port(bp->mac_port.line);
4160	if (bp->nmea_port.line != -1)
4161		serial8250_unregister_port(bp->nmea_port.line);
4162	platform_device_unregister(bp->spi_flash);
4163	platform_device_unregister(bp->i2c_ctrl);
4164	if (bp->i2c_clk)
4165		clk_hw_unregister_fixed_rate(bp->i2c_clk);
4166	if (bp->n_irqs)
4167		pci_free_irq_vectors(bp->pdev);
4168	if (bp->ptp)
4169		ptp_clock_unregister(bp->ptp);
4170	kfree(bp->ptp_info.pin_config);
4171	device_unregister(&bp->dev);
4172}
4173
4174static int
4175ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4176{
4177	struct devlink *devlink;
4178	struct ptp_ocp *bp;
4179	int err;
4180
4181	devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
4182	if (!devlink) {
4183		dev_err(&pdev->dev, "devlink_alloc failed\n");
4184		return -ENOMEM;
4185	}
4186
4187	err = pci_enable_device(pdev);
4188	if (err) {
4189		dev_err(&pdev->dev, "pci_enable_device\n");
4190		goto out_free;
4191	}
4192
4193	bp = devlink_priv(devlink);
4194	err = ptp_ocp_device_init(bp, pdev);
4195	if (err)
4196		goto out_disable;
4197
4198	/* compat mode.
4199	 * Older FPGA firmware only returns 2 irq's.
4200	 * allow this - if not all of the IRQ's are returned, skip the
4201	 * extra devices and just register the clock.
4202	 */
4203	err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
4204	if (err < 0) {
4205		dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
4206		goto out;
4207	}
4208	bp->n_irqs = err;
4209	pci_set_master(pdev);
4210
4211	err = ptp_ocp_register_resources(bp, id->driver_data);
4212	if (err)
4213		goto out;
4214
4215	bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
4216	if (IS_ERR(bp->ptp)) {
4217		err = PTR_ERR(bp->ptp);
4218		dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
4219		bp->ptp = NULL;
4220		goto out;
4221	}
4222
4223	err = ptp_ocp_complete(bp);
4224	if (err)
4225		goto out;
4226
4227	ptp_ocp_info(bp);
4228	devlink_register(devlink);
4229	return 0;
4230
4231out:
4232	ptp_ocp_detach(bp);
4233out_disable:
4234	pci_disable_device(pdev);
4235out_free:
4236	devlink_free(devlink);
4237	return err;
4238}
4239
4240static void
4241ptp_ocp_remove(struct pci_dev *pdev)
4242{
4243	struct ptp_ocp *bp = pci_get_drvdata(pdev);
4244	struct devlink *devlink = priv_to_devlink(bp);
4245
4246	devlink_unregister(devlink);
4247	ptp_ocp_detach(bp);
4248	pci_disable_device(pdev);
4249
4250	devlink_free(devlink);
4251}
4252
4253static struct pci_driver ptp_ocp_driver = {
4254	.name		= KBUILD_MODNAME,
4255	.id_table	= ptp_ocp_pcidev_id,
4256	.probe		= ptp_ocp_probe,
4257	.remove		= ptp_ocp_remove,
4258};
4259
4260static int
4261ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
4262			  unsigned long action, void *data)
4263{
4264	struct device *dev, *child = data;
4265	struct ptp_ocp *bp;
4266	bool add;
4267
4268	switch (action) {
4269	case BUS_NOTIFY_ADD_DEVICE:
4270	case BUS_NOTIFY_DEL_DEVICE:
4271		add = action == BUS_NOTIFY_ADD_DEVICE;
4272		break;
4273	default:
4274		return 0;
4275	}
4276
4277	if (!i2c_verify_adapter(child))
4278		return 0;
4279
4280	dev = child;
4281	while ((dev = dev->parent))
4282		if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
4283			goto found;
4284	return 0;
4285
4286found:
4287	bp = dev_get_drvdata(dev);
4288	if (add)
4289		ptp_ocp_symlink(bp, child, "i2c");
4290	else
4291		sysfs_remove_link(&bp->dev.kobj, "i2c");
4292
4293	return 0;
4294}
4295
4296static struct notifier_block ptp_ocp_i2c_notifier = {
4297	.notifier_call = ptp_ocp_i2c_notifier_call,
4298};
4299
4300static int __init
4301ptp_ocp_init(void)
4302{
4303	const char *what;
4304	int err;
4305
4306	ptp_ocp_debugfs_init();
4307
4308	what = "timecard class";
4309	err = class_register(&timecard_class);
4310	if (err)
4311		goto out;
4312
4313	what = "i2c notifier";
4314	err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4315	if (err)
4316		goto out_notifier;
4317
4318	what = "ptp_ocp driver";
4319	err = pci_register_driver(&ptp_ocp_driver);
4320	if (err)
4321		goto out_register;
4322
4323	return 0;
4324
4325out_register:
4326	bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4327out_notifier:
4328	class_unregister(&timecard_class);
4329out:
4330	ptp_ocp_debugfs_fini();
4331	pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
4332	return err;
4333}
4334
4335static void __exit
4336ptp_ocp_fini(void)
4337{
4338	bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4339	pci_unregister_driver(&ptp_ocp_driver);
4340	class_unregister(&timecard_class);
4341	ptp_ocp_debugfs_fini();
4342}
4343
4344module_init(ptp_ocp_init);
4345module_exit(ptp_ocp_fini);
4346
4347MODULE_DESCRIPTION("OpenCompute TimeCard driver");
4348MODULE_LICENSE("GPL v2");