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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
4 * synchronization devices.
5 *
6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
7 */
8#include <linux/firmware.h>
9#include <linux/i2c.h>
10#include <linux/module.h>
11#include <linux/ptp_clock_kernel.h>
12#include <linux/delay.h>
13#include <linux/jiffies.h>
14#include <linux/kernel.h>
15#include <linux/timekeeping.h>
16#include <linux/string.h>
17
18#include "ptp_private.h"
19#include "ptp_clockmatrix.h"
20
21MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
22MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
23MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
24MODULE_VERSION("1.0");
25MODULE_LICENSE("GPL");
26
27/*
28 * The name of the firmware file to be loaded
29 * over-rides any automatic selection
30 */
31static char *firmware;
32module_param(firmware, charp, 0);
33
34#define SETTIME_CORRECTION (0)
35
36static long set_write_phase_ready(struct ptp_clock_info *ptp)
37{
38 struct idtcm_channel *channel =
39 container_of(ptp, struct idtcm_channel, caps);
40
41 channel->write_phase_ready = 1;
42
43 return 0;
44}
45
46static int char_array_to_timespec(u8 *buf,
47 u8 count,
48 struct timespec64 *ts)
49{
50 u8 i;
51 u64 nsec;
52 time64_t sec;
53
54 if (count < TOD_BYTE_COUNT)
55 return 1;
56
57 /* Sub-nanoseconds are in buf[0]. */
58 nsec = buf[4];
59 for (i = 0; i < 3; i++) {
60 nsec <<= 8;
61 nsec |= buf[3 - i];
62 }
63
64 sec = buf[10];
65 for (i = 0; i < 5; i++) {
66 sec <<= 8;
67 sec |= buf[9 - i];
68 }
69
70 ts->tv_sec = sec;
71 ts->tv_nsec = nsec;
72
73 return 0;
74}
75
76static int timespec_to_char_array(struct timespec64 const *ts,
77 u8 *buf,
78 u8 count)
79{
80 u8 i;
81 s32 nsec;
82 time64_t sec;
83
84 if (count < TOD_BYTE_COUNT)
85 return 1;
86
87 nsec = ts->tv_nsec;
88 sec = ts->tv_sec;
89
90 /* Sub-nanoseconds are in buf[0]. */
91 buf[0] = 0;
92 for (i = 1; i < 5; i++) {
93 buf[i] = nsec & 0xff;
94 nsec >>= 8;
95 }
96
97 for (i = 5; i < TOD_BYTE_COUNT; i++) {
98
99 buf[i] = sec & 0xff;
100 sec >>= 8;
101 }
102
103 return 0;
104}
105
106static int idtcm_strverscmp(const char *ver1, const char *ver2)
107{
108 u8 num1;
109 u8 num2;
110 int result = 0;
111
112 /* loop through each level of the version string */
113 while (result == 0) {
114 /* extract leading version numbers */
115 if (kstrtou8(ver1, 10, &num1) < 0)
116 return -1;
117
118 if (kstrtou8(ver2, 10, &num2) < 0)
119 return -1;
120
121 /* if numbers differ, then set the result */
122 if (num1 < num2)
123 result = -1;
124 else if (num1 > num2)
125 result = 1;
126 else {
127 /* if numbers are the same, go to next level */
128 ver1 = strchr(ver1, '.');
129 ver2 = strchr(ver2, '.');
130 if (!ver1 && !ver2)
131 break;
132 else if (!ver1)
133 result = -1;
134 else if (!ver2)
135 result = 1;
136 else {
137 ver1++;
138 ver2++;
139 }
140 }
141 }
142 return result;
143}
144
145static int idtcm_xfer_read(struct idtcm *idtcm,
146 u8 regaddr,
147 u8 *buf,
148 u16 count)
149{
150 struct i2c_client *client = idtcm->client;
151 struct i2c_msg msg[2];
152 int cnt;
153 char *fmt = "i2c_transfer failed at %d in %s, at addr: %04X!\n";
154
155 msg[0].addr = client->addr;
156 msg[0].flags = 0;
157 msg[0].len = 1;
158 msg[0].buf = ®addr;
159
160 msg[1].addr = client->addr;
161 msg[1].flags = I2C_M_RD;
162 msg[1].len = count;
163 msg[1].buf = buf;
164
165 cnt = i2c_transfer(client->adapter, msg, 2);
166
167 if (cnt < 0) {
168 dev_err(&client->dev,
169 fmt,
170 __LINE__,
171 __func__,
172 regaddr);
173 return cnt;
174 } else if (cnt != 2) {
175 dev_err(&client->dev,
176 "i2c_transfer sent only %d of %d messages\n", cnt, 2);
177 return -EIO;
178 }
179
180 return 0;
181}
182
183static int idtcm_xfer_write(struct idtcm *idtcm,
184 u8 regaddr,
185 u8 *buf,
186 u16 count)
187{
188 struct i2c_client *client = idtcm->client;
189 /* we add 1 byte for device register */
190 u8 msg[IDTCM_MAX_WRITE_COUNT + 1];
191 int cnt;
192 char *fmt = "i2c_master_send failed at %d in %s, at addr: %04X!\n";
193
194 if (count > IDTCM_MAX_WRITE_COUNT)
195 return -EINVAL;
196
197 msg[0] = regaddr;
198 memcpy(&msg[1], buf, count);
199
200 cnt = i2c_master_send(client, msg, count + 1);
201
202 if (cnt < 0) {
203 dev_err(&client->dev,
204 fmt,
205 __LINE__,
206 __func__,
207 regaddr);
208 return cnt;
209 }
210
211 return 0;
212}
213
214static int idtcm_page_offset(struct idtcm *idtcm, u8 val)
215{
216 u8 buf[4];
217 int err;
218
219 if (idtcm->page_offset == val)
220 return 0;
221
222 buf[0] = 0x0;
223 buf[1] = val;
224 buf[2] = 0x10;
225 buf[3] = 0x20;
226
227 err = idtcm_xfer_write(idtcm, PAGE_ADDR, buf, sizeof(buf));
228
229 if (err) {
230 idtcm->page_offset = 0xff;
231 dev_err(&idtcm->client->dev, "failed to set page offset\n");
232 } else {
233 idtcm->page_offset = val;
234 }
235
236 return err;
237}
238
239static int _idtcm_rdwr(struct idtcm *idtcm,
240 u16 regaddr,
241 u8 *buf,
242 u16 count,
243 bool write)
244{
245 u8 hi;
246 u8 lo;
247 int err;
248
249 hi = (regaddr >> 8) & 0xff;
250 lo = regaddr & 0xff;
251
252 err = idtcm_page_offset(idtcm, hi);
253
254 if (err)
255 return err;
256
257 if (write)
258 return idtcm_xfer_write(idtcm, lo, buf, count);
259
260 return idtcm_xfer_read(idtcm, lo, buf, count);
261}
262
263static int idtcm_read(struct idtcm *idtcm,
264 u16 module,
265 u16 regaddr,
266 u8 *buf,
267 u16 count)
268{
269 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false);
270}
271
272static int idtcm_write(struct idtcm *idtcm,
273 u16 module,
274 u16 regaddr,
275 u8 *buf,
276 u16 count)
277{
278 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true);
279}
280
281static int _idtcm_gettime(struct idtcm_channel *channel,
282 struct timespec64 *ts)
283{
284 struct idtcm *idtcm = channel->idtcm;
285 u8 buf[TOD_BYTE_COUNT];
286 u8 timeout = 10;
287 u8 trigger;
288 int err;
289
290 err = idtcm_read(idtcm, channel->tod_read_primary,
291 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
292 if (err)
293 return err;
294
295 trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT);
296 trigger |= (1 << TOD_READ_TRIGGER_SHIFT);
297 trigger &= ~TOD_READ_TRIGGER_MODE; /* single shot */
298
299 err = idtcm_write(idtcm, channel->tod_read_primary,
300 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
301 if (err)
302 return err;
303
304 /* wait trigger to be 0 */
305 while (trigger & TOD_READ_TRIGGER_MASK) {
306
307 if (idtcm->calculate_overhead_flag)
308 idtcm->start_time = ktime_get_raw();
309
310 err = idtcm_read(idtcm, channel->tod_read_primary,
311 TOD_READ_PRIMARY_CMD, &trigger,
312 sizeof(trigger));
313
314 if (err)
315 return err;
316
317 if (--timeout == 0)
318 return -EIO;
319 }
320
321 err = idtcm_read(idtcm, channel->tod_read_primary,
322 TOD_READ_PRIMARY, buf, sizeof(buf));
323
324 if (err)
325 return err;
326
327 err = char_array_to_timespec(buf, sizeof(buf), ts);
328
329 return err;
330}
331
332static int _sync_pll_output(struct idtcm *idtcm,
333 u8 pll,
334 u8 sync_src,
335 u8 qn,
336 u8 qn_plus_1)
337{
338 int err;
339 u8 val;
340 u16 sync_ctrl0;
341 u16 sync_ctrl1;
342 u8 temp;
343
344 if ((qn == 0) && (qn_plus_1 == 0))
345 return 0;
346
347 switch (pll) {
348 case 0:
349 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
350 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
351 break;
352 case 1:
353 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
354 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
355 break;
356 case 2:
357 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
358 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
359 break;
360 case 3:
361 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
362 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
363 break;
364 case 4:
365 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
366 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
367 break;
368 case 5:
369 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
370 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
371 break;
372 case 6:
373 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
374 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
375 break;
376 case 7:
377 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
378 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
379 break;
380 default:
381 return -EINVAL;
382 }
383
384 val = SYNCTRL1_MASTER_SYNC_RST;
385
386 /* Place master sync in reset */
387 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
388 if (err)
389 return err;
390
391 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
392 if (err)
393 return err;
394
395 /* Set sync trigger mask */
396 val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
397
398 if (qn)
399 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
400
401 if (qn_plus_1)
402 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
403
404 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
405 if (err)
406 return err;
407
408 /* PLL5 can have OUT8 as second additional output. */
409 if ((pll == 5) && (qn_plus_1 != 0)) {
410 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
411 &temp, sizeof(temp));
412 if (err)
413 return err;
414
415 temp &= ~(Q9_TO_Q8_SYNC_TRIG);
416
417 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
418 &temp, sizeof(temp));
419 if (err)
420 return err;
421
422 temp |= Q9_TO_Q8_SYNC_TRIG;
423
424 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
425 &temp, sizeof(temp));
426 if (err)
427 return err;
428 }
429
430 /* PLL6 can have OUT11 as second additional output. */
431 if ((pll == 6) && (qn_plus_1 != 0)) {
432 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
433 &temp, sizeof(temp));
434 if (err)
435 return err;
436
437 temp &= ~(Q10_TO_Q11_SYNC_TRIG);
438
439 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
440 &temp, sizeof(temp));
441 if (err)
442 return err;
443
444 temp |= Q10_TO_Q11_SYNC_TRIG;
445
446 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
447 &temp, sizeof(temp));
448 if (err)
449 return err;
450 }
451
452 /* Place master sync out of reset */
453 val &= ~(SYNCTRL1_MASTER_SYNC_RST);
454 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
455
456 return err;
457}
458
459static int sync_source_dpll_tod_pps(u16 tod_addr, u8 *sync_src)
460{
461 int err = 0;
462
463 switch (tod_addr) {
464 case TOD_0:
465 *sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
466 break;
467 case TOD_1:
468 *sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
469 break;
470 case TOD_2:
471 *sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
472 break;
473 case TOD_3:
474 *sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
475 break;
476 default:
477 err = -EINVAL;
478 }
479
480 return err;
481}
482
483static int idtcm_sync_pps_output(struct idtcm_channel *channel)
484{
485 struct idtcm *idtcm = channel->idtcm;
486
487 u8 pll;
488 u8 sync_src;
489 u8 qn;
490 u8 qn_plus_1;
491 int err = 0;
492 u8 out8_mux = 0;
493 u8 out11_mux = 0;
494 u8 temp;
495
496 u16 output_mask = channel->output_mask;
497
498 err = sync_source_dpll_tod_pps(channel->tod_n, &sync_src);
499 if (err)
500 return err;
501
502 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
503 &temp, sizeof(temp));
504 if (err)
505 return err;
506
507 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
508 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
509 out8_mux = 1;
510
511 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
512 &temp, sizeof(temp));
513 if (err)
514 return err;
515
516 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
517 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
518 out11_mux = 1;
519
520 for (pll = 0; pll < 8; pll++) {
521 qn = 0;
522 qn_plus_1 = 0;
523
524 if (pll < 4) {
525 /* First 4 pll has 2 outputs */
526 qn = output_mask & 0x1;
527 output_mask = output_mask >> 1;
528 qn_plus_1 = output_mask & 0x1;
529 output_mask = output_mask >> 1;
530 } else if (pll == 4) {
531 if (out8_mux == 0) {
532 qn = output_mask & 0x1;
533 output_mask = output_mask >> 1;
534 }
535 } else if (pll == 5) {
536 if (out8_mux) {
537 qn_plus_1 = output_mask & 0x1;
538 output_mask = output_mask >> 1;
539 }
540 qn = output_mask & 0x1;
541 output_mask = output_mask >> 1;
542 } else if (pll == 6) {
543 qn = output_mask & 0x1;
544 output_mask = output_mask >> 1;
545 if (out11_mux) {
546 qn_plus_1 = output_mask & 0x1;
547 output_mask = output_mask >> 1;
548 }
549 } else if (pll == 7) {
550 if (out11_mux == 0) {
551 qn = output_mask & 0x1;
552 output_mask = output_mask >> 1;
553 }
554 }
555
556 if ((qn != 0) || (qn_plus_1 != 0))
557 err = _sync_pll_output(idtcm, pll, sync_src, qn,
558 qn_plus_1);
559
560 if (err)
561 return err;
562 }
563
564 return err;
565}
566
567static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
568 struct timespec64 const *ts,
569 enum hw_tod_write_trig_sel wr_trig)
570{
571 struct idtcm *idtcm = channel->idtcm;
572
573 u8 buf[TOD_BYTE_COUNT];
574 u8 cmd;
575 int err;
576 struct timespec64 local_ts = *ts;
577 s64 total_overhead_ns;
578
579 /* Configure HW TOD write trigger. */
580 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
581 &cmd, sizeof(cmd));
582
583 if (err)
584 return err;
585
586 cmd &= ~(0x0f);
587 cmd |= wr_trig | 0x08;
588
589 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
590 &cmd, sizeof(cmd));
591
592 if (err)
593 return err;
594
595 if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) {
596
597 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
598
599 if (err)
600 return err;
601
602 err = idtcm_write(idtcm, channel->hw_dpll_n,
603 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
604
605 if (err)
606 return err;
607 }
608
609 /* ARM HW TOD write trigger. */
610 cmd &= ~(0x08);
611
612 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
613 &cmd, sizeof(cmd));
614
615 if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
616
617 if (idtcm->calculate_overhead_flag) {
618 /* Assumption: I2C @ 400KHz */
619 total_overhead_ns = ktime_to_ns(ktime_get_raw()
620 - idtcm->start_time)
621 + idtcm->tod_write_overhead_ns
622 + SETTIME_CORRECTION;
623
624 timespec64_add_ns(&local_ts, total_overhead_ns);
625
626 idtcm->calculate_overhead_flag = 0;
627 }
628
629 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
630
631 if (err)
632 return err;
633
634 err = idtcm_write(idtcm, channel->hw_dpll_n,
635 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
636 }
637
638 return err;
639}
640
641static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
642 struct timespec64 const *ts,
643 enum scsr_tod_write_trig_sel wr_trig,
644 enum scsr_tod_write_type_sel wr_type)
645{
646 struct idtcm *idtcm = channel->idtcm;
647 unsigned char buf[TOD_BYTE_COUNT], cmd;
648 struct timespec64 local_ts = *ts;
649 int err, count = 0;
650
651 timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
652
653 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
654
655 if (err)
656 return err;
657
658 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
659 buf, sizeof(buf));
660 if (err)
661 return err;
662
663 /* Trigger the write operation. */
664 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
665 &cmd, sizeof(cmd));
666 if (err)
667 return err;
668
669 cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
670 cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
671 cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
672 cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
673
674 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
675 &cmd, sizeof(cmd));
676 if (err)
677 return err;
678
679 /* Wait for the operation to complete. */
680 while (1) {
681 /* pps trigger takes up to 1 sec to complete */
682 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
683 msleep(50);
684
685 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
686 &cmd, sizeof(cmd));
687 if (err)
688 return err;
689
690 if (cmd == 0)
691 break;
692
693 if (++count > 20) {
694 dev_err(&idtcm->client->dev,
695 "Timed out waiting for the write counter\n");
696 return -EIO;
697 }
698 }
699
700 return 0;
701}
702
703static int _idtcm_settime(struct idtcm_channel *channel,
704 struct timespec64 const *ts,
705 enum hw_tod_write_trig_sel wr_trig)
706{
707 struct idtcm *idtcm = channel->idtcm;
708 int err;
709 int i;
710 u8 trig_sel;
711
712 err = _idtcm_set_dpll_hw_tod(channel, ts, wr_trig);
713
714 if (err)
715 return err;
716
717 /* Wait for the operation to complete. */
718 for (i = 0; i < 10000; i++) {
719 err = idtcm_read(idtcm, channel->hw_dpll_n,
720 HW_DPLL_TOD_CTRL_1, &trig_sel,
721 sizeof(trig_sel));
722
723 if (err)
724 return err;
725
726 if (trig_sel == 0x4a)
727 break;
728
729 err = 1;
730 }
731
732 if (err) {
733 dev_err(&idtcm->client->dev,
734 "Failed at line %d in func %s!\n",
735 __LINE__,
736 __func__);
737 return err;
738 }
739
740 return idtcm_sync_pps_output(channel);
741}
742
743static int _idtcm_settime_v487(struct idtcm_channel *channel,
744 struct timespec64 const *ts,
745 enum scsr_tod_write_type_sel wr_type)
746{
747 return _idtcm_set_dpll_scsr_tod(channel, ts,
748 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
749 wr_type);
750}
751
752static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
753 s32 offset_ns)
754{
755 int err;
756 int i;
757 struct idtcm *idtcm = channel->idtcm;
758
759 u8 buf[4];
760
761 for (i = 0; i < 4; i++) {
762 buf[i] = 0xff & (offset_ns);
763 offset_ns >>= 8;
764 }
765
766 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
767 buf, sizeof(buf));
768
769 return err;
770}
771
772static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
773 u32 max_ffo_ppb)
774{
775 int err;
776 u8 i;
777 struct idtcm *idtcm = channel->idtcm;
778
779 u8 buf[3];
780
781 if (max_ffo_ppb & 0xff000000)
782 max_ffo_ppb = 0;
783
784 for (i = 0; i < 3; i++) {
785 buf[i] = 0xff & (max_ffo_ppb);
786 max_ffo_ppb >>= 8;
787 }
788
789 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
790 PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
791
792 return err;
793}
794
795static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
796{
797 int err;
798 struct idtcm *idtcm = channel->idtcm;
799
800 u8 buf;
801
802 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
803 &buf, sizeof(buf));
804
805 if (err)
806 return err;
807
808 if (buf == 0) {
809 buf = 0x01;
810 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
811 PULL_IN_CTRL, &buf, sizeof(buf));
812 } else {
813 err = -EBUSY;
814 }
815
816 return err;
817}
818
819static int idtcm_do_phase_pull_in(struct idtcm_channel *channel,
820 s32 offset_ns,
821 u32 max_ffo_ppb)
822{
823 int err;
824
825 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
826
827 if (err)
828 return err;
829
830 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
831
832 if (err)
833 return err;
834
835 err = idtcm_start_phase_pull_in(channel);
836
837 return err;
838}
839
840static int set_tod_write_overhead(struct idtcm_channel *channel)
841{
842 struct idtcm *idtcm = channel->idtcm;
843 s64 current_ns = 0;
844 s64 lowest_ns = 0;
845 int err;
846 u8 i;
847
848 ktime_t start;
849 ktime_t stop;
850
851 char buf[TOD_BYTE_COUNT] = {0};
852
853 /* Set page offset */
854 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
855 buf, sizeof(buf));
856
857 for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
858
859 start = ktime_get_raw();
860
861 err = idtcm_write(idtcm, channel->hw_dpll_n,
862 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
863
864 if (err)
865 return err;
866
867 stop = ktime_get_raw();
868
869 current_ns = ktime_to_ns(stop - start);
870
871 if (i == 0) {
872 lowest_ns = current_ns;
873 } else {
874 if (current_ns < lowest_ns)
875 lowest_ns = current_ns;
876 }
877 }
878
879 idtcm->tod_write_overhead_ns = lowest_ns;
880
881 return err;
882}
883
884static int _idtcm_adjtime(struct idtcm_channel *channel, s64 delta)
885{
886 int err;
887 struct idtcm *idtcm = channel->idtcm;
888 struct timespec64 ts;
889 s64 now;
890
891 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
892 err = idtcm_do_phase_pull_in(channel, delta, 0);
893 } else {
894 idtcm->calculate_overhead_flag = 1;
895
896 err = set_tod_write_overhead(channel);
897
898 if (err)
899 return err;
900
901 err = _idtcm_gettime(channel, &ts);
902
903 if (err)
904 return err;
905
906 now = timespec64_to_ns(&ts);
907 now += delta;
908
909 ts = ns_to_timespec64(now);
910
911 err = _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
912 }
913
914 return err;
915}
916
917static int idtcm_state_machine_reset(struct idtcm *idtcm)
918{
919 int err;
920 u8 byte = SM_RESET_CMD;
921
922 err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte));
923
924 if (!err)
925 msleep_interruptible(POST_SM_RESET_DELAY_MS);
926
927 return err;
928}
929
930static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
931{
932 return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
933}
934
935static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
936{
937 int err;
938 u8 buf[2] = {0};
939
940 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
941
942 *product_id = (buf[1] << 8) | buf[0];
943
944 return err;
945}
946
947static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
948{
949 int err;
950 u8 buf = 0;
951
952 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
953
954 *major = buf >> 1;
955
956 return err;
957}
958
959static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
960{
961 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
962}
963
964static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
965{
966 return idtcm_read(idtcm,
967 GENERAL_STATUS,
968 HOTFIX_REL,
969 hotfix,
970 sizeof(u8));
971}
972
973static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
974 u8 *config_select)
975{
976 return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
977 config_select, sizeof(u8));
978}
979
980static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
981{
982 int err = 0;
983
984 switch (addr) {
985 case TOD0_OUT_ALIGN_MASK_ADDR:
986 SET_U16_LSB(idtcm->channel[0].output_mask, val);
987 break;
988 case TOD0_OUT_ALIGN_MASK_ADDR + 1:
989 SET_U16_MSB(idtcm->channel[0].output_mask, val);
990 break;
991 case TOD1_OUT_ALIGN_MASK_ADDR:
992 SET_U16_LSB(idtcm->channel[1].output_mask, val);
993 break;
994 case TOD1_OUT_ALIGN_MASK_ADDR + 1:
995 SET_U16_MSB(idtcm->channel[1].output_mask, val);
996 break;
997 case TOD2_OUT_ALIGN_MASK_ADDR:
998 SET_U16_LSB(idtcm->channel[2].output_mask, val);
999 break;
1000 case TOD2_OUT_ALIGN_MASK_ADDR + 1:
1001 SET_U16_MSB(idtcm->channel[2].output_mask, val);
1002 break;
1003 case TOD3_OUT_ALIGN_MASK_ADDR:
1004 SET_U16_LSB(idtcm->channel[3].output_mask, val);
1005 break;
1006 case TOD3_OUT_ALIGN_MASK_ADDR + 1:
1007 SET_U16_MSB(idtcm->channel[3].output_mask, val);
1008 break;
1009 default:
1010 err = -EFAULT; /* Bad address */;
1011 break;
1012 }
1013
1014 return err;
1015}
1016
1017static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
1018{
1019 if (index >= MAX_TOD) {
1020 dev_err(&idtcm->client->dev, "ToD%d not supported\n", index);
1021 return -EINVAL;
1022 }
1023
1024 if (pll >= MAX_PLL) {
1025 dev_err(&idtcm->client->dev, "Pll%d not supported\n", pll);
1026 return -EINVAL;
1027 }
1028
1029 idtcm->channel[index].pll = pll;
1030
1031 return 0;
1032}
1033
1034static int check_and_set_masks(struct idtcm *idtcm,
1035 u16 regaddr,
1036 u8 val)
1037{
1038 int err = 0;
1039
1040 switch (regaddr) {
1041 case TOD_MASK_ADDR:
1042 if ((val & 0xf0) || !(val & 0x0f)) {
1043 dev_err(&idtcm->client->dev,
1044 "Invalid TOD mask 0x%hhx\n", val);
1045 err = -EINVAL;
1046 } else {
1047 idtcm->tod_mask = val;
1048 }
1049 break;
1050 case TOD0_PTP_PLL_ADDR:
1051 err = set_tod_ptp_pll(idtcm, 0, val);
1052 break;
1053 case TOD1_PTP_PLL_ADDR:
1054 err = set_tod_ptp_pll(idtcm, 1, val);
1055 break;
1056 case TOD2_PTP_PLL_ADDR:
1057 err = set_tod_ptp_pll(idtcm, 2, val);
1058 break;
1059 case TOD3_PTP_PLL_ADDR:
1060 err = set_tod_ptp_pll(idtcm, 3, val);
1061 break;
1062 default:
1063 err = set_pll_output_mask(idtcm, regaddr, val);
1064 break;
1065 }
1066
1067 return err;
1068}
1069
1070static void display_pll_and_masks(struct idtcm *idtcm)
1071{
1072 u8 i;
1073 u8 mask;
1074
1075 dev_dbg(&idtcm->client->dev, "tod_mask = 0x%02x\n", idtcm->tod_mask);
1076
1077 for (i = 0; i < MAX_TOD; i++) {
1078 mask = 1 << i;
1079
1080 if (mask & idtcm->tod_mask)
1081 dev_dbg(&idtcm->client->dev,
1082 "TOD%d pll = %d output_mask = 0x%04x\n",
1083 i, idtcm->channel[i].pll,
1084 idtcm->channel[i].output_mask);
1085 }
1086}
1087
1088static int idtcm_load_firmware(struct idtcm *idtcm,
1089 struct device *dev)
1090{
1091 char fname[128] = FW_FILENAME;
1092 const struct firmware *fw;
1093 struct idtcm_fwrc *rec;
1094 u32 regaddr;
1095 int err;
1096 s32 len;
1097 u8 val;
1098 u8 loaddr;
1099
1100 if (firmware) /* module parameter */
1101 snprintf(fname, sizeof(fname), "%s", firmware);
1102
1103 dev_dbg(&idtcm->client->dev, "requesting firmware '%s'\n", fname);
1104
1105 err = request_firmware(&fw, fname, dev);
1106
1107 if (err) {
1108 dev_err(&idtcm->client->dev,
1109 "Failed at line %d in func %s!\n",
1110 __LINE__,
1111 __func__);
1112 return err;
1113 }
1114
1115 dev_dbg(&idtcm->client->dev, "firmware size %zu bytes\n", fw->size);
1116
1117 rec = (struct idtcm_fwrc *) fw->data;
1118
1119 if (fw->size > 0)
1120 idtcm_state_machine_reset(idtcm);
1121
1122 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
1123
1124 if (rec->reserved) {
1125 dev_err(&idtcm->client->dev,
1126 "bad firmware, reserved field non-zero\n");
1127 err = -EINVAL;
1128 } else {
1129 regaddr = rec->hiaddr << 8;
1130 regaddr |= rec->loaddr;
1131
1132 val = rec->value;
1133 loaddr = rec->loaddr;
1134
1135 rec++;
1136
1137 err = check_and_set_masks(idtcm, regaddr, val);
1138 }
1139
1140 if (err != -EINVAL) {
1141 err = 0;
1142
1143 /* Top (status registers) and bottom are read-only */
1144 if ((regaddr < GPIO_USER_CONTROL)
1145 || (regaddr >= SCRATCH))
1146 continue;
1147
1148 /* Page size 128, last 4 bytes of page skipped */
1149 if (((loaddr > 0x7b) && (loaddr <= 0x7f))
1150 || loaddr > 0xfb)
1151 continue;
1152
1153 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1154 }
1155
1156 if (err)
1157 goto out;
1158 }
1159
1160 display_pll_and_masks(idtcm);
1161
1162out:
1163 release_firmware(fw);
1164 return err;
1165}
1166
1167static int idtcm_output_enable(struct idtcm_channel *channel,
1168 bool enable, unsigned int outn)
1169{
1170 struct idtcm *idtcm = channel->idtcm;
1171 int err;
1172 u8 val;
1173
1174 err = idtcm_read(idtcm, OUTPUT_MODULE_FROM_INDEX(outn),
1175 OUT_CTRL_1, &val, sizeof(val));
1176
1177 if (err)
1178 return err;
1179
1180 if (enable)
1181 val |= SQUELCH_DISABLE;
1182 else
1183 val &= ~SQUELCH_DISABLE;
1184
1185 return idtcm_write(idtcm, OUTPUT_MODULE_FROM_INDEX(outn),
1186 OUT_CTRL_1, &val, sizeof(val));
1187}
1188
1189static int idtcm_output_mask_enable(struct idtcm_channel *channel,
1190 bool enable)
1191{
1192 u16 mask;
1193 int err;
1194 u8 outn;
1195
1196 mask = channel->output_mask;
1197 outn = 0;
1198
1199 while (mask) {
1200
1201 if (mask & 0x1) {
1202
1203 err = idtcm_output_enable(channel, enable, outn);
1204
1205 if (err)
1206 return err;
1207 }
1208
1209 mask >>= 0x1;
1210 outn++;
1211 }
1212
1213 return 0;
1214}
1215
1216static int idtcm_perout_enable(struct idtcm_channel *channel,
1217 bool enable,
1218 struct ptp_perout_request *perout)
1219{
1220 unsigned int flags = perout->flags;
1221
1222 if (flags == PEROUT_ENABLE_OUTPUT_MASK)
1223 return idtcm_output_mask_enable(channel, enable);
1224
1225 /* Enable/disable individual output instead */
1226 return idtcm_output_enable(channel, enable, perout->index);
1227}
1228
1229static int idtcm_set_pll_mode(struct idtcm_channel *channel,
1230 enum pll_mode pll_mode)
1231{
1232 struct idtcm *idtcm = channel->idtcm;
1233 int err;
1234 u8 dpll_mode;
1235
1236 err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1237 &dpll_mode, sizeof(dpll_mode));
1238 if (err)
1239 return err;
1240
1241 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
1242
1243 dpll_mode |= (pll_mode << PLL_MODE_SHIFT);
1244
1245 channel->pll_mode = pll_mode;
1246
1247 err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE,
1248 &dpll_mode, sizeof(dpll_mode));
1249 if (err)
1250 return err;
1251
1252 return 0;
1253}
1254
1255/* PTP Hardware Clock interface */
1256
1257/**
1258 * @brief Maximum absolute value for write phase offset in picoseconds
1259 *
1260 * Destination signed register is 32-bit register in resolution of 50ps
1261 *
1262 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
1263 */
1264static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1265{
1266 struct idtcm *idtcm = channel->idtcm;
1267
1268 int err;
1269 u8 i;
1270 u8 buf[4] = {0};
1271 s32 phase_50ps;
1272 s64 offset_ps;
1273
1274 if (channel->pll_mode != PLL_MODE_WRITE_PHASE) {
1275
1276 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1277
1278 if (err)
1279 return err;
1280
1281 channel->write_phase_ready = 0;
1282
1283 ptp_schedule_worker(channel->ptp_clock,
1284 msecs_to_jiffies(WR_PHASE_SETUP_MS));
1285 }
1286
1287 if (!channel->write_phase_ready)
1288 delta_ns = 0;
1289
1290 offset_ps = (s64)delta_ns * 1000;
1291
1292 /*
1293 * Check for 32-bit signed max * 50:
1294 *
1295 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
1296 */
1297 if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
1298 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
1299 else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
1300 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
1301
1302 phase_50ps = DIV_ROUND_CLOSEST(div64_s64(offset_ps, 50), 1);
1303
1304 for (i = 0; i < 4; i++) {
1305 buf[i] = phase_50ps & 0xff;
1306 phase_50ps >>= 8;
1307 }
1308
1309 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1310 buf, sizeof(buf));
1311
1312 return err;
1313}
1314
1315static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
1316{
1317 struct idtcm *idtcm = channel->idtcm;
1318 u8 i;
1319 bool neg_adj = 0;
1320 int err;
1321 u8 buf[6] = {0};
1322 s64 fcw;
1323
1324 if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) {
1325 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1326 if (err)
1327 return err;
1328 }
1329
1330 /*
1331 * Frequency Control Word unit is: 1.11 * 10^-10 ppm
1332 *
1333 * adjfreq:
1334 * ppb * 10^9
1335 * FCW = ----------
1336 * 111
1337 *
1338 * adjfine:
1339 * ppm_16 * 5^12
1340 * FCW = -------------
1341 * 111 * 2^4
1342 */
1343 if (scaled_ppm < 0) {
1344 neg_adj = 1;
1345 scaled_ppm = -scaled_ppm;
1346 }
1347
1348 /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */
1349 fcw = scaled_ppm * 244140625ULL;
1350
1351 fcw = div_u64(fcw, 1776);
1352
1353 if (neg_adj)
1354 fcw = -fcw;
1355
1356 for (i = 0; i < 6; i++) {
1357 buf[i] = fcw & 0xff;
1358 fcw >>= 8;
1359 }
1360
1361 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1362 buf, sizeof(buf));
1363
1364 return err;
1365}
1366
1367static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
1368{
1369 struct idtcm_channel *channel =
1370 container_of(ptp, struct idtcm_channel, caps);
1371 struct idtcm *idtcm = channel->idtcm;
1372 int err;
1373
1374 mutex_lock(&idtcm->reg_lock);
1375
1376 err = _idtcm_gettime(channel, ts);
1377
1378 if (err)
1379 dev_err(&idtcm->client->dev,
1380 "Failed at line %d in func %s!\n",
1381 __LINE__,
1382 __func__);
1383
1384 mutex_unlock(&idtcm->reg_lock);
1385
1386 return err;
1387}
1388
1389static int idtcm_settime(struct ptp_clock_info *ptp,
1390 const struct timespec64 *ts)
1391{
1392 struct idtcm_channel *channel =
1393 container_of(ptp, struct idtcm_channel, caps);
1394 struct idtcm *idtcm = channel->idtcm;
1395 int err;
1396
1397 mutex_lock(&idtcm->reg_lock);
1398
1399 err = _idtcm_settime(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
1400
1401 if (err)
1402 dev_err(&idtcm->client->dev,
1403 "Failed at line %d in func %s!\n",
1404 __LINE__,
1405 __func__);
1406
1407 mutex_unlock(&idtcm->reg_lock);
1408
1409 return err;
1410}
1411
1412static int idtcm_settime_v487(struct ptp_clock_info *ptp,
1413 const struct timespec64 *ts)
1414{
1415 struct idtcm_channel *channel =
1416 container_of(ptp, struct idtcm_channel, caps);
1417 struct idtcm *idtcm = channel->idtcm;
1418 int err;
1419
1420 mutex_lock(&idtcm->reg_lock);
1421
1422 err = _idtcm_settime_v487(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1423
1424 if (err)
1425 dev_err(&idtcm->client->dev,
1426 "Failed at line %d in func %s!\n",
1427 __LINE__,
1428 __func__);
1429
1430 mutex_unlock(&idtcm->reg_lock);
1431
1432 return err;
1433}
1434
1435static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
1436{
1437 struct idtcm_channel *channel =
1438 container_of(ptp, struct idtcm_channel, caps);
1439 struct idtcm *idtcm = channel->idtcm;
1440 int err;
1441
1442 mutex_lock(&idtcm->reg_lock);
1443
1444 err = _idtcm_adjtime(channel, delta);
1445
1446 if (err)
1447 dev_err(&idtcm->client->dev,
1448 "Failed at line %d in func %s!\n",
1449 __LINE__,
1450 __func__);
1451
1452 mutex_unlock(&idtcm->reg_lock);
1453
1454 return err;
1455}
1456
1457static int idtcm_adjtime_v487(struct ptp_clock_info *ptp, s64 delta)
1458{
1459 struct idtcm_channel *channel =
1460 container_of(ptp, struct idtcm_channel, caps);
1461 struct idtcm *idtcm = channel->idtcm;
1462 struct timespec64 ts;
1463 enum scsr_tod_write_type_sel type;
1464 int err;
1465
1466 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_V487) {
1467 err = idtcm_do_phase_pull_in(channel, delta, 0);
1468 if (err)
1469 dev_err(&idtcm->client->dev,
1470 "Failed at line %d in func %s!\n",
1471 __LINE__,
1472 __func__);
1473 return err;
1474 }
1475
1476 if (delta >= 0) {
1477 ts = ns_to_timespec64(delta);
1478 type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
1479 } else {
1480 ts = ns_to_timespec64(-delta);
1481 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
1482 }
1483
1484 mutex_lock(&idtcm->reg_lock);
1485
1486 err = _idtcm_settime_v487(channel, &ts, type);
1487
1488 if (err)
1489 dev_err(&idtcm->client->dev,
1490 "Failed at line %d in func %s!\n",
1491 __LINE__,
1492 __func__);
1493
1494 mutex_unlock(&idtcm->reg_lock);
1495
1496 return err;
1497}
1498
1499static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta)
1500{
1501 struct idtcm_channel *channel =
1502 container_of(ptp, struct idtcm_channel, caps);
1503
1504 struct idtcm *idtcm = channel->idtcm;
1505
1506 int err;
1507
1508 mutex_lock(&idtcm->reg_lock);
1509
1510 err = _idtcm_adjphase(channel, delta);
1511
1512 if (err)
1513 dev_err(&idtcm->client->dev,
1514 "Failed at line %d in func %s!\n",
1515 __LINE__,
1516 __func__);
1517
1518 mutex_unlock(&idtcm->reg_lock);
1519
1520 return err;
1521}
1522
1523static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
1524{
1525 struct idtcm_channel *channel =
1526 container_of(ptp, struct idtcm_channel, caps);
1527
1528 struct idtcm *idtcm = channel->idtcm;
1529
1530 int err;
1531
1532 mutex_lock(&idtcm->reg_lock);
1533
1534 err = _idtcm_adjfine(channel, scaled_ppm);
1535
1536 if (err)
1537 dev_err(&idtcm->client->dev,
1538 "Failed at line %d in func %s!\n",
1539 __LINE__,
1540 __func__);
1541
1542 mutex_unlock(&idtcm->reg_lock);
1543
1544 return err;
1545}
1546
1547static int idtcm_enable(struct ptp_clock_info *ptp,
1548 struct ptp_clock_request *rq, int on)
1549{
1550 int err;
1551
1552 struct idtcm_channel *channel =
1553 container_of(ptp, struct idtcm_channel, caps);
1554
1555 switch (rq->type) {
1556 case PTP_CLK_REQ_PEROUT:
1557 if (!on) {
1558 err = idtcm_perout_enable(channel, false, &rq->perout);
1559 if (err)
1560 dev_err(&channel->idtcm->client->dev,
1561 "Failed at line %d in func %s!\n",
1562 __LINE__,
1563 __func__);
1564 return err;
1565 }
1566
1567 /* Only accept a 1-PPS aligned to the second. */
1568 if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
1569 rq->perout.period.nsec)
1570 return -ERANGE;
1571
1572 err = idtcm_perout_enable(channel, true, &rq->perout);
1573 if (err)
1574 dev_err(&channel->idtcm->client->dev,
1575 "Failed at line %d in func %s!\n",
1576 __LINE__,
1577 __func__);
1578 return err;
1579 default:
1580 break;
1581 }
1582
1583 return -EOPNOTSUPP;
1584}
1585
1586static int _enable_pll_tod_sync(struct idtcm *idtcm,
1587 u8 pll,
1588 u8 sync_src,
1589 u8 qn,
1590 u8 qn_plus_1)
1591{
1592 int err;
1593 u8 val;
1594 u16 dpll;
1595 u16 out0 = 0, out1 = 0;
1596
1597 if ((qn == 0) && (qn_plus_1 == 0))
1598 return 0;
1599
1600 switch (pll) {
1601 case 0:
1602 dpll = DPLL_0;
1603 if (qn)
1604 out0 = OUTPUT_0;
1605 if (qn_plus_1)
1606 out1 = OUTPUT_1;
1607 break;
1608 case 1:
1609 dpll = DPLL_1;
1610 if (qn)
1611 out0 = OUTPUT_2;
1612 if (qn_plus_1)
1613 out1 = OUTPUT_3;
1614 break;
1615 case 2:
1616 dpll = DPLL_2;
1617 if (qn)
1618 out0 = OUTPUT_4;
1619 if (qn_plus_1)
1620 out1 = OUTPUT_5;
1621 break;
1622 case 3:
1623 dpll = DPLL_3;
1624 if (qn)
1625 out0 = OUTPUT_6;
1626 if (qn_plus_1)
1627 out1 = OUTPUT_7;
1628 break;
1629 case 4:
1630 dpll = DPLL_4;
1631 if (qn)
1632 out0 = OUTPUT_8;
1633 break;
1634 case 5:
1635 dpll = DPLL_5;
1636 if (qn)
1637 out0 = OUTPUT_9;
1638 if (qn_plus_1)
1639 out1 = OUTPUT_8;
1640 break;
1641 case 6:
1642 dpll = DPLL_6;
1643 if (qn)
1644 out0 = OUTPUT_10;
1645 if (qn_plus_1)
1646 out1 = OUTPUT_11;
1647 break;
1648 case 7:
1649 dpll = DPLL_7;
1650 if (qn)
1651 out0 = OUTPUT_11;
1652 break;
1653 default:
1654 return -EINVAL;
1655 }
1656
1657 /*
1658 * Enable OUTPUT OUT_SYNC.
1659 */
1660 if (out0) {
1661 err = idtcm_read(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1662
1663 if (err)
1664 return err;
1665
1666 val &= ~OUT_SYNC_DISABLE;
1667
1668 err = idtcm_write(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1669
1670 if (err)
1671 return err;
1672 }
1673
1674 if (out1) {
1675 err = idtcm_read(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1676
1677 if (err)
1678 return err;
1679
1680 val &= ~OUT_SYNC_DISABLE;
1681
1682 err = idtcm_write(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1683
1684 if (err)
1685 return err;
1686 }
1687
1688 /* enable dpll sync tod pps, must be set before dpll_mode */
1689 err = idtcm_read(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1690 if (err)
1691 return err;
1692
1693 val &= ~(TOD_SYNC_SOURCE_MASK << TOD_SYNC_SOURCE_SHIFT);
1694 val |= (sync_src << TOD_SYNC_SOURCE_SHIFT);
1695 val |= TOD_SYNC_EN;
1696
1697 return idtcm_write(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1698}
1699
1700static int idtcm_enable_tod_sync(struct idtcm_channel *channel)
1701{
1702 struct idtcm *idtcm = channel->idtcm;
1703
1704 u8 pll;
1705 u8 sync_src;
1706 u8 qn;
1707 u8 qn_plus_1;
1708 u8 cfg;
1709 int err = 0;
1710 u16 output_mask = channel->output_mask;
1711 u8 out8_mux = 0;
1712 u8 out11_mux = 0;
1713 u8 temp;
1714
1715 /*
1716 * set tod_out_sync_enable to 0.
1717 */
1718 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1719 if (err)
1720 return err;
1721
1722 cfg &= ~TOD_OUT_SYNC_ENABLE;
1723
1724 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1725 if (err)
1726 return err;
1727
1728 switch (channel->tod_n) {
1729 case TOD_0:
1730 sync_src = 0;
1731 break;
1732 case TOD_1:
1733 sync_src = 1;
1734 break;
1735 case TOD_2:
1736 sync_src = 2;
1737 break;
1738 case TOD_3:
1739 sync_src = 3;
1740 break;
1741 default:
1742 return -EINVAL;
1743 }
1744
1745 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
1746 &temp, sizeof(temp));
1747 if (err)
1748 return err;
1749
1750 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1751 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1752 out8_mux = 1;
1753
1754 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
1755 &temp, sizeof(temp));
1756 if (err)
1757 return err;
1758
1759 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1760 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1761 out11_mux = 1;
1762
1763 for (pll = 0; pll < 8; pll++) {
1764 qn = 0;
1765 qn_plus_1 = 0;
1766
1767 if (pll < 4) {
1768 /* First 4 pll has 2 outputs */
1769 qn = output_mask & 0x1;
1770 output_mask = output_mask >> 1;
1771 qn_plus_1 = output_mask & 0x1;
1772 output_mask = output_mask >> 1;
1773 } else if (pll == 4) {
1774 if (out8_mux == 0) {
1775 qn = output_mask & 0x1;
1776 output_mask = output_mask >> 1;
1777 }
1778 } else if (pll == 5) {
1779 if (out8_mux) {
1780 qn_plus_1 = output_mask & 0x1;
1781 output_mask = output_mask >> 1;
1782 }
1783 qn = output_mask & 0x1;
1784 output_mask = output_mask >> 1;
1785 } else if (pll == 6) {
1786 qn = output_mask & 0x1;
1787 output_mask = output_mask >> 1;
1788 if (out11_mux) {
1789 qn_plus_1 = output_mask & 0x1;
1790 output_mask = output_mask >> 1;
1791 }
1792 } else if (pll == 7) {
1793 if (out11_mux == 0) {
1794 qn = output_mask & 0x1;
1795 output_mask = output_mask >> 1;
1796 }
1797 }
1798
1799 if ((qn != 0) || (qn_plus_1 != 0))
1800 err = _enable_pll_tod_sync(idtcm, pll, sync_src, qn,
1801 qn_plus_1);
1802
1803 if (err)
1804 return err;
1805 }
1806
1807 return err;
1808}
1809
1810static int idtcm_enable_tod(struct idtcm_channel *channel)
1811{
1812 struct idtcm *idtcm = channel->idtcm;
1813 struct timespec64 ts = {0, 0};
1814 u8 cfg;
1815 int err;
1816
1817 /*
1818 * Start the TOD clock ticking.
1819 */
1820 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1821 if (err)
1822 return err;
1823
1824 cfg |= TOD_ENABLE;
1825
1826 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1827 if (err)
1828 return err;
1829
1830 return _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
1831}
1832
1833static void idtcm_display_version_info(struct idtcm *idtcm)
1834{
1835 u8 major;
1836 u8 minor;
1837 u8 hotfix;
1838 u16 product_id;
1839 u8 hw_rev_id;
1840 u8 config_select;
1841 char *fmt = "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d\n";
1842
1843 idtcm_read_major_release(idtcm, &major);
1844 idtcm_read_minor_release(idtcm, &minor);
1845 idtcm_read_hotfix_release(idtcm, &hotfix);
1846
1847 idtcm_read_product_id(idtcm, &product_id);
1848 idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
1849
1850 idtcm_read_otp_scsr_config_select(idtcm, &config_select);
1851
1852 snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
1853 major, minor, hotfix);
1854
1855 dev_info(&idtcm->client->dev, fmt, major, minor, hotfix,
1856 product_id, hw_rev_id, config_select);
1857}
1858
1859static const struct ptp_clock_info idtcm_caps_v487 = {
1860 .owner = THIS_MODULE,
1861 .max_adj = 244000,
1862 .n_per_out = 12,
1863 .adjphase = &idtcm_adjphase,
1864 .adjfine = &idtcm_adjfine,
1865 .adjtime = &idtcm_adjtime_v487,
1866 .gettime64 = &idtcm_gettime,
1867 .settime64 = &idtcm_settime_v487,
1868 .enable = &idtcm_enable,
1869 .do_aux_work = &set_write_phase_ready,
1870};
1871
1872static const struct ptp_clock_info idtcm_caps = {
1873 .owner = THIS_MODULE,
1874 .max_adj = 244000,
1875 .n_per_out = 12,
1876 .adjphase = &idtcm_adjphase,
1877 .adjfine = &idtcm_adjfine,
1878 .adjtime = &idtcm_adjtime,
1879 .gettime64 = &idtcm_gettime,
1880 .settime64 = &idtcm_settime,
1881 .enable = &idtcm_enable,
1882 .do_aux_work = &set_write_phase_ready,
1883};
1884
1885static int configure_channel_pll(struct idtcm_channel *channel)
1886{
1887 int err = 0;
1888
1889 switch (channel->pll) {
1890 case 0:
1891 channel->dpll_freq = DPLL_FREQ_0;
1892 channel->dpll_n = DPLL_0;
1893 channel->hw_dpll_n = HW_DPLL_0;
1894 channel->dpll_phase = DPLL_PHASE_0;
1895 channel->dpll_ctrl_n = DPLL_CTRL_0;
1896 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
1897 break;
1898 case 1:
1899 channel->dpll_freq = DPLL_FREQ_1;
1900 channel->dpll_n = DPLL_1;
1901 channel->hw_dpll_n = HW_DPLL_1;
1902 channel->dpll_phase = DPLL_PHASE_1;
1903 channel->dpll_ctrl_n = DPLL_CTRL_1;
1904 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
1905 break;
1906 case 2:
1907 channel->dpll_freq = DPLL_FREQ_2;
1908 channel->dpll_n = DPLL_2;
1909 channel->hw_dpll_n = HW_DPLL_2;
1910 channel->dpll_phase = DPLL_PHASE_2;
1911 channel->dpll_ctrl_n = DPLL_CTRL_2;
1912 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
1913 break;
1914 case 3:
1915 channel->dpll_freq = DPLL_FREQ_3;
1916 channel->dpll_n = DPLL_3;
1917 channel->hw_dpll_n = HW_DPLL_3;
1918 channel->dpll_phase = DPLL_PHASE_3;
1919 channel->dpll_ctrl_n = DPLL_CTRL_3;
1920 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
1921 break;
1922 case 4:
1923 channel->dpll_freq = DPLL_FREQ_4;
1924 channel->dpll_n = DPLL_4;
1925 channel->hw_dpll_n = HW_DPLL_4;
1926 channel->dpll_phase = DPLL_PHASE_4;
1927 channel->dpll_ctrl_n = DPLL_CTRL_4;
1928 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
1929 break;
1930 case 5:
1931 channel->dpll_freq = DPLL_FREQ_5;
1932 channel->dpll_n = DPLL_5;
1933 channel->hw_dpll_n = HW_DPLL_5;
1934 channel->dpll_phase = DPLL_PHASE_5;
1935 channel->dpll_ctrl_n = DPLL_CTRL_5;
1936 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
1937 break;
1938 case 6:
1939 channel->dpll_freq = DPLL_FREQ_6;
1940 channel->dpll_n = DPLL_6;
1941 channel->hw_dpll_n = HW_DPLL_6;
1942 channel->dpll_phase = DPLL_PHASE_6;
1943 channel->dpll_ctrl_n = DPLL_CTRL_6;
1944 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
1945 break;
1946 case 7:
1947 channel->dpll_freq = DPLL_FREQ_7;
1948 channel->dpll_n = DPLL_7;
1949 channel->hw_dpll_n = HW_DPLL_7;
1950 channel->dpll_phase = DPLL_PHASE_7;
1951 channel->dpll_ctrl_n = DPLL_CTRL_7;
1952 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
1953 break;
1954 default:
1955 err = -EINVAL;
1956 }
1957
1958 return err;
1959}
1960
1961static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
1962{
1963 struct idtcm_channel *channel;
1964 int err;
1965
1966 if (!(index < MAX_TOD))
1967 return -EINVAL;
1968
1969 channel = &idtcm->channel[index];
1970
1971 /* Set pll addresses */
1972 err = configure_channel_pll(channel);
1973 if (err)
1974 return err;
1975
1976 /* Set tod addresses */
1977 switch (index) {
1978 case 0:
1979 channel->tod_read_primary = TOD_READ_PRIMARY_0;
1980 channel->tod_write = TOD_WRITE_0;
1981 channel->tod_n = TOD_0;
1982 break;
1983 case 1:
1984 channel->tod_read_primary = TOD_READ_PRIMARY_1;
1985 channel->tod_write = TOD_WRITE_1;
1986 channel->tod_n = TOD_1;
1987 break;
1988 case 2:
1989 channel->tod_read_primary = TOD_READ_PRIMARY_2;
1990 channel->tod_write = TOD_WRITE_2;
1991 channel->tod_n = TOD_2;
1992 break;
1993 case 3:
1994 channel->tod_read_primary = TOD_READ_PRIMARY_3;
1995 channel->tod_write = TOD_WRITE_3;
1996 channel->tod_n = TOD_3;
1997 break;
1998 default:
1999 return -EINVAL;
2000 }
2001
2002 channel->idtcm = idtcm;
2003
2004 if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0)
2005 channel->caps = idtcm_caps_v487;
2006 else
2007 channel->caps = idtcm_caps;
2008
2009 snprintf(channel->caps.name, sizeof(channel->caps.name),
2010 "IDT CM TOD%u", index);
2011
2012 if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0) {
2013 err = idtcm_enable_tod_sync(channel);
2014 if (err) {
2015 dev_err(&idtcm->client->dev,
2016 "Failed at line %d in func %s!\n",
2017 __LINE__,
2018 __func__);
2019 return err;
2020 }
2021 }
2022
2023 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
2024 if (err) {
2025 dev_err(&idtcm->client->dev,
2026 "Failed at line %d in func %s!\n",
2027 __LINE__,
2028 __func__);
2029 return err;
2030 }
2031
2032 err = idtcm_enable_tod(channel);
2033 if (err) {
2034 dev_err(&idtcm->client->dev,
2035 "Failed at line %d in func %s!\n",
2036 __LINE__,
2037 __func__);
2038 return err;
2039 }
2040
2041 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2042
2043 if (IS_ERR(channel->ptp_clock)) {
2044 err = PTR_ERR(channel->ptp_clock);
2045 channel->ptp_clock = NULL;
2046 return err;
2047 }
2048
2049 if (!channel->ptp_clock)
2050 return -ENOTSUPP;
2051
2052 channel->write_phase_ready = 0;
2053
2054 dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d\n",
2055 index, channel->ptp_clock->index);
2056
2057 return 0;
2058}
2059
2060static void ptp_clock_unregister_all(struct idtcm *idtcm)
2061{
2062 u8 i;
2063 struct idtcm_channel *channel;
2064
2065 for (i = 0; i < MAX_TOD; i++) {
2066
2067 channel = &idtcm->channel[i];
2068
2069 if (channel->ptp_clock)
2070 ptp_clock_unregister(channel->ptp_clock);
2071 }
2072}
2073
2074static void set_default_masks(struct idtcm *idtcm)
2075{
2076 idtcm->tod_mask = DEFAULT_TOD_MASK;
2077
2078 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2079 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2080 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2081 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
2082
2083 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2084 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2085 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2086 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2087}
2088
2089static int idtcm_probe(struct i2c_client *client,
2090 const struct i2c_device_id *id)
2091{
2092 struct idtcm *idtcm;
2093 int err;
2094 u8 i;
2095 char *fmt = "Failed at %d in line %s with channel output %d!\n";
2096
2097 /* Unused for now */
2098 (void)id;
2099
2100 idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL);
2101
2102 if (!idtcm)
2103 return -ENOMEM;
2104
2105 idtcm->client = client;
2106 idtcm->page_offset = 0xff;
2107 idtcm->calculate_overhead_flag = 0;
2108
2109 set_default_masks(idtcm);
2110
2111 mutex_init(&idtcm->reg_lock);
2112 mutex_lock(&idtcm->reg_lock);
2113
2114 idtcm_display_version_info(idtcm);
2115
2116 err = idtcm_load_firmware(idtcm, &client->dev);
2117
2118 if (err)
2119 dev_warn(&idtcm->client->dev,
2120 "loading firmware failed with %d\n", err);
2121
2122 if (idtcm->tod_mask) {
2123 for (i = 0; i < MAX_TOD; i++) {
2124 if (idtcm->tod_mask & (1 << i)) {
2125 err = idtcm_enable_channel(idtcm, i);
2126 if (err) {
2127 dev_err(&idtcm->client->dev,
2128 fmt,
2129 __LINE__,
2130 __func__,
2131 i);
2132 break;
2133 }
2134 }
2135 }
2136 } else {
2137 dev_err(&idtcm->client->dev,
2138 "no PLLs flagged as PHCs, nothing to do\n");
2139 err = -ENODEV;
2140 }
2141
2142 mutex_unlock(&idtcm->reg_lock);
2143
2144 if (err) {
2145 ptp_clock_unregister_all(idtcm);
2146 return err;
2147 }
2148
2149 i2c_set_clientdata(client, idtcm);
2150
2151 return 0;
2152}
2153
2154static int idtcm_remove(struct i2c_client *client)
2155{
2156 struct idtcm *idtcm = i2c_get_clientdata(client);
2157
2158 ptp_clock_unregister_all(idtcm);
2159
2160 mutex_destroy(&idtcm->reg_lock);
2161
2162 return 0;
2163}
2164
2165#ifdef CONFIG_OF
2166static const struct of_device_id idtcm_dt_id[] = {
2167 { .compatible = "idt,8a34000" },
2168 { .compatible = "idt,8a34001" },
2169 { .compatible = "idt,8a34002" },
2170 { .compatible = "idt,8a34003" },
2171 { .compatible = "idt,8a34004" },
2172 { .compatible = "idt,8a34005" },
2173 { .compatible = "idt,8a34006" },
2174 { .compatible = "idt,8a34007" },
2175 { .compatible = "idt,8a34008" },
2176 { .compatible = "idt,8a34009" },
2177 { .compatible = "idt,8a34010" },
2178 { .compatible = "idt,8a34011" },
2179 { .compatible = "idt,8a34012" },
2180 { .compatible = "idt,8a34013" },
2181 { .compatible = "idt,8a34014" },
2182 { .compatible = "idt,8a34015" },
2183 { .compatible = "idt,8a34016" },
2184 { .compatible = "idt,8a34017" },
2185 { .compatible = "idt,8a34018" },
2186 { .compatible = "idt,8a34019" },
2187 { .compatible = "idt,8a34040" },
2188 { .compatible = "idt,8a34041" },
2189 { .compatible = "idt,8a34042" },
2190 { .compatible = "idt,8a34043" },
2191 { .compatible = "idt,8a34044" },
2192 { .compatible = "idt,8a34045" },
2193 { .compatible = "idt,8a34046" },
2194 { .compatible = "idt,8a34047" },
2195 { .compatible = "idt,8a34048" },
2196 { .compatible = "idt,8a34049" },
2197 {},
2198};
2199MODULE_DEVICE_TABLE(of, idtcm_dt_id);
2200#endif
2201
2202static const struct i2c_device_id idtcm_i2c_id[] = {
2203 { "8a34000" },
2204 { "8a34001" },
2205 { "8a34002" },
2206 { "8a34003" },
2207 { "8a34004" },
2208 { "8a34005" },
2209 { "8a34006" },
2210 { "8a34007" },
2211 { "8a34008" },
2212 { "8a34009" },
2213 { "8a34010" },
2214 { "8a34011" },
2215 { "8a34012" },
2216 { "8a34013" },
2217 { "8a34014" },
2218 { "8a34015" },
2219 { "8a34016" },
2220 { "8a34017" },
2221 { "8a34018" },
2222 { "8a34019" },
2223 { "8a34040" },
2224 { "8a34041" },
2225 { "8a34042" },
2226 { "8a34043" },
2227 { "8a34044" },
2228 { "8a34045" },
2229 { "8a34046" },
2230 { "8a34047" },
2231 { "8a34048" },
2232 { "8a34049" },
2233 {},
2234};
2235MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id);
2236
2237static struct i2c_driver idtcm_driver = {
2238 .driver = {
2239 .of_match_table = of_match_ptr(idtcm_dt_id),
2240 .name = "idtcm",
2241 },
2242 .probe = idtcm_probe,
2243 .remove = idtcm_remove,
2244 .id_table = idtcm_i2c_id,
2245};
2246
2247module_i2c_driver(idtcm_driver);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
4 * synchronization devices.
5 *
6 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
7 */
8#include <linux/firmware.h>
9#include <linux/platform_device.h>
10#include <linux/module.h>
11#include <linux/ptp_clock_kernel.h>
12#include <linux/delay.h>
13#include <linux/jiffies.h>
14#include <linux/kernel.h>
15#include <linux/timekeeping.h>
16#include <linux/string.h>
17#include <linux/of.h>
18#include <linux/mfd/rsmu.h>
19#include <linux/mfd/idt8a340_reg.h>
20#include <asm/unaligned.h>
21
22#include "ptp_private.h"
23#include "ptp_clockmatrix.h"
24
25MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
26MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
27MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
28MODULE_VERSION("1.0");
29MODULE_LICENSE("GPL");
30
31/*
32 * The name of the firmware file to be loaded
33 * over-rides any automatic selection
34 */
35static char *firmware;
36module_param(firmware, charp, 0);
37
38#define SETTIME_CORRECTION (0)
39#define EXTTS_PERIOD_MS (95)
40
41static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm);
42
43static inline int idtcm_read(struct idtcm *idtcm,
44 u16 module,
45 u16 regaddr,
46 u8 *buf,
47 u16 count)
48{
49 return regmap_bulk_read(idtcm->regmap, module + regaddr, buf, count);
50}
51
52static inline int idtcm_write(struct idtcm *idtcm,
53 u16 module,
54 u16 regaddr,
55 u8 *buf,
56 u16 count)
57{
58 return regmap_bulk_write(idtcm->regmap, module + regaddr, buf, count);
59}
60
61static int contains_full_configuration(struct idtcm *idtcm,
62 const struct firmware *fw)
63{
64 struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data;
65 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);
66 s32 full_count;
67 s32 count = 0;
68 u16 regaddr;
69 u8 loaddr;
70 s32 len;
71
72 /* 4 bytes skipped every 0x80 */
73 full_count = (scratch - GPIO_USER_CONTROL) -
74 ((scratch >> 7) - (GPIO_USER_CONTROL >> 7)) * 4;
75
76 /* If the firmware contains 'full configuration' SM_RESET can be used
77 * to ensure proper configuration.
78 *
79 * Full configuration is defined as the number of programmable
80 * bytes within the configuration range minus page offset addr range.
81 */
82 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
83 regaddr = rec->hiaddr << 8;
84 regaddr |= rec->loaddr;
85
86 loaddr = rec->loaddr;
87
88 rec++;
89
90 /* Top (status registers) and bottom are read-only */
91 if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch)
92 continue;
93
94 /* Page size 128, last 4 bytes of page skipped */
95 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
96 continue;
97
98 count++;
99 }
100
101 return (count >= full_count);
102}
103
104static int char_array_to_timespec(u8 *buf,
105 u8 count,
106 struct timespec64 *ts)
107{
108 u8 i;
109 u64 nsec;
110 time64_t sec;
111
112 if (count < TOD_BYTE_COUNT)
113 return 1;
114
115 /* Sub-nanoseconds are in buf[0]. */
116 nsec = buf[4];
117 for (i = 0; i < 3; i++) {
118 nsec <<= 8;
119 nsec |= buf[3 - i];
120 }
121
122 sec = buf[10];
123 for (i = 0; i < 5; i++) {
124 sec <<= 8;
125 sec |= buf[9 - i];
126 }
127
128 ts->tv_sec = sec;
129 ts->tv_nsec = nsec;
130
131 return 0;
132}
133
134static int timespec_to_char_array(struct timespec64 const *ts,
135 u8 *buf,
136 u8 count)
137{
138 u8 i;
139 s32 nsec;
140 time64_t sec;
141
142 if (count < TOD_BYTE_COUNT)
143 return 1;
144
145 nsec = ts->tv_nsec;
146 sec = ts->tv_sec;
147
148 /* Sub-nanoseconds are in buf[0]. */
149 buf[0] = 0;
150 for (i = 1; i < 5; i++) {
151 buf[i] = nsec & 0xff;
152 nsec >>= 8;
153 }
154
155 for (i = 5; i < TOD_BYTE_COUNT; i++) {
156
157 buf[i] = sec & 0xff;
158 sec >>= 8;
159 }
160
161 return 0;
162}
163
164static int idtcm_strverscmp(const char *version1, const char *version2)
165{
166 u8 ver1[3], ver2[3];
167 int i;
168
169 if (sscanf(version1, "%hhu.%hhu.%hhu",
170 &ver1[0], &ver1[1], &ver1[2]) != 3)
171 return -1;
172 if (sscanf(version2, "%hhu.%hhu.%hhu",
173 &ver2[0], &ver2[1], &ver2[2]) != 3)
174 return -1;
175
176 for (i = 0; i < 3; i++) {
177 if (ver1[i] > ver2[i])
178 return 1;
179 if (ver1[i] < ver2[i])
180 return -1;
181 }
182
183 return 0;
184}
185
186static enum fw_version idtcm_fw_version(const char *version)
187{
188 enum fw_version ver = V_DEFAULT;
189
190 if (idtcm_strverscmp(version, "4.8.7") >= 0)
191 ver = V487;
192
193 if (idtcm_strverscmp(version, "5.2.0") >= 0)
194 ver = V520;
195
196 return ver;
197}
198
199static int clear_boot_status(struct idtcm *idtcm)
200{
201 u8 buf[4] = {0};
202
203 return idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
204}
205
206static int read_boot_status(struct idtcm *idtcm, u32 *status)
207{
208 int err;
209 u8 buf[4] = {0};
210
211 err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
212
213 *status = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
214
215 return err;
216}
217
218static int wait_for_boot_status_ready(struct idtcm *idtcm)
219{
220 u32 status = 0;
221 u8 i = 30; /* 30 * 100ms = 3s */
222 int err;
223
224 do {
225 err = read_boot_status(idtcm, &status);
226 if (err)
227 return err;
228
229 if (status == 0xA0)
230 return 0;
231
232 msleep(100);
233 i--;
234
235 } while (i);
236
237 dev_warn(idtcm->dev, "%s timed out", __func__);
238
239 return -EBUSY;
240}
241
242static int arm_tod_read_trig_sel_refclk(struct idtcm_channel *channel, u8 ref)
243{
244 struct idtcm *idtcm = channel->idtcm;
245 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
246 u8 val = 0;
247 int err;
248
249 val &= ~(WR_REF_INDEX_MASK << WR_REF_INDEX_SHIFT);
250 val |= (ref << WR_REF_INDEX_SHIFT);
251
252 err = idtcm_write(idtcm, channel->tod_read_secondary,
253 TOD_READ_SECONDARY_SEL_CFG_0, &val, sizeof(val));
254 if (err)
255 return err;
256
257 val = 0 | (SCSR_TOD_READ_TRIG_SEL_REFCLK << TOD_READ_TRIGGER_SHIFT);
258
259 err = idtcm_write(idtcm, channel->tod_read_secondary, tod_read_cmd,
260 &val, sizeof(val));
261 if (err)
262 dev_err(idtcm->dev, "%s: err = %d", __func__, err);
263
264 return err;
265}
266
267static bool is_single_shot(u8 mask)
268{
269 /* Treat single bit ToD masks as continuous trigger */
270 return !(mask <= 8 && is_power_of_2(mask));
271}
272
273static int idtcm_extts_enable(struct idtcm_channel *channel,
274 struct ptp_clock_request *rq, int on)
275{
276 u8 index = rq->extts.index;
277 struct idtcm *idtcm;
278 u8 mask = 1 << index;
279 int err = 0;
280 u8 old_mask;
281 int ref;
282
283 idtcm = channel->idtcm;
284 old_mask = idtcm->extts_mask;
285
286 /* Reject requests with unsupported flags */
287 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
288 PTP_RISING_EDGE |
289 PTP_FALLING_EDGE |
290 PTP_STRICT_FLAGS))
291 return -EOPNOTSUPP;
292
293 /* Reject requests to enable time stamping on falling edge */
294 if ((rq->extts.flags & PTP_ENABLE_FEATURE) &&
295 (rq->extts.flags & PTP_FALLING_EDGE))
296 return -EOPNOTSUPP;
297
298 if (index >= MAX_TOD)
299 return -EINVAL;
300
301 if (on) {
302 /* Support triggering more than one TOD_0/1/2/3 by same pin */
303 /* Use the pin configured for the channel */
304 ref = ptp_find_pin(channel->ptp_clock, PTP_PF_EXTTS, channel->tod);
305
306 if (ref < 0) {
307 dev_err(idtcm->dev, "%s: No valid pin found for TOD%d!\n",
308 __func__, channel->tod);
309 return -EBUSY;
310 }
311
312 err = arm_tod_read_trig_sel_refclk(&idtcm->channel[index], ref);
313
314 if (err == 0) {
315 idtcm->extts_mask |= mask;
316 idtcm->event_channel[index] = channel;
317 idtcm->channel[index].refn = ref;
318 idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
319
320 if (old_mask)
321 return 0;
322
323 schedule_delayed_work(&idtcm->extts_work,
324 msecs_to_jiffies(EXTTS_PERIOD_MS));
325 }
326 } else {
327 idtcm->extts_mask &= ~mask;
328 idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
329
330 if (idtcm->extts_mask == 0)
331 cancel_delayed_work(&idtcm->extts_work);
332 }
333
334 return err;
335}
336
337static int read_sys_apll_status(struct idtcm *idtcm, u8 *status)
338{
339 return idtcm_read(idtcm, STATUS, DPLL_SYS_APLL_STATUS, status,
340 sizeof(u8));
341}
342
343static int read_sys_dpll_status(struct idtcm *idtcm, u8 *status)
344{
345 return idtcm_read(idtcm, STATUS, DPLL_SYS_STATUS, status, sizeof(u8));
346}
347
348static int wait_for_sys_apll_dpll_lock(struct idtcm *idtcm)
349{
350 unsigned long timeout = jiffies + msecs_to_jiffies(LOCK_TIMEOUT_MS);
351 u8 apll = 0;
352 u8 dpll = 0;
353 int err;
354
355 do {
356 err = read_sys_apll_status(idtcm, &apll);
357 if (err)
358 return err;
359
360 err = read_sys_dpll_status(idtcm, &dpll);
361 if (err)
362 return err;
363
364 apll &= SYS_APLL_LOSS_LOCK_LIVE_MASK;
365 dpll &= DPLL_SYS_STATE_MASK;
366
367 if (apll == SYS_APLL_LOSS_LOCK_LIVE_LOCKED &&
368 dpll == DPLL_STATE_LOCKED) {
369 return 0;
370 } else if (dpll == DPLL_STATE_FREERUN ||
371 dpll == DPLL_STATE_HOLDOVER ||
372 dpll == DPLL_STATE_OPEN_LOOP) {
373 dev_warn(idtcm->dev,
374 "No wait state: DPLL_SYS_STATE %d", dpll);
375 return -EPERM;
376 }
377
378 msleep(LOCK_POLL_INTERVAL_MS);
379 } while (time_is_after_jiffies(timeout));
380
381 dev_warn(idtcm->dev,
382 "%d ms lock timeout: SYS APLL Loss Lock %d SYS DPLL state %d",
383 LOCK_TIMEOUT_MS, apll, dpll);
384
385 return -ETIME;
386}
387
388static void wait_for_chip_ready(struct idtcm *idtcm)
389{
390 if (wait_for_boot_status_ready(idtcm))
391 dev_warn(idtcm->dev, "BOOT_STATUS != 0xA0");
392
393 if (wait_for_sys_apll_dpll_lock(idtcm))
394 dev_warn(idtcm->dev,
395 "Continuing while SYS APLL/DPLL is not locked");
396}
397
398static int _idtcm_gettime_triggered(struct idtcm_channel *channel,
399 struct timespec64 *ts)
400{
401 struct idtcm *idtcm = channel->idtcm;
402 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
403 u8 buf[TOD_BYTE_COUNT];
404 u8 trigger;
405 int err;
406
407 err = idtcm_read(idtcm, channel->tod_read_secondary,
408 tod_read_cmd, &trigger, sizeof(trigger));
409 if (err)
410 return err;
411
412 if (trigger & TOD_READ_TRIGGER_MASK)
413 return -EBUSY;
414
415 err = idtcm_read(idtcm, channel->tod_read_secondary,
416 TOD_READ_SECONDARY_BASE, buf, sizeof(buf));
417 if (err)
418 return err;
419
420 return char_array_to_timespec(buf, sizeof(buf), ts);
421}
422
423static int _idtcm_gettime(struct idtcm_channel *channel,
424 struct timespec64 *ts, u8 timeout)
425{
426 struct idtcm *idtcm = channel->idtcm;
427 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
428 u8 buf[TOD_BYTE_COUNT];
429 u8 trigger;
430 int err;
431
432 /* wait trigger to be 0 */
433 do {
434 if (timeout-- == 0)
435 return -EIO;
436
437 if (idtcm->calculate_overhead_flag)
438 idtcm->start_time = ktime_get_raw();
439
440 err = idtcm_read(idtcm, channel->tod_read_primary,
441 tod_read_cmd, &trigger,
442 sizeof(trigger));
443 if (err)
444 return err;
445 } while (trigger & TOD_READ_TRIGGER_MASK);
446
447 err = idtcm_read(idtcm, channel->tod_read_primary,
448 TOD_READ_PRIMARY_BASE, buf, sizeof(buf));
449 if (err)
450 return err;
451
452 err = char_array_to_timespec(buf, sizeof(buf), ts);
453
454 return err;
455}
456
457static int idtcm_extts_check_channel(struct idtcm *idtcm, u8 todn)
458{
459 struct idtcm_channel *ptp_channel, *extts_channel;
460 struct ptp_clock_event event;
461 struct timespec64 ts;
462 u32 dco_delay = 0;
463 int err;
464
465 extts_channel = &idtcm->channel[todn];
466 ptp_channel = idtcm->event_channel[todn];
467
468 if (extts_channel == ptp_channel)
469 dco_delay = ptp_channel->dco_delay;
470
471 err = _idtcm_gettime_triggered(extts_channel, &ts);
472 if (err)
473 return err;
474
475 /* Triggered - save timestamp */
476 event.type = PTP_CLOCK_EXTTS;
477 event.index = todn;
478 event.timestamp = timespec64_to_ns(&ts) - dco_delay;
479 ptp_clock_event(ptp_channel->ptp_clock, &event);
480
481 return err;
482}
483
484static int _idtcm_gettime_immediate(struct idtcm_channel *channel,
485 struct timespec64 *ts)
486{
487 struct idtcm *idtcm = channel->idtcm;
488
489 u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
490 u8 val = (SCSR_TOD_READ_TRIG_SEL_IMMEDIATE << TOD_READ_TRIGGER_SHIFT);
491 int err;
492
493 err = idtcm_write(idtcm, channel->tod_read_primary,
494 tod_read_cmd, &val, sizeof(val));
495 if (err)
496 return err;
497
498 return _idtcm_gettime(channel, ts, 10);
499}
500
501static int _sync_pll_output(struct idtcm *idtcm,
502 u8 pll,
503 u8 sync_src,
504 u8 qn,
505 u8 qn_plus_1)
506{
507 int err;
508 u8 val;
509 u16 sync_ctrl0;
510 u16 sync_ctrl1;
511 u8 temp;
512
513 if (qn == 0 && qn_plus_1 == 0)
514 return 0;
515
516 switch (pll) {
517 case 0:
518 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
519 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
520 break;
521 case 1:
522 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
523 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
524 break;
525 case 2:
526 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
527 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
528 break;
529 case 3:
530 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
531 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
532 break;
533 case 4:
534 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
535 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
536 break;
537 case 5:
538 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
539 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
540 break;
541 case 6:
542 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
543 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
544 break;
545 case 7:
546 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
547 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
548 break;
549 default:
550 return -EINVAL;
551 }
552
553 val = SYNCTRL1_MASTER_SYNC_RST;
554
555 /* Place master sync in reset */
556 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
557 if (err)
558 return err;
559
560 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
561 if (err)
562 return err;
563
564 /* Set sync trigger mask */
565 val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
566
567 if (qn)
568 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
569
570 if (qn_plus_1)
571 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
572
573 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
574 if (err)
575 return err;
576
577 /* PLL5 can have OUT8 as second additional output. */
578 if (pll == 5 && qn_plus_1 != 0) {
579 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
580 &temp, sizeof(temp));
581 if (err)
582 return err;
583
584 temp &= ~(Q9_TO_Q8_SYNC_TRIG);
585
586 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
587 &temp, sizeof(temp));
588 if (err)
589 return err;
590
591 temp |= Q9_TO_Q8_SYNC_TRIG;
592
593 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
594 &temp, sizeof(temp));
595 if (err)
596 return err;
597 }
598
599 /* PLL6 can have OUT11 as second additional output. */
600 if (pll == 6 && qn_plus_1 != 0) {
601 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
602 &temp, sizeof(temp));
603 if (err)
604 return err;
605
606 temp &= ~(Q10_TO_Q11_SYNC_TRIG);
607
608 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
609 &temp, sizeof(temp));
610 if (err)
611 return err;
612
613 temp |= Q10_TO_Q11_SYNC_TRIG;
614
615 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
616 &temp, sizeof(temp));
617 if (err)
618 return err;
619 }
620
621 /* Place master sync out of reset */
622 val &= ~(SYNCTRL1_MASTER_SYNC_RST);
623 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
624
625 return err;
626}
627
628static int idtcm_sync_pps_output(struct idtcm_channel *channel)
629{
630 struct idtcm *idtcm = channel->idtcm;
631 u8 pll;
632 u8 qn;
633 u8 qn_plus_1;
634 int err = 0;
635 u8 out8_mux = 0;
636 u8 out11_mux = 0;
637 u8 temp;
638 u16 output_mask = channel->output_mask;
639
640 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
641 &temp, sizeof(temp));
642 if (err)
643 return err;
644
645 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
646 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
647 out8_mux = 1;
648
649 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
650 &temp, sizeof(temp));
651 if (err)
652 return err;
653
654 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
655 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
656 out11_mux = 1;
657
658 for (pll = 0; pll < 8; pll++) {
659 qn = 0;
660 qn_plus_1 = 0;
661
662 if (pll < 4) {
663 /* First 4 pll has 2 outputs */
664 qn = output_mask & 0x1;
665 output_mask = output_mask >> 1;
666 qn_plus_1 = output_mask & 0x1;
667 output_mask = output_mask >> 1;
668 } else if (pll == 4) {
669 if (out8_mux == 0) {
670 qn = output_mask & 0x1;
671 output_mask = output_mask >> 1;
672 }
673 } else if (pll == 5) {
674 if (out8_mux) {
675 qn_plus_1 = output_mask & 0x1;
676 output_mask = output_mask >> 1;
677 }
678 qn = output_mask & 0x1;
679 output_mask = output_mask >> 1;
680 } else if (pll == 6) {
681 qn = output_mask & 0x1;
682 output_mask = output_mask >> 1;
683 if (out11_mux) {
684 qn_plus_1 = output_mask & 0x1;
685 output_mask = output_mask >> 1;
686 }
687 } else if (pll == 7) {
688 if (out11_mux == 0) {
689 qn = output_mask & 0x1;
690 output_mask = output_mask >> 1;
691 }
692 }
693
694 if (qn != 0 || qn_plus_1 != 0)
695 err = _sync_pll_output(idtcm, pll, channel->sync_src,
696 qn, qn_plus_1);
697
698 if (err)
699 return err;
700 }
701
702 return err;
703}
704
705static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
706 struct timespec64 const *ts,
707 enum hw_tod_write_trig_sel wr_trig)
708{
709 struct idtcm *idtcm = channel->idtcm;
710 u8 buf[TOD_BYTE_COUNT];
711 u8 cmd;
712 int err;
713 struct timespec64 local_ts = *ts;
714 s64 total_overhead_ns;
715
716 /* Configure HW TOD write trigger. */
717 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
718 &cmd, sizeof(cmd));
719 if (err)
720 return err;
721
722 cmd &= ~(0x0f);
723 cmd |= wr_trig | 0x08;
724
725 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
726 &cmd, sizeof(cmd));
727 if (err)
728 return err;
729
730 if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) {
731 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
732 if (err)
733 return err;
734
735 err = idtcm_write(idtcm, channel->hw_dpll_n,
736 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
737 if (err)
738 return err;
739 }
740
741 /* ARM HW TOD write trigger. */
742 cmd &= ~(0x08);
743
744 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
745 &cmd, sizeof(cmd));
746
747 if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
748 if (idtcm->calculate_overhead_flag) {
749 /* Assumption: I2C @ 400KHz */
750 ktime_t diff = ktime_sub(ktime_get_raw(),
751 idtcm->start_time);
752 total_overhead_ns = ktime_to_ns(diff)
753 + idtcm->tod_write_overhead_ns
754 + SETTIME_CORRECTION;
755
756 timespec64_add_ns(&local_ts, total_overhead_ns);
757
758 idtcm->calculate_overhead_flag = 0;
759 }
760
761 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
762 if (err)
763 return err;
764
765 err = idtcm_write(idtcm, channel->hw_dpll_n,
766 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
767 }
768
769 return err;
770}
771
772static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
773 struct timespec64 const *ts,
774 enum scsr_tod_write_trig_sel wr_trig,
775 enum scsr_tod_write_type_sel wr_type)
776{
777 struct idtcm *idtcm = channel->idtcm;
778 unsigned char buf[TOD_BYTE_COUNT], cmd;
779 struct timespec64 local_ts = *ts;
780 int err, count = 0;
781
782 timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
783
784 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
785 if (err)
786 return err;
787
788 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
789 buf, sizeof(buf));
790 if (err)
791 return err;
792
793 /* Trigger the write operation. */
794 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
795 &cmd, sizeof(cmd));
796 if (err)
797 return err;
798
799 cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
800 cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
801 cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
802 cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
803
804 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
805 &cmd, sizeof(cmd));
806 if (err)
807 return err;
808
809 /* Wait for the operation to complete. */
810 while (1) {
811 /* pps trigger takes up to 1 sec to complete */
812 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
813 msleep(50);
814
815 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
816 &cmd, sizeof(cmd));
817 if (err)
818 return err;
819
820 if ((cmd & TOD_WRITE_SELECTION_MASK) == 0)
821 break;
822
823 if (++count > 20) {
824 dev_err(idtcm->dev,
825 "Timed out waiting for the write counter");
826 return -EIO;
827 }
828 }
829
830 return 0;
831}
832
833static int get_output_base_addr(enum fw_version ver, u8 outn)
834{
835 int base;
836
837 switch (outn) {
838 case 0:
839 base = IDTCM_FW_REG(ver, V520, OUTPUT_0);
840 break;
841 case 1:
842 base = IDTCM_FW_REG(ver, V520, OUTPUT_1);
843 break;
844 case 2:
845 base = IDTCM_FW_REG(ver, V520, OUTPUT_2);
846 break;
847 case 3:
848 base = IDTCM_FW_REG(ver, V520, OUTPUT_3);
849 break;
850 case 4:
851 base = IDTCM_FW_REG(ver, V520, OUTPUT_4);
852 break;
853 case 5:
854 base = IDTCM_FW_REG(ver, V520, OUTPUT_5);
855 break;
856 case 6:
857 base = IDTCM_FW_REG(ver, V520, OUTPUT_6);
858 break;
859 case 7:
860 base = IDTCM_FW_REG(ver, V520, OUTPUT_7);
861 break;
862 case 8:
863 base = IDTCM_FW_REG(ver, V520, OUTPUT_8);
864 break;
865 case 9:
866 base = IDTCM_FW_REG(ver, V520, OUTPUT_9);
867 break;
868 case 10:
869 base = IDTCM_FW_REG(ver, V520, OUTPUT_10);
870 break;
871 case 11:
872 base = IDTCM_FW_REG(ver, V520, OUTPUT_11);
873 break;
874 default:
875 base = -EINVAL;
876 }
877
878 return base;
879}
880
881static int _idtcm_settime_deprecated(struct idtcm_channel *channel,
882 struct timespec64 const *ts)
883{
884 struct idtcm *idtcm = channel->idtcm;
885 int err;
886
887 err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
888 if (err) {
889 dev_err(idtcm->dev,
890 "%s: Set HW ToD failed", __func__);
891 return err;
892 }
893
894 return idtcm_sync_pps_output(channel);
895}
896
897static int _idtcm_settime(struct idtcm_channel *channel,
898 struct timespec64 const *ts,
899 enum scsr_tod_write_type_sel wr_type)
900{
901 return _idtcm_set_dpll_scsr_tod(channel, ts,
902 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
903 wr_type);
904}
905
906static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
907 s32 offset_ns)
908{
909 int err;
910 int i;
911 struct idtcm *idtcm = channel->idtcm;
912 u8 buf[4];
913
914 for (i = 0; i < 4; i++) {
915 buf[i] = 0xff & (offset_ns);
916 offset_ns >>= 8;
917 }
918
919 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
920 buf, sizeof(buf));
921
922 return err;
923}
924
925static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
926 u32 max_ffo_ppb)
927{
928 int err;
929 u8 i;
930 struct idtcm *idtcm = channel->idtcm;
931 u8 buf[3];
932
933 if (max_ffo_ppb & 0xff000000)
934 max_ffo_ppb = 0;
935
936 for (i = 0; i < 3; i++) {
937 buf[i] = 0xff & (max_ffo_ppb);
938 max_ffo_ppb >>= 8;
939 }
940
941 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
942 PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
943
944 return err;
945}
946
947static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
948{
949 int err;
950 struct idtcm *idtcm = channel->idtcm;
951 u8 buf;
952
953 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
954 &buf, sizeof(buf));
955 if (err)
956 return err;
957
958 if (buf == 0) {
959 buf = 0x01;
960 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
961 PULL_IN_CTRL, &buf, sizeof(buf));
962 } else {
963 err = -EBUSY;
964 }
965
966 return err;
967}
968
969static int do_phase_pull_in_fw(struct idtcm_channel *channel,
970 s32 offset_ns,
971 u32 max_ffo_ppb)
972{
973 int err;
974
975 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
976 if (err)
977 return err;
978
979 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
980 if (err)
981 return err;
982
983 err = idtcm_start_phase_pull_in(channel);
984
985 return err;
986}
987
988static int set_tod_write_overhead(struct idtcm_channel *channel)
989{
990 struct idtcm *idtcm = channel->idtcm;
991 s64 current_ns = 0;
992 s64 lowest_ns = 0;
993 int err;
994 u8 i;
995 ktime_t start;
996 ktime_t stop;
997 ktime_t diff;
998
999 char buf[TOD_BYTE_COUNT] = {0};
1000
1001 /* Set page offset */
1002 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
1003 buf, sizeof(buf));
1004
1005 for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
1006 start = ktime_get_raw();
1007
1008 err = idtcm_write(idtcm, channel->hw_dpll_n,
1009 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
1010 if (err)
1011 return err;
1012
1013 stop = ktime_get_raw();
1014
1015 diff = ktime_sub(stop, start);
1016
1017 current_ns = ktime_to_ns(diff);
1018
1019 if (i == 0) {
1020 lowest_ns = current_ns;
1021 } else {
1022 if (current_ns < lowest_ns)
1023 lowest_ns = current_ns;
1024 }
1025 }
1026
1027 idtcm->tod_write_overhead_ns = lowest_ns;
1028
1029 return err;
1030}
1031
1032static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta)
1033{
1034 int err;
1035 struct idtcm *idtcm = channel->idtcm;
1036 struct timespec64 ts;
1037 s64 now;
1038
1039 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) {
1040 err = channel->do_phase_pull_in(channel, delta, 0);
1041 } else {
1042 idtcm->calculate_overhead_flag = 1;
1043
1044 err = set_tod_write_overhead(channel);
1045 if (err)
1046 return err;
1047
1048 err = _idtcm_gettime_immediate(channel, &ts);
1049 if (err)
1050 return err;
1051
1052 now = timespec64_to_ns(&ts);
1053 now += delta;
1054
1055 ts = ns_to_timespec64(now);
1056
1057 err = _idtcm_settime_deprecated(channel, &ts);
1058 }
1059
1060 return err;
1061}
1062
1063static int idtcm_state_machine_reset(struct idtcm *idtcm)
1064{
1065 u8 byte = SM_RESET_CMD;
1066 u32 status = 0;
1067 int err;
1068 u8 i;
1069
1070 clear_boot_status(idtcm);
1071
1072 err = idtcm_write(idtcm, RESET_CTRL,
1073 IDTCM_FW_REG(idtcm->fw_ver, V520, SM_RESET),
1074 &byte, sizeof(byte));
1075
1076 if (!err) {
1077 for (i = 0; i < 30; i++) {
1078 msleep_interruptible(100);
1079 read_boot_status(idtcm, &status);
1080
1081 if (status == 0xA0) {
1082 dev_dbg(idtcm->dev,
1083 "SM_RESET completed in %d ms", i * 100);
1084 break;
1085 }
1086 }
1087
1088 if (!status)
1089 dev_err(idtcm->dev,
1090 "Timed out waiting for CM_RESET to complete");
1091 }
1092
1093 return err;
1094}
1095
1096static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
1097{
1098 return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
1099}
1100
1101static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
1102{
1103 int err;
1104 u8 buf[2] = {0};
1105
1106 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
1107
1108 *product_id = (buf[1] << 8) | buf[0];
1109
1110 return err;
1111}
1112
1113static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
1114{
1115 int err;
1116 u8 buf = 0;
1117
1118 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
1119
1120 *major = buf >> 1;
1121
1122 return err;
1123}
1124
1125static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
1126{
1127 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
1128}
1129
1130static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
1131{
1132 return idtcm_read(idtcm,
1133 GENERAL_STATUS,
1134 HOTFIX_REL,
1135 hotfix,
1136 sizeof(u8));
1137}
1138
1139static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
1140 u8 *config_select)
1141{
1142 return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
1143 config_select, sizeof(u8));
1144}
1145
1146static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
1147{
1148 int err = 0;
1149
1150 switch (addr) {
1151 case TOD0_OUT_ALIGN_MASK_ADDR:
1152 SET_U16_LSB(idtcm->channel[0].output_mask, val);
1153 break;
1154 case TOD0_OUT_ALIGN_MASK_ADDR + 1:
1155 SET_U16_MSB(idtcm->channel[0].output_mask, val);
1156 break;
1157 case TOD1_OUT_ALIGN_MASK_ADDR:
1158 SET_U16_LSB(idtcm->channel[1].output_mask, val);
1159 break;
1160 case TOD1_OUT_ALIGN_MASK_ADDR + 1:
1161 SET_U16_MSB(idtcm->channel[1].output_mask, val);
1162 break;
1163 case TOD2_OUT_ALIGN_MASK_ADDR:
1164 SET_U16_LSB(idtcm->channel[2].output_mask, val);
1165 break;
1166 case TOD2_OUT_ALIGN_MASK_ADDR + 1:
1167 SET_U16_MSB(idtcm->channel[2].output_mask, val);
1168 break;
1169 case TOD3_OUT_ALIGN_MASK_ADDR:
1170 SET_U16_LSB(idtcm->channel[3].output_mask, val);
1171 break;
1172 case TOD3_OUT_ALIGN_MASK_ADDR + 1:
1173 SET_U16_MSB(idtcm->channel[3].output_mask, val);
1174 break;
1175 default:
1176 err = -EFAULT; /* Bad address */;
1177 break;
1178 }
1179
1180 return err;
1181}
1182
1183static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
1184{
1185 if (index >= MAX_TOD) {
1186 dev_err(idtcm->dev, "ToD%d not supported", index);
1187 return -EINVAL;
1188 }
1189
1190 if (pll >= MAX_PLL) {
1191 dev_err(idtcm->dev, "Pll%d not supported", pll);
1192 return -EINVAL;
1193 }
1194
1195 idtcm->channel[index].pll = pll;
1196
1197 return 0;
1198}
1199
1200static int check_and_set_masks(struct idtcm *idtcm,
1201 u16 regaddr,
1202 u8 val)
1203{
1204 int err = 0;
1205
1206 switch (regaddr) {
1207 case TOD_MASK_ADDR:
1208 if ((val & 0xf0) || !(val & 0x0f)) {
1209 dev_err(idtcm->dev, "Invalid TOD mask 0x%02x", val);
1210 err = -EINVAL;
1211 } else {
1212 idtcm->tod_mask = val;
1213 }
1214 break;
1215 case TOD0_PTP_PLL_ADDR:
1216 err = set_tod_ptp_pll(idtcm, 0, val);
1217 break;
1218 case TOD1_PTP_PLL_ADDR:
1219 err = set_tod_ptp_pll(idtcm, 1, val);
1220 break;
1221 case TOD2_PTP_PLL_ADDR:
1222 err = set_tod_ptp_pll(idtcm, 2, val);
1223 break;
1224 case TOD3_PTP_PLL_ADDR:
1225 err = set_tod_ptp_pll(idtcm, 3, val);
1226 break;
1227 default:
1228 err = set_pll_output_mask(idtcm, regaddr, val);
1229 break;
1230 }
1231
1232 return err;
1233}
1234
1235static void display_pll_and_masks(struct idtcm *idtcm)
1236{
1237 u8 i;
1238 u8 mask;
1239
1240 dev_dbg(idtcm->dev, "tod_mask = 0x%02x", idtcm->tod_mask);
1241
1242 for (i = 0; i < MAX_TOD; i++) {
1243 mask = 1 << i;
1244
1245 if (mask & idtcm->tod_mask)
1246 dev_dbg(idtcm->dev,
1247 "TOD%d pll = %d output_mask = 0x%04x",
1248 i, idtcm->channel[i].pll,
1249 idtcm->channel[i].output_mask);
1250 }
1251}
1252
1253static int idtcm_load_firmware(struct idtcm *idtcm,
1254 struct device *dev)
1255{
1256 u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);
1257 char fname[128] = FW_FILENAME;
1258 const struct firmware *fw;
1259 struct idtcm_fwrc *rec;
1260 u32 regaddr;
1261 int err;
1262 s32 len;
1263 u8 val;
1264 u8 loaddr;
1265
1266 if (firmware) /* module parameter */
1267 snprintf(fname, sizeof(fname), "%s", firmware);
1268
1269 dev_info(idtcm->dev, "requesting firmware '%s'", fname);
1270
1271 err = request_firmware(&fw, fname, dev);
1272 if (err) {
1273 dev_err(idtcm->dev,
1274 "Failed at line %d in %s!", __LINE__, __func__);
1275 return err;
1276 }
1277
1278 dev_dbg(idtcm->dev, "firmware size %zu bytes", fw->size);
1279
1280 rec = (struct idtcm_fwrc *) fw->data;
1281
1282 if (contains_full_configuration(idtcm, fw))
1283 idtcm_state_machine_reset(idtcm);
1284
1285 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
1286 if (rec->reserved) {
1287 dev_err(idtcm->dev,
1288 "bad firmware, reserved field non-zero");
1289 err = -EINVAL;
1290 } else {
1291 regaddr = rec->hiaddr << 8;
1292 regaddr |= rec->loaddr;
1293
1294 val = rec->value;
1295 loaddr = rec->loaddr;
1296
1297 rec++;
1298
1299 err = check_and_set_masks(idtcm, regaddr, val);
1300 }
1301
1302 if (err != -EINVAL) {
1303 err = 0;
1304
1305 /* Top (status registers) and bottom are read-only */
1306 if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch)
1307 continue;
1308
1309 /* Page size 128, last 4 bytes of page skipped */
1310 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
1311 continue;
1312
1313 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1314 }
1315
1316 if (err)
1317 goto out;
1318 }
1319
1320 display_pll_and_masks(idtcm);
1321
1322out:
1323 release_firmware(fw);
1324 return err;
1325}
1326
1327static int idtcm_output_enable(struct idtcm_channel *channel,
1328 bool enable, unsigned int outn)
1329{
1330 struct idtcm *idtcm = channel->idtcm;
1331 int base;
1332 int err;
1333 u8 val;
1334
1335 base = get_output_base_addr(idtcm->fw_ver, outn);
1336
1337 if (!(base > 0)) {
1338 dev_err(idtcm->dev,
1339 "%s - Unsupported out%d", __func__, outn);
1340 return base;
1341 }
1342
1343 err = idtcm_read(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1344 if (err)
1345 return err;
1346
1347 if (enable)
1348 val |= SQUELCH_DISABLE;
1349 else
1350 val &= ~SQUELCH_DISABLE;
1351
1352 return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1353}
1354
1355static int idtcm_perout_enable(struct idtcm_channel *channel,
1356 struct ptp_perout_request *perout,
1357 bool enable)
1358{
1359 struct idtcm *idtcm = channel->idtcm;
1360 struct timespec64 ts = {0, 0};
1361 int err;
1362
1363 err = idtcm_output_enable(channel, enable, perout->index);
1364
1365 if (err) {
1366 dev_err(idtcm->dev, "Unable to set output enable");
1367 return err;
1368 }
1369
1370 /* Align output to internal 1 PPS */
1371 return _idtcm_settime(channel, &ts, SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS);
1372}
1373
1374static int idtcm_get_pll_mode(struct idtcm_channel *channel,
1375 enum pll_mode *mode)
1376{
1377 struct idtcm *idtcm = channel->idtcm;
1378 int err;
1379 u8 dpll_mode;
1380
1381 err = idtcm_read(idtcm, channel->dpll_n,
1382 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
1383 &dpll_mode, sizeof(dpll_mode));
1384 if (err)
1385 return err;
1386
1387 *mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
1388
1389 return 0;
1390}
1391
1392static int idtcm_set_pll_mode(struct idtcm_channel *channel,
1393 enum pll_mode mode)
1394{
1395 struct idtcm *idtcm = channel->idtcm;
1396 int err;
1397 u8 dpll_mode;
1398
1399 err = idtcm_read(idtcm, channel->dpll_n,
1400 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
1401 &dpll_mode, sizeof(dpll_mode));
1402 if (err)
1403 return err;
1404
1405 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
1406
1407 dpll_mode |= (mode << PLL_MODE_SHIFT);
1408
1409 err = idtcm_write(idtcm, channel->dpll_n,
1410 IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
1411 &dpll_mode, sizeof(dpll_mode));
1412 return err;
1413}
1414
1415static int idtcm_get_manual_reference(struct idtcm_channel *channel,
1416 enum manual_reference *ref)
1417{
1418 struct idtcm *idtcm = channel->idtcm;
1419 u8 dpll_manu_ref_cfg;
1420 int err;
1421
1422 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
1423 DPLL_CTRL_DPLL_MANU_REF_CFG,
1424 &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
1425 if (err)
1426 return err;
1427
1428 dpll_manu_ref_cfg &= (MANUAL_REFERENCE_MASK << MANUAL_REFERENCE_SHIFT);
1429
1430 *ref = dpll_manu_ref_cfg >> MANUAL_REFERENCE_SHIFT;
1431
1432 return 0;
1433}
1434
1435static int idtcm_set_manual_reference(struct idtcm_channel *channel,
1436 enum manual_reference ref)
1437{
1438 struct idtcm *idtcm = channel->idtcm;
1439 u8 dpll_manu_ref_cfg;
1440 int err;
1441
1442 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
1443 DPLL_CTRL_DPLL_MANU_REF_CFG,
1444 &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
1445 if (err)
1446 return err;
1447
1448 dpll_manu_ref_cfg &= ~(MANUAL_REFERENCE_MASK << MANUAL_REFERENCE_SHIFT);
1449
1450 dpll_manu_ref_cfg |= (ref << MANUAL_REFERENCE_SHIFT);
1451
1452 err = idtcm_write(idtcm, channel->dpll_ctrl_n,
1453 DPLL_CTRL_DPLL_MANU_REF_CFG,
1454 &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
1455
1456 return err;
1457}
1458
1459static int configure_dpll_mode_write_frequency(struct idtcm_channel *channel)
1460{
1461 struct idtcm *idtcm = channel->idtcm;
1462 int err;
1463
1464 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1465
1466 if (err)
1467 dev_err(idtcm->dev, "Failed to set pll mode to write frequency");
1468 else
1469 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1470
1471 return err;
1472}
1473
1474static int configure_dpll_mode_write_phase(struct idtcm_channel *channel)
1475{
1476 struct idtcm *idtcm = channel->idtcm;
1477 int err;
1478
1479 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1480
1481 if (err)
1482 dev_err(idtcm->dev, "Failed to set pll mode to write phase");
1483 else
1484 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1485
1486 return err;
1487}
1488
1489static int configure_manual_reference_write_frequency(struct idtcm_channel *channel)
1490{
1491 struct idtcm *idtcm = channel->idtcm;
1492 int err;
1493
1494 err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_FREQUENCY);
1495
1496 if (err)
1497 dev_err(idtcm->dev, "Failed to set manual reference to write frequency");
1498 else
1499 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1500
1501 return err;
1502}
1503
1504static int configure_manual_reference_write_phase(struct idtcm_channel *channel)
1505{
1506 struct idtcm *idtcm = channel->idtcm;
1507 int err;
1508
1509 err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_PHASE);
1510
1511 if (err)
1512 dev_err(idtcm->dev, "Failed to set manual reference to write phase");
1513 else
1514 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1515
1516 return err;
1517}
1518
1519static int idtcm_stop_phase_pull_in(struct idtcm_channel *channel)
1520{
1521 int err;
1522
1523 err = _idtcm_adjfine(channel, channel->current_freq_scaled_ppm);
1524 if (err)
1525 return err;
1526
1527 channel->phase_pull_in = false;
1528
1529 return 0;
1530}
1531
1532static long idtcm_work_handler(struct ptp_clock_info *ptp)
1533{
1534 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1535 struct idtcm *idtcm = channel->idtcm;
1536
1537 mutex_lock(idtcm->lock);
1538
1539 (void)idtcm_stop_phase_pull_in(channel);
1540
1541 mutex_unlock(idtcm->lock);
1542
1543 /* Return a negative value here to not reschedule */
1544 return -1;
1545}
1546
1547static s32 phase_pull_in_scaled_ppm(s32 current_ppm, s32 phase_pull_in_ppb)
1548{
1549 /* ppb = scaled_ppm * 125 / 2^13 */
1550 /* scaled_ppm = ppb * 2^13 / 125 */
1551
1552 s64 max_scaled_ppm = div_s64((s64)PHASE_PULL_IN_MAX_PPB << 13, 125);
1553 s64 scaled_ppm = div_s64((s64)phase_pull_in_ppb << 13, 125);
1554
1555 current_ppm += scaled_ppm;
1556
1557 if (current_ppm > max_scaled_ppm)
1558 current_ppm = max_scaled_ppm;
1559 else if (current_ppm < -max_scaled_ppm)
1560 current_ppm = -max_scaled_ppm;
1561
1562 return current_ppm;
1563}
1564
1565static int do_phase_pull_in_sw(struct idtcm_channel *channel,
1566 s32 delta_ns,
1567 u32 max_ffo_ppb)
1568{
1569 s32 current_ppm = channel->current_freq_scaled_ppm;
1570 u32 duration_ms = MSEC_PER_SEC;
1571 s32 delta_ppm;
1572 s32 ppb;
1573 int err;
1574
1575 /* If the ToD correction is less than PHASE_PULL_IN_MIN_THRESHOLD_NS,
1576 * skip. The error introduced by the ToD adjustment procedure would
1577 * be bigger than the required ToD correction
1578 */
1579 if (abs(delta_ns) < PHASE_PULL_IN_MIN_THRESHOLD_NS)
1580 return 0;
1581
1582 if (max_ffo_ppb == 0)
1583 max_ffo_ppb = PHASE_PULL_IN_MAX_PPB;
1584
1585 /* For most cases, keep phase pull-in duration 1 second */
1586 ppb = delta_ns;
1587 while (abs(ppb) > max_ffo_ppb) {
1588 duration_ms *= 2;
1589 ppb /= 2;
1590 }
1591
1592 delta_ppm = phase_pull_in_scaled_ppm(current_ppm, ppb);
1593
1594 err = _idtcm_adjfine(channel, delta_ppm);
1595
1596 if (err)
1597 return err;
1598
1599 /* schedule the worker to cancel phase pull-in */
1600 ptp_schedule_worker(channel->ptp_clock,
1601 msecs_to_jiffies(duration_ms) - 1);
1602
1603 channel->phase_pull_in = true;
1604
1605 return 0;
1606}
1607
1608static int initialize_operating_mode_with_manual_reference(struct idtcm_channel *channel,
1609 enum manual_reference ref)
1610{
1611 struct idtcm *idtcm = channel->idtcm;
1612
1613 channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1614 channel->configure_write_frequency = configure_manual_reference_write_frequency;
1615 channel->configure_write_phase = configure_manual_reference_write_phase;
1616 channel->do_phase_pull_in = do_phase_pull_in_sw;
1617
1618 switch (ref) {
1619 case MANU_REF_WRITE_PHASE:
1620 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1621 break;
1622 case MANU_REF_WRITE_FREQUENCY:
1623 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1624 break;
1625 default:
1626 dev_warn(idtcm->dev,
1627 "Unsupported MANUAL_REFERENCE: 0x%02x", ref);
1628 }
1629
1630 return 0;
1631}
1632
1633static int initialize_operating_mode_with_pll_mode(struct idtcm_channel *channel,
1634 enum pll_mode mode)
1635{
1636 struct idtcm *idtcm = channel->idtcm;
1637 int err = 0;
1638
1639 channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1640 channel->configure_write_frequency = configure_dpll_mode_write_frequency;
1641 channel->configure_write_phase = configure_dpll_mode_write_phase;
1642 channel->do_phase_pull_in = do_phase_pull_in_fw;
1643
1644 switch (mode) {
1645 case PLL_MODE_WRITE_PHASE:
1646 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1647 break;
1648 case PLL_MODE_WRITE_FREQUENCY:
1649 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1650 break;
1651 default:
1652 dev_err(idtcm->dev,
1653 "Unsupported PLL_MODE: 0x%02x", mode);
1654 err = -EINVAL;
1655 }
1656
1657 return err;
1658}
1659
1660static int initialize_dco_operating_mode(struct idtcm_channel *channel)
1661{
1662 enum manual_reference ref = MANU_REF_XO_DPLL;
1663 enum pll_mode mode = PLL_MODE_DISABLED;
1664 struct idtcm *idtcm = channel->idtcm;
1665 int err;
1666
1667 channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1668
1669 err = idtcm_get_pll_mode(channel, &mode);
1670 if (err) {
1671 dev_err(idtcm->dev, "Unable to read pll mode!");
1672 return err;
1673 }
1674
1675 if (mode == PLL_MODE_PLL) {
1676 err = idtcm_get_manual_reference(channel, &ref);
1677 if (err) {
1678 dev_err(idtcm->dev, "Unable to read manual reference!");
1679 return err;
1680 }
1681 err = initialize_operating_mode_with_manual_reference(channel, ref);
1682 } else {
1683 err = initialize_operating_mode_with_pll_mode(channel, mode);
1684 }
1685
1686 if (channel->mode == PTP_PLL_MODE_WRITE_PHASE)
1687 channel->configure_write_frequency(channel);
1688
1689 return err;
1690}
1691
1692/* PTP Hardware Clock interface */
1693
1694/*
1695 * Maximum absolute value for write phase offset in picoseconds
1696 *
1697 * @channel: channel
1698 * @delta_ns: delta in nanoseconds
1699 *
1700 * Destination signed register is 32-bit register in resolution of 50ps
1701 *
1702 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
1703 */
1704static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1705{
1706 struct idtcm *idtcm = channel->idtcm;
1707 int err;
1708 u8 i;
1709 u8 buf[4] = {0};
1710 s32 phase_50ps;
1711 s64 offset_ps;
1712
1713 if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) {
1714 err = channel->configure_write_phase(channel);
1715 if (err)
1716 return err;
1717 }
1718
1719 offset_ps = (s64)delta_ns * 1000;
1720
1721 /*
1722 * Check for 32-bit signed max * 50:
1723 *
1724 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
1725 */
1726 if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
1727 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
1728 else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
1729 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
1730
1731 phase_50ps = div_s64(offset_ps, 50);
1732
1733 for (i = 0; i < 4; i++) {
1734 buf[i] = phase_50ps & 0xff;
1735 phase_50ps >>= 8;
1736 }
1737
1738 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1739 buf, sizeof(buf));
1740
1741 return err;
1742}
1743
1744static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
1745{
1746 struct idtcm *idtcm = channel->idtcm;
1747 u8 i;
1748 int err;
1749 u8 buf[6] = {0};
1750 s64 fcw;
1751
1752 if (channel->mode != PTP_PLL_MODE_WRITE_FREQUENCY) {
1753 err = channel->configure_write_frequency(channel);
1754 if (err)
1755 return err;
1756 }
1757
1758 /*
1759 * Frequency Control Word unit is: 1.11 * 10^-10 ppm
1760 *
1761 * adjfreq:
1762 * ppb * 10^9
1763 * FCW = ----------
1764 * 111
1765 *
1766 * adjfine:
1767 * ppm_16 * 5^12
1768 * FCW = -------------
1769 * 111 * 2^4
1770 */
1771
1772 /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */
1773 fcw = scaled_ppm * 244140625ULL;
1774
1775 fcw = div_s64(fcw, 1776);
1776
1777 for (i = 0; i < 6; i++) {
1778 buf[i] = fcw & 0xff;
1779 fcw >>= 8;
1780 }
1781
1782 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1783 buf, sizeof(buf));
1784
1785 return err;
1786}
1787
1788static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
1789{
1790 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1791 struct idtcm *idtcm = channel->idtcm;
1792 int err;
1793
1794 mutex_lock(idtcm->lock);
1795 err = _idtcm_gettime_immediate(channel, ts);
1796 mutex_unlock(idtcm->lock);
1797
1798 if (err)
1799 dev_err(idtcm->dev, "Failed at line %d in %s!",
1800 __LINE__, __func__);
1801
1802 return err;
1803}
1804
1805static int idtcm_settime_deprecated(struct ptp_clock_info *ptp,
1806 const struct timespec64 *ts)
1807{
1808 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1809 struct idtcm *idtcm = channel->idtcm;
1810 int err;
1811
1812 mutex_lock(idtcm->lock);
1813 err = _idtcm_settime_deprecated(channel, ts);
1814 mutex_unlock(idtcm->lock);
1815
1816 if (err)
1817 dev_err(idtcm->dev,
1818 "Failed at line %d in %s!", __LINE__, __func__);
1819
1820 return err;
1821}
1822
1823static int idtcm_settime(struct ptp_clock_info *ptp,
1824 const struct timespec64 *ts)
1825{
1826 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1827 struct idtcm *idtcm = channel->idtcm;
1828 int err;
1829
1830 mutex_lock(idtcm->lock);
1831 err = _idtcm_settime(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1832 mutex_unlock(idtcm->lock);
1833
1834 if (err)
1835 dev_err(idtcm->dev,
1836 "Failed at line %d in %s!", __LINE__, __func__);
1837
1838 return err;
1839}
1840
1841static int idtcm_adjtime_deprecated(struct ptp_clock_info *ptp, s64 delta)
1842{
1843 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1844 struct idtcm *idtcm = channel->idtcm;
1845 int err;
1846
1847 mutex_lock(idtcm->lock);
1848 err = _idtcm_adjtime_deprecated(channel, delta);
1849 mutex_unlock(idtcm->lock);
1850
1851 if (err)
1852 dev_err(idtcm->dev,
1853 "Failed at line %d in %s!", __LINE__, __func__);
1854
1855 return err;
1856}
1857
1858static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
1859{
1860 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1861 struct idtcm *idtcm = channel->idtcm;
1862 struct timespec64 ts;
1863 enum scsr_tod_write_type_sel type;
1864 int err;
1865
1866 if (channel->phase_pull_in == true)
1867 return -EBUSY;
1868
1869 mutex_lock(idtcm->lock);
1870
1871 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
1872 err = channel->do_phase_pull_in(channel, delta, 0);
1873 } else {
1874 if (delta >= 0) {
1875 ts = ns_to_timespec64(delta);
1876 type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
1877 } else {
1878 ts = ns_to_timespec64(-delta);
1879 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
1880 }
1881 err = _idtcm_settime(channel, &ts, type);
1882 }
1883
1884 mutex_unlock(idtcm->lock);
1885
1886 if (err)
1887 dev_err(idtcm->dev,
1888 "Failed at line %d in %s!", __LINE__, __func__);
1889
1890 return err;
1891}
1892
1893static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta)
1894{
1895 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1896 struct idtcm *idtcm = channel->idtcm;
1897 int err;
1898
1899 mutex_lock(idtcm->lock);
1900 err = _idtcm_adjphase(channel, delta);
1901 mutex_unlock(idtcm->lock);
1902
1903 if (err)
1904 dev_err(idtcm->dev,
1905 "Failed at line %d in %s!", __LINE__, __func__);
1906
1907 return err;
1908}
1909
1910static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
1911{
1912 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1913 struct idtcm *idtcm = channel->idtcm;
1914 int err;
1915
1916 if (channel->phase_pull_in == true)
1917 return 0;
1918
1919 if (scaled_ppm == channel->current_freq_scaled_ppm)
1920 return 0;
1921
1922 mutex_lock(idtcm->lock);
1923 err = _idtcm_adjfine(channel, scaled_ppm);
1924 mutex_unlock(idtcm->lock);
1925
1926 if (err)
1927 dev_err(idtcm->dev,
1928 "Failed at line %d in %s!", __LINE__, __func__);
1929 else
1930 channel->current_freq_scaled_ppm = scaled_ppm;
1931
1932 return err;
1933}
1934
1935static int idtcm_enable(struct ptp_clock_info *ptp,
1936 struct ptp_clock_request *rq, int on)
1937{
1938 struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1939 struct idtcm *idtcm = channel->idtcm;
1940 int err = -EOPNOTSUPP;
1941
1942 mutex_lock(idtcm->lock);
1943
1944 switch (rq->type) {
1945 case PTP_CLK_REQ_PEROUT:
1946 if (!on)
1947 err = idtcm_perout_enable(channel, &rq->perout, false);
1948 /* Only accept a 1-PPS aligned to the second. */
1949 else if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
1950 rq->perout.period.nsec)
1951 err = -ERANGE;
1952 else
1953 err = idtcm_perout_enable(channel, &rq->perout, true);
1954 break;
1955 case PTP_CLK_REQ_EXTTS:
1956 err = idtcm_extts_enable(channel, rq, on);
1957 break;
1958 default:
1959 break;
1960 }
1961
1962 mutex_unlock(idtcm->lock);
1963
1964 if (err)
1965 dev_err(channel->idtcm->dev,
1966 "Failed in %s with err %d!", __func__, err);
1967
1968 return err;
1969}
1970
1971static int idtcm_enable_tod(struct idtcm_channel *channel)
1972{
1973 struct idtcm *idtcm = channel->idtcm;
1974 struct timespec64 ts = {0, 0};
1975 u16 tod_cfg = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_CFG);
1976 u8 cfg;
1977 int err;
1978
1979 /*
1980 * Start the TOD clock ticking.
1981 */
1982 err = idtcm_read(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg));
1983 if (err)
1984 return err;
1985
1986 cfg |= TOD_ENABLE;
1987
1988 err = idtcm_write(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg));
1989 if (err)
1990 return err;
1991
1992 if (idtcm->fw_ver < V487)
1993 return _idtcm_settime_deprecated(channel, &ts);
1994 else
1995 return _idtcm_settime(channel, &ts,
1996 SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1997}
1998
1999static void idtcm_set_version_info(struct idtcm *idtcm)
2000{
2001 u8 major;
2002 u8 minor;
2003 u8 hotfix;
2004 u16 product_id;
2005 u8 hw_rev_id;
2006 u8 config_select;
2007
2008 idtcm_read_major_release(idtcm, &major);
2009 idtcm_read_minor_release(idtcm, &minor);
2010 idtcm_read_hotfix_release(idtcm, &hotfix);
2011
2012 idtcm_read_product_id(idtcm, &product_id);
2013 idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
2014
2015 idtcm_read_otp_scsr_config_select(idtcm, &config_select);
2016
2017 snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
2018 major, minor, hotfix);
2019
2020 idtcm->fw_ver = idtcm_fw_version(idtcm->version);
2021
2022 dev_info(idtcm->dev,
2023 "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d",
2024 major, minor, hotfix,
2025 product_id, hw_rev_id, config_select);
2026}
2027
2028static int idtcm_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
2029 enum ptp_pin_function func, unsigned int chan)
2030{
2031 switch (func) {
2032 case PTP_PF_NONE:
2033 case PTP_PF_EXTTS:
2034 break;
2035 case PTP_PF_PEROUT:
2036 case PTP_PF_PHYSYNC:
2037 return -1;
2038 }
2039 return 0;
2040}
2041
2042static struct ptp_pin_desc pin_config[MAX_TOD][MAX_REF_CLK];
2043
2044static const struct ptp_clock_info idtcm_caps = {
2045 .owner = THIS_MODULE,
2046 .max_adj = 244000,
2047 .n_per_out = 12,
2048 .n_ext_ts = MAX_TOD,
2049 .n_pins = MAX_REF_CLK,
2050 .adjphase = &idtcm_adjphase,
2051 .adjfine = &idtcm_adjfine,
2052 .adjtime = &idtcm_adjtime,
2053 .gettime64 = &idtcm_gettime,
2054 .settime64 = &idtcm_settime,
2055 .enable = &idtcm_enable,
2056 .verify = &idtcm_verify_pin,
2057 .do_aux_work = &idtcm_work_handler,
2058};
2059
2060static const struct ptp_clock_info idtcm_caps_deprecated = {
2061 .owner = THIS_MODULE,
2062 .max_adj = 244000,
2063 .n_per_out = 12,
2064 .n_ext_ts = MAX_TOD,
2065 .n_pins = MAX_REF_CLK,
2066 .adjphase = &idtcm_adjphase,
2067 .adjfine = &idtcm_adjfine,
2068 .adjtime = &idtcm_adjtime_deprecated,
2069 .gettime64 = &idtcm_gettime,
2070 .settime64 = &idtcm_settime_deprecated,
2071 .enable = &idtcm_enable,
2072 .verify = &idtcm_verify_pin,
2073 .do_aux_work = &idtcm_work_handler,
2074};
2075
2076static int configure_channel_pll(struct idtcm_channel *channel)
2077{
2078 struct idtcm *idtcm = channel->idtcm;
2079 int err = 0;
2080
2081 switch (channel->pll) {
2082 case 0:
2083 channel->dpll_freq = DPLL_FREQ_0;
2084 channel->dpll_n = DPLL_0;
2085 channel->hw_dpll_n = HW_DPLL_0;
2086 channel->dpll_phase = DPLL_PHASE_0;
2087 channel->dpll_ctrl_n = DPLL_CTRL_0;
2088 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
2089 break;
2090 case 1:
2091 channel->dpll_freq = DPLL_FREQ_1;
2092 channel->dpll_n = DPLL_1;
2093 channel->hw_dpll_n = HW_DPLL_1;
2094 channel->dpll_phase = DPLL_PHASE_1;
2095 channel->dpll_ctrl_n = DPLL_CTRL_1;
2096 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
2097 break;
2098 case 2:
2099 channel->dpll_freq = DPLL_FREQ_2;
2100 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_2);
2101 channel->hw_dpll_n = HW_DPLL_2;
2102 channel->dpll_phase = DPLL_PHASE_2;
2103 channel->dpll_ctrl_n = DPLL_CTRL_2;
2104 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
2105 break;
2106 case 3:
2107 channel->dpll_freq = DPLL_FREQ_3;
2108 channel->dpll_n = DPLL_3;
2109 channel->hw_dpll_n = HW_DPLL_3;
2110 channel->dpll_phase = DPLL_PHASE_3;
2111 channel->dpll_ctrl_n = DPLL_CTRL_3;
2112 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
2113 break;
2114 case 4:
2115 channel->dpll_freq = DPLL_FREQ_4;
2116 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_4);
2117 channel->hw_dpll_n = HW_DPLL_4;
2118 channel->dpll_phase = DPLL_PHASE_4;
2119 channel->dpll_ctrl_n = DPLL_CTRL_4;
2120 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
2121 break;
2122 case 5:
2123 channel->dpll_freq = DPLL_FREQ_5;
2124 channel->dpll_n = DPLL_5;
2125 channel->hw_dpll_n = HW_DPLL_5;
2126 channel->dpll_phase = DPLL_PHASE_5;
2127 channel->dpll_ctrl_n = DPLL_CTRL_5;
2128 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
2129 break;
2130 case 6:
2131 channel->dpll_freq = DPLL_FREQ_6;
2132 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_6);
2133 channel->hw_dpll_n = HW_DPLL_6;
2134 channel->dpll_phase = DPLL_PHASE_6;
2135 channel->dpll_ctrl_n = DPLL_CTRL_6;
2136 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
2137 break;
2138 case 7:
2139 channel->dpll_freq = DPLL_FREQ_7;
2140 channel->dpll_n = DPLL_7;
2141 channel->hw_dpll_n = HW_DPLL_7;
2142 channel->dpll_phase = DPLL_PHASE_7;
2143 channel->dpll_ctrl_n = DPLL_CTRL_7;
2144 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
2145 break;
2146 default:
2147 err = -EINVAL;
2148 }
2149
2150 return err;
2151}
2152
2153/*
2154 * Compensate for the PTP DCO input-to-output delay.
2155 * This delay is 18 FOD cycles.
2156 */
2157static u32 idtcm_get_dco_delay(struct idtcm_channel *channel)
2158{
2159 struct idtcm *idtcm = channel->idtcm;
2160 u8 mbuf[8] = {0};
2161 u8 nbuf[2] = {0};
2162 u32 fodFreq;
2163 int err;
2164 u64 m;
2165 u16 n;
2166
2167 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
2168 DPLL_CTRL_DPLL_FOD_FREQ, mbuf, 6);
2169 if (err)
2170 return 0;
2171
2172 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
2173 DPLL_CTRL_DPLL_FOD_FREQ + 6, nbuf, 2);
2174 if (err)
2175 return 0;
2176
2177 m = get_unaligned_le64(mbuf);
2178 n = get_unaligned_le16(nbuf);
2179
2180 if (n == 0)
2181 n = 1;
2182
2183 fodFreq = (u32)div_u64(m, n);
2184
2185 if (fodFreq >= 500000000)
2186 return (u32)div_u64(18 * (u64)NSEC_PER_SEC, fodFreq);
2187
2188 return 0;
2189}
2190
2191static int configure_channel_tod(struct idtcm_channel *channel, u32 index)
2192{
2193 enum fw_version fw_ver = channel->idtcm->fw_ver;
2194
2195 /* Set tod addresses */
2196 switch (index) {
2197 case 0:
2198 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_0);
2199 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_0);
2200 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_0);
2201 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_0);
2202 channel->sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
2203 break;
2204 case 1:
2205 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_1);
2206 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_1);
2207 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_1);
2208 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_1);
2209 channel->sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
2210 break;
2211 case 2:
2212 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_2);
2213 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_2);
2214 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_2);
2215 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_2);
2216 channel->sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
2217 break;
2218 case 3:
2219 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_3);
2220 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_3);
2221 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_3);
2222 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_3);
2223 channel->sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
2224 break;
2225 default:
2226 return -EINVAL;
2227 }
2228
2229 return 0;
2230}
2231
2232static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
2233{
2234 struct idtcm_channel *channel;
2235 int err;
2236 int i;
2237
2238 if (!(index < MAX_TOD))
2239 return -EINVAL;
2240
2241 channel = &idtcm->channel[index];
2242
2243 channel->idtcm = idtcm;
2244 channel->current_freq_scaled_ppm = 0;
2245
2246 /* Set pll addresses */
2247 err = configure_channel_pll(channel);
2248 if (err)
2249 return err;
2250
2251 /* Set tod addresses */
2252 err = configure_channel_tod(channel, index);
2253 if (err)
2254 return err;
2255
2256 if (idtcm->fw_ver < V487)
2257 channel->caps = idtcm_caps_deprecated;
2258 else
2259 channel->caps = idtcm_caps;
2260
2261 snprintf(channel->caps.name, sizeof(channel->caps.name),
2262 "IDT CM TOD%u", index);
2263
2264 channel->caps.pin_config = pin_config[index];
2265
2266 for (i = 0; i < channel->caps.n_pins; ++i) {
2267 struct ptp_pin_desc *ppd = &channel->caps.pin_config[i];
2268
2269 snprintf(ppd->name, sizeof(ppd->name), "input_ref%d", i);
2270 ppd->index = i;
2271 ppd->func = PTP_PF_NONE;
2272 ppd->chan = index;
2273 }
2274
2275 err = initialize_dco_operating_mode(channel);
2276 if (err)
2277 return err;
2278
2279 err = idtcm_enable_tod(channel);
2280 if (err) {
2281 dev_err(idtcm->dev,
2282 "Failed at line %d in %s!", __LINE__, __func__);
2283 return err;
2284 }
2285
2286 channel->dco_delay = idtcm_get_dco_delay(channel);
2287
2288 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2289
2290 if (IS_ERR(channel->ptp_clock)) {
2291 err = PTR_ERR(channel->ptp_clock);
2292 channel->ptp_clock = NULL;
2293 return err;
2294 }
2295
2296 if (!channel->ptp_clock)
2297 return -ENOTSUPP;
2298
2299 dev_info(idtcm->dev, "PLL%d registered as ptp%d",
2300 index, channel->ptp_clock->index);
2301
2302 return 0;
2303}
2304
2305static int idtcm_enable_extts_channel(struct idtcm *idtcm, u32 index)
2306{
2307 struct idtcm_channel *channel;
2308 int err;
2309
2310 if (!(index < MAX_TOD))
2311 return -EINVAL;
2312
2313 channel = &idtcm->channel[index];
2314 channel->idtcm = idtcm;
2315
2316 /* Set tod addresses */
2317 err = configure_channel_tod(channel, index);
2318 if (err)
2319 return err;
2320
2321 channel->idtcm = idtcm;
2322
2323 return 0;
2324}
2325
2326static void idtcm_extts_check(struct work_struct *work)
2327{
2328 struct idtcm *idtcm = container_of(work, struct idtcm, extts_work.work);
2329 struct idtcm_channel *channel;
2330 u8 mask;
2331 int err;
2332 int i;
2333
2334 if (idtcm->extts_mask == 0)
2335 return;
2336
2337 mutex_lock(idtcm->lock);
2338
2339 for (i = 0; i < MAX_TOD; i++) {
2340 mask = 1 << i;
2341
2342 if ((idtcm->extts_mask & mask) == 0)
2343 continue;
2344
2345 err = idtcm_extts_check_channel(idtcm, i);
2346
2347 if (err == 0) {
2348 /* trigger clears itself, so clear the mask */
2349 if (idtcm->extts_single_shot) {
2350 idtcm->extts_mask &= ~mask;
2351 } else {
2352 /* Re-arm */
2353 channel = &idtcm->channel[i];
2354 arm_tod_read_trig_sel_refclk(channel, channel->refn);
2355 }
2356 }
2357 }
2358
2359 if (idtcm->extts_mask)
2360 schedule_delayed_work(&idtcm->extts_work,
2361 msecs_to_jiffies(EXTTS_PERIOD_MS));
2362
2363 mutex_unlock(idtcm->lock);
2364}
2365
2366static void ptp_clock_unregister_all(struct idtcm *idtcm)
2367{
2368 u8 i;
2369 struct idtcm_channel *channel;
2370
2371 for (i = 0; i < MAX_TOD; i++) {
2372 channel = &idtcm->channel[i];
2373 if (channel->ptp_clock)
2374 ptp_clock_unregister(channel->ptp_clock);
2375 }
2376}
2377
2378static void set_default_masks(struct idtcm *idtcm)
2379{
2380 idtcm->tod_mask = DEFAULT_TOD_MASK;
2381 idtcm->extts_mask = 0;
2382
2383 idtcm->channel[0].tod = 0;
2384 idtcm->channel[1].tod = 1;
2385 idtcm->channel[2].tod = 2;
2386 idtcm->channel[3].tod = 3;
2387
2388 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2389 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2390 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2391 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
2392
2393 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2394 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2395 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2396 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2397}
2398
2399static int idtcm_probe(struct platform_device *pdev)
2400{
2401 struct rsmu_ddata *ddata = dev_get_drvdata(pdev->dev.parent);
2402 struct idtcm *idtcm;
2403 int err;
2404 u8 i;
2405
2406 idtcm = devm_kzalloc(&pdev->dev, sizeof(struct idtcm), GFP_KERNEL);
2407
2408 if (!idtcm)
2409 return -ENOMEM;
2410
2411 idtcm->dev = &pdev->dev;
2412 idtcm->mfd = pdev->dev.parent;
2413 idtcm->lock = &ddata->lock;
2414 idtcm->regmap = ddata->regmap;
2415 idtcm->calculate_overhead_flag = 0;
2416
2417 INIT_DELAYED_WORK(&idtcm->extts_work, idtcm_extts_check);
2418
2419 set_default_masks(idtcm);
2420
2421 mutex_lock(idtcm->lock);
2422
2423 idtcm_set_version_info(idtcm);
2424
2425 err = idtcm_load_firmware(idtcm, &pdev->dev);
2426
2427 if (err)
2428 dev_warn(idtcm->dev, "loading firmware failed with %d", err);
2429
2430 wait_for_chip_ready(idtcm);
2431
2432 if (idtcm->tod_mask) {
2433 for (i = 0; i < MAX_TOD; i++) {
2434 if (idtcm->tod_mask & (1 << i))
2435 err = idtcm_enable_channel(idtcm, i);
2436 else
2437 err = idtcm_enable_extts_channel(idtcm, i);
2438 if (err) {
2439 dev_err(idtcm->dev,
2440 "idtcm_enable_channel %d failed!", i);
2441 break;
2442 }
2443 }
2444 } else {
2445 dev_err(idtcm->dev,
2446 "no PLLs flagged as PHCs, nothing to do");
2447 err = -ENODEV;
2448 }
2449
2450 mutex_unlock(idtcm->lock);
2451
2452 if (err) {
2453 ptp_clock_unregister_all(idtcm);
2454 return err;
2455 }
2456
2457 platform_set_drvdata(pdev, idtcm);
2458
2459 return 0;
2460}
2461
2462static int idtcm_remove(struct platform_device *pdev)
2463{
2464 struct idtcm *idtcm = platform_get_drvdata(pdev);
2465
2466 idtcm->extts_mask = 0;
2467 ptp_clock_unregister_all(idtcm);
2468 cancel_delayed_work_sync(&idtcm->extts_work);
2469
2470 return 0;
2471}
2472
2473static struct platform_driver idtcm_driver = {
2474 .driver = {
2475 .name = "8a3400x-phc",
2476 },
2477 .probe = idtcm_probe,
2478 .remove = idtcm_remove,
2479};
2480
2481module_platform_driver(idtcm_driver);