Loading...
Note: File does not exist in v5.9.
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel Moorefield SoC pinctrl driver
4 *
5 * Copyright (C) 2022, Intel Corporation
6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 */
8
9#include <linux/bits.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/mod_devicetable.h>
14#include <linux/platform_device.h>
15#include <linux/seq_file.h>
16
17#include <linux/pinctrl/pinconf-generic.h>
18#include <linux/pinctrl/pinconf.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h>
21
22#include "pinctrl-intel.h"
23
24#define MOFLD_FAMILY_NR 64
25#define MOFLD_FAMILY_LEN 0x400
26
27#define SLEW_OFFSET 0x000
28#define BUFCFG_OFFSET 0x100
29#define MISC_OFFSET 0x300
30
31#define BUFCFG_PINMODE_SHIFT 0
32#define BUFCFG_PINMODE_MASK GENMASK(2, 0)
33#define BUFCFG_PINMODE_GPIO 0
34#define BUFCFG_PUPD_VAL_SHIFT 4
35#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4)
36#define BUFCFG_PUPD_VAL_2K 0
37#define BUFCFG_PUPD_VAL_20K 1
38#define BUFCFG_PUPD_VAL_50K 2
39#define BUFCFG_PUPD_VAL_910 3
40#define BUFCFG_PU_EN BIT(8)
41#define BUFCFG_PD_EN BIT(9)
42#define BUFCFG_Px_EN_MASK GENMASK(9, 8)
43#define BUFCFG_SLEWSEL BIT(10)
44#define BUFCFG_OVINEN BIT(12)
45#define BUFCFG_OVINEN_EN BIT(13)
46#define BUFCFG_OVINEN_MASK GENMASK(13, 12)
47#define BUFCFG_OVOUTEN BIT(14)
48#define BUFCFG_OVOUTEN_EN BIT(15)
49#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14)
50#define BUFCFG_INDATAOV_VAL BIT(16)
51#define BUFCFG_INDATAOV_EN BIT(17)
52#define BUFCFG_INDATAOV_MASK GENMASK(17, 16)
53#define BUFCFG_OUTDATAOV_VAL BIT(18)
54#define BUFCFG_OUTDATAOV_EN BIT(19)
55#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18)
56#define BUFCFG_OD_EN BIT(21)
57
58/**
59 * struct mofld_family - Intel pin family description
60 * @barno: MMIO BAR number where registers for this family reside
61 * @pin_base: Starting pin of pins in this family
62 * @npins: Number of pins in this family
63 * @protected: True if family is protected by access
64 * @regs: family specific common registers
65 */
66struct mofld_family {
67 unsigned int barno;
68 unsigned int pin_base;
69 size_t npins;
70 bool protected;
71 void __iomem *regs;
72};
73
74#define MOFLD_FAMILY(b, s, e) \
75 { \
76 .barno = (b), \
77 .pin_base = (s), \
78 .npins = (e) - (s) + 1, \
79 }
80
81static const struct pinctrl_pin_desc mofld_pins[] = {
82 /* ULPI (13 pins) */
83 PINCTRL_PIN(0, "GP101_ULPI_CLK"),
84 PINCTRL_PIN(1, "GP136_ULPI_D0"),
85 PINCTRL_PIN(2, "GP143_ULPI_D1"),
86 PINCTRL_PIN(3, "GP144_ULPI_D2"),
87 PINCTRL_PIN(4, "GP145_ULPI_D3"),
88 PINCTRL_PIN(5, "GP146_ULPI_D4"),
89 PINCTRL_PIN(6, "GP147_ULPI_D5"),
90 PINCTRL_PIN(7, "GP148_ULPI_D6"),
91 PINCTRL_PIN(8, "GP149_ULPI_D7"),
92 PINCTRL_PIN(9, "ULPI_DIR"),
93 PINCTRL_PIN(10, "ULPI_NXT"),
94 PINCTRL_PIN(11, "ULPI_REFCLK"),
95 PINCTRL_PIN(12, "ULPI_STP"),
96 /* eMMC (12 pins) */
97 PINCTRL_PIN(13, "EMMC_CLK"),
98 PINCTRL_PIN(14, "EMMC_CMD"),
99 PINCTRL_PIN(15, "EMMC_D0"),
100 PINCTRL_PIN(16, "EMMC_D1"),
101 PINCTRL_PIN(17, "EMMC_D2"),
102 PINCTRL_PIN(18, "EMMC_D3"),
103 PINCTRL_PIN(19, "EMMC_D4"),
104 PINCTRL_PIN(20, "EMMC_D5"),
105 PINCTRL_PIN(21, "EMMC_D6"),
106 PINCTRL_PIN(22, "EMMC_D7"),
107 PINCTRL_PIN(23, "EMMC_RST_N"),
108 PINCTRL_PIN(24, "EMMC_RCLK"),
109 /* SDIO (20 pins) */
110 PINCTRL_PIN(25, "GP77_SD_CD"),
111 PINCTRL_PIN(26, "GP78_SD_CLK"),
112 PINCTRL_PIN(27, "GP79_SD_CMD"),
113 PINCTRL_PIN(28, "GP80_SD_D0"),
114 PINCTRL_PIN(29, "GP81_SD_D1"),
115 PINCTRL_PIN(30, "GP82_SD_D2"),
116 PINCTRL_PIN(31, "GP83_SD_D3"),
117 PINCTRL_PIN(32, "GP84_SD_LS_CLK_FB"),
118 PINCTRL_PIN(33, "GP85_SD_LS_CMD_DIR"),
119 PINCTRL_PIN(34, "GP86_SD_LS_D_DIR"),
120 PINCTRL_PIN(35, "GP88_SD_LS_SEL"),
121 PINCTRL_PIN(36, "GP87_SD_PD"),
122 PINCTRL_PIN(37, "GP89_SD_WP"),
123 PINCTRL_PIN(38, "GP90_SDIO_CLK"),
124 PINCTRL_PIN(39, "GP91_SDIO_CMD"),
125 PINCTRL_PIN(40, "GP92_SDIO_D0"),
126 PINCTRL_PIN(41, "GP93_SDIO_D1"),
127 PINCTRL_PIN(42, "GP94_SDIO_D2"),
128 PINCTRL_PIN(43, "GP95_SDIO_D3"),
129 PINCTRL_PIN(44, "GP96_SDIO_PD"),
130 /* HSI (8 pins) */
131 PINCTRL_PIN(45, "HSI_ACDATA"),
132 PINCTRL_PIN(46, "HSI_ACFLAG"),
133 PINCTRL_PIN(47, "HSI_ACREADY"),
134 PINCTRL_PIN(48, "HSI_ACWAKE"),
135 PINCTRL_PIN(49, "HSI_CADATA"),
136 PINCTRL_PIN(50, "HSI_CAFLAG"),
137 PINCTRL_PIN(51, "HSI_CAREADY"),
138 PINCTRL_PIN(52, "HSI_CAWAKE"),
139 /* SSP Audio (14 pins) */
140 PINCTRL_PIN(53, "GP70"),
141 PINCTRL_PIN(54, "GP71"),
142 PINCTRL_PIN(55, "GP32_I2S_0_CLK"),
143 PINCTRL_PIN(56, "GP33_I2S_0_FS"),
144 PINCTRL_PIN(57, "GP34_I2S_0_RXD"),
145 PINCTRL_PIN(58, "GP35_I2S_0_TXD"),
146 PINCTRL_PIN(59, "GP36_I2S_1_CLK"),
147 PINCTRL_PIN(60, "GP37_I2S_1_FS"),
148 PINCTRL_PIN(61, "GP38_I2S_1_RXD"),
149 PINCTRL_PIN(62, "GP39_I2S_1_TXD"),
150 PINCTRL_PIN(63, "GP40_I2S_2_CLK"),
151 PINCTRL_PIN(64, "GP41_I2S_2_FS"),
152 PINCTRL_PIN(65, "GP42_I2S_2_RXD"),
153 PINCTRL_PIN(66, "GP43_I2S_2_TXD"),
154 /* GP SSP (22 pins) */
155 PINCTRL_PIN(67, "GP120_SPI_0_CLK"),
156 PINCTRL_PIN(68, "GP121_SPI_0_SS"),
157 PINCTRL_PIN(69, "GP122_SPI_0_RXD"),
158 PINCTRL_PIN(70, "GP123_SPI_0_TXD"),
159 PINCTRL_PIN(71, "GP102_SPI_1_CLK"),
160 PINCTRL_PIN(72, "GP103_SPI_1_SS0"),
161 PINCTRL_PIN(73, "GP104_SPI_1_SS1"),
162 PINCTRL_PIN(74, "GP105_SPI_1_SS2"),
163 PINCTRL_PIN(75, "GP106_SPI_1_SS3"),
164 PINCTRL_PIN(76, "GP107_SPI_1_RXD"),
165 PINCTRL_PIN(77, "GP108_SPI_1_TXD"),
166 PINCTRL_PIN(78, "GP109_SPI_2_CLK"),
167 PINCTRL_PIN(79, "GP110_SPI_2_SS0"),
168 PINCTRL_PIN(80, "GP111_SPI_2_SS1"),
169 PINCTRL_PIN(81, "GP112_SPI_2_SS2"),
170 PINCTRL_PIN(82, "GP113_SPI_2_SS3"),
171 PINCTRL_PIN(83, "GP114_SPI_2_RXD"),
172 PINCTRL_PIN(84, "GP115_SPI_2_TXD"),
173 PINCTRL_PIN(85, "GP116_SPI_3_CLK"),
174 PINCTRL_PIN(86, "GP117_SPI_3_SS"),
175 PINCTRL_PIN(87, "GP118_SPI_3_RXD"),
176 PINCTRL_PIN(88, "GP119_SPI_3_TXD"),
177 /* I2C (20 pins) */
178 PINCTRL_PIN(89, "I2C_0_SCL"),
179 PINCTRL_PIN(90, "I2C_0_SDA"),
180 PINCTRL_PIN(91, "GP19_I2C_1_SCL"),
181 PINCTRL_PIN(92, "GP20_I2C_1_SDA"),
182 PINCTRL_PIN(93, "GP21_I2C_2_SCL"),
183 PINCTRL_PIN(94, "GP22_I2C_2_SDA"),
184 PINCTRL_PIN(95, "GP17_I2C_3_SCL_HDMI"),
185 PINCTRL_PIN(96, "GP18_I2C_3_SDA_HDMI"),
186 PINCTRL_PIN(97, "GP23_I2C_4_SCL"),
187 PINCTRL_PIN(98, "GP24_I2C_4_SDA"),
188 PINCTRL_PIN(99, "GP25_I2C_5_SCL"),
189 PINCTRL_PIN(100, "GP26_I2C_5_SDA"),
190 PINCTRL_PIN(101, "GP27_I2C_6_SCL"),
191 PINCTRL_PIN(102, "GP28_I2C_6_SDA"),
192 PINCTRL_PIN(103, "GP29_I2C_7_SCL"),
193 PINCTRL_PIN(104, "GP30_I2C_7_SDA"),
194 PINCTRL_PIN(105, "I2C_8_SCL"),
195 PINCTRL_PIN(106, "I2C_8_SDA"),
196 PINCTRL_PIN(107, "I2C_9_SCL"),
197 PINCTRL_PIN(108, "I2C_9_SDA"),
198 /* UART (23 pins) */
199 PINCTRL_PIN(109, "GP124_UART_0_CTS"),
200 PINCTRL_PIN(110, "GP125_UART_0_RTS"),
201 PINCTRL_PIN(111, "GP126_UART_0_RX"),
202 PINCTRL_PIN(112, "GP127_UART_0_TX"),
203 PINCTRL_PIN(113, "GP128_UART_1_CTS"),
204 PINCTRL_PIN(114, "GP129_UART_1_RTS"),
205 PINCTRL_PIN(115, "GP130_UART_1_RX"),
206 PINCTRL_PIN(116, "GP131_UART_1_TX"),
207 PINCTRL_PIN(117, "GP132_UART_2_CTS"),
208 PINCTRL_PIN(118, "GP133_UART_2_RTS"),
209 PINCTRL_PIN(119, "GP134_UART_2_RX"),
210 PINCTRL_PIN(120, "GP135_UART_2_TX"),
211 PINCTRL_PIN(121, "GP97"),
212 PINCTRL_PIN(122, "GP154"),
213 PINCTRL_PIN(123, "GP155"),
214 PINCTRL_PIN(124, "GP156"),
215 PINCTRL_PIN(125, "GP157"),
216 PINCTRL_PIN(126, "GP158"),
217 PINCTRL_PIN(127, "GP159"),
218 PINCTRL_PIN(128, "GP160"),
219 PINCTRL_PIN(129, "GP161"),
220 PINCTRL_PIN(130, "GP12_PWM0"),
221 PINCTRL_PIN(131, "GP13_PWM1"),
222 /* GPIO South (20 pins) */
223 PINCTRL_PIN(132, "GP176"),
224 PINCTRL_PIN(133, "GP177"),
225 PINCTRL_PIN(134, "GP178"),
226 PINCTRL_PIN(135, "GP179"),
227 PINCTRL_PIN(136, "GP180"),
228 PINCTRL_PIN(137, "GP181"),
229 PINCTRL_PIN(138, "GP182_PWM2"),
230 PINCTRL_PIN(139, "GP183_PWM3"),
231 PINCTRL_PIN(140, "GP184"),
232 PINCTRL_PIN(141, "GP185"),
233 PINCTRL_PIN(142, "GP186"),
234 PINCTRL_PIN(143, "GP187"),
235 PINCTRL_PIN(144, "GP188"),
236 PINCTRL_PIN(145, "GP189"),
237 PINCTRL_PIN(146, "GP190"),
238 PINCTRL_PIN(147, "GP191"),
239 PINCTRL_PIN(148, "GP14"),
240 PINCTRL_PIN(149, "GP15"),
241 PINCTRL_PIN(150, "GP162"),
242 PINCTRL_PIN(151, "GP163"),
243 /* Camera Sideband (15 pins) */
244 PINCTRL_PIN(152, "GP0"),
245 PINCTRL_PIN(153, "GP1"),
246 PINCTRL_PIN(154, "GP2"),
247 PINCTRL_PIN(155, "GP3"),
248 PINCTRL_PIN(156, "GP4"),
249 PINCTRL_PIN(157, "GP5"),
250 PINCTRL_PIN(158, "GP6"),
251 PINCTRL_PIN(159, "GP7"),
252 PINCTRL_PIN(160, "GP8"),
253 PINCTRL_PIN(161, "GP9"),
254 PINCTRL_PIN(162, "GP10"),
255 PINCTRL_PIN(163, "GP11"),
256 PINCTRL_PIN(164, "GP16_HDMI_HPD"),
257 PINCTRL_PIN(165, "GP68_DSI_A_TE"),
258 PINCTRL_PIN(166, "GP69_DSI_C_TE"),
259 /* Clock (14 pins) */
260 PINCTRL_PIN(167, "GP137"),
261 PINCTRL_PIN(168, "GP138"),
262 PINCTRL_PIN(169, "GP139"),
263 PINCTRL_PIN(170, "GP140"),
264 PINCTRL_PIN(171, "GP141"),
265 PINCTRL_PIN(172, "GP142"),
266 PINCTRL_PIN(173, "GP98"),
267 PINCTRL_PIN(174, "OSC_CLK_CTRL0"),
268 PINCTRL_PIN(175, "OSC_CLK_CTRL1"),
269 PINCTRL_PIN(176, "OSC_CLK0"),
270 PINCTRL_PIN(177, "OSC_CLK1"),
271 PINCTRL_PIN(178, "OSC_CLK2"),
272 PINCTRL_PIN(179, "OSC_CLK3"),
273 PINCTRL_PIN(180, "OSC_CLK4"),
274 /* PMIC (15 pins) */
275 PINCTRL_PIN(181, "PROCHOT"),
276 PINCTRL_PIN(182, "RESETOUT"),
277 PINCTRL_PIN(183, "RTC_CLK"),
278 PINCTRL_PIN(184, "STANDBY"),
279 PINCTRL_PIN(185, "SVID_ALERT"),
280 PINCTRL_PIN(186, "SVID_CLK"),
281 PINCTRL_PIN(187, "SVID_D"),
282 PINCTRL_PIN(188, "THERMTRIP"),
283 PINCTRL_PIN(189, "PREQ"),
284 PINCTRL_PIN(190, "ZQ_A"),
285 PINCTRL_PIN(191, "ZQ_B"),
286 PINCTRL_PIN(192, "GP64_FAST_INT0"),
287 PINCTRL_PIN(193, "GP65_FAST_INT1"),
288 PINCTRL_PIN(194, "GP66_FAST_INT2"),
289 PINCTRL_PIN(195, "GP67_FAST_INT3"),
290 /* Keyboard (20 pins) */
291 PINCTRL_PIN(196, "GP44"),
292 PINCTRL_PIN(197, "GP45"),
293 PINCTRL_PIN(198, "GP46"),
294 PINCTRL_PIN(199, "GP47"),
295 PINCTRL_PIN(200, "GP48"),
296 PINCTRL_PIN(201, "GP49"),
297 PINCTRL_PIN(202, "GP50"),
298 PINCTRL_PIN(203, "GP51"),
299 PINCTRL_PIN(204, "GP52"),
300 PINCTRL_PIN(205, "GP53"),
301 PINCTRL_PIN(206, "GP54"),
302 PINCTRL_PIN(207, "GP55"),
303 PINCTRL_PIN(208, "GP56"),
304 PINCTRL_PIN(209, "GP57"),
305 PINCTRL_PIN(210, "GP58"),
306 PINCTRL_PIN(211, "GP59"),
307 PINCTRL_PIN(212, "GP60"),
308 PINCTRL_PIN(213, "GP61"),
309 PINCTRL_PIN(214, "GP62"),
310 PINCTRL_PIN(215, "GP63"),
311 /* GPIO North (13 pins) */
312 PINCTRL_PIN(216, "GP164"),
313 PINCTRL_PIN(217, "GP165"),
314 PINCTRL_PIN(218, "GP166"),
315 PINCTRL_PIN(219, "GP167"),
316 PINCTRL_PIN(220, "GP168_MJTAG_TCK"),
317 PINCTRL_PIN(221, "GP169_MJTAG_TDI"),
318 PINCTRL_PIN(222, "GP170_MJTAG_TDO"),
319 PINCTRL_PIN(223, "GP171_MJTAG_TMS"),
320 PINCTRL_PIN(224, "GP172_MJTAG_TRST"),
321 PINCTRL_PIN(225, "GP173"),
322 PINCTRL_PIN(226, "GP174"),
323 PINCTRL_PIN(227, "GP175"),
324 PINCTRL_PIN(228, "GP176"),
325 /* PTI (22 pins) */
326 PINCTRL_PIN(229, "GP72_PTI_CLK"),
327 PINCTRL_PIN(230, "GP73_PTI_D0"),
328 PINCTRL_PIN(231, "GP74_PTI_D1"),
329 PINCTRL_PIN(232, "GP75_PTI_D2"),
330 PINCTRL_PIN(233, "GP76_PTI_D3"),
331 PINCTRL_PIN(234, "GP164"),
332 PINCTRL_PIN(235, "GP165"),
333 PINCTRL_PIN(236, "GP166"),
334 PINCTRL_PIN(237, "GP167"),
335 PINCTRL_PIN(238, "GP168_MJTAG_TCK"),
336 PINCTRL_PIN(239, "GP169_MJTAG_TDI"),
337 PINCTRL_PIN(240, "GP170_MJTAG_TDO"),
338 PINCTRL_PIN(241, "GP171_MJTAG_TMS"),
339 PINCTRL_PIN(242, "GP172_MJTAG_TRST"),
340 PINCTRL_PIN(243, "GP173"),
341 PINCTRL_PIN(244, "GP174"),
342 PINCTRL_PIN(245, "GP175"),
343 PINCTRL_PIN(246, "JTAG_TCK"),
344 PINCTRL_PIN(247, "JTAG_TDI"),
345 PINCTRL_PIN(248, "JTAG_TDO"),
346 PINCTRL_PIN(249, "JTAG_TMS"),
347 PINCTRL_PIN(250, "JTAG_TRST"),
348};
349
350static const struct mofld_family mofld_families[] = {
351 MOFLD_FAMILY(0, 0, 12),
352 MOFLD_FAMILY(1, 13, 24),
353 MOFLD_FAMILY(2, 25, 44),
354 MOFLD_FAMILY(3, 45, 52),
355 MOFLD_FAMILY(4, 53, 66),
356 MOFLD_FAMILY(5, 67, 88),
357 MOFLD_FAMILY(6, 89, 108),
358 MOFLD_FAMILY(7, 109, 131),
359 MOFLD_FAMILY(8, 132, 151),
360 MOFLD_FAMILY(9, 152, 166),
361 MOFLD_FAMILY(10, 167, 180),
362 MOFLD_FAMILY(11, 181, 195),
363 MOFLD_FAMILY(12, 196, 215),
364 MOFLD_FAMILY(13, 216, 228),
365 MOFLD_FAMILY(14, 229, 250),
366};
367
368/**
369 * struct mofld_pinctrl - Intel Merrifield pinctrl private structure
370 * @dev: Pointer to the device structure
371 * @lock: Lock to serialize register access
372 * @pctldesc: Pin controller description
373 * @pctldev: Pointer to the pin controller device
374 * @families: Array of families this pinctrl handles
375 * @nfamilies: Number of families in the array
376 * @functions: Array of functions
377 * @nfunctions: Number of functions in the array
378 * @groups: Array of pin groups
379 * @ngroups: Number of groups in the array
380 * @pins: Array of pins this pinctrl controls
381 * @npins: Number of pins in the array
382 */
383struct mofld_pinctrl {
384 struct device *dev;
385 raw_spinlock_t lock;
386 struct pinctrl_desc pctldesc;
387 struct pinctrl_dev *pctldev;
388
389 /* Pin controller configuration */
390 const struct mofld_family *families;
391 size_t nfamilies;
392 const struct intel_function *functions;
393 size_t nfunctions;
394 const struct intel_pingroup *groups;
395 size_t ngroups;
396 const struct pinctrl_pin_desc *pins;
397 size_t npins;
398};
399
400#define pin_to_bufno(f, p) ((p) - (f)->pin_base)
401
402static const struct mofld_family *mofld_get_family(struct mofld_pinctrl *mp, unsigned int pin)
403{
404 const struct mofld_family *family;
405 unsigned int i;
406
407 for (i = 0; i < mp->nfamilies; i++) {
408 family = &mp->families[i];
409 if (pin >= family->pin_base &&
410 pin < family->pin_base + family->npins)
411 return family;
412 }
413
414 dev_warn(mp->dev, "failed to find family for pin %u\n", pin);
415 return NULL;
416}
417
418static bool mofld_buf_available(struct mofld_pinctrl *mp, unsigned int pin)
419{
420 const struct mofld_family *family;
421
422 family = mofld_get_family(mp, pin);
423 if (!family)
424 return false;
425
426 return !family->protected;
427}
428
429static void __iomem *mofld_get_bufcfg(struct mofld_pinctrl *mp, unsigned int pin)
430{
431 const struct mofld_family *family;
432 unsigned int bufno;
433
434 family = mofld_get_family(mp, pin);
435 if (!family)
436 return NULL;
437
438 bufno = pin_to_bufno(family, pin);
439 return family->regs + BUFCFG_OFFSET + bufno * 4;
440}
441
442static int mofld_read_bufcfg(struct mofld_pinctrl *mp, unsigned int pin, u32 *value)
443{
444 void __iomem *bufcfg;
445
446 if (!mofld_buf_available(mp, pin))
447 return -EBUSY;
448
449 bufcfg = mofld_get_bufcfg(mp, pin);
450 *value = readl(bufcfg);
451
452 return 0;
453}
454
455static void mofld_update_bufcfg(struct mofld_pinctrl *mp, unsigned int pin, u32 bits, u32 mask)
456{
457 void __iomem *bufcfg;
458 u32 value;
459
460 bufcfg = mofld_get_bufcfg(mp, pin);
461 value = readl(bufcfg);
462
463 value &= ~mask;
464 value |= bits & mask;
465
466 writel(value, bufcfg);
467}
468
469static int mofld_get_groups_count(struct pinctrl_dev *pctldev)
470{
471 struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
472
473 return mp->ngroups;
474}
475
476static const char *mofld_get_group_name(struct pinctrl_dev *pctldev, unsigned int group)
477{
478 struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
479
480 return mp->groups[group].grp.name;
481}
482
483static int mofld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
484 const unsigned int **pins, unsigned int *npins)
485{
486 struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
487
488 *pins = mp->groups[group].grp.pins;
489 *npins = mp->groups[group].grp.npins;
490 return 0;
491}
492
493static void mofld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
494 unsigned int pin)
495{
496 struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
497 u32 value, mode;
498 int ret;
499
500 ret = mofld_read_bufcfg(mp, pin, &value);
501 if (ret) {
502 seq_puts(s, "not available");
503 return;
504 }
505
506 mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
507 if (!mode)
508 seq_puts(s, "GPIO ");
509 else
510 seq_printf(s, "mode %d ", mode);
511
512 seq_printf(s, "0x%08x", value);
513}
514
515static const struct pinctrl_ops mofld_pinctrl_ops = {
516 .get_groups_count = mofld_get_groups_count,
517 .get_group_name = mofld_get_group_name,
518 .get_group_pins = mofld_get_group_pins,
519 .pin_dbg_show = mofld_pin_dbg_show,
520};
521
522static int mofld_get_functions_count(struct pinctrl_dev *pctldev)
523{
524 struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
525
526 return mp->nfunctions;
527}
528
529static const char *mofld_get_function_name(struct pinctrl_dev *pctldev, unsigned int function)
530{
531 struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
532
533 return mp->functions[function].name;
534}
535
536static int mofld_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
537 const char * const **groups, unsigned int * const ngroups)
538{
539 struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
540
541 *groups = mp->functions[function].groups;
542 *ngroups = mp->functions[function].ngroups;
543 return 0;
544}
545
546static int mofld_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
547 unsigned int group)
548{
549 struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
550 const struct intel_pingroup *grp = &mp->groups[group];
551 u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
552 u32 mask = BUFCFG_PINMODE_MASK;
553 unsigned long flags;
554 unsigned int i;
555
556 /*
557 * All pins in the groups needs to be accessible and writable
558 * before we can enable the mux for this group.
559 */
560 for (i = 0; i < grp->grp.npins; i++) {
561 if (!mofld_buf_available(mp, grp->grp.pins[i]))
562 return -EBUSY;
563 }
564
565 /* Now enable the mux setting for each pin in the group */
566 raw_spin_lock_irqsave(&mp->lock, flags);
567 for (i = 0; i < grp->grp.npins; i++)
568 mofld_update_bufcfg(mp, grp->grp.pins[i], bits, mask);
569 raw_spin_unlock_irqrestore(&mp->lock, flags);
570
571 return 0;
572}
573
574static int mofld_gpio_request_enable(struct pinctrl_dev *pctldev,
575 struct pinctrl_gpio_range *range,
576 unsigned int pin)
577{
578 struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
579 u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
580 u32 mask = BUFCFG_PINMODE_MASK;
581 unsigned long flags;
582
583 if (!mofld_buf_available(mp, pin))
584 return -EBUSY;
585
586 raw_spin_lock_irqsave(&mp->lock, flags);
587 mofld_update_bufcfg(mp, pin, bits, mask);
588 raw_spin_unlock_irqrestore(&mp->lock, flags);
589
590 return 0;
591}
592
593static const struct pinmux_ops mofld_pinmux_ops = {
594 .get_functions_count = mofld_get_functions_count,
595 .get_function_name = mofld_get_function_name,
596 .get_function_groups = mofld_get_function_groups,
597 .set_mux = mofld_pinmux_set_mux,
598 .gpio_request_enable = mofld_gpio_request_enable,
599};
600
601static int mofld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
602 unsigned long *config)
603{
604 struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
605 enum pin_config_param param = pinconf_to_config_param(*config);
606 u32 value, term;
607 u16 arg = 0;
608 int ret;
609
610 ret = mofld_read_bufcfg(mp, pin, &value);
611 if (ret)
612 return -ENOTSUPP;
613
614 term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
615
616 switch (param) {
617 case PIN_CONFIG_BIAS_DISABLE:
618 if (value & BUFCFG_Px_EN_MASK)
619 return -EINVAL;
620 break;
621
622 case PIN_CONFIG_BIAS_PULL_UP:
623 if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN)
624 return -EINVAL;
625
626 switch (term) {
627 case BUFCFG_PUPD_VAL_910:
628 arg = 910;
629 break;
630 case BUFCFG_PUPD_VAL_2K:
631 arg = 2000;
632 break;
633 case BUFCFG_PUPD_VAL_20K:
634 arg = 20000;
635 break;
636 case BUFCFG_PUPD_VAL_50K:
637 arg = 50000;
638 break;
639 }
640
641 break;
642
643 case PIN_CONFIG_BIAS_PULL_DOWN:
644 if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN)
645 return -EINVAL;
646
647 switch (term) {
648 case BUFCFG_PUPD_VAL_910:
649 arg = 910;
650 break;
651 case BUFCFG_PUPD_VAL_2K:
652 arg = 2000;
653 break;
654 case BUFCFG_PUPD_VAL_20K:
655 arg = 20000;
656 break;
657 case BUFCFG_PUPD_VAL_50K:
658 arg = 50000;
659 break;
660 }
661
662 break;
663
664 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
665 if (!(value & BUFCFG_OD_EN))
666 return -EINVAL;
667 break;
668
669 case PIN_CONFIG_SLEW_RATE:
670 if (!(value & BUFCFG_SLEWSEL))
671 arg = 0;
672 else
673 arg = 1;
674 break;
675
676 default:
677 return -ENOTSUPP;
678 }
679
680 *config = pinconf_to_config_packed(param, arg);
681 return 0;
682}
683
684static int mofld_config_set_pin(struct mofld_pinctrl *mp, unsigned int pin,
685 unsigned long config)
686{
687 unsigned int param = pinconf_to_config_param(config);
688 unsigned int arg = pinconf_to_config_argument(config);
689 u32 bits = 0, mask = 0;
690 unsigned long flags;
691
692 switch (param) {
693 case PIN_CONFIG_BIAS_DISABLE:
694 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
695 break;
696
697 case PIN_CONFIG_BIAS_PULL_UP:
698 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
699 bits |= BUFCFG_PU_EN;
700
701 switch (arg) {
702 case 50000:
703 bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
704 break;
705 case 20000:
706 bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
707 break;
708 case 2000:
709 bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
710 break;
711 default:
712 return -EINVAL;
713 }
714
715 break;
716
717 case PIN_CONFIG_BIAS_PULL_DOWN:
718 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
719 bits |= BUFCFG_PD_EN;
720
721 switch (arg) {
722 case 50000:
723 bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
724 break;
725 case 20000:
726 bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
727 break;
728 case 2000:
729 bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
730 break;
731 default:
732 return -EINVAL;
733 }
734
735 break;
736
737 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
738 mask |= BUFCFG_OD_EN;
739 if (arg)
740 bits |= BUFCFG_OD_EN;
741 break;
742
743 case PIN_CONFIG_SLEW_RATE:
744 mask |= BUFCFG_SLEWSEL;
745 if (arg)
746 bits |= BUFCFG_SLEWSEL;
747 break;
748 }
749
750 raw_spin_lock_irqsave(&mp->lock, flags);
751 mofld_update_bufcfg(mp, pin, bits, mask);
752 raw_spin_unlock_irqrestore(&mp->lock, flags);
753
754 return 0;
755}
756
757static int mofld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
758 unsigned long *configs, unsigned int nconfigs)
759{
760 struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
761 unsigned int i;
762 int ret;
763
764 if (!mofld_buf_available(mp, pin))
765 return -ENOTSUPP;
766
767 for (i = 0; i < nconfigs; i++) {
768 switch (pinconf_to_config_param(configs[i])) {
769 case PIN_CONFIG_BIAS_DISABLE:
770 case PIN_CONFIG_BIAS_PULL_UP:
771 case PIN_CONFIG_BIAS_PULL_DOWN:
772 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
773 case PIN_CONFIG_SLEW_RATE:
774 ret = mofld_config_set_pin(mp, pin, configs[i]);
775 if (ret)
776 return ret;
777 break;
778
779 default:
780 return -ENOTSUPP;
781 }
782 }
783
784 return 0;
785}
786
787static int mofld_config_group_get(struct pinctrl_dev *pctldev, unsigned int group,
788 unsigned long *config)
789{
790 const unsigned int *pins;
791 unsigned int npins;
792 int ret;
793
794 ret = mofld_get_group_pins(pctldev, group, &pins, &npins);
795 if (ret)
796 return ret;
797
798 ret = mofld_config_get(pctldev, pins[0], config);
799 if (ret)
800 return ret;
801
802 return 0;
803}
804
805static int mofld_config_group_set(struct pinctrl_dev *pctldev, unsigned int group,
806 unsigned long *configs, unsigned int num_configs)
807{
808 const unsigned int *pins;
809 unsigned int npins;
810 int i, ret;
811
812 ret = mofld_get_group_pins(pctldev, group, &pins, &npins);
813 if (ret)
814 return ret;
815
816 for (i = 0; i < npins; i++) {
817 ret = mofld_config_set(pctldev, pins[i], configs, num_configs);
818 if (ret)
819 return ret;
820 }
821
822 return 0;
823}
824
825static const struct pinconf_ops mofld_pinconf_ops = {
826 .is_generic = true,
827 .pin_config_get = mofld_config_get,
828 .pin_config_set = mofld_config_set,
829 .pin_config_group_get = mofld_config_group_get,
830 .pin_config_group_set = mofld_config_group_set,
831};
832
833static const struct pinctrl_desc mofld_pinctrl_desc = {
834 .pctlops = &mofld_pinctrl_ops,
835 .pmxops = &mofld_pinmux_ops,
836 .confops = &mofld_pinconf_ops,
837 .owner = THIS_MODULE,
838};
839
840static int mofld_pinctrl_probe(struct platform_device *pdev)
841{
842 struct device *dev = &pdev->dev;
843 struct mofld_family *families;
844 struct mofld_pinctrl *mp;
845 void __iomem *regs;
846 size_t nfamilies;
847 unsigned int i;
848
849 mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
850 if (!mp)
851 return -ENOMEM;
852
853 mp->dev = dev;
854 raw_spin_lock_init(&mp->lock);
855
856 regs = devm_platform_ioremap_resource(pdev, 0);
857 if (IS_ERR(regs))
858 return PTR_ERR(regs);
859
860 nfamilies = ARRAY_SIZE(mofld_families),
861 families = devm_kmemdup(dev, mofld_families, sizeof(mofld_families), GFP_KERNEL);
862 if (!families)
863 return -ENOMEM;
864
865 /* Splice memory resource by chunk per family */
866 for (i = 0; i < nfamilies; i++) {
867 struct mofld_family *family = &families[i];
868
869 family->regs = regs + family->barno * MOFLD_FAMILY_LEN;
870 }
871
872 mp->families = families;
873 mp->nfamilies = nfamilies;
874 mp->pctldesc = mofld_pinctrl_desc;
875 mp->pctldesc.name = dev_name(dev);
876 mp->pctldesc.pins = mofld_pins;
877 mp->pctldesc.npins = ARRAY_SIZE(mofld_pins);
878
879 mp->pctldev = devm_pinctrl_register(dev, &mp->pctldesc, mp);
880 if (IS_ERR(mp->pctldev))
881 return PTR_ERR(mp->pctldev);
882
883 platform_set_drvdata(pdev, mp);
884 return 0;
885}
886
887static const struct acpi_device_id mofld_acpi_table[] = {
888 { "INTC1003" },
889 { }
890};
891MODULE_DEVICE_TABLE(acpi, mofld_acpi_table);
892
893static struct platform_driver mofld_pinctrl_driver = {
894 .probe = mofld_pinctrl_probe,
895 .driver = {
896 .name = "pinctrl-moorefield",
897 .acpi_match_table = mofld_acpi_table,
898 },
899};
900
901static int __init mofld_pinctrl_init(void)
902{
903 return platform_driver_register(&mofld_pinctrl_driver);
904}
905subsys_initcall(mofld_pinctrl_init);
906
907static void __exit mofld_pinctrl_exit(void)
908{
909 platform_driver_unregister(&mofld_pinctrl_driver);
910}
911module_exit(mofld_pinctrl_exit);
912
913MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
914MODULE_DESCRIPTION("Intel Moorefield SoC pinctrl driver");
915MODULE_LICENSE("GPL v2");
916MODULE_ALIAS("platform:pinctrl-moorefield");