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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
9 */
10
11#include <linux/delay.h>
12#include <linux/of.h>
13#include <linux/types.h>
14
15#include "../../pci.h"
16#include "pcie-designware.h"
17
18/*
19 * These interfaces resemble the pci_find_*capability() interfaces, but these
20 * are for configuring host controllers, which are bridges *to* PCI devices but
21 * are not PCI devices themselves.
22 */
23static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
24 u8 cap)
25{
26 u8 cap_id, next_cap_ptr;
27 u16 reg;
28
29 if (!cap_ptr)
30 return 0;
31
32 reg = dw_pcie_readw_dbi(pci, cap_ptr);
33 cap_id = (reg & 0x00ff);
34
35 if (cap_id > PCI_CAP_ID_MAX)
36 return 0;
37
38 if (cap_id == cap)
39 return cap_ptr;
40
41 next_cap_ptr = (reg & 0xff00) >> 8;
42 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
43}
44
45u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
46{
47 u8 next_cap_ptr;
48 u16 reg;
49
50 reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
51 next_cap_ptr = (reg & 0x00ff);
52
53 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
54}
55EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
56
57static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
58 u8 cap)
59{
60 u32 header;
61 int ttl;
62 int pos = PCI_CFG_SPACE_SIZE;
63
64 /* minimum 8 bytes per capability */
65 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
66
67 if (start)
68 pos = start;
69
70 header = dw_pcie_readl_dbi(pci, pos);
71 /*
72 * If we have no capabilities, this is indicated by cap ID,
73 * cap version and next pointer all being 0.
74 */
75 if (header == 0)
76 return 0;
77
78 while (ttl-- > 0) {
79 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
80 return pos;
81
82 pos = PCI_EXT_CAP_NEXT(header);
83 if (pos < PCI_CFG_SPACE_SIZE)
84 break;
85
86 header = dw_pcie_readl_dbi(pci, pos);
87 }
88
89 return 0;
90}
91
92u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
93{
94 return dw_pcie_find_next_ext_capability(pci, 0, cap);
95}
96EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
97
98int dw_pcie_read(void __iomem *addr, int size, u32 *val)
99{
100 if (!IS_ALIGNED((uintptr_t)addr, size)) {
101 *val = 0;
102 return PCIBIOS_BAD_REGISTER_NUMBER;
103 }
104
105 if (size == 4) {
106 *val = readl(addr);
107 } else if (size == 2) {
108 *val = readw(addr);
109 } else if (size == 1) {
110 *val = readb(addr);
111 } else {
112 *val = 0;
113 return PCIBIOS_BAD_REGISTER_NUMBER;
114 }
115
116 return PCIBIOS_SUCCESSFUL;
117}
118EXPORT_SYMBOL_GPL(dw_pcie_read);
119
120int dw_pcie_write(void __iomem *addr, int size, u32 val)
121{
122 if (!IS_ALIGNED((uintptr_t)addr, size))
123 return PCIBIOS_BAD_REGISTER_NUMBER;
124
125 if (size == 4)
126 writel(val, addr);
127 else if (size == 2)
128 writew(val, addr);
129 else if (size == 1)
130 writeb(val, addr);
131 else
132 return PCIBIOS_BAD_REGISTER_NUMBER;
133
134 return PCIBIOS_SUCCESSFUL;
135}
136EXPORT_SYMBOL_GPL(dw_pcie_write);
137
138u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size)
139{
140 int ret;
141 u32 val;
142
143 if (pci->ops->read_dbi)
144 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size);
145
146 ret = dw_pcie_read(pci->dbi_base + reg, size, &val);
147 if (ret)
148 dev_err(pci->dev, "Read DBI address failed\n");
149
150 return val;
151}
152EXPORT_SYMBOL_GPL(dw_pcie_read_dbi);
153
154void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
155{
156 int ret;
157
158 if (pci->ops->write_dbi) {
159 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val);
160 return;
161 }
162
163 ret = dw_pcie_write(pci->dbi_base + reg, size, val);
164 if (ret)
165 dev_err(pci->dev, "Write DBI address failed\n");
166}
167EXPORT_SYMBOL_GPL(dw_pcie_write_dbi);
168
169u32 dw_pcie_read_dbi2(struct dw_pcie *pci, u32 reg, size_t size)
170{
171 int ret;
172 u32 val;
173
174 if (pci->ops->read_dbi2)
175 return pci->ops->read_dbi2(pci, pci->dbi_base2, reg, size);
176
177 ret = dw_pcie_read(pci->dbi_base2 + reg, size, &val);
178 if (ret)
179 dev_err(pci->dev, "read DBI address failed\n");
180
181 return val;
182}
183
184void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
185{
186 int ret;
187
188 if (pci->ops->write_dbi2) {
189 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val);
190 return;
191 }
192
193 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
194 if (ret)
195 dev_err(pci->dev, "write DBI address failed\n");
196}
197
198u32 dw_pcie_read_atu(struct dw_pcie *pci, u32 reg, size_t size)
199{
200 int ret;
201 u32 val;
202
203 if (pci->ops->read_dbi)
204 return pci->ops->read_dbi(pci, pci->atu_base, reg, size);
205
206 ret = dw_pcie_read(pci->atu_base + reg, size, &val);
207 if (ret)
208 dev_err(pci->dev, "Read ATU address failed\n");
209
210 return val;
211}
212
213void dw_pcie_write_atu(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
214{
215 int ret;
216
217 if (pci->ops->write_dbi) {
218 pci->ops->write_dbi(pci, pci->atu_base, reg, size, val);
219 return;
220 }
221
222 ret = dw_pcie_write(pci->atu_base + reg, size, val);
223 if (ret)
224 dev_err(pci->dev, "Write ATU address failed\n");
225}
226
227static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
228{
229 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
230
231 return dw_pcie_readl_atu(pci, offset + reg);
232}
233
234static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
235 u32 val)
236{
237 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
238
239 dw_pcie_writel_atu(pci, offset + reg, val);
240}
241
242static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
243 int type, u64 cpu_addr,
244 u64 pci_addr, u32 size)
245{
246 u32 retries, val;
247 u64 limit_addr = cpu_addr + size - 1;
248
249 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
250 lower_32_bits(cpu_addr));
251 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
252 upper_32_bits(cpu_addr));
253 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_LIMIT,
254 lower_32_bits(limit_addr));
255 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT,
256 upper_32_bits(limit_addr));
257 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
258 lower_32_bits(pci_addr));
259 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
260 upper_32_bits(pci_addr));
261 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
262 type);
263 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
264 PCIE_ATU_ENABLE);
265
266 /*
267 * Make sure ATU enable takes effect before any subsequent config
268 * and I/O accesses.
269 */
270 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
271 val = dw_pcie_readl_ob_unroll(pci, index,
272 PCIE_ATU_UNR_REGION_CTRL2);
273 if (val & PCIE_ATU_ENABLE)
274 return;
275
276 mdelay(LINK_WAIT_IATU);
277 }
278 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
279}
280
281void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
282 u64 cpu_addr, u64 pci_addr, u32 size)
283{
284 u32 retries, val;
285
286 if (pci->ops->cpu_addr_fixup)
287 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
288
289 if (pci->iatu_unroll_enabled) {
290 dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
291 pci_addr, size);
292 return;
293 }
294
295 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
296 PCIE_ATU_REGION_OUTBOUND | index);
297 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
298 lower_32_bits(cpu_addr));
299 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
300 upper_32_bits(cpu_addr));
301 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
302 lower_32_bits(cpu_addr + size - 1));
303 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
304 lower_32_bits(pci_addr));
305 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
306 upper_32_bits(pci_addr));
307 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
308 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
309
310 /*
311 * Make sure ATU enable takes effect before any subsequent config
312 * and I/O accesses.
313 */
314 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
315 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
316 if (val & PCIE_ATU_ENABLE)
317 return;
318
319 mdelay(LINK_WAIT_IATU);
320 }
321 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
322}
323
324static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
325{
326 u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
327
328 return dw_pcie_readl_atu(pci, offset + reg);
329}
330
331static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
332 u32 val)
333{
334 u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
335
336 dw_pcie_writel_atu(pci, offset + reg, val);
337}
338
339static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
340 int bar, u64 cpu_addr,
341 enum dw_pcie_as_type as_type)
342{
343 int type;
344 u32 retries, val;
345
346 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
347 lower_32_bits(cpu_addr));
348 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
349 upper_32_bits(cpu_addr));
350
351 switch (as_type) {
352 case DW_PCIE_AS_MEM:
353 type = PCIE_ATU_TYPE_MEM;
354 break;
355 case DW_PCIE_AS_IO:
356 type = PCIE_ATU_TYPE_IO;
357 break;
358 default:
359 return -EINVAL;
360 }
361
362 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type);
363 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
364 PCIE_ATU_ENABLE |
365 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
366
367 /*
368 * Make sure ATU enable takes effect before any subsequent config
369 * and I/O accesses.
370 */
371 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
372 val = dw_pcie_readl_ib_unroll(pci, index,
373 PCIE_ATU_UNR_REGION_CTRL2);
374 if (val & PCIE_ATU_ENABLE)
375 return 0;
376
377 mdelay(LINK_WAIT_IATU);
378 }
379 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
380
381 return -EBUSY;
382}
383
384int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
385 u64 cpu_addr, enum dw_pcie_as_type as_type)
386{
387 int type;
388 u32 retries, val;
389
390 if (pci->iatu_unroll_enabled)
391 return dw_pcie_prog_inbound_atu_unroll(pci, index, bar,
392 cpu_addr, as_type);
393
394 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
395 index);
396 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
397 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));
398
399 switch (as_type) {
400 case DW_PCIE_AS_MEM:
401 type = PCIE_ATU_TYPE_MEM;
402 break;
403 case DW_PCIE_AS_IO:
404 type = PCIE_ATU_TYPE_IO;
405 break;
406 default:
407 return -EINVAL;
408 }
409
410 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
411 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE
412 | PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
413
414 /*
415 * Make sure ATU enable takes effect before any subsequent config
416 * and I/O accesses.
417 */
418 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
419 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
420 if (val & PCIE_ATU_ENABLE)
421 return 0;
422
423 mdelay(LINK_WAIT_IATU);
424 }
425 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
426
427 return -EBUSY;
428}
429
430void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
431 enum dw_pcie_region_type type)
432{
433 int region;
434
435 switch (type) {
436 case DW_PCIE_REGION_INBOUND:
437 region = PCIE_ATU_REGION_INBOUND;
438 break;
439 case DW_PCIE_REGION_OUTBOUND:
440 region = PCIE_ATU_REGION_OUTBOUND;
441 break;
442 default:
443 return;
444 }
445
446 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
447 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, (u32)~PCIE_ATU_ENABLE);
448}
449
450int dw_pcie_wait_for_link(struct dw_pcie *pci)
451{
452 int retries;
453
454 /* Check if the link is up or not */
455 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
456 if (dw_pcie_link_up(pci)) {
457 dev_info(pci->dev, "Link up\n");
458 return 0;
459 }
460 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
461 }
462
463 dev_info(pci->dev, "Phy link never came up\n");
464
465 return -ETIMEDOUT;
466}
467EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link);
468
469int dw_pcie_link_up(struct dw_pcie *pci)
470{
471 u32 val;
472
473 if (pci->ops->link_up)
474 return pci->ops->link_up(pci);
475
476 val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
477 return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
478 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
479}
480
481void dw_pcie_upconfig_setup(struct dw_pcie *pci)
482{
483 u32 val;
484
485 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);
486 val |= PORT_MLTI_UPCFG_SUPPORT;
487 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);
488}
489EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
490
491void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
492{
493 u32 reg, val;
494 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
495
496 reg = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
497 reg &= ~PCI_EXP_LNKCTL2_TLS;
498
499 switch (pcie_link_speed[link_gen]) {
500 case PCIE_SPEED_2_5GT:
501 reg |= PCI_EXP_LNKCTL2_TLS_2_5GT;
502 break;
503 case PCIE_SPEED_5_0GT:
504 reg |= PCI_EXP_LNKCTL2_TLS_5_0GT;
505 break;
506 case PCIE_SPEED_8_0GT:
507 reg |= PCI_EXP_LNKCTL2_TLS_8_0GT;
508 break;
509 case PCIE_SPEED_16_0GT:
510 reg |= PCI_EXP_LNKCTL2_TLS_16_0GT;
511 break;
512 default:
513 /* Use hardware capability */
514 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
515 val = FIELD_GET(PCI_EXP_LNKCAP_SLS, val);
516 reg &= ~PCI_EXP_LNKCTL2_HASD;
517 reg |= FIELD_PREP(PCI_EXP_LNKCTL2_TLS, val);
518 break;
519 }
520
521 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, reg);
522}
523EXPORT_SYMBOL_GPL(dw_pcie_link_set_max_speed);
524
525void dw_pcie_link_set_n_fts(struct dw_pcie *pci, u32 n_fts)
526{
527 u32 val;
528
529 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
530 val &= ~PORT_LOGIC_N_FTS_MASK;
531 val |= n_fts & PORT_LOGIC_N_FTS_MASK;
532 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
533}
534EXPORT_SYMBOL_GPL(dw_pcie_link_set_n_fts);
535
536static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
537{
538 u32 val;
539
540 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
541 if (val == 0xffffffff)
542 return 1;
543
544 return 0;
545}
546
547void dw_pcie_setup(struct dw_pcie *pci)
548{
549 int ret;
550 u32 val;
551 u32 lanes;
552 struct device *dev = pci->dev;
553 struct device_node *np = dev->of_node;
554
555 if (pci->version >= 0x480A || (!pci->version &&
556 dw_pcie_iatu_unroll_enabled(pci))) {
557 pci->iatu_unroll_enabled = true;
558 if (!pci->atu_base)
559 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
560 }
561 dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
562 "enabled" : "disabled");
563
564
565 ret = of_property_read_u32(np, "num-lanes", &lanes);
566 if (ret) {
567 dev_dbg(pci->dev, "property num-lanes isn't found\n");
568 return;
569 }
570
571 /* Set the number of lanes */
572 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
573 val &= ~PORT_LINK_MODE_MASK;
574 switch (lanes) {
575 case 1:
576 val |= PORT_LINK_MODE_1_LANES;
577 break;
578 case 2:
579 val |= PORT_LINK_MODE_2_LANES;
580 break;
581 case 4:
582 val |= PORT_LINK_MODE_4_LANES;
583 break;
584 case 8:
585 val |= PORT_LINK_MODE_8_LANES;
586 break;
587 default:
588 dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
589 return;
590 }
591 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
592
593 /* Set link width speed control register */
594 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
595 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
596 switch (lanes) {
597 case 1:
598 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
599 break;
600 case 2:
601 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
602 break;
603 case 4:
604 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
605 break;
606 case 8:
607 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
608 break;
609 }
610 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
611
612 if (of_property_read_bool(np, "snps,enable-cdm-check")) {
613 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
614 val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
615 PCIE_PL_CHK_REG_CHK_REG_START;
616 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
617 }
618}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
9 */
10
11#include <linux/align.h>
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/gpio/consumer.h>
16#include <linux/ioport.h>
17#include <linux/of.h>
18#include <linux/of_platform.h>
19#include <linux/sizes.h>
20#include <linux/types.h>
21
22#include "../../pci.h"
23#include "pcie-designware.h"
24
25static const char * const dw_pcie_app_clks[DW_PCIE_NUM_APP_CLKS] = {
26 [DW_PCIE_DBI_CLK] = "dbi",
27 [DW_PCIE_MSTR_CLK] = "mstr",
28 [DW_PCIE_SLV_CLK] = "slv",
29};
30
31static const char * const dw_pcie_core_clks[DW_PCIE_NUM_CORE_CLKS] = {
32 [DW_PCIE_PIPE_CLK] = "pipe",
33 [DW_PCIE_CORE_CLK] = "core",
34 [DW_PCIE_AUX_CLK] = "aux",
35 [DW_PCIE_REF_CLK] = "ref",
36};
37
38static const char * const dw_pcie_app_rsts[DW_PCIE_NUM_APP_RSTS] = {
39 [DW_PCIE_DBI_RST] = "dbi",
40 [DW_PCIE_MSTR_RST] = "mstr",
41 [DW_PCIE_SLV_RST] = "slv",
42};
43
44static const char * const dw_pcie_core_rsts[DW_PCIE_NUM_CORE_RSTS] = {
45 [DW_PCIE_NON_STICKY_RST] = "non-sticky",
46 [DW_PCIE_STICKY_RST] = "sticky",
47 [DW_PCIE_CORE_RST] = "core",
48 [DW_PCIE_PIPE_RST] = "pipe",
49 [DW_PCIE_PHY_RST] = "phy",
50 [DW_PCIE_HOT_RST] = "hot",
51 [DW_PCIE_PWR_RST] = "pwr",
52};
53
54static int dw_pcie_get_clocks(struct dw_pcie *pci)
55{
56 int i, ret;
57
58 for (i = 0; i < DW_PCIE_NUM_APP_CLKS; i++)
59 pci->app_clks[i].id = dw_pcie_app_clks[i];
60
61 for (i = 0; i < DW_PCIE_NUM_CORE_CLKS; i++)
62 pci->core_clks[i].id = dw_pcie_core_clks[i];
63
64 ret = devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_APP_CLKS,
65 pci->app_clks);
66 if (ret)
67 return ret;
68
69 return devm_clk_bulk_get_optional(pci->dev, DW_PCIE_NUM_CORE_CLKS,
70 pci->core_clks);
71}
72
73static int dw_pcie_get_resets(struct dw_pcie *pci)
74{
75 int i, ret;
76
77 for (i = 0; i < DW_PCIE_NUM_APP_RSTS; i++)
78 pci->app_rsts[i].id = dw_pcie_app_rsts[i];
79
80 for (i = 0; i < DW_PCIE_NUM_CORE_RSTS; i++)
81 pci->core_rsts[i].id = dw_pcie_core_rsts[i];
82
83 ret = devm_reset_control_bulk_get_optional_shared(pci->dev,
84 DW_PCIE_NUM_APP_RSTS,
85 pci->app_rsts);
86 if (ret)
87 return ret;
88
89 ret = devm_reset_control_bulk_get_optional_exclusive(pci->dev,
90 DW_PCIE_NUM_CORE_RSTS,
91 pci->core_rsts);
92 if (ret)
93 return ret;
94
95 pci->pe_rst = devm_gpiod_get_optional(pci->dev, "reset", GPIOD_OUT_HIGH);
96 if (IS_ERR(pci->pe_rst))
97 return PTR_ERR(pci->pe_rst);
98
99 return 0;
100}
101
102int dw_pcie_get_resources(struct dw_pcie *pci)
103{
104 struct platform_device *pdev = to_platform_device(pci->dev);
105 struct device_node *np = dev_of_node(pci->dev);
106 struct resource *res;
107 int ret;
108
109 if (!pci->dbi_base) {
110 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
111 pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res);
112 if (IS_ERR(pci->dbi_base))
113 return PTR_ERR(pci->dbi_base);
114 }
115
116 /* DBI2 is mainly useful for the endpoint controller */
117 if (!pci->dbi_base2) {
118 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
119 if (res) {
120 pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res);
121 if (IS_ERR(pci->dbi_base2))
122 return PTR_ERR(pci->dbi_base2);
123 } else {
124 pci->dbi_base2 = pci->dbi_base + SZ_4K;
125 }
126 }
127
128 /* For non-unrolled iATU/eDMA platforms this range will be ignored */
129 if (!pci->atu_base) {
130 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
131 if (res) {
132 pci->atu_size = resource_size(res);
133 pci->atu_base = devm_ioremap_resource(pci->dev, res);
134 if (IS_ERR(pci->atu_base))
135 return PTR_ERR(pci->atu_base);
136 } else {
137 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
138 }
139 }
140
141 /* Set a default value suitable for at most 8 in and 8 out windows */
142 if (!pci->atu_size)
143 pci->atu_size = SZ_4K;
144
145 /* LLDD is supposed to manually switch the clocks and resets state */
146 if (dw_pcie_cap_is(pci, REQ_RES)) {
147 ret = dw_pcie_get_clocks(pci);
148 if (ret)
149 return ret;
150
151 ret = dw_pcie_get_resets(pci);
152 if (ret)
153 return ret;
154 }
155
156 if (pci->link_gen < 1)
157 pci->link_gen = of_pci_get_max_link_speed(np);
158
159 of_property_read_u32(np, "num-lanes", &pci->num_lanes);
160
161 if (of_property_read_bool(np, "snps,enable-cdm-check"))
162 dw_pcie_cap_set(pci, CDM_CHECK);
163
164 return 0;
165}
166
167void dw_pcie_version_detect(struct dw_pcie *pci)
168{
169 u32 ver;
170
171 /* The content of the CSR is zero on DWC PCIe older than v4.70a */
172 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_NUMBER);
173 if (!ver)
174 return;
175
176 if (pci->version && pci->version != ver)
177 dev_warn(pci->dev, "Versions don't match (%08x != %08x)\n",
178 pci->version, ver);
179 else
180 pci->version = ver;
181
182 ver = dw_pcie_readl_dbi(pci, PCIE_VERSION_TYPE);
183
184 if (pci->type && pci->type != ver)
185 dev_warn(pci->dev, "Types don't match (%08x != %08x)\n",
186 pci->type, ver);
187 else
188 pci->type = ver;
189}
190
191/*
192 * These interfaces resemble the pci_find_*capability() interfaces, but these
193 * are for configuring host controllers, which are bridges *to* PCI devices but
194 * are not PCI devices themselves.
195 */
196static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
197 u8 cap)
198{
199 u8 cap_id, next_cap_ptr;
200 u16 reg;
201
202 if (!cap_ptr)
203 return 0;
204
205 reg = dw_pcie_readw_dbi(pci, cap_ptr);
206 cap_id = (reg & 0x00ff);
207
208 if (cap_id > PCI_CAP_ID_MAX)
209 return 0;
210
211 if (cap_id == cap)
212 return cap_ptr;
213
214 next_cap_ptr = (reg & 0xff00) >> 8;
215 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
216}
217
218u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
219{
220 u8 next_cap_ptr;
221 u16 reg;
222
223 reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
224 next_cap_ptr = (reg & 0x00ff);
225
226 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
227}
228EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
229
230static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
231 u8 cap)
232{
233 u32 header;
234 int ttl;
235 int pos = PCI_CFG_SPACE_SIZE;
236
237 /* minimum 8 bytes per capability */
238 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
239
240 if (start)
241 pos = start;
242
243 header = dw_pcie_readl_dbi(pci, pos);
244 /*
245 * If we have no capabilities, this is indicated by cap ID,
246 * cap version and next pointer all being 0.
247 */
248 if (header == 0)
249 return 0;
250
251 while (ttl-- > 0) {
252 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
253 return pos;
254
255 pos = PCI_EXT_CAP_NEXT(header);
256 if (pos < PCI_CFG_SPACE_SIZE)
257 break;
258
259 header = dw_pcie_readl_dbi(pci, pos);
260 }
261
262 return 0;
263}
264
265u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
266{
267 return dw_pcie_find_next_ext_capability(pci, 0, cap);
268}
269EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
270
271int dw_pcie_read(void __iomem *addr, int size, u32 *val)
272{
273 if (!IS_ALIGNED((uintptr_t)addr, size)) {
274 *val = 0;
275 return PCIBIOS_BAD_REGISTER_NUMBER;
276 }
277
278 if (size == 4) {
279 *val = readl(addr);
280 } else if (size == 2) {
281 *val = readw(addr);
282 } else if (size == 1) {
283 *val = readb(addr);
284 } else {
285 *val = 0;
286 return PCIBIOS_BAD_REGISTER_NUMBER;
287 }
288
289 return PCIBIOS_SUCCESSFUL;
290}
291EXPORT_SYMBOL_GPL(dw_pcie_read);
292
293int dw_pcie_write(void __iomem *addr, int size, u32 val)
294{
295 if (!IS_ALIGNED((uintptr_t)addr, size))
296 return PCIBIOS_BAD_REGISTER_NUMBER;
297
298 if (size == 4)
299 writel(val, addr);
300 else if (size == 2)
301 writew(val, addr);
302 else if (size == 1)
303 writeb(val, addr);
304 else
305 return PCIBIOS_BAD_REGISTER_NUMBER;
306
307 return PCIBIOS_SUCCESSFUL;
308}
309EXPORT_SYMBOL_GPL(dw_pcie_write);
310
311u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size)
312{
313 int ret;
314 u32 val;
315
316 if (pci->ops && pci->ops->read_dbi)
317 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size);
318
319 ret = dw_pcie_read(pci->dbi_base + reg, size, &val);
320 if (ret)
321 dev_err(pci->dev, "Read DBI address failed\n");
322
323 return val;
324}
325EXPORT_SYMBOL_GPL(dw_pcie_read_dbi);
326
327void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
328{
329 int ret;
330
331 if (pci->ops && pci->ops->write_dbi) {
332 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val);
333 return;
334 }
335
336 ret = dw_pcie_write(pci->dbi_base + reg, size, val);
337 if (ret)
338 dev_err(pci->dev, "Write DBI address failed\n");
339}
340EXPORT_SYMBOL_GPL(dw_pcie_write_dbi);
341
342void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
343{
344 int ret;
345
346 if (pci->ops && pci->ops->write_dbi2) {
347 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val);
348 return;
349 }
350
351 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
352 if (ret)
353 dev_err(pci->dev, "write DBI address failed\n");
354}
355
356static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir,
357 u32 index)
358{
359 if (dw_pcie_cap_is(pci, IATU_UNROLL))
360 return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index);
361
362 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, dir | index);
363 return pci->atu_base;
364}
365
366static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 dir, u32 index, u32 reg)
367{
368 void __iomem *base;
369 int ret;
370 u32 val;
371
372 base = dw_pcie_select_atu(pci, dir, index);
373
374 if (pci->ops && pci->ops->read_dbi)
375 return pci->ops->read_dbi(pci, base, reg, 4);
376
377 ret = dw_pcie_read(base + reg, 4, &val);
378 if (ret)
379 dev_err(pci->dev, "Read ATU address failed\n");
380
381 return val;
382}
383
384static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 dir, u32 index,
385 u32 reg, u32 val)
386{
387 void __iomem *base;
388 int ret;
389
390 base = dw_pcie_select_atu(pci, dir, index);
391
392 if (pci->ops && pci->ops->write_dbi) {
393 pci->ops->write_dbi(pci, base, reg, 4, val);
394 return;
395 }
396
397 ret = dw_pcie_write(base + reg, 4, val);
398 if (ret)
399 dev_err(pci->dev, "Write ATU address failed\n");
400}
401
402static inline u32 dw_pcie_readl_atu_ob(struct dw_pcie *pci, u32 index, u32 reg)
403{
404 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg);
405}
406
407static inline void dw_pcie_writel_atu_ob(struct dw_pcie *pci, u32 index, u32 reg,
408 u32 val)
409{
410 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_OB, index, reg, val);
411}
412
413static inline u32 dw_pcie_enable_ecrc(u32 val)
414{
415 /*
416 * DesignWare core version 4.90A has a design issue where the 'TD'
417 * bit in the Control register-1 of the ATU outbound region acts
418 * like an override for the ECRC setting, i.e., the presence of TLP
419 * Digest (ECRC) in the outgoing TLPs is solely determined by this
420 * bit. This is contrary to the PCIe spec which says that the
421 * enablement of the ECRC is solely determined by the AER
422 * registers.
423 *
424 * Because of this, even when the ECRC is enabled through AER
425 * registers, the transactions going through ATU won't have TLP
426 * Digest as there is no way the PCI core AER code could program
427 * the TD bit which is specific to the DesignWare core.
428 *
429 * The best way to handle this scenario is to program the TD bit
430 * always. It affects only the traffic from root port to downstream
431 * devices.
432 *
433 * At this point,
434 * When ECRC is enabled in AER registers, everything works normally
435 * When ECRC is NOT enabled in AER registers, then,
436 * on Root Port:- TLP Digest (DWord size) gets appended to each packet
437 * even through it is not required. Since downstream
438 * TLPs are mostly for configuration accesses and BAR
439 * accesses, they are not in critical path and won't
440 * have much negative effect on the performance.
441 * on End Point:- TLP Digest is received for some/all the packets coming
442 * from the root port. TLP Digest is ignored because,
443 * as per the PCIe Spec r5.0 v1.0 section 2.2.3
444 * "TLP Digest Rules", when an endpoint receives TLP
445 * Digest when its ECRC check functionality is disabled
446 * in AER registers, received TLP Digest is just ignored.
447 * Since there is no issue or error reported either side, best way to
448 * handle the scenario is to program TD bit by default.
449 */
450
451 return val | PCIE_ATU_TD;
452}
453
454static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
455 int index, int type, u64 cpu_addr,
456 u64 pci_addr, u64 size)
457{
458 u32 retries, val;
459 u64 limit_addr;
460
461 if (pci->ops && pci->ops->cpu_addr_fixup)
462 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
463
464 limit_addr = cpu_addr + size - 1;
465
466 if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) ||
467 !IS_ALIGNED(cpu_addr, pci->region_align) ||
468 !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
469 return -EINVAL;
470 }
471
472 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE,
473 lower_32_bits(cpu_addr));
474 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE,
475 upper_32_bits(cpu_addr));
476
477 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT,
478 lower_32_bits(limit_addr));
479 if (dw_pcie_ver_is_ge(pci, 460A))
480 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT,
481 upper_32_bits(limit_addr));
482
483 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET,
484 lower_32_bits(pci_addr));
485 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET,
486 upper_32_bits(pci_addr));
487
488 val = type | PCIE_ATU_FUNC_NUM(func_no);
489 if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
490 dw_pcie_ver_is_ge(pci, 460A))
491 val |= PCIE_ATU_INCREASE_REGION_SIZE;
492 if (dw_pcie_ver_is(pci, 490A))
493 val = dw_pcie_enable_ecrc(val);
494 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val);
495
496 dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
497
498 /*
499 * Make sure ATU enable takes effect before any subsequent config
500 * and I/O accesses.
501 */
502 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
503 val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2);
504 if (val & PCIE_ATU_ENABLE)
505 return 0;
506
507 mdelay(LINK_WAIT_IATU);
508 }
509
510 dev_err(pci->dev, "Outbound iATU is not being enabled\n");
511
512 return -ETIMEDOUT;
513}
514
515int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
516 u64 cpu_addr, u64 pci_addr, u64 size)
517{
518 return __dw_pcie_prog_outbound_atu(pci, 0, index, type,
519 cpu_addr, pci_addr, size);
520}
521
522int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
523 int type, u64 cpu_addr, u64 pci_addr,
524 u64 size)
525{
526 return __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
527 cpu_addr, pci_addr, size);
528}
529
530static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
531{
532 return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
533}
534
535static inline void dw_pcie_writel_atu_ib(struct dw_pcie *pci, u32 index, u32 reg,
536 u32 val)
537{
538 dw_pcie_writel_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg, val);
539}
540
541int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
542 u64 cpu_addr, u64 pci_addr, u64 size)
543{
544 u64 limit_addr = pci_addr + size - 1;
545 u32 retries, val;
546
547 if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) ||
548 !IS_ALIGNED(cpu_addr, pci->region_align) ||
549 !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
550 return -EINVAL;
551 }
552
553 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_BASE,
554 lower_32_bits(pci_addr));
555 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_BASE,
556 upper_32_bits(pci_addr));
557
558 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LIMIT,
559 lower_32_bits(limit_addr));
560 if (dw_pcie_ver_is_ge(pci, 460A))
561 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_LIMIT,
562 upper_32_bits(limit_addr));
563
564 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET,
565 lower_32_bits(cpu_addr));
566 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET,
567 upper_32_bits(cpu_addr));
568
569 val = type;
570 if (upper_32_bits(limit_addr) > upper_32_bits(pci_addr) &&
571 dw_pcie_ver_is_ge(pci, 460A))
572 val |= PCIE_ATU_INCREASE_REGION_SIZE;
573 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, val);
574 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
575
576 /*
577 * Make sure ATU enable takes effect before any subsequent config
578 * and I/O accesses.
579 */
580 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
581 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2);
582 if (val & PCIE_ATU_ENABLE)
583 return 0;
584
585 mdelay(LINK_WAIT_IATU);
586 }
587
588 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
589
590 return -ETIMEDOUT;
591}
592
593int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
594 int type, u64 cpu_addr, u8 bar)
595{
596 u32 retries, val;
597
598 if (!IS_ALIGNED(cpu_addr, pci->region_align))
599 return -EINVAL;
600
601 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET,
602 lower_32_bits(cpu_addr));
603 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_UPPER_TARGET,
604 upper_32_bits(cpu_addr));
605
606 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL1, type |
607 PCIE_ATU_FUNC_NUM(func_no));
608 dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2,
609 PCIE_ATU_ENABLE | PCIE_ATU_FUNC_NUM_MATCH_EN |
610 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
611
612 /*
613 * Make sure ATU enable takes effect before any subsequent config
614 * and I/O accesses.
615 */
616 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
617 val = dw_pcie_readl_atu_ib(pci, index, PCIE_ATU_REGION_CTRL2);
618 if (val & PCIE_ATU_ENABLE)
619 return 0;
620
621 mdelay(LINK_WAIT_IATU);
622 }
623
624 dev_err(pci->dev, "Inbound iATU is not being enabled\n");
625
626 return -ETIMEDOUT;
627}
628
629void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index)
630{
631 dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0);
632}
633
634int dw_pcie_wait_for_link(struct dw_pcie *pci)
635{
636 u32 offset, val;
637 int retries;
638
639 /* Check if the link is up or not */
640 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
641 if (dw_pcie_link_up(pci))
642 break;
643
644 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
645 }
646
647 if (retries >= LINK_WAIT_MAX_RETRIES) {
648 dev_info(pci->dev, "Phy link never came up\n");
649 return -ETIMEDOUT;
650 }
651
652 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
653 val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
654
655 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n",
656 FIELD_GET(PCI_EXP_LNKSTA_CLS, val),
657 FIELD_GET(PCI_EXP_LNKSTA_NLW, val));
658
659 return 0;
660}
661EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link);
662
663int dw_pcie_link_up(struct dw_pcie *pci)
664{
665 u32 val;
666
667 if (pci->ops && pci->ops->link_up)
668 return pci->ops->link_up(pci);
669
670 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1);
671 return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
672 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
673}
674EXPORT_SYMBOL_GPL(dw_pcie_link_up);
675
676void dw_pcie_upconfig_setup(struct dw_pcie *pci)
677{
678 u32 val;
679
680 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);
681 val |= PORT_MLTI_UPCFG_SUPPORT;
682 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);
683}
684EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
685
686static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
687{
688 u32 cap, ctrl2, link_speed;
689 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
690
691 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
692 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
693 ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
694
695 switch (pcie_link_speed[link_gen]) {
696 case PCIE_SPEED_2_5GT:
697 link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
698 break;
699 case PCIE_SPEED_5_0GT:
700 link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
701 break;
702 case PCIE_SPEED_8_0GT:
703 link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
704 break;
705 case PCIE_SPEED_16_0GT:
706 link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;
707 break;
708 default:
709 /* Use hardware capability */
710 link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
711 ctrl2 &= ~PCI_EXP_LNKCTL2_HASD;
712 break;
713 }
714
715 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
716
717 cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
718 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);
719
720}
721
722void dw_pcie_iatu_detect(struct dw_pcie *pci)
723{
724 int max_region, ob, ib;
725 u32 val, min, dir;
726 u64 max;
727
728 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
729 if (val == 0xFFFFFFFF) {
730 dw_pcie_cap_set(pci, IATU_UNROLL);
731
732 max_region = min((int)pci->atu_size / 512, 256);
733 } else {
734 pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE;
735 pci->atu_size = PCIE_ATU_VIEWPORT_SIZE;
736
737 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF);
738 max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1;
739 }
740
741 for (ob = 0; ob < max_region; ob++) {
742 dw_pcie_writel_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET, 0x11110000);
743 val = dw_pcie_readl_atu_ob(pci, ob, PCIE_ATU_LOWER_TARGET);
744 if (val != 0x11110000)
745 break;
746 }
747
748 for (ib = 0; ib < max_region; ib++) {
749 dw_pcie_writel_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET, 0x11110000);
750 val = dw_pcie_readl_atu_ib(pci, ib, PCIE_ATU_LOWER_TARGET);
751 if (val != 0x11110000)
752 break;
753 }
754
755 if (ob) {
756 dir = PCIE_ATU_REGION_DIR_OB;
757 } else if (ib) {
758 dir = PCIE_ATU_REGION_DIR_IB;
759 } else {
760 dev_err(pci->dev, "No iATU regions found\n");
761 return;
762 }
763
764 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_LIMIT, 0x0);
765 min = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_LIMIT);
766
767 if (dw_pcie_ver_is_ge(pci, 460A)) {
768 dw_pcie_writel_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT, 0xFFFFFFFF);
769 max = dw_pcie_readl_atu(pci, dir, 0, PCIE_ATU_UPPER_LIMIT);
770 } else {
771 max = 0;
772 }
773
774 pci->num_ob_windows = ob;
775 pci->num_ib_windows = ib;
776 pci->region_align = 1 << fls(min);
777 pci->region_limit = (max << 32) | (SZ_4G - 1);
778
779 dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n",
780 dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F",
781 pci->num_ob_windows, pci->num_ib_windows,
782 pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G);
783}
784
785void dw_pcie_setup(struct dw_pcie *pci)
786{
787 u32 val;
788
789 if (pci->link_gen > 0)
790 dw_pcie_link_set_max_speed(pci, pci->link_gen);
791
792 /* Configure Gen1 N_FTS */
793 if (pci->n_fts[0]) {
794 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
795 val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK);
796 val |= PORT_AFR_N_FTS(pci->n_fts[0]);
797 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]);
798 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
799 }
800
801 /* Configure Gen2+ N_FTS */
802 if (pci->n_fts[1]) {
803 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
804 val &= ~PORT_LOGIC_N_FTS_MASK;
805 val |= pci->n_fts[1];
806 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
807 }
808
809 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
810 val &= ~PORT_LINK_FAST_LINK_MODE;
811 val |= PORT_LINK_DLL_LINK_EN;
812 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
813
814 if (dw_pcie_cap_is(pci, CDM_CHECK)) {
815 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
816 val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
817 PCIE_PL_CHK_REG_CHK_REG_START;
818 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
819 }
820
821 if (!pci->num_lanes) {
822 dev_dbg(pci->dev, "Using h/w default number of lanes\n");
823 return;
824 }
825
826 /* Set the number of lanes */
827 val &= ~PORT_LINK_FAST_LINK_MODE;
828 val &= ~PORT_LINK_MODE_MASK;
829 switch (pci->num_lanes) {
830 case 1:
831 val |= PORT_LINK_MODE_1_LANES;
832 break;
833 case 2:
834 val |= PORT_LINK_MODE_2_LANES;
835 break;
836 case 4:
837 val |= PORT_LINK_MODE_4_LANES;
838 break;
839 case 8:
840 val |= PORT_LINK_MODE_8_LANES;
841 break;
842 default:
843 dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
844 return;
845 }
846 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
847
848 /* Set link width speed control register */
849 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
850 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
851 switch (pci->num_lanes) {
852 case 1:
853 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
854 break;
855 case 2:
856 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
857 break;
858 case 4:
859 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
860 break;
861 case 8:
862 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
863 break;
864 }
865 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
866}