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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Marvell 10G 88x3310 PHY driver
4 *
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
6 * from two different companies.
7 *
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
11 *
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
15 *
16 * With XAUI, observation shows:
17 *
18 * XAUI PHYXS -- <appropriate PCS as above>
19 *
20 * and no switching of the host interface mode occurs.
21 *
22 * If both the fiber and copper ports are connected, the first to gain
23 * link takes priority and the other port is completely locked out.
24 */
25#include <linux/ctype.h>
26#include <linux/delay.h>
27#include <linux/hwmon.h>
28#include <linux/marvell_phy.h>
29#include <linux/phy.h>
30#include <linux/sfp.h>
31
32#define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
33#define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
34
35enum {
36 MV_PMA_FW_VER0 = 0xc011,
37 MV_PMA_FW_VER1 = 0xc012,
38 MV_PMA_BOOT = 0xc050,
39 MV_PMA_BOOT_FATAL = BIT(0),
40
41 MV_PCS_BASE_T = 0x0000,
42 MV_PCS_BASE_R = 0x1000,
43 MV_PCS_1000BASEX = 0x2000,
44
45 MV_PCS_CSCR1 = 0x8000,
46 MV_PCS_CSCR1_ED_MASK = 0x0300,
47 MV_PCS_CSCR1_ED_OFF = 0x0000,
48 MV_PCS_CSCR1_ED_RX = 0x0200,
49 MV_PCS_CSCR1_ED_NLP = 0x0300,
50 MV_PCS_CSCR1_MDIX_MASK = 0x0060,
51 MV_PCS_CSCR1_MDIX_MDI = 0x0000,
52 MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
53 MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
54
55 MV_PCS_CSSR1 = 0x8008,
56 MV_PCS_CSSR1_SPD1_MASK = 0xc000,
57 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000,
58 MV_PCS_CSSR1_SPD1_1000 = 0x8000,
59 MV_PCS_CSSR1_SPD1_100 = 0x4000,
60 MV_PCS_CSSR1_SPD1_10 = 0x0000,
61 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13),
62 MV_PCS_CSSR1_RESOLVED = BIT(11),
63 MV_PCS_CSSR1_MDIX = BIT(6),
64 MV_PCS_CSSR1_SPD2_MASK = 0x000c,
65 MV_PCS_CSSR1_SPD2_5000 = 0x0008,
66 MV_PCS_CSSR1_SPD2_2500 = 0x0004,
67 MV_PCS_CSSR1_SPD2_10000 = 0x0000,
68
69 /* Temperature read register (88E2110 only) */
70 MV_PCS_TEMP = 0x8042,
71
72 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
73 * registers appear to set themselves to the 0x800X when AN is
74 * restarted, but status registers appear readable from either.
75 */
76 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
77 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
78
79 /* Vendor2 MMD registers */
80 MV_V2_PORT_CTRL = 0xf001,
81 MV_V2_PORT_CTRL_SWRST = BIT(15),
82 MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
83 MV_V2_PORT_MAC_TYPE_MASK = 0x7,
84 MV_V2_PORT_MAC_TYPE_RATE_MATCH = 0x6,
85 /* Temperature control/read registers (88X3310 only) */
86 MV_V2_TEMP_CTRL = 0xf08a,
87 MV_V2_TEMP_CTRL_MASK = 0xc000,
88 MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
89 MV_V2_TEMP_CTRL_DISABLE = 0xc000,
90 MV_V2_TEMP = 0xf08c,
91 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
92};
93
94struct mv3310_priv {
95 u32 firmware_ver;
96 bool rate_match;
97
98 struct device *hwmon_dev;
99 char *hwmon_name;
100};
101
102#ifdef CONFIG_HWMON
103static umode_t mv3310_hwmon_is_visible(const void *data,
104 enum hwmon_sensor_types type,
105 u32 attr, int channel)
106{
107 if (type == hwmon_chip && attr == hwmon_chip_update_interval)
108 return 0444;
109 if (type == hwmon_temp && attr == hwmon_temp_input)
110 return 0444;
111 return 0;
112}
113
114static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev)
115{
116 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
117}
118
119static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev)
120{
121 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP);
122}
123
124static int mv10g_hwmon_read_temp_reg(struct phy_device *phydev)
125{
126 if (phydev->drv->phy_id == MARVELL_PHY_ID_88X3310)
127 return mv3310_hwmon_read_temp_reg(phydev);
128 else /* MARVELL_PHY_ID_88E2110 */
129 return mv2110_hwmon_read_temp_reg(phydev);
130}
131
132static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
133 u32 attr, int channel, long *value)
134{
135 struct phy_device *phydev = dev_get_drvdata(dev);
136 int temp;
137
138 if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
139 *value = MSEC_PER_SEC;
140 return 0;
141 }
142
143 if (type == hwmon_temp && attr == hwmon_temp_input) {
144 temp = mv10g_hwmon_read_temp_reg(phydev);
145 if (temp < 0)
146 return temp;
147
148 *value = ((temp & 0xff) - 75) * 1000;
149
150 return 0;
151 }
152
153 return -EOPNOTSUPP;
154}
155
156static const struct hwmon_ops mv3310_hwmon_ops = {
157 .is_visible = mv3310_hwmon_is_visible,
158 .read = mv3310_hwmon_read,
159};
160
161static u32 mv3310_hwmon_chip_config[] = {
162 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
163 0,
164};
165
166static const struct hwmon_channel_info mv3310_hwmon_chip = {
167 .type = hwmon_chip,
168 .config = mv3310_hwmon_chip_config,
169};
170
171static u32 mv3310_hwmon_temp_config[] = {
172 HWMON_T_INPUT,
173 0,
174};
175
176static const struct hwmon_channel_info mv3310_hwmon_temp = {
177 .type = hwmon_temp,
178 .config = mv3310_hwmon_temp_config,
179};
180
181static const struct hwmon_channel_info *mv3310_hwmon_info[] = {
182 &mv3310_hwmon_chip,
183 &mv3310_hwmon_temp,
184 NULL,
185};
186
187static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
188 .ops = &mv3310_hwmon_ops,
189 .info = mv3310_hwmon_info,
190};
191
192static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
193{
194 u16 val;
195 int ret;
196
197 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310)
198 return 0;
199
200 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
201 MV_V2_TEMP_UNKNOWN);
202 if (ret < 0)
203 return ret;
204
205 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
206
207 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
208 MV_V2_TEMP_CTRL_MASK, val);
209}
210
211static int mv3310_hwmon_probe(struct phy_device *phydev)
212{
213 struct device *dev = &phydev->mdio.dev;
214 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
215 int i, j, ret;
216
217 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
218 if (!priv->hwmon_name)
219 return -ENODEV;
220
221 for (i = j = 0; priv->hwmon_name[i]; i++) {
222 if (isalnum(priv->hwmon_name[i])) {
223 if (i != j)
224 priv->hwmon_name[j] = priv->hwmon_name[i];
225 j++;
226 }
227 }
228 priv->hwmon_name[j] = '\0';
229
230 ret = mv3310_hwmon_config(phydev, true);
231 if (ret)
232 return ret;
233
234 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
235 priv->hwmon_name, phydev,
236 &mv3310_hwmon_chip_info, NULL);
237
238 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
239}
240#else
241static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
242{
243 return 0;
244}
245
246static int mv3310_hwmon_probe(struct phy_device *phydev)
247{
248 return 0;
249}
250#endif
251
252static int mv3310_power_down(struct phy_device *phydev)
253{
254 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
255 MV_V2_PORT_CTRL_PWRDOWN);
256}
257
258static int mv3310_power_up(struct phy_device *phydev)
259{
260 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
261 int ret;
262
263 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
264 MV_V2_PORT_CTRL_PWRDOWN);
265
266 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
267 priv->firmware_ver < 0x00030000)
268 return ret;
269
270 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
271 MV_V2_PORT_CTRL_SWRST);
272}
273
274static int mv3310_reset(struct phy_device *phydev, u32 unit)
275{
276 int val, err;
277
278 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
279 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
280 if (err < 0)
281 return err;
282
283 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
284 unit + MDIO_CTRL1, val,
285 !(val & MDIO_CTRL1_RESET),
286 5000, 100000, true);
287}
288
289static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
290{
291 int val;
292
293 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1);
294 if (val < 0)
295 return val;
296
297 switch (val & MV_PCS_CSCR1_ED_MASK) {
298 case MV_PCS_CSCR1_ED_NLP:
299 *edpd = 1000;
300 break;
301 case MV_PCS_CSCR1_ED_RX:
302 *edpd = ETHTOOL_PHY_EDPD_NO_TX;
303 break;
304 default:
305 *edpd = ETHTOOL_PHY_EDPD_DISABLE;
306 break;
307 }
308 return 0;
309}
310
311static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd)
312{
313 u16 val;
314 int err;
315
316 switch (edpd) {
317 case 1000:
318 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
319 val = MV_PCS_CSCR1_ED_NLP;
320 break;
321
322 case ETHTOOL_PHY_EDPD_NO_TX:
323 val = MV_PCS_CSCR1_ED_RX;
324 break;
325
326 case ETHTOOL_PHY_EDPD_DISABLE:
327 val = MV_PCS_CSCR1_ED_OFF;
328 break;
329
330 default:
331 return -EINVAL;
332 }
333
334 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
335 MV_PCS_CSCR1_ED_MASK, val);
336 if (err > 0)
337 err = mv3310_reset(phydev, MV_PCS_BASE_T);
338
339 return err;
340}
341
342static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
343{
344 struct phy_device *phydev = upstream;
345 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
346 phy_interface_t iface;
347
348 sfp_parse_support(phydev->sfp_bus, id, support);
349 iface = sfp_select_interface(phydev->sfp_bus, support);
350
351 if (iface != PHY_INTERFACE_MODE_10GBASER) {
352 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
353 return -EINVAL;
354 }
355 return 0;
356}
357
358static const struct sfp_upstream_ops mv3310_sfp_ops = {
359 .attach = phy_sfp_attach,
360 .detach = phy_sfp_detach,
361 .module_insert = mv3310_sfp_insert,
362};
363
364static int mv3310_probe(struct phy_device *phydev)
365{
366 struct mv3310_priv *priv;
367 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
368 int ret;
369
370 if (!phydev->is_c45 ||
371 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
372 return -ENODEV;
373
374 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
375 if (ret < 0)
376 return ret;
377
378 if (ret & MV_PMA_BOOT_FATAL) {
379 dev_warn(&phydev->mdio.dev,
380 "PHY failed to boot firmware, status=%04x\n", ret);
381 return -ENODEV;
382 }
383
384 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
385 if (!priv)
386 return -ENOMEM;
387
388 dev_set_drvdata(&phydev->mdio.dev, priv);
389
390 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
391 if (ret < 0)
392 return ret;
393
394 priv->firmware_ver = ret << 16;
395
396 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
397 if (ret < 0)
398 return ret;
399
400 priv->firmware_ver |= ret;
401
402 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n",
403 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
404 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
405
406 /* Powering down the port when not in use saves about 600mW */
407 ret = mv3310_power_down(phydev);
408 if (ret)
409 return ret;
410
411 ret = mv3310_hwmon_probe(phydev);
412 if (ret)
413 return ret;
414
415 return phy_sfp_probe(phydev, &mv3310_sfp_ops);
416}
417
418static void mv3310_remove(struct phy_device *phydev)
419{
420 mv3310_hwmon_config(phydev, false);
421}
422
423static int mv3310_suspend(struct phy_device *phydev)
424{
425 return mv3310_power_down(phydev);
426}
427
428static int mv3310_resume(struct phy_device *phydev)
429{
430 int ret;
431
432 ret = mv3310_power_up(phydev);
433 if (ret)
434 return ret;
435
436 return mv3310_hwmon_config(phydev, true);
437}
438
439/* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
440 * don't set bit 14 in PMA Extended Abilities (1.11), although they do
441 * support 2.5GBASET and 5GBASET. For these models, we can still read their
442 * 2.5G/5G extended abilities register (1.21). We detect these models based on
443 * the PMA device identifier, with a mask matching models known to have this
444 * issue
445 */
446static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
447{
448 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
449 return false;
450
451 /* Only some revisions of the 88X3310 family PMA seem to be impacted */
452 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
453 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
454}
455
456static int mv3310_config_init(struct phy_device *phydev)
457{
458 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
459 int err;
460 int val;
461
462 /* Check that the PHY interface type is compatible */
463 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
464 phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
465 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
466 phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
467 phydev->interface != PHY_INTERFACE_MODE_10GBASER)
468 return -ENODEV;
469
470 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
471
472 /* Power up so reset works */
473 err = mv3310_power_up(phydev);
474 if (err)
475 return err;
476
477 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
478 if (val < 0)
479 return val;
480 priv->rate_match = ((val & MV_V2_PORT_MAC_TYPE_MASK) ==
481 MV_V2_PORT_MAC_TYPE_RATE_MATCH);
482
483 /* Enable EDPD mode - saving 600mW */
484 return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
485}
486
487static int mv3310_get_features(struct phy_device *phydev)
488{
489 int ret, val;
490
491 ret = genphy_c45_pma_read_abilities(phydev);
492 if (ret)
493 return ret;
494
495 if (mv3310_has_pma_ngbaset_quirk(phydev)) {
496 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
497 MDIO_PMA_NG_EXTABLE);
498 if (val < 0)
499 return val;
500
501 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
502 phydev->supported,
503 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
504
505 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
506 phydev->supported,
507 val & MDIO_PMA_NG_EXTABLE_5GBT);
508 }
509
510 return 0;
511}
512
513static int mv3310_config_mdix(struct phy_device *phydev)
514{
515 u16 val;
516 int err;
517
518 switch (phydev->mdix_ctrl) {
519 case ETH_TP_MDI_AUTO:
520 val = MV_PCS_CSCR1_MDIX_AUTO;
521 break;
522 case ETH_TP_MDI_X:
523 val = MV_PCS_CSCR1_MDIX_MDIX;
524 break;
525 case ETH_TP_MDI:
526 val = MV_PCS_CSCR1_MDIX_MDI;
527 break;
528 default:
529 return -EINVAL;
530 }
531
532 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
533 MV_PCS_CSCR1_MDIX_MASK, val);
534 if (err > 0)
535 err = mv3310_reset(phydev, MV_PCS_BASE_T);
536
537 return err;
538}
539
540static int mv3310_config_aneg(struct phy_device *phydev)
541{
542 bool changed = false;
543 u16 reg;
544 int ret;
545
546 ret = mv3310_config_mdix(phydev);
547 if (ret < 0)
548 return ret;
549
550 if (phydev->autoneg == AUTONEG_DISABLE)
551 return genphy_c45_pma_setup_forced(phydev);
552
553 ret = genphy_c45_an_config_aneg(phydev);
554 if (ret < 0)
555 return ret;
556 if (ret > 0)
557 changed = true;
558
559 /* Clause 45 has no standardized support for 1000BaseT, therefore
560 * use vendor registers for this mode.
561 */
562 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
563 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
564 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
565 if (ret < 0)
566 return ret;
567 if (ret > 0)
568 changed = true;
569
570 return genphy_c45_check_and_restart_aneg(phydev, changed);
571}
572
573static int mv3310_aneg_done(struct phy_device *phydev)
574{
575 int val;
576
577 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
578 if (val < 0)
579 return val;
580
581 if (val & MDIO_STAT1_LSTATUS)
582 return 1;
583
584 return genphy_c45_aneg_done(phydev);
585}
586
587static void mv3310_update_interface(struct phy_device *phydev)
588{
589 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
590
591 /* In "XFI with Rate Matching" mode the PHY interface is fixed at
592 * 10Gb. The PHY adapts the rate to actual wire speed with help of
593 * internal 16KB buffer.
594 */
595 if (priv->rate_match) {
596 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
597 return;
598 }
599
600 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
601 phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
602 phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
603 phydev->link) {
604 /* The PHY automatically switches its serdes interface (and
605 * active PHYXS instance) between Cisco SGMII, 10GBase-R and
606 * 2500BaseX modes according to the speed. Florian suggests
607 * setting phydev->interface to communicate this to the MAC.
608 * Only do this if we are already in one of the above modes.
609 */
610 switch (phydev->speed) {
611 case SPEED_10000:
612 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
613 break;
614 case SPEED_2500:
615 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
616 break;
617 case SPEED_1000:
618 case SPEED_100:
619 case SPEED_10:
620 phydev->interface = PHY_INTERFACE_MODE_SGMII;
621 break;
622 default:
623 break;
624 }
625 }
626}
627
628/* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
629static int mv3310_read_status_10gbaser(struct phy_device *phydev)
630{
631 phydev->link = 1;
632 phydev->speed = SPEED_10000;
633 phydev->duplex = DUPLEX_FULL;
634
635 return 0;
636}
637
638static int mv3310_read_status_copper(struct phy_device *phydev)
639{
640 int cssr1, speed, val;
641
642 val = genphy_c45_read_link(phydev);
643 if (val < 0)
644 return val;
645
646 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
647 if (val < 0)
648 return val;
649
650 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
651 if (cssr1 < 0)
652 return val;
653
654 /* If the link settings are not resolved, mark the link down */
655 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) {
656 phydev->link = 0;
657 return 0;
658 }
659
660 /* Read the copper link settings */
661 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK;
662 if (speed == MV_PCS_CSSR1_SPD1_SPD2)
663 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK;
664
665 switch (speed) {
666 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000:
667 phydev->speed = SPEED_10000;
668 break;
669
670 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000:
671 phydev->speed = SPEED_5000;
672 break;
673
674 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500:
675 phydev->speed = SPEED_2500;
676 break;
677
678 case MV_PCS_CSSR1_SPD1_1000:
679 phydev->speed = SPEED_1000;
680 break;
681
682 case MV_PCS_CSSR1_SPD1_100:
683 phydev->speed = SPEED_100;
684 break;
685
686 case MV_PCS_CSSR1_SPD1_10:
687 phydev->speed = SPEED_10;
688 break;
689 }
690
691 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ?
692 DUPLEX_FULL : DUPLEX_HALF;
693 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ?
694 ETH_TP_MDI_X : ETH_TP_MDI;
695
696 if (val & MDIO_AN_STAT1_COMPLETE) {
697 val = genphy_c45_read_lpa(phydev);
698 if (val < 0)
699 return val;
700
701 /* Read the link partner's 1G advertisement */
702 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
703 if (val < 0)
704 return val;
705
706 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
707
708 /* Update the pause status */
709 phy_resolve_aneg_pause(phydev);
710 }
711
712 return 0;
713}
714
715static int mv3310_read_status(struct phy_device *phydev)
716{
717 int err, val;
718
719 phydev->speed = SPEED_UNKNOWN;
720 phydev->duplex = DUPLEX_UNKNOWN;
721 linkmode_zero(phydev->lp_advertising);
722 phydev->link = 0;
723 phydev->pause = 0;
724 phydev->asym_pause = 0;
725 phydev->mdix = ETH_TP_MDI_INVALID;
726
727 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
728 if (val < 0)
729 return val;
730
731 if (val & MDIO_STAT1_LSTATUS)
732 err = mv3310_read_status_10gbaser(phydev);
733 else
734 err = mv3310_read_status_copper(phydev);
735 if (err < 0)
736 return err;
737
738 if (phydev->link)
739 mv3310_update_interface(phydev);
740
741 return 0;
742}
743
744static int mv3310_get_tunable(struct phy_device *phydev,
745 struct ethtool_tunable *tuna, void *data)
746{
747 switch (tuna->id) {
748 case ETHTOOL_PHY_EDPD:
749 return mv3310_get_edpd(phydev, data);
750 default:
751 return -EOPNOTSUPP;
752 }
753}
754
755static int mv3310_set_tunable(struct phy_device *phydev,
756 struct ethtool_tunable *tuna, const void *data)
757{
758 switch (tuna->id) {
759 case ETHTOOL_PHY_EDPD:
760 return mv3310_set_edpd(phydev, *(u16 *)data);
761 default:
762 return -EOPNOTSUPP;
763 }
764}
765
766static struct phy_driver mv3310_drivers[] = {
767 {
768 .phy_id = MARVELL_PHY_ID_88X3310,
769 .phy_id_mask = MARVELL_PHY_ID_MASK,
770 .name = "mv88x3310",
771 .get_features = mv3310_get_features,
772 .config_init = mv3310_config_init,
773 .probe = mv3310_probe,
774 .suspend = mv3310_suspend,
775 .resume = mv3310_resume,
776 .config_aneg = mv3310_config_aneg,
777 .aneg_done = mv3310_aneg_done,
778 .read_status = mv3310_read_status,
779 .get_tunable = mv3310_get_tunable,
780 .set_tunable = mv3310_set_tunable,
781 .remove = mv3310_remove,
782 },
783 {
784 .phy_id = MARVELL_PHY_ID_88E2110,
785 .phy_id_mask = MARVELL_PHY_ID_MASK,
786 .name = "mv88x2110",
787 .probe = mv3310_probe,
788 .suspend = mv3310_suspend,
789 .resume = mv3310_resume,
790 .config_init = mv3310_config_init,
791 .config_aneg = mv3310_config_aneg,
792 .aneg_done = mv3310_aneg_done,
793 .read_status = mv3310_read_status,
794 .get_tunable = mv3310_get_tunable,
795 .set_tunable = mv3310_set_tunable,
796 .remove = mv3310_remove,
797 },
798};
799
800module_phy_driver(mv3310_drivers);
801
802static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
803 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
804 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
805 { },
806};
807MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
808MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
809MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Marvell 10G 88x3310 PHY driver
4 *
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
6 * from two different companies.
7 *
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
11 *
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
15 *
16 * With XAUI, observation shows:
17 *
18 * XAUI PHYXS -- <appropriate PCS as above>
19 *
20 * and no switching of the host interface mode occurs.
21 *
22 * If both the fiber and copper ports are connected, the first to gain
23 * link takes priority and the other port is completely locked out.
24 */
25#include <linux/bitfield.h>
26#include <linux/ctype.h>
27#include <linux/delay.h>
28#include <linux/hwmon.h>
29#include <linux/marvell_phy.h>
30#include <linux/phy.h>
31#include <linux/sfp.h>
32#include <linux/netdevice.h>
33
34#define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
35#define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
36
37#define MV_VERSION(a,b,c,d) ((a) << 24 | (b) << 16 | (c) << 8 | (d))
38
39enum {
40 MV_PMA_FW_VER0 = 0xc011,
41 MV_PMA_FW_VER1 = 0xc012,
42 MV_PMA_21X0_PORT_CTRL = 0xc04a,
43 MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15),
44 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7,
45 MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0,
46 MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1,
47 MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2,
48 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4,
49 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5,
50 MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
51 MV_PMA_BOOT = 0xc050,
52 MV_PMA_BOOT_FATAL = BIT(0),
53
54 MV_PCS_BASE_T = 0x0000,
55 MV_PCS_BASE_R = 0x1000,
56 MV_PCS_1000BASEX = 0x2000,
57
58 MV_PCS_CSCR1 = 0x8000,
59 MV_PCS_CSCR1_ED_MASK = 0x0300,
60 MV_PCS_CSCR1_ED_OFF = 0x0000,
61 MV_PCS_CSCR1_ED_RX = 0x0200,
62 MV_PCS_CSCR1_ED_NLP = 0x0300,
63 MV_PCS_CSCR1_MDIX_MASK = 0x0060,
64 MV_PCS_CSCR1_MDIX_MDI = 0x0000,
65 MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
66 MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
67
68 MV_PCS_DSC1 = 0x8003,
69 MV_PCS_DSC1_ENABLE = BIT(9),
70 MV_PCS_DSC1_10GBT = 0x01c0,
71 MV_PCS_DSC1_1GBR = 0x0038,
72 MV_PCS_DSC1_100BTX = 0x0007,
73 MV_PCS_DSC2 = 0x8004,
74 MV_PCS_DSC2_2P5G = 0xf000,
75 MV_PCS_DSC2_5G = 0x0f00,
76
77 MV_PCS_CSSR1 = 0x8008,
78 MV_PCS_CSSR1_SPD1_MASK = 0xc000,
79 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000,
80 MV_PCS_CSSR1_SPD1_1000 = 0x8000,
81 MV_PCS_CSSR1_SPD1_100 = 0x4000,
82 MV_PCS_CSSR1_SPD1_10 = 0x0000,
83 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13),
84 MV_PCS_CSSR1_RESOLVED = BIT(11),
85 MV_PCS_CSSR1_MDIX = BIT(6),
86 MV_PCS_CSSR1_SPD2_MASK = 0x000c,
87 MV_PCS_CSSR1_SPD2_5000 = 0x0008,
88 MV_PCS_CSSR1_SPD2_2500 = 0x0004,
89 MV_PCS_CSSR1_SPD2_10000 = 0x0000,
90
91 /* Temperature read register (88E2110 only) */
92 MV_PCS_TEMP = 0x8042,
93
94 /* Number of ports on the device */
95 MV_PCS_PORT_INFO = 0xd00d,
96 MV_PCS_PORT_INFO_NPORTS_MASK = 0x0380,
97 MV_PCS_PORT_INFO_NPORTS_SHIFT = 7,
98
99 /* SerDes reinitialization 88E21X0 */
100 MV_AN_21X0_SERDES_CTRL2 = 0x800f,
101 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS = BIT(13),
102 MV_AN_21X0_SERDES_CTRL2_RUN_INIT = BIT(15),
103
104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
105 * registers appear to set themselves to the 0x800X when AN is
106 * restarted, but status registers appear readable from either.
107 */
108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
110
111 /* Vendor2 MMD registers */
112 MV_V2_PORT_CTRL = 0xf001,
113 MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
114 MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
115 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
116 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0,
117 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1,
118 MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1,
119 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2,
120 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3,
121 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4,
122 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5,
123 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
124 MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7,
125 MV_V2_PORT_INTR_STS = 0xf040,
126 MV_V2_PORT_INTR_MASK = 0xf043,
127 MV_V2_PORT_INTR_STS_WOL_EN = BIT(8),
128 MV_V2_MAGIC_PKT_WORD0 = 0xf06b,
129 MV_V2_MAGIC_PKT_WORD1 = 0xf06c,
130 MV_V2_MAGIC_PKT_WORD2 = 0xf06d,
131 /* Wake on LAN registers */
132 MV_V2_WOL_CTRL = 0xf06e,
133 MV_V2_WOL_CTRL_CLEAR_STS = BIT(15),
134 MV_V2_WOL_CTRL_MAGIC_PKT_EN = BIT(0),
135 /* Temperature control/read registers (88X3310 only) */
136 MV_V2_TEMP_CTRL = 0xf08a,
137 MV_V2_TEMP_CTRL_MASK = 0xc000,
138 MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
139 MV_V2_TEMP_CTRL_DISABLE = 0xc000,
140 MV_V2_TEMP = 0xf08c,
141 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
142};
143
144struct mv3310_chip {
145 bool (*has_downshift)(struct phy_device *phydev);
146 void (*init_supported_interfaces)(unsigned long *mask);
147 int (*get_mactype)(struct phy_device *phydev);
148 int (*set_mactype)(struct phy_device *phydev, int mactype);
149 int (*select_mactype)(unsigned long *interfaces);
150 int (*init_interface)(struct phy_device *phydev, int mactype);
151
152#ifdef CONFIG_HWMON
153 int (*hwmon_read_temp_reg)(struct phy_device *phydev);
154#endif
155};
156
157struct mv3310_priv {
158 DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX);
159
160 u32 firmware_ver;
161 bool has_downshift;
162 bool rate_match;
163 phy_interface_t const_interface;
164
165 struct device *hwmon_dev;
166 char *hwmon_name;
167};
168
169static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev)
170{
171 return phydev->drv->driver_data;
172}
173
174#ifdef CONFIG_HWMON
175static umode_t mv3310_hwmon_is_visible(const void *data,
176 enum hwmon_sensor_types type,
177 u32 attr, int channel)
178{
179 if (type == hwmon_chip && attr == hwmon_chip_update_interval)
180 return 0444;
181 if (type == hwmon_temp && attr == hwmon_temp_input)
182 return 0444;
183 return 0;
184}
185
186static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev)
187{
188 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
189}
190
191static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev)
192{
193 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP);
194}
195
196static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
197 u32 attr, int channel, long *value)
198{
199 struct phy_device *phydev = dev_get_drvdata(dev);
200 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
201 int temp;
202
203 if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
204 *value = MSEC_PER_SEC;
205 return 0;
206 }
207
208 if (type == hwmon_temp && attr == hwmon_temp_input) {
209 temp = chip->hwmon_read_temp_reg(phydev);
210 if (temp < 0)
211 return temp;
212
213 *value = ((temp & 0xff) - 75) * 1000;
214
215 return 0;
216 }
217
218 return -EOPNOTSUPP;
219}
220
221static const struct hwmon_ops mv3310_hwmon_ops = {
222 .is_visible = mv3310_hwmon_is_visible,
223 .read = mv3310_hwmon_read,
224};
225
226static u32 mv3310_hwmon_chip_config[] = {
227 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
228 0,
229};
230
231static const struct hwmon_channel_info mv3310_hwmon_chip = {
232 .type = hwmon_chip,
233 .config = mv3310_hwmon_chip_config,
234};
235
236static u32 mv3310_hwmon_temp_config[] = {
237 HWMON_T_INPUT,
238 0,
239};
240
241static const struct hwmon_channel_info mv3310_hwmon_temp = {
242 .type = hwmon_temp,
243 .config = mv3310_hwmon_temp_config,
244};
245
246static const struct hwmon_channel_info *mv3310_hwmon_info[] = {
247 &mv3310_hwmon_chip,
248 &mv3310_hwmon_temp,
249 NULL,
250};
251
252static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
253 .ops = &mv3310_hwmon_ops,
254 .info = mv3310_hwmon_info,
255};
256
257static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
258{
259 u16 val;
260 int ret;
261
262 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310)
263 return 0;
264
265 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
266 MV_V2_TEMP_UNKNOWN);
267 if (ret < 0)
268 return ret;
269
270 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
271
272 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
273 MV_V2_TEMP_CTRL_MASK, val);
274}
275
276static int mv3310_hwmon_probe(struct phy_device *phydev)
277{
278 struct device *dev = &phydev->mdio.dev;
279 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
280 int i, j, ret;
281
282 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
283 if (!priv->hwmon_name)
284 return -ENODEV;
285
286 for (i = j = 0; priv->hwmon_name[i]; i++) {
287 if (isalnum(priv->hwmon_name[i])) {
288 if (i != j)
289 priv->hwmon_name[j] = priv->hwmon_name[i];
290 j++;
291 }
292 }
293 priv->hwmon_name[j] = '\0';
294
295 ret = mv3310_hwmon_config(phydev, true);
296 if (ret)
297 return ret;
298
299 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
300 priv->hwmon_name, phydev,
301 &mv3310_hwmon_chip_info, NULL);
302
303 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
304}
305#else
306static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
307{
308 return 0;
309}
310
311static int mv3310_hwmon_probe(struct phy_device *phydev)
312{
313 return 0;
314}
315#endif
316
317static int mv3310_power_down(struct phy_device *phydev)
318{
319 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
320 MV_V2_PORT_CTRL_PWRDOWN);
321}
322
323static int mv3310_power_up(struct phy_device *phydev)
324{
325 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
326 int ret;
327
328 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
329 MV_V2_PORT_CTRL_PWRDOWN);
330
331 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
332 priv->firmware_ver < 0x00030000)
333 return ret;
334
335 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
336 MV_V2_33X0_PORT_CTRL_SWRST);
337}
338
339static int mv3310_reset(struct phy_device *phydev, u32 unit)
340{
341 int val, err;
342
343 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
344 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
345 if (err < 0)
346 return err;
347
348 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
349 unit + MDIO_CTRL1, val,
350 !(val & MDIO_CTRL1_RESET),
351 5000, 100000, true);
352}
353
354static int mv3310_get_downshift(struct phy_device *phydev, u8 *ds)
355{
356 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
357 int val;
358
359 if (!priv->has_downshift)
360 return -EOPNOTSUPP;
361
362 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1);
363 if (val < 0)
364 return val;
365
366 if (val & MV_PCS_DSC1_ENABLE)
367 /* assume that all fields are the same */
368 *ds = 1 + FIELD_GET(MV_PCS_DSC1_10GBT, (u16)val);
369 else
370 *ds = DOWNSHIFT_DEV_DISABLE;
371
372 return 0;
373}
374
375static int mv3310_set_downshift(struct phy_device *phydev, u8 ds)
376{
377 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
378 u16 val;
379 int err;
380
381 if (!priv->has_downshift)
382 return -EOPNOTSUPP;
383
384 if (ds == DOWNSHIFT_DEV_DISABLE)
385 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
386 MV_PCS_DSC1_ENABLE);
387
388 /* DOWNSHIFT_DEV_DEFAULT_COUNT is confusing. It looks like it should
389 * set the default settings for the PHY. However, it is used for
390 * "ethtool --set-phy-tunable ethN downshift on". The intention is
391 * to enable downshift at a default number of retries. The default
392 * settings for 88x3310 are for two retries with downshift disabled.
393 * So let's use two retries with downshift enabled.
394 */
395 if (ds == DOWNSHIFT_DEV_DEFAULT_COUNT)
396 ds = 2;
397
398 if (ds > 8)
399 return -E2BIG;
400
401 ds -= 1;
402 val = FIELD_PREP(MV_PCS_DSC2_2P5G, ds);
403 val |= FIELD_PREP(MV_PCS_DSC2_5G, ds);
404 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2,
405 MV_PCS_DSC2_2P5G | MV_PCS_DSC2_5G, val);
406 if (err < 0)
407 return err;
408
409 val = MV_PCS_DSC1_ENABLE;
410 val |= FIELD_PREP(MV_PCS_DSC1_10GBT, ds);
411 val |= FIELD_PREP(MV_PCS_DSC1_1GBR, ds);
412 val |= FIELD_PREP(MV_PCS_DSC1_100BTX, ds);
413
414 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
415 MV_PCS_DSC1_ENABLE | MV_PCS_DSC1_10GBT |
416 MV_PCS_DSC1_1GBR | MV_PCS_DSC1_100BTX, val);
417}
418
419static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
420{
421 int val;
422
423 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1);
424 if (val < 0)
425 return val;
426
427 switch (val & MV_PCS_CSCR1_ED_MASK) {
428 case MV_PCS_CSCR1_ED_NLP:
429 *edpd = 1000;
430 break;
431 case MV_PCS_CSCR1_ED_RX:
432 *edpd = ETHTOOL_PHY_EDPD_NO_TX;
433 break;
434 default:
435 *edpd = ETHTOOL_PHY_EDPD_DISABLE;
436 break;
437 }
438 return 0;
439}
440
441static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd)
442{
443 u16 val;
444 int err;
445
446 switch (edpd) {
447 case 1000:
448 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
449 val = MV_PCS_CSCR1_ED_NLP;
450 break;
451
452 case ETHTOOL_PHY_EDPD_NO_TX:
453 val = MV_PCS_CSCR1_ED_RX;
454 break;
455
456 case ETHTOOL_PHY_EDPD_DISABLE:
457 val = MV_PCS_CSCR1_ED_OFF;
458 break;
459
460 default:
461 return -EINVAL;
462 }
463
464 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
465 MV_PCS_CSCR1_ED_MASK, val);
466 if (err > 0)
467 err = mv3310_reset(phydev, MV_PCS_BASE_T);
468
469 return err;
470}
471
472static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
473{
474 struct phy_device *phydev = upstream;
475 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
476 DECLARE_PHY_INTERFACE_MASK(interfaces);
477 phy_interface_t iface;
478
479 sfp_parse_support(phydev->sfp_bus, id, support, interfaces);
480 iface = sfp_select_interface(phydev->sfp_bus, support);
481
482 if (iface != PHY_INTERFACE_MODE_10GBASER) {
483 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
484 return -EINVAL;
485 }
486 return 0;
487}
488
489static const struct sfp_upstream_ops mv3310_sfp_ops = {
490 .attach = phy_sfp_attach,
491 .detach = phy_sfp_detach,
492 .module_insert = mv3310_sfp_insert,
493};
494
495static int mv3310_probe(struct phy_device *phydev)
496{
497 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
498 struct mv3310_priv *priv;
499 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
500 int ret;
501
502 if (!phydev->is_c45 ||
503 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
504 return -ENODEV;
505
506 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
507 if (ret < 0)
508 return ret;
509
510 if (ret & MV_PMA_BOOT_FATAL) {
511 dev_warn(&phydev->mdio.dev,
512 "PHY failed to boot firmware, status=%04x\n", ret);
513 return -ENODEV;
514 }
515
516 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
517 if (!priv)
518 return -ENOMEM;
519
520 dev_set_drvdata(&phydev->mdio.dev, priv);
521
522 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
523 if (ret < 0)
524 return ret;
525
526 priv->firmware_ver = ret << 16;
527
528 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
529 if (ret < 0)
530 return ret;
531
532 priv->firmware_ver |= ret;
533
534 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n",
535 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
536 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
537
538 if (chip->has_downshift)
539 priv->has_downshift = chip->has_downshift(phydev);
540
541 /* Powering down the port when not in use saves about 600mW */
542 ret = mv3310_power_down(phydev);
543 if (ret)
544 return ret;
545
546 ret = mv3310_hwmon_probe(phydev);
547 if (ret)
548 return ret;
549
550 chip->init_supported_interfaces(priv->supported_interfaces);
551
552 return phy_sfp_probe(phydev, &mv3310_sfp_ops);
553}
554
555static void mv3310_remove(struct phy_device *phydev)
556{
557 mv3310_hwmon_config(phydev, false);
558}
559
560static int mv3310_suspend(struct phy_device *phydev)
561{
562 return mv3310_power_down(phydev);
563}
564
565static int mv3310_resume(struct phy_device *phydev)
566{
567 int ret;
568
569 ret = mv3310_power_up(phydev);
570 if (ret)
571 return ret;
572
573 return mv3310_hwmon_config(phydev, true);
574}
575
576/* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
577 * don't set bit 14 in PMA Extended Abilities (1.11), although they do
578 * support 2.5GBASET and 5GBASET. For these models, we can still read their
579 * 2.5G/5G extended abilities register (1.21). We detect these models based on
580 * the PMA device identifier, with a mask matching models known to have this
581 * issue
582 */
583static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
584{
585 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
586 return false;
587
588 /* Only some revisions of the 88X3310 family PMA seem to be impacted */
589 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
590 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
591}
592
593static int mv2110_get_mactype(struct phy_device *phydev)
594{
595 int mactype;
596
597 mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
598 if (mactype < 0)
599 return mactype;
600
601 return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
602}
603
604static int mv2110_set_mactype(struct phy_device *phydev, int mactype)
605{
606 int err, val;
607
608 mactype &= MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
609 err = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL,
610 MV_PMA_21X0_PORT_CTRL_SWRST |
611 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK,
612 MV_PMA_21X0_PORT_CTRL_SWRST | mactype);
613 if (err)
614 return err;
615
616 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
617 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS |
618 MV_AN_21X0_SERDES_CTRL2_RUN_INIT);
619 if (err)
620 return err;
621
622 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN,
623 MV_AN_21X0_SERDES_CTRL2, val,
624 !(val &
625 MV_AN_21X0_SERDES_CTRL2_RUN_INIT),
626 5000, 100000, true);
627 if (err)
628 return err;
629
630 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
631 MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS);
632}
633
634static int mv2110_select_mactype(unsigned long *interfaces)
635{
636 if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces))
637 return MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII;
638 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
639 !test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
640 return MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER;
641 else if (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
642 return MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
643 else
644 return -1;
645}
646
647static int mv3310_get_mactype(struct phy_device *phydev)
648{
649 int mactype;
650
651 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
652 if (mactype < 0)
653 return mactype;
654
655 return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
656}
657
658static int mv3310_set_mactype(struct phy_device *phydev, int mactype)
659{
660 int ret;
661
662 mactype &= MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
663 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
664 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK,
665 mactype);
666 if (ret <= 0)
667 return ret;
668
669 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
670 MV_V2_33X0_PORT_CTRL_SWRST);
671}
672
673static int mv3310_select_mactype(unsigned long *interfaces)
674{
675 if (test_bit(PHY_INTERFACE_MODE_USXGMII, interfaces))
676 return MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII;
677 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
678 test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
679 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
680 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
681 test_bit(PHY_INTERFACE_MODE_RXAUI, interfaces))
682 return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI;
683 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces) &&
684 test_bit(PHY_INTERFACE_MODE_XAUI, interfaces))
685 return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI;
686 else if (test_bit(PHY_INTERFACE_MODE_10GBASER, interfaces))
687 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
688 else if (test_bit(PHY_INTERFACE_MODE_RXAUI, interfaces))
689 return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH;
690 else if (test_bit(PHY_INTERFACE_MODE_XAUI, interfaces))
691 return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH;
692 else if (test_bit(PHY_INTERFACE_MODE_SGMII, interfaces))
693 return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
694 else
695 return -1;
696}
697
698static int mv2110_init_interface(struct phy_device *phydev, int mactype)
699{
700 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
701
702 priv->rate_match = false;
703
704 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
705 priv->rate_match = true;
706
707 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII)
708 priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
709 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
710 priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
711 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER ||
712 mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN)
713 priv->const_interface = PHY_INTERFACE_MODE_NA;
714 else
715 return -EINVAL;
716
717 return 0;
718}
719
720static int mv3310_init_interface(struct phy_device *phydev, int mactype)
721{
722 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
723
724 priv->rate_match = false;
725
726 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
727 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
728 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
729 priv->rate_match = true;
730
731 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII)
732 priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
733 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
734 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN ||
735 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER)
736 priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
737 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
738 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI)
739 priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
740 else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH ||
741 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI)
742 priv->const_interface = PHY_INTERFACE_MODE_XAUI;
743 else
744 return -EINVAL;
745
746 return 0;
747}
748
749static int mv3340_init_interface(struct phy_device *phydev, int mactype)
750{
751 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
752 int err = 0;
753
754 priv->rate_match = false;
755
756 if (mactype == MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN)
757 priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
758 else
759 err = mv3310_init_interface(phydev, mactype);
760
761 return err;
762}
763
764static int mv3310_config_init(struct phy_device *phydev)
765{
766 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
767 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
768 int err, mactype;
769
770 /* Check that the PHY interface type is compatible */
771 if (!test_bit(phydev->interface, priv->supported_interfaces))
772 return -ENODEV;
773
774 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
775
776 /* Power up so reset works */
777 err = mv3310_power_up(phydev);
778 if (err)
779 return err;
780
781 /* If host provided host supported interface modes, try to select the
782 * best one
783 */
784 if (!phy_interface_empty(phydev->host_interfaces)) {
785 mactype = chip->select_mactype(phydev->host_interfaces);
786 if (mactype >= 0) {
787 phydev_info(phydev, "Changing MACTYPE to %i\n",
788 mactype);
789 err = chip->set_mactype(phydev, mactype);
790 if (err)
791 return err;
792 }
793 }
794
795 mactype = chip->get_mactype(phydev);
796 if (mactype < 0)
797 return mactype;
798
799 err = chip->init_interface(phydev, mactype);
800 if (err) {
801 phydev_err(phydev, "MACTYPE configuration invalid\n");
802 return err;
803 }
804
805 /* Enable EDPD mode - saving 600mW */
806 err = mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
807 if (err)
808 return err;
809
810 /* Allow downshift */
811 err = mv3310_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
812 if (err && err != -EOPNOTSUPP)
813 return err;
814
815 return 0;
816}
817
818static int mv3310_get_features(struct phy_device *phydev)
819{
820 int ret, val;
821
822 ret = genphy_c45_pma_read_abilities(phydev);
823 if (ret)
824 return ret;
825
826 if (mv3310_has_pma_ngbaset_quirk(phydev)) {
827 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
828 MDIO_PMA_NG_EXTABLE);
829 if (val < 0)
830 return val;
831
832 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
833 phydev->supported,
834 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
835
836 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
837 phydev->supported,
838 val & MDIO_PMA_NG_EXTABLE_5GBT);
839 }
840
841 return 0;
842}
843
844static int mv3310_config_mdix(struct phy_device *phydev)
845{
846 u16 val;
847 int err;
848
849 switch (phydev->mdix_ctrl) {
850 case ETH_TP_MDI_AUTO:
851 val = MV_PCS_CSCR1_MDIX_AUTO;
852 break;
853 case ETH_TP_MDI_X:
854 val = MV_PCS_CSCR1_MDIX_MDIX;
855 break;
856 case ETH_TP_MDI:
857 val = MV_PCS_CSCR1_MDIX_MDI;
858 break;
859 default:
860 return -EINVAL;
861 }
862
863 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
864 MV_PCS_CSCR1_MDIX_MASK, val);
865 if (err > 0)
866 err = mv3310_reset(phydev, MV_PCS_BASE_T);
867
868 return err;
869}
870
871static int mv3310_config_aneg(struct phy_device *phydev)
872{
873 bool changed = false;
874 u16 reg;
875 int ret;
876
877 ret = mv3310_config_mdix(phydev);
878 if (ret < 0)
879 return ret;
880
881 if (phydev->autoneg == AUTONEG_DISABLE)
882 return genphy_c45_pma_setup_forced(phydev);
883
884 ret = genphy_c45_an_config_aneg(phydev);
885 if (ret < 0)
886 return ret;
887 if (ret > 0)
888 changed = true;
889
890 /* Clause 45 has no standardized support for 1000BaseT, therefore
891 * use vendor registers for this mode.
892 */
893 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
894 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
895 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
896 if (ret < 0)
897 return ret;
898 if (ret > 0)
899 changed = true;
900
901 return genphy_c45_check_and_restart_aneg(phydev, changed);
902}
903
904static int mv3310_aneg_done(struct phy_device *phydev)
905{
906 int val;
907
908 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
909 if (val < 0)
910 return val;
911
912 if (val & MDIO_STAT1_LSTATUS)
913 return 1;
914
915 return genphy_c45_aneg_done(phydev);
916}
917
918static void mv3310_update_interface(struct phy_device *phydev)
919{
920 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
921
922 if (!phydev->link)
923 return;
924
925 /* In all of the "* with Rate Matching" modes the PHY interface is fixed
926 * at 10Gb. The PHY adapts the rate to actual wire speed with help of
927 * internal 16KB buffer.
928 *
929 * In USXGMII mode the PHY interface mode is also fixed.
930 */
931 if (priv->rate_match ||
932 priv->const_interface == PHY_INTERFACE_MODE_USXGMII) {
933 phydev->interface = priv->const_interface;
934 return;
935 }
936
937 /* The PHY automatically switches its serdes interface (and active PHYXS
938 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R /
939 * xaui / rxaui modes according to the speed.
940 * Florian suggests setting phydev->interface to communicate this to the
941 * MAC. Only do this if we are already in one of the above modes.
942 */
943 switch (phydev->speed) {
944 case SPEED_10000:
945 phydev->interface = priv->const_interface;
946 break;
947 case SPEED_5000:
948 phydev->interface = PHY_INTERFACE_MODE_5GBASER;
949 break;
950 case SPEED_2500:
951 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
952 break;
953 case SPEED_1000:
954 case SPEED_100:
955 case SPEED_10:
956 phydev->interface = PHY_INTERFACE_MODE_SGMII;
957 break;
958 default:
959 break;
960 }
961}
962
963/* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
964static int mv3310_read_status_10gbaser(struct phy_device *phydev)
965{
966 phydev->link = 1;
967 phydev->speed = SPEED_10000;
968 phydev->duplex = DUPLEX_FULL;
969 phydev->port = PORT_FIBRE;
970
971 return 0;
972}
973
974static int mv3310_read_status_copper(struct phy_device *phydev)
975{
976 int cssr1, speed, val;
977
978 val = genphy_c45_read_link(phydev);
979 if (val < 0)
980 return val;
981
982 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
983 if (val < 0)
984 return val;
985
986 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
987 if (cssr1 < 0)
988 return cssr1;
989
990 /* If the link settings are not resolved, mark the link down */
991 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) {
992 phydev->link = 0;
993 return 0;
994 }
995
996 /* Read the copper link settings */
997 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK;
998 if (speed == MV_PCS_CSSR1_SPD1_SPD2)
999 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK;
1000
1001 switch (speed) {
1002 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000:
1003 phydev->speed = SPEED_10000;
1004 break;
1005
1006 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000:
1007 phydev->speed = SPEED_5000;
1008 break;
1009
1010 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500:
1011 phydev->speed = SPEED_2500;
1012 break;
1013
1014 case MV_PCS_CSSR1_SPD1_1000:
1015 phydev->speed = SPEED_1000;
1016 break;
1017
1018 case MV_PCS_CSSR1_SPD1_100:
1019 phydev->speed = SPEED_100;
1020 break;
1021
1022 case MV_PCS_CSSR1_SPD1_10:
1023 phydev->speed = SPEED_10;
1024 break;
1025 }
1026
1027 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ?
1028 DUPLEX_FULL : DUPLEX_HALF;
1029 phydev->port = PORT_TP;
1030 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ?
1031 ETH_TP_MDI_X : ETH_TP_MDI;
1032
1033 if (val & MDIO_AN_STAT1_COMPLETE) {
1034 val = genphy_c45_read_lpa(phydev);
1035 if (val < 0)
1036 return val;
1037
1038 /* Read the link partner's 1G advertisement */
1039 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
1040 if (val < 0)
1041 return val;
1042
1043 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
1044
1045 /* Update the pause status */
1046 phy_resolve_aneg_pause(phydev);
1047 }
1048
1049 return 0;
1050}
1051
1052static int mv3310_read_status(struct phy_device *phydev)
1053{
1054 int err, val;
1055
1056 phydev->speed = SPEED_UNKNOWN;
1057 phydev->duplex = DUPLEX_UNKNOWN;
1058 linkmode_zero(phydev->lp_advertising);
1059 phydev->link = 0;
1060 phydev->pause = 0;
1061 phydev->asym_pause = 0;
1062 phydev->mdix = ETH_TP_MDI_INVALID;
1063
1064 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
1065 if (val < 0)
1066 return val;
1067
1068 if (val & MDIO_STAT1_LSTATUS)
1069 err = mv3310_read_status_10gbaser(phydev);
1070 else
1071 err = mv3310_read_status_copper(phydev);
1072 if (err < 0)
1073 return err;
1074
1075 if (phydev->link)
1076 mv3310_update_interface(phydev);
1077
1078 return 0;
1079}
1080
1081static int mv3310_get_tunable(struct phy_device *phydev,
1082 struct ethtool_tunable *tuna, void *data)
1083{
1084 switch (tuna->id) {
1085 case ETHTOOL_PHY_DOWNSHIFT:
1086 return mv3310_get_downshift(phydev, data);
1087 case ETHTOOL_PHY_EDPD:
1088 return mv3310_get_edpd(phydev, data);
1089 default:
1090 return -EOPNOTSUPP;
1091 }
1092}
1093
1094static int mv3310_set_tunable(struct phy_device *phydev,
1095 struct ethtool_tunable *tuna, const void *data)
1096{
1097 switch (tuna->id) {
1098 case ETHTOOL_PHY_DOWNSHIFT:
1099 return mv3310_set_downshift(phydev, *(u8 *)data);
1100 case ETHTOOL_PHY_EDPD:
1101 return mv3310_set_edpd(phydev, *(u16 *)data);
1102 default:
1103 return -EOPNOTSUPP;
1104 }
1105}
1106
1107static bool mv3310_has_downshift(struct phy_device *phydev)
1108{
1109 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
1110
1111 /* Fails to downshift with firmware older than v0.3.5.0 */
1112 return priv->firmware_ver >= MV_VERSION(0,3,5,0);
1113}
1114
1115static void mv3310_init_supported_interfaces(unsigned long *mask)
1116{
1117 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1118 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1119 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
1120 __set_bit(PHY_INTERFACE_MODE_XAUI, mask);
1121 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
1122 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1123 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1124}
1125
1126static void mv3340_init_supported_interfaces(unsigned long *mask)
1127{
1128 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1129 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1130 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
1131 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
1132 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1133 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1134}
1135
1136static void mv2110_init_supported_interfaces(unsigned long *mask)
1137{
1138 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1139 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1140 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
1141 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1142 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1143}
1144
1145static void mv2111_init_supported_interfaces(unsigned long *mask)
1146{
1147 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
1148 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
1149 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
1150 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
1151}
1152
1153static const struct mv3310_chip mv3310_type = {
1154 .has_downshift = mv3310_has_downshift,
1155 .init_supported_interfaces = mv3310_init_supported_interfaces,
1156 .get_mactype = mv3310_get_mactype,
1157 .set_mactype = mv3310_set_mactype,
1158 .select_mactype = mv3310_select_mactype,
1159 .init_interface = mv3310_init_interface,
1160
1161#ifdef CONFIG_HWMON
1162 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
1163#endif
1164};
1165
1166static const struct mv3310_chip mv3340_type = {
1167 .has_downshift = mv3310_has_downshift,
1168 .init_supported_interfaces = mv3340_init_supported_interfaces,
1169 .get_mactype = mv3310_get_mactype,
1170 .set_mactype = mv3310_set_mactype,
1171 .select_mactype = mv3310_select_mactype,
1172 .init_interface = mv3340_init_interface,
1173
1174#ifdef CONFIG_HWMON
1175 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
1176#endif
1177};
1178
1179static const struct mv3310_chip mv2110_type = {
1180 .init_supported_interfaces = mv2110_init_supported_interfaces,
1181 .get_mactype = mv2110_get_mactype,
1182 .set_mactype = mv2110_set_mactype,
1183 .select_mactype = mv2110_select_mactype,
1184 .init_interface = mv2110_init_interface,
1185
1186#ifdef CONFIG_HWMON
1187 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
1188#endif
1189};
1190
1191static const struct mv3310_chip mv2111_type = {
1192 .init_supported_interfaces = mv2111_init_supported_interfaces,
1193 .get_mactype = mv2110_get_mactype,
1194 .set_mactype = mv2110_set_mactype,
1195 .select_mactype = mv2110_select_mactype,
1196 .init_interface = mv2110_init_interface,
1197
1198#ifdef CONFIG_HWMON
1199 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
1200#endif
1201};
1202
1203static int mv3310_get_number_of_ports(struct phy_device *phydev)
1204{
1205 int ret;
1206
1207 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO);
1208 if (ret < 0)
1209 return ret;
1210
1211 ret &= MV_PCS_PORT_INFO_NPORTS_MASK;
1212 ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT;
1213
1214 return ret + 1;
1215}
1216
1217static int mv3310_match_phy_device(struct phy_device *phydev)
1218{
1219 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1220 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
1221 return 0;
1222
1223 return mv3310_get_number_of_ports(phydev) == 1;
1224}
1225
1226static int mv3340_match_phy_device(struct phy_device *phydev)
1227{
1228 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1229 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
1230 return 0;
1231
1232 return mv3310_get_number_of_ports(phydev) == 4;
1233}
1234
1235static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g)
1236{
1237 int val;
1238
1239 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1240 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110)
1241 return 0;
1242
1243 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED);
1244 if (val < 0)
1245 return val;
1246
1247 return !!(val & MDIO_PCS_SPEED_5G) == has_5g;
1248}
1249
1250static int mv2110_match_phy_device(struct phy_device *phydev)
1251{
1252 return mv211x_match_phy_device(phydev, true);
1253}
1254
1255static int mv2111_match_phy_device(struct phy_device *phydev)
1256{
1257 return mv211x_match_phy_device(phydev, false);
1258}
1259
1260static void mv3110_get_wol(struct phy_device *phydev,
1261 struct ethtool_wolinfo *wol)
1262{
1263 int ret;
1264
1265 wol->supported = WAKE_MAGIC;
1266 wol->wolopts = 0;
1267
1268 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL);
1269 if (ret < 0)
1270 return;
1271
1272 if (ret & MV_V2_WOL_CTRL_MAGIC_PKT_EN)
1273 wol->wolopts |= WAKE_MAGIC;
1274}
1275
1276static int mv3110_set_wol(struct phy_device *phydev,
1277 struct ethtool_wolinfo *wol)
1278{
1279 int ret;
1280
1281 if (wol->wolopts & WAKE_MAGIC) {
1282 /* Enable the WOL interrupt */
1283 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1284 MV_V2_PORT_INTR_MASK,
1285 MV_V2_PORT_INTR_STS_WOL_EN);
1286 if (ret < 0)
1287 return ret;
1288
1289 /* Store the device address for the magic packet */
1290 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1291 MV_V2_MAGIC_PKT_WORD2,
1292 ((phydev->attached_dev->dev_addr[5] << 8) |
1293 phydev->attached_dev->dev_addr[4]));
1294 if (ret < 0)
1295 return ret;
1296
1297 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1298 MV_V2_MAGIC_PKT_WORD1,
1299 ((phydev->attached_dev->dev_addr[3] << 8) |
1300 phydev->attached_dev->dev_addr[2]));
1301 if (ret < 0)
1302 return ret;
1303
1304 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1305 MV_V2_MAGIC_PKT_WORD0,
1306 ((phydev->attached_dev->dev_addr[1] << 8) |
1307 phydev->attached_dev->dev_addr[0]));
1308 if (ret < 0)
1309 return ret;
1310
1311 /* Clear WOL status and enable magic packet matching */
1312 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1313 MV_V2_WOL_CTRL,
1314 MV_V2_WOL_CTRL_MAGIC_PKT_EN |
1315 MV_V2_WOL_CTRL_CLEAR_STS);
1316 if (ret < 0)
1317 return ret;
1318 } else {
1319 /* Disable magic packet matching & reset WOL status bit */
1320 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1321 MV_V2_WOL_CTRL,
1322 MV_V2_WOL_CTRL_MAGIC_PKT_EN,
1323 MV_V2_WOL_CTRL_CLEAR_STS);
1324 if (ret < 0)
1325 return ret;
1326 }
1327
1328 /* Reset the clear WOL status bit as it does not self-clear */
1329 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
1330 MV_V2_WOL_CTRL,
1331 MV_V2_WOL_CTRL_CLEAR_STS);
1332}
1333
1334static struct phy_driver mv3310_drivers[] = {
1335 {
1336 .phy_id = MARVELL_PHY_ID_88X3310,
1337 .phy_id_mask = MARVELL_PHY_ID_MASK,
1338 .match_phy_device = mv3310_match_phy_device,
1339 .name = "mv88x3310",
1340 .driver_data = &mv3310_type,
1341 .get_features = mv3310_get_features,
1342 .config_init = mv3310_config_init,
1343 .probe = mv3310_probe,
1344 .suspend = mv3310_suspend,
1345 .resume = mv3310_resume,
1346 .config_aneg = mv3310_config_aneg,
1347 .aneg_done = mv3310_aneg_done,
1348 .read_status = mv3310_read_status,
1349 .get_tunable = mv3310_get_tunable,
1350 .set_tunable = mv3310_set_tunable,
1351 .remove = mv3310_remove,
1352 .set_loopback = genphy_c45_loopback,
1353 .get_wol = mv3110_get_wol,
1354 .set_wol = mv3110_set_wol,
1355 },
1356 {
1357 .phy_id = MARVELL_PHY_ID_88X3310,
1358 .phy_id_mask = MARVELL_PHY_ID_MASK,
1359 .match_phy_device = mv3340_match_phy_device,
1360 .name = "mv88x3340",
1361 .driver_data = &mv3340_type,
1362 .get_features = mv3310_get_features,
1363 .config_init = mv3310_config_init,
1364 .probe = mv3310_probe,
1365 .suspend = mv3310_suspend,
1366 .resume = mv3310_resume,
1367 .config_aneg = mv3310_config_aneg,
1368 .aneg_done = mv3310_aneg_done,
1369 .read_status = mv3310_read_status,
1370 .get_tunable = mv3310_get_tunable,
1371 .set_tunable = mv3310_set_tunable,
1372 .remove = mv3310_remove,
1373 .set_loopback = genphy_c45_loopback,
1374 },
1375 {
1376 .phy_id = MARVELL_PHY_ID_88E2110,
1377 .phy_id_mask = MARVELL_PHY_ID_MASK,
1378 .match_phy_device = mv2110_match_phy_device,
1379 .name = "mv88e2110",
1380 .driver_data = &mv2110_type,
1381 .probe = mv3310_probe,
1382 .suspend = mv3310_suspend,
1383 .resume = mv3310_resume,
1384 .config_init = mv3310_config_init,
1385 .config_aneg = mv3310_config_aneg,
1386 .aneg_done = mv3310_aneg_done,
1387 .read_status = mv3310_read_status,
1388 .get_tunable = mv3310_get_tunable,
1389 .set_tunable = mv3310_set_tunable,
1390 .remove = mv3310_remove,
1391 .set_loopback = genphy_c45_loopback,
1392 .get_wol = mv3110_get_wol,
1393 .set_wol = mv3110_set_wol,
1394 },
1395 {
1396 .phy_id = MARVELL_PHY_ID_88E2110,
1397 .phy_id_mask = MARVELL_PHY_ID_MASK,
1398 .match_phy_device = mv2111_match_phy_device,
1399 .name = "mv88e2111",
1400 .driver_data = &mv2111_type,
1401 .probe = mv3310_probe,
1402 .suspend = mv3310_suspend,
1403 .resume = mv3310_resume,
1404 .config_init = mv3310_config_init,
1405 .config_aneg = mv3310_config_aneg,
1406 .aneg_done = mv3310_aneg_done,
1407 .read_status = mv3310_read_status,
1408 .get_tunable = mv3310_get_tunable,
1409 .set_tunable = mv3310_set_tunable,
1410 .remove = mv3310_remove,
1411 .set_loopback = genphy_c45_loopback,
1412 },
1413};
1414
1415module_phy_driver(mv3310_drivers);
1416
1417static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
1418 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
1419 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
1420 { },
1421};
1422MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
1423MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");
1424MODULE_LICENSE("GPL");