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1// SPDX-License-Identifier: GPL-2.0-only
2/**
3 * Host side test driver to test endpoint functionality
4 *
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9#include <linux/crc32.h>
10#include <linux/delay.h>
11#include <linux/fs.h>
12#include <linux/io.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/miscdevice.h>
16#include <linux/module.h>
17#include <linux/mutex.h>
18#include <linux/random.h>
19#include <linux/slab.h>
20#include <linux/uaccess.h>
21#include <linux/pci.h>
22#include <linux/pci_ids.h>
23
24#include <linux/pci_regs.h>
25
26#include <uapi/linux/pcitest.h>
27
28#define DRV_MODULE_NAME "pci-endpoint-test"
29
30#define IRQ_TYPE_UNDEFINED -1
31#define IRQ_TYPE_LEGACY 0
32#define IRQ_TYPE_MSI 1
33#define IRQ_TYPE_MSIX 2
34
35#define PCI_ENDPOINT_TEST_MAGIC 0x0
36
37#define PCI_ENDPOINT_TEST_COMMAND 0x4
38#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
39#define COMMAND_RAISE_MSI_IRQ BIT(1)
40#define COMMAND_RAISE_MSIX_IRQ BIT(2)
41#define COMMAND_READ BIT(3)
42#define COMMAND_WRITE BIT(4)
43#define COMMAND_COPY BIT(5)
44
45#define PCI_ENDPOINT_TEST_STATUS 0x8
46#define STATUS_READ_SUCCESS BIT(0)
47#define STATUS_READ_FAIL BIT(1)
48#define STATUS_WRITE_SUCCESS BIT(2)
49#define STATUS_WRITE_FAIL BIT(3)
50#define STATUS_COPY_SUCCESS BIT(4)
51#define STATUS_COPY_FAIL BIT(5)
52#define STATUS_IRQ_RAISED BIT(6)
53#define STATUS_SRC_ADDR_INVALID BIT(7)
54#define STATUS_DST_ADDR_INVALID BIT(8)
55
56#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
57#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
58
59#define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
60#define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
61
62#define PCI_ENDPOINT_TEST_SIZE 0x1c
63#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
64
65#define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
66#define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
67
68#define PCI_ENDPOINT_TEST_FLAGS 0x2c
69#define FLAG_USE_DMA BIT(0)
70
71#define PCI_DEVICE_ID_TI_J721E 0xb00d
72#define PCI_DEVICE_ID_TI_AM654 0xb00c
73
74#define is_am654_pci_dev(pdev) \
75 ((pdev)->device == PCI_DEVICE_ID_TI_AM654)
76
77#define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
78
79static DEFINE_IDA(pci_endpoint_test_ida);
80
81#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
82 miscdev)
83
84static bool no_msi;
85module_param(no_msi, bool, 0444);
86MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
87
88static int irq_type = IRQ_TYPE_MSI;
89module_param(irq_type, int, 0444);
90MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
91
92enum pci_barno {
93 BAR_0,
94 BAR_1,
95 BAR_2,
96 BAR_3,
97 BAR_4,
98 BAR_5,
99};
100
101struct pci_endpoint_test {
102 struct pci_dev *pdev;
103 void __iomem *base;
104 void __iomem *bar[PCI_STD_NUM_BARS];
105 struct completion irq_raised;
106 int last_irq;
107 int num_irqs;
108 int irq_type;
109 /* mutex to protect the ioctls */
110 struct mutex mutex;
111 struct miscdevice miscdev;
112 enum pci_barno test_reg_bar;
113 size_t alignment;
114 const char *name;
115};
116
117struct pci_endpoint_test_data {
118 enum pci_barno test_reg_bar;
119 size_t alignment;
120 int irq_type;
121};
122
123static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
124 u32 offset)
125{
126 return readl(test->base + offset);
127}
128
129static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
130 u32 offset, u32 value)
131{
132 writel(value, test->base + offset);
133}
134
135static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
136 int bar, int offset)
137{
138 return readl(test->bar[bar] + offset);
139}
140
141static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
142 int bar, u32 offset, u32 value)
143{
144 writel(value, test->bar[bar] + offset);
145}
146
147static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
148{
149 struct pci_endpoint_test *test = dev_id;
150 u32 reg;
151
152 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
153 if (reg & STATUS_IRQ_RAISED) {
154 test->last_irq = irq;
155 complete(&test->irq_raised);
156 reg &= ~STATUS_IRQ_RAISED;
157 }
158 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
159 reg);
160
161 return IRQ_HANDLED;
162}
163
164static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
165{
166 struct pci_dev *pdev = test->pdev;
167
168 pci_free_irq_vectors(pdev);
169 test->irq_type = IRQ_TYPE_UNDEFINED;
170}
171
172static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
173 int type)
174{
175 int irq = -1;
176 struct pci_dev *pdev = test->pdev;
177 struct device *dev = &pdev->dev;
178 bool res = true;
179
180 switch (type) {
181 case IRQ_TYPE_LEGACY:
182 irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
183 if (irq < 0)
184 dev_err(dev, "Failed to get Legacy interrupt\n");
185 break;
186 case IRQ_TYPE_MSI:
187 irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
188 if (irq < 0)
189 dev_err(dev, "Failed to get MSI interrupts\n");
190 break;
191 case IRQ_TYPE_MSIX:
192 irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
193 if (irq < 0)
194 dev_err(dev, "Failed to get MSI-X interrupts\n");
195 break;
196 default:
197 dev_err(dev, "Invalid IRQ type selected\n");
198 }
199
200 if (irq < 0) {
201 irq = 0;
202 res = false;
203 }
204
205 test->irq_type = type;
206 test->num_irqs = irq;
207
208 return res;
209}
210
211static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
212{
213 int i;
214 struct pci_dev *pdev = test->pdev;
215 struct device *dev = &pdev->dev;
216
217 for (i = 0; i < test->num_irqs; i++)
218 devm_free_irq(dev, pci_irq_vector(pdev, i), test);
219
220 test->num_irqs = 0;
221}
222
223static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
224{
225 int i;
226 int err;
227 struct pci_dev *pdev = test->pdev;
228 struct device *dev = &pdev->dev;
229
230 for (i = 0; i < test->num_irqs; i++) {
231 err = devm_request_irq(dev, pci_irq_vector(pdev, i),
232 pci_endpoint_test_irqhandler,
233 IRQF_SHARED, test->name, test);
234 if (err)
235 goto fail;
236 }
237
238 return true;
239
240fail:
241 switch (irq_type) {
242 case IRQ_TYPE_LEGACY:
243 dev_err(dev, "Failed to request IRQ %d for Legacy\n",
244 pci_irq_vector(pdev, i));
245 break;
246 case IRQ_TYPE_MSI:
247 dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
248 pci_irq_vector(pdev, i),
249 i + 1);
250 break;
251 case IRQ_TYPE_MSIX:
252 dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
253 pci_irq_vector(pdev, i),
254 i + 1);
255 break;
256 }
257
258 return false;
259}
260
261static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
262 enum pci_barno barno)
263{
264 int j;
265 u32 val;
266 int size;
267 struct pci_dev *pdev = test->pdev;
268
269 if (!test->bar[barno])
270 return false;
271
272 size = pci_resource_len(pdev, barno);
273
274 if (barno == test->test_reg_bar)
275 size = 0x4;
276
277 for (j = 0; j < size; j += 4)
278 pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
279
280 for (j = 0; j < size; j += 4) {
281 val = pci_endpoint_test_bar_readl(test, barno, j);
282 if (val != 0xA0A0A0A0)
283 return false;
284 }
285
286 return true;
287}
288
289static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
290{
291 u32 val;
292
293 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
294 IRQ_TYPE_LEGACY);
295 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
296 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
297 COMMAND_RAISE_LEGACY_IRQ);
298 val = wait_for_completion_timeout(&test->irq_raised,
299 msecs_to_jiffies(1000));
300 if (!val)
301 return false;
302
303 return true;
304}
305
306static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
307 u16 msi_num, bool msix)
308{
309 u32 val;
310 struct pci_dev *pdev = test->pdev;
311
312 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
313 msix == false ? IRQ_TYPE_MSI :
314 IRQ_TYPE_MSIX);
315 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
316 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
317 msix == false ? COMMAND_RAISE_MSI_IRQ :
318 COMMAND_RAISE_MSIX_IRQ);
319 val = wait_for_completion_timeout(&test->irq_raised,
320 msecs_to_jiffies(1000));
321 if (!val)
322 return false;
323
324 if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
325 return true;
326
327 return false;
328}
329
330static bool pci_endpoint_test_copy(struct pci_endpoint_test *test,
331 unsigned long arg)
332{
333 struct pci_endpoint_test_xfer_param param;
334 bool ret = false;
335 void *src_addr;
336 void *dst_addr;
337 u32 flags = 0;
338 bool use_dma;
339 size_t size;
340 dma_addr_t src_phys_addr;
341 dma_addr_t dst_phys_addr;
342 struct pci_dev *pdev = test->pdev;
343 struct device *dev = &pdev->dev;
344 void *orig_src_addr;
345 dma_addr_t orig_src_phys_addr;
346 void *orig_dst_addr;
347 dma_addr_t orig_dst_phys_addr;
348 size_t offset;
349 size_t alignment = test->alignment;
350 int irq_type = test->irq_type;
351 u32 src_crc32;
352 u32 dst_crc32;
353 int err;
354
355 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
356 if (err) {
357 dev_err(dev, "Failed to get transfer param\n");
358 return false;
359 }
360
361 size = param.size;
362 if (size > SIZE_MAX - alignment)
363 goto err;
364
365 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
366 if (use_dma)
367 flags |= FLAG_USE_DMA;
368
369 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
370 dev_err(dev, "Invalid IRQ type option\n");
371 goto err;
372 }
373
374 orig_src_addr = kzalloc(size + alignment, GFP_KERNEL);
375 if (!orig_src_addr) {
376 dev_err(dev, "Failed to allocate source buffer\n");
377 ret = false;
378 goto err;
379 }
380
381 get_random_bytes(orig_src_addr, size + alignment);
382 orig_src_phys_addr = dma_map_single(dev, orig_src_addr,
383 size + alignment, DMA_TO_DEVICE);
384 if (dma_mapping_error(dev, orig_src_phys_addr)) {
385 dev_err(dev, "failed to map source buffer address\n");
386 ret = false;
387 goto err_src_phys_addr;
388 }
389
390 if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
391 src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
392 offset = src_phys_addr - orig_src_phys_addr;
393 src_addr = orig_src_addr + offset;
394 } else {
395 src_phys_addr = orig_src_phys_addr;
396 src_addr = orig_src_addr;
397 }
398
399 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
400 lower_32_bits(src_phys_addr));
401
402 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
403 upper_32_bits(src_phys_addr));
404
405 src_crc32 = crc32_le(~0, src_addr, size);
406
407 orig_dst_addr = kzalloc(size + alignment, GFP_KERNEL);
408 if (!orig_dst_addr) {
409 dev_err(dev, "Failed to allocate destination address\n");
410 ret = false;
411 goto err_dst_addr;
412 }
413
414 orig_dst_phys_addr = dma_map_single(dev, orig_dst_addr,
415 size + alignment, DMA_FROM_DEVICE);
416 if (dma_mapping_error(dev, orig_dst_phys_addr)) {
417 dev_err(dev, "failed to map destination buffer address\n");
418 ret = false;
419 goto err_dst_phys_addr;
420 }
421
422 if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
423 dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
424 offset = dst_phys_addr - orig_dst_phys_addr;
425 dst_addr = orig_dst_addr + offset;
426 } else {
427 dst_phys_addr = orig_dst_phys_addr;
428 dst_addr = orig_dst_addr;
429 }
430
431 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
432 lower_32_bits(dst_phys_addr));
433 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
434 upper_32_bits(dst_phys_addr));
435
436 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
437 size);
438
439 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
440 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
441 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
442 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
443 COMMAND_COPY);
444
445 wait_for_completion(&test->irq_raised);
446
447 dma_unmap_single(dev, orig_dst_phys_addr, size + alignment,
448 DMA_FROM_DEVICE);
449
450 dst_crc32 = crc32_le(~0, dst_addr, size);
451 if (dst_crc32 == src_crc32)
452 ret = true;
453
454err_dst_phys_addr:
455 kfree(orig_dst_addr);
456
457err_dst_addr:
458 dma_unmap_single(dev, orig_src_phys_addr, size + alignment,
459 DMA_TO_DEVICE);
460
461err_src_phys_addr:
462 kfree(orig_src_addr);
463
464err:
465 return ret;
466}
467
468static bool pci_endpoint_test_write(struct pci_endpoint_test *test,
469 unsigned long arg)
470{
471 struct pci_endpoint_test_xfer_param param;
472 bool ret = false;
473 u32 flags = 0;
474 bool use_dma;
475 u32 reg;
476 void *addr;
477 dma_addr_t phys_addr;
478 struct pci_dev *pdev = test->pdev;
479 struct device *dev = &pdev->dev;
480 void *orig_addr;
481 dma_addr_t orig_phys_addr;
482 size_t offset;
483 size_t alignment = test->alignment;
484 int irq_type = test->irq_type;
485 size_t size;
486 u32 crc32;
487 int err;
488
489 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
490 if (err != 0) {
491 dev_err(dev, "Failed to get transfer param\n");
492 return false;
493 }
494
495 size = param.size;
496 if (size > SIZE_MAX - alignment)
497 goto err;
498
499 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
500 if (use_dma)
501 flags |= FLAG_USE_DMA;
502
503 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
504 dev_err(dev, "Invalid IRQ type option\n");
505 goto err;
506 }
507
508 orig_addr = kzalloc(size + alignment, GFP_KERNEL);
509 if (!orig_addr) {
510 dev_err(dev, "Failed to allocate address\n");
511 ret = false;
512 goto err;
513 }
514
515 get_random_bytes(orig_addr, size + alignment);
516
517 orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
518 DMA_TO_DEVICE);
519 if (dma_mapping_error(dev, orig_phys_addr)) {
520 dev_err(dev, "failed to map source buffer address\n");
521 ret = false;
522 goto err_phys_addr;
523 }
524
525 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
526 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
527 offset = phys_addr - orig_phys_addr;
528 addr = orig_addr + offset;
529 } else {
530 phys_addr = orig_phys_addr;
531 addr = orig_addr;
532 }
533
534 crc32 = crc32_le(~0, addr, size);
535 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
536 crc32);
537
538 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
539 lower_32_bits(phys_addr));
540 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
541 upper_32_bits(phys_addr));
542
543 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
544
545 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
546 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
547 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
548 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
549 COMMAND_READ);
550
551 wait_for_completion(&test->irq_raised);
552
553 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
554 if (reg & STATUS_READ_SUCCESS)
555 ret = true;
556
557 dma_unmap_single(dev, orig_phys_addr, size + alignment,
558 DMA_TO_DEVICE);
559
560err_phys_addr:
561 kfree(orig_addr);
562
563err:
564 return ret;
565}
566
567static bool pci_endpoint_test_read(struct pci_endpoint_test *test,
568 unsigned long arg)
569{
570 struct pci_endpoint_test_xfer_param param;
571 bool ret = false;
572 u32 flags = 0;
573 bool use_dma;
574 size_t size;
575 void *addr;
576 dma_addr_t phys_addr;
577 struct pci_dev *pdev = test->pdev;
578 struct device *dev = &pdev->dev;
579 void *orig_addr;
580 dma_addr_t orig_phys_addr;
581 size_t offset;
582 size_t alignment = test->alignment;
583 int irq_type = test->irq_type;
584 u32 crc32;
585 int err;
586
587 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
588 if (err) {
589 dev_err(dev, "Failed to get transfer param\n");
590 return false;
591 }
592
593 size = param.size;
594 if (size > SIZE_MAX - alignment)
595 goto err;
596
597 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
598 if (use_dma)
599 flags |= FLAG_USE_DMA;
600
601 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
602 dev_err(dev, "Invalid IRQ type option\n");
603 goto err;
604 }
605
606 orig_addr = kzalloc(size + alignment, GFP_KERNEL);
607 if (!orig_addr) {
608 dev_err(dev, "Failed to allocate destination address\n");
609 ret = false;
610 goto err;
611 }
612
613 orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
614 DMA_FROM_DEVICE);
615 if (dma_mapping_error(dev, orig_phys_addr)) {
616 dev_err(dev, "failed to map source buffer address\n");
617 ret = false;
618 goto err_phys_addr;
619 }
620
621 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
622 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
623 offset = phys_addr - orig_phys_addr;
624 addr = orig_addr + offset;
625 } else {
626 phys_addr = orig_phys_addr;
627 addr = orig_addr;
628 }
629
630 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
631 lower_32_bits(phys_addr));
632 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
633 upper_32_bits(phys_addr));
634
635 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
636
637 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
638 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
639 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
640 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
641 COMMAND_WRITE);
642
643 wait_for_completion(&test->irq_raised);
644
645 dma_unmap_single(dev, orig_phys_addr, size + alignment,
646 DMA_FROM_DEVICE);
647
648 crc32 = crc32_le(~0, addr, size);
649 if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
650 ret = true;
651
652err_phys_addr:
653 kfree(orig_addr);
654err:
655 return ret;
656}
657
658static bool pci_endpoint_test_clear_irq(struct pci_endpoint_test *test)
659{
660 pci_endpoint_test_release_irq(test);
661 pci_endpoint_test_free_irq_vectors(test);
662 return true;
663}
664
665static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
666 int req_irq_type)
667{
668 struct pci_dev *pdev = test->pdev;
669 struct device *dev = &pdev->dev;
670
671 if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
672 dev_err(dev, "Invalid IRQ type option\n");
673 return false;
674 }
675
676 if (test->irq_type == req_irq_type)
677 return true;
678
679 pci_endpoint_test_release_irq(test);
680 pci_endpoint_test_free_irq_vectors(test);
681
682 if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
683 goto err;
684
685 if (!pci_endpoint_test_request_irq(test))
686 goto err;
687
688 return true;
689
690err:
691 pci_endpoint_test_free_irq_vectors(test);
692 return false;
693}
694
695static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
696 unsigned long arg)
697{
698 int ret = -EINVAL;
699 enum pci_barno bar;
700 struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
701 struct pci_dev *pdev = test->pdev;
702
703 mutex_lock(&test->mutex);
704 switch (cmd) {
705 case PCITEST_BAR:
706 bar = arg;
707 if (bar < 0 || bar > 5)
708 goto ret;
709 if (is_am654_pci_dev(pdev) && bar == BAR_0)
710 goto ret;
711 ret = pci_endpoint_test_bar(test, bar);
712 break;
713 case PCITEST_LEGACY_IRQ:
714 ret = pci_endpoint_test_legacy_irq(test);
715 break;
716 case PCITEST_MSI:
717 case PCITEST_MSIX:
718 ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
719 break;
720 case PCITEST_WRITE:
721 ret = pci_endpoint_test_write(test, arg);
722 break;
723 case PCITEST_READ:
724 ret = pci_endpoint_test_read(test, arg);
725 break;
726 case PCITEST_COPY:
727 ret = pci_endpoint_test_copy(test, arg);
728 break;
729 case PCITEST_SET_IRQTYPE:
730 ret = pci_endpoint_test_set_irq(test, arg);
731 break;
732 case PCITEST_GET_IRQTYPE:
733 ret = irq_type;
734 break;
735 case PCITEST_CLEAR_IRQ:
736 ret = pci_endpoint_test_clear_irq(test);
737 break;
738 }
739
740ret:
741 mutex_unlock(&test->mutex);
742 return ret;
743}
744
745static const struct file_operations pci_endpoint_test_fops = {
746 .owner = THIS_MODULE,
747 .unlocked_ioctl = pci_endpoint_test_ioctl,
748};
749
750static int pci_endpoint_test_probe(struct pci_dev *pdev,
751 const struct pci_device_id *ent)
752{
753 int err;
754 int id;
755 char name[24];
756 enum pci_barno bar;
757 void __iomem *base;
758 struct device *dev = &pdev->dev;
759 struct pci_endpoint_test *test;
760 struct pci_endpoint_test_data *data;
761 enum pci_barno test_reg_bar = BAR_0;
762 struct miscdevice *misc_device;
763
764 if (pci_is_bridge(pdev))
765 return -ENODEV;
766
767 test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
768 if (!test)
769 return -ENOMEM;
770
771 test->test_reg_bar = 0;
772 test->alignment = 0;
773 test->pdev = pdev;
774 test->irq_type = IRQ_TYPE_UNDEFINED;
775
776 if (no_msi)
777 irq_type = IRQ_TYPE_LEGACY;
778
779 data = (struct pci_endpoint_test_data *)ent->driver_data;
780 if (data) {
781 test_reg_bar = data->test_reg_bar;
782 test->test_reg_bar = test_reg_bar;
783 test->alignment = data->alignment;
784 irq_type = data->irq_type;
785 }
786
787 init_completion(&test->irq_raised);
788 mutex_init(&test->mutex);
789
790 if ((dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)) != 0) &&
791 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
792 dev_err(dev, "Cannot set DMA mask\n");
793 return -EINVAL;
794 }
795
796 err = pci_enable_device(pdev);
797 if (err) {
798 dev_err(dev, "Cannot enable PCI device\n");
799 return err;
800 }
801
802 err = pci_request_regions(pdev, DRV_MODULE_NAME);
803 if (err) {
804 dev_err(dev, "Cannot obtain PCI resources\n");
805 goto err_disable_pdev;
806 }
807
808 pci_set_master(pdev);
809
810 if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type))
811 goto err_disable_irq;
812
813 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
814 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
815 base = pci_ioremap_bar(pdev, bar);
816 if (!base) {
817 dev_err(dev, "Failed to read BAR%d\n", bar);
818 WARN_ON(bar == test_reg_bar);
819 }
820 test->bar[bar] = base;
821 }
822 }
823
824 test->base = test->bar[test_reg_bar];
825 if (!test->base) {
826 err = -ENOMEM;
827 dev_err(dev, "Cannot perform PCI test without BAR%d\n",
828 test_reg_bar);
829 goto err_iounmap;
830 }
831
832 pci_set_drvdata(pdev, test);
833
834 id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
835 if (id < 0) {
836 err = id;
837 dev_err(dev, "Unable to get id\n");
838 goto err_iounmap;
839 }
840
841 snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
842 test->name = kstrdup(name, GFP_KERNEL);
843 if (!test->name) {
844 err = -ENOMEM;
845 goto err_ida_remove;
846 }
847
848 if (!pci_endpoint_test_request_irq(test))
849 goto err_kfree_test_name;
850
851 misc_device = &test->miscdev;
852 misc_device->minor = MISC_DYNAMIC_MINOR;
853 misc_device->name = kstrdup(name, GFP_KERNEL);
854 if (!misc_device->name) {
855 err = -ENOMEM;
856 goto err_release_irq;
857 }
858 misc_device->fops = &pci_endpoint_test_fops,
859
860 err = misc_register(misc_device);
861 if (err) {
862 dev_err(dev, "Failed to register device\n");
863 goto err_kfree_name;
864 }
865
866 return 0;
867
868err_kfree_name:
869 kfree(misc_device->name);
870
871err_release_irq:
872 pci_endpoint_test_release_irq(test);
873
874err_kfree_test_name:
875 kfree(test->name);
876
877err_ida_remove:
878 ida_simple_remove(&pci_endpoint_test_ida, id);
879
880err_iounmap:
881 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
882 if (test->bar[bar])
883 pci_iounmap(pdev, test->bar[bar]);
884 }
885
886err_disable_irq:
887 pci_endpoint_test_free_irq_vectors(test);
888 pci_release_regions(pdev);
889
890err_disable_pdev:
891 pci_disable_device(pdev);
892
893 return err;
894}
895
896static void pci_endpoint_test_remove(struct pci_dev *pdev)
897{
898 int id;
899 enum pci_barno bar;
900 struct pci_endpoint_test *test = pci_get_drvdata(pdev);
901 struct miscdevice *misc_device = &test->miscdev;
902
903 if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
904 return;
905 if (id < 0)
906 return;
907
908 misc_deregister(&test->miscdev);
909 kfree(misc_device->name);
910 kfree(test->name);
911 ida_simple_remove(&pci_endpoint_test_ida, id);
912 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
913 if (test->bar[bar])
914 pci_iounmap(pdev, test->bar[bar]);
915 }
916
917 pci_endpoint_test_release_irq(test);
918 pci_endpoint_test_free_irq_vectors(test);
919
920 pci_release_regions(pdev);
921 pci_disable_device(pdev);
922}
923
924static const struct pci_endpoint_test_data default_data = {
925 .test_reg_bar = BAR_0,
926 .alignment = SZ_4K,
927 .irq_type = IRQ_TYPE_MSI,
928};
929
930static const struct pci_endpoint_test_data am654_data = {
931 .test_reg_bar = BAR_2,
932 .alignment = SZ_64K,
933 .irq_type = IRQ_TYPE_MSI,
934};
935
936static const struct pci_endpoint_test_data j721e_data = {
937 .alignment = 256,
938 .irq_type = IRQ_TYPE_MSI,
939};
940
941static const struct pci_device_id pci_endpoint_test_tbl[] = {
942 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),
943 .driver_data = (kernel_ulong_t)&default_data,
944 },
945 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x),
946 .driver_data = (kernel_ulong_t)&default_data,
947 },
948 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) },
949 { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
950 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
951 .driver_data = (kernel_ulong_t)&am654_data
952 },
953 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),
954 },
955 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
956 .driver_data = (kernel_ulong_t)&j721e_data,
957 },
958 { }
959};
960MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
961
962static struct pci_driver pci_endpoint_test_driver = {
963 .name = DRV_MODULE_NAME,
964 .id_table = pci_endpoint_test_tbl,
965 .probe = pci_endpoint_test_probe,
966 .remove = pci_endpoint_test_remove,
967};
968module_pci_driver(pci_endpoint_test_driver);
969
970MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
971MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
972MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/**
3 * Host side test driver to test endpoint functionality
4 *
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9#include <linux/crc32.h>
10#include <linux/delay.h>
11#include <linux/fs.h>
12#include <linux/io.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/miscdevice.h>
16#include <linux/module.h>
17#include <linux/mutex.h>
18#include <linux/random.h>
19#include <linux/slab.h>
20#include <linux/uaccess.h>
21#include <linux/pci.h>
22#include <linux/pci_ids.h>
23
24#include <linux/pci_regs.h>
25
26#include <uapi/linux/pcitest.h>
27
28#define DRV_MODULE_NAME "pci-endpoint-test"
29
30#define IRQ_TYPE_UNDEFINED -1
31#define IRQ_TYPE_LEGACY 0
32#define IRQ_TYPE_MSI 1
33#define IRQ_TYPE_MSIX 2
34
35#define PCI_ENDPOINT_TEST_MAGIC 0x0
36
37#define PCI_ENDPOINT_TEST_COMMAND 0x4
38#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
39#define COMMAND_RAISE_MSI_IRQ BIT(1)
40#define COMMAND_RAISE_MSIX_IRQ BIT(2)
41#define COMMAND_READ BIT(3)
42#define COMMAND_WRITE BIT(4)
43#define COMMAND_COPY BIT(5)
44
45#define PCI_ENDPOINT_TEST_STATUS 0x8
46#define STATUS_READ_SUCCESS BIT(0)
47#define STATUS_READ_FAIL BIT(1)
48#define STATUS_WRITE_SUCCESS BIT(2)
49#define STATUS_WRITE_FAIL BIT(3)
50#define STATUS_COPY_SUCCESS BIT(4)
51#define STATUS_COPY_FAIL BIT(5)
52#define STATUS_IRQ_RAISED BIT(6)
53#define STATUS_SRC_ADDR_INVALID BIT(7)
54#define STATUS_DST_ADDR_INVALID BIT(8)
55
56#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
57#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
58
59#define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
60#define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
61
62#define PCI_ENDPOINT_TEST_SIZE 0x1c
63#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
64
65#define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
66#define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
67
68#define PCI_ENDPOINT_TEST_FLAGS 0x2c
69#define FLAG_USE_DMA BIT(0)
70
71#define PCI_DEVICE_ID_TI_AM654 0xb00c
72#define PCI_DEVICE_ID_TI_J7200 0xb00f
73#define PCI_DEVICE_ID_TI_AM64 0xb010
74#define PCI_DEVICE_ID_LS1088A 0x80c0
75
76#define is_am654_pci_dev(pdev) \
77 ((pdev)->device == PCI_DEVICE_ID_TI_AM654)
78
79#define PCI_DEVICE_ID_RENESAS_R8A774A1 0x0028
80#define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b
81#define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
82#define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025
83
84static DEFINE_IDA(pci_endpoint_test_ida);
85
86#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
87 miscdev)
88
89static bool no_msi;
90module_param(no_msi, bool, 0444);
91MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
92
93static int irq_type = IRQ_TYPE_MSI;
94module_param(irq_type, int, 0444);
95MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
96
97enum pci_barno {
98 BAR_0,
99 BAR_1,
100 BAR_2,
101 BAR_3,
102 BAR_4,
103 BAR_5,
104};
105
106struct pci_endpoint_test {
107 struct pci_dev *pdev;
108 void __iomem *base;
109 void __iomem *bar[PCI_STD_NUM_BARS];
110 struct completion irq_raised;
111 int last_irq;
112 int num_irqs;
113 int irq_type;
114 /* mutex to protect the ioctls */
115 struct mutex mutex;
116 struct miscdevice miscdev;
117 enum pci_barno test_reg_bar;
118 size_t alignment;
119 const char *name;
120};
121
122struct pci_endpoint_test_data {
123 enum pci_barno test_reg_bar;
124 size_t alignment;
125 int irq_type;
126};
127
128static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
129 u32 offset)
130{
131 return readl(test->base + offset);
132}
133
134static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
135 u32 offset, u32 value)
136{
137 writel(value, test->base + offset);
138}
139
140static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
141 int bar, int offset)
142{
143 return readl(test->bar[bar] + offset);
144}
145
146static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
147 int bar, u32 offset, u32 value)
148{
149 writel(value, test->bar[bar] + offset);
150}
151
152static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
153{
154 struct pci_endpoint_test *test = dev_id;
155 u32 reg;
156
157 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
158 if (reg & STATUS_IRQ_RAISED) {
159 test->last_irq = irq;
160 complete(&test->irq_raised);
161 reg &= ~STATUS_IRQ_RAISED;
162 }
163 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
164 reg);
165
166 return IRQ_HANDLED;
167}
168
169static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
170{
171 struct pci_dev *pdev = test->pdev;
172
173 pci_free_irq_vectors(pdev);
174 test->irq_type = IRQ_TYPE_UNDEFINED;
175}
176
177static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
178 int type)
179{
180 int irq = -1;
181 struct pci_dev *pdev = test->pdev;
182 struct device *dev = &pdev->dev;
183 bool res = true;
184
185 switch (type) {
186 case IRQ_TYPE_LEGACY:
187 irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
188 if (irq < 0)
189 dev_err(dev, "Failed to get Legacy interrupt\n");
190 break;
191 case IRQ_TYPE_MSI:
192 irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
193 if (irq < 0)
194 dev_err(dev, "Failed to get MSI interrupts\n");
195 break;
196 case IRQ_TYPE_MSIX:
197 irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
198 if (irq < 0)
199 dev_err(dev, "Failed to get MSI-X interrupts\n");
200 break;
201 default:
202 dev_err(dev, "Invalid IRQ type selected\n");
203 }
204
205 if (irq < 0) {
206 irq = 0;
207 res = false;
208 }
209
210 test->irq_type = type;
211 test->num_irqs = irq;
212
213 return res;
214}
215
216static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
217{
218 int i;
219 struct pci_dev *pdev = test->pdev;
220 struct device *dev = &pdev->dev;
221
222 for (i = 0; i < test->num_irqs; i++)
223 devm_free_irq(dev, pci_irq_vector(pdev, i), test);
224
225 test->num_irqs = 0;
226}
227
228static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
229{
230 int i;
231 int err;
232 struct pci_dev *pdev = test->pdev;
233 struct device *dev = &pdev->dev;
234
235 for (i = 0; i < test->num_irqs; i++) {
236 err = devm_request_irq(dev, pci_irq_vector(pdev, i),
237 pci_endpoint_test_irqhandler,
238 IRQF_SHARED, test->name, test);
239 if (err)
240 goto fail;
241 }
242
243 return true;
244
245fail:
246 switch (irq_type) {
247 case IRQ_TYPE_LEGACY:
248 dev_err(dev, "Failed to request IRQ %d for Legacy\n",
249 pci_irq_vector(pdev, i));
250 break;
251 case IRQ_TYPE_MSI:
252 dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
253 pci_irq_vector(pdev, i),
254 i + 1);
255 break;
256 case IRQ_TYPE_MSIX:
257 dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
258 pci_irq_vector(pdev, i),
259 i + 1);
260 break;
261 }
262
263 return false;
264}
265
266static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
267 enum pci_barno barno)
268{
269 int j;
270 u32 val;
271 int size;
272 struct pci_dev *pdev = test->pdev;
273
274 if (!test->bar[barno])
275 return false;
276
277 size = pci_resource_len(pdev, barno);
278
279 if (barno == test->test_reg_bar)
280 size = 0x4;
281
282 for (j = 0; j < size; j += 4)
283 pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
284
285 for (j = 0; j < size; j += 4) {
286 val = pci_endpoint_test_bar_readl(test, barno, j);
287 if (val != 0xA0A0A0A0)
288 return false;
289 }
290
291 return true;
292}
293
294static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
295{
296 u32 val;
297
298 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
299 IRQ_TYPE_LEGACY);
300 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
301 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
302 COMMAND_RAISE_LEGACY_IRQ);
303 val = wait_for_completion_timeout(&test->irq_raised,
304 msecs_to_jiffies(1000));
305 if (!val)
306 return false;
307
308 return true;
309}
310
311static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
312 u16 msi_num, bool msix)
313{
314 u32 val;
315 struct pci_dev *pdev = test->pdev;
316
317 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
318 msix == false ? IRQ_TYPE_MSI :
319 IRQ_TYPE_MSIX);
320 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
321 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
322 msix == false ? COMMAND_RAISE_MSI_IRQ :
323 COMMAND_RAISE_MSIX_IRQ);
324 val = wait_for_completion_timeout(&test->irq_raised,
325 msecs_to_jiffies(1000));
326 if (!val)
327 return false;
328
329 if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
330 return true;
331
332 return false;
333}
334
335static int pci_endpoint_test_validate_xfer_params(struct device *dev,
336 struct pci_endpoint_test_xfer_param *param, size_t alignment)
337{
338 if (!param->size) {
339 dev_dbg(dev, "Data size is zero\n");
340 return -EINVAL;
341 }
342
343 if (param->size > SIZE_MAX - alignment) {
344 dev_dbg(dev, "Maximum transfer data size exceeded\n");
345 return -EINVAL;
346 }
347
348 return 0;
349}
350
351static bool pci_endpoint_test_copy(struct pci_endpoint_test *test,
352 unsigned long arg)
353{
354 struct pci_endpoint_test_xfer_param param;
355 bool ret = false;
356 void *src_addr;
357 void *dst_addr;
358 u32 flags = 0;
359 bool use_dma;
360 size_t size;
361 dma_addr_t src_phys_addr;
362 dma_addr_t dst_phys_addr;
363 struct pci_dev *pdev = test->pdev;
364 struct device *dev = &pdev->dev;
365 void *orig_src_addr;
366 dma_addr_t orig_src_phys_addr;
367 void *orig_dst_addr;
368 dma_addr_t orig_dst_phys_addr;
369 size_t offset;
370 size_t alignment = test->alignment;
371 int irq_type = test->irq_type;
372 u32 src_crc32;
373 u32 dst_crc32;
374 int err;
375
376 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
377 if (err) {
378 dev_err(dev, "Failed to get transfer param\n");
379 return false;
380 }
381
382 err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment);
383 if (err)
384 return false;
385
386 size = param.size;
387
388 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
389 if (use_dma)
390 flags |= FLAG_USE_DMA;
391
392 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
393 dev_err(dev, "Invalid IRQ type option\n");
394 goto err;
395 }
396
397 orig_src_addr = kzalloc(size + alignment, GFP_KERNEL);
398 if (!orig_src_addr) {
399 dev_err(dev, "Failed to allocate source buffer\n");
400 ret = false;
401 goto err;
402 }
403
404 get_random_bytes(orig_src_addr, size + alignment);
405 orig_src_phys_addr = dma_map_single(dev, orig_src_addr,
406 size + alignment, DMA_TO_DEVICE);
407 if (dma_mapping_error(dev, orig_src_phys_addr)) {
408 dev_err(dev, "failed to map source buffer address\n");
409 ret = false;
410 goto err_src_phys_addr;
411 }
412
413 if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
414 src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
415 offset = src_phys_addr - orig_src_phys_addr;
416 src_addr = orig_src_addr + offset;
417 } else {
418 src_phys_addr = orig_src_phys_addr;
419 src_addr = orig_src_addr;
420 }
421
422 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
423 lower_32_bits(src_phys_addr));
424
425 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
426 upper_32_bits(src_phys_addr));
427
428 src_crc32 = crc32_le(~0, src_addr, size);
429
430 orig_dst_addr = kzalloc(size + alignment, GFP_KERNEL);
431 if (!orig_dst_addr) {
432 dev_err(dev, "Failed to allocate destination address\n");
433 ret = false;
434 goto err_dst_addr;
435 }
436
437 orig_dst_phys_addr = dma_map_single(dev, orig_dst_addr,
438 size + alignment, DMA_FROM_DEVICE);
439 if (dma_mapping_error(dev, orig_dst_phys_addr)) {
440 dev_err(dev, "failed to map destination buffer address\n");
441 ret = false;
442 goto err_dst_phys_addr;
443 }
444
445 if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
446 dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
447 offset = dst_phys_addr - orig_dst_phys_addr;
448 dst_addr = orig_dst_addr + offset;
449 } else {
450 dst_phys_addr = orig_dst_phys_addr;
451 dst_addr = orig_dst_addr;
452 }
453
454 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
455 lower_32_bits(dst_phys_addr));
456 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
457 upper_32_bits(dst_phys_addr));
458
459 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
460 size);
461
462 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
463 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
464 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
465 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
466 COMMAND_COPY);
467
468 wait_for_completion(&test->irq_raised);
469
470 dma_unmap_single(dev, orig_dst_phys_addr, size + alignment,
471 DMA_FROM_DEVICE);
472
473 dst_crc32 = crc32_le(~0, dst_addr, size);
474 if (dst_crc32 == src_crc32)
475 ret = true;
476
477err_dst_phys_addr:
478 kfree(orig_dst_addr);
479
480err_dst_addr:
481 dma_unmap_single(dev, orig_src_phys_addr, size + alignment,
482 DMA_TO_DEVICE);
483
484err_src_phys_addr:
485 kfree(orig_src_addr);
486
487err:
488 return ret;
489}
490
491static bool pci_endpoint_test_write(struct pci_endpoint_test *test,
492 unsigned long arg)
493{
494 struct pci_endpoint_test_xfer_param param;
495 bool ret = false;
496 u32 flags = 0;
497 bool use_dma;
498 u32 reg;
499 void *addr;
500 dma_addr_t phys_addr;
501 struct pci_dev *pdev = test->pdev;
502 struct device *dev = &pdev->dev;
503 void *orig_addr;
504 dma_addr_t orig_phys_addr;
505 size_t offset;
506 size_t alignment = test->alignment;
507 int irq_type = test->irq_type;
508 size_t size;
509 u32 crc32;
510 int err;
511
512 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
513 if (err != 0) {
514 dev_err(dev, "Failed to get transfer param\n");
515 return false;
516 }
517
518 err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment);
519 if (err)
520 return false;
521
522 size = param.size;
523
524 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
525 if (use_dma)
526 flags |= FLAG_USE_DMA;
527
528 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
529 dev_err(dev, "Invalid IRQ type option\n");
530 goto err;
531 }
532
533 orig_addr = kzalloc(size + alignment, GFP_KERNEL);
534 if (!orig_addr) {
535 dev_err(dev, "Failed to allocate address\n");
536 ret = false;
537 goto err;
538 }
539
540 get_random_bytes(orig_addr, size + alignment);
541
542 orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
543 DMA_TO_DEVICE);
544 if (dma_mapping_error(dev, orig_phys_addr)) {
545 dev_err(dev, "failed to map source buffer address\n");
546 ret = false;
547 goto err_phys_addr;
548 }
549
550 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
551 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
552 offset = phys_addr - orig_phys_addr;
553 addr = orig_addr + offset;
554 } else {
555 phys_addr = orig_phys_addr;
556 addr = orig_addr;
557 }
558
559 crc32 = crc32_le(~0, addr, size);
560 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
561 crc32);
562
563 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
564 lower_32_bits(phys_addr));
565 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
566 upper_32_bits(phys_addr));
567
568 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
569
570 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
571 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
572 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
573 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
574 COMMAND_READ);
575
576 wait_for_completion(&test->irq_raised);
577
578 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
579 if (reg & STATUS_READ_SUCCESS)
580 ret = true;
581
582 dma_unmap_single(dev, orig_phys_addr, size + alignment,
583 DMA_TO_DEVICE);
584
585err_phys_addr:
586 kfree(orig_addr);
587
588err:
589 return ret;
590}
591
592static bool pci_endpoint_test_read(struct pci_endpoint_test *test,
593 unsigned long arg)
594{
595 struct pci_endpoint_test_xfer_param param;
596 bool ret = false;
597 u32 flags = 0;
598 bool use_dma;
599 size_t size;
600 void *addr;
601 dma_addr_t phys_addr;
602 struct pci_dev *pdev = test->pdev;
603 struct device *dev = &pdev->dev;
604 void *orig_addr;
605 dma_addr_t orig_phys_addr;
606 size_t offset;
607 size_t alignment = test->alignment;
608 int irq_type = test->irq_type;
609 u32 crc32;
610 int err;
611
612 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
613 if (err) {
614 dev_err(dev, "Failed to get transfer param\n");
615 return false;
616 }
617
618 err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment);
619 if (err)
620 return false;
621
622 size = param.size;
623
624 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
625 if (use_dma)
626 flags |= FLAG_USE_DMA;
627
628 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
629 dev_err(dev, "Invalid IRQ type option\n");
630 goto err;
631 }
632
633 orig_addr = kzalloc(size + alignment, GFP_KERNEL);
634 if (!orig_addr) {
635 dev_err(dev, "Failed to allocate destination address\n");
636 ret = false;
637 goto err;
638 }
639
640 orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
641 DMA_FROM_DEVICE);
642 if (dma_mapping_error(dev, orig_phys_addr)) {
643 dev_err(dev, "failed to map source buffer address\n");
644 ret = false;
645 goto err_phys_addr;
646 }
647
648 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
649 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
650 offset = phys_addr - orig_phys_addr;
651 addr = orig_addr + offset;
652 } else {
653 phys_addr = orig_phys_addr;
654 addr = orig_addr;
655 }
656
657 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
658 lower_32_bits(phys_addr));
659 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
660 upper_32_bits(phys_addr));
661
662 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
663
664 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
665 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
666 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
667 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
668 COMMAND_WRITE);
669
670 wait_for_completion(&test->irq_raised);
671
672 dma_unmap_single(dev, orig_phys_addr, size + alignment,
673 DMA_FROM_DEVICE);
674
675 crc32 = crc32_le(~0, addr, size);
676 if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
677 ret = true;
678
679err_phys_addr:
680 kfree(orig_addr);
681err:
682 return ret;
683}
684
685static bool pci_endpoint_test_clear_irq(struct pci_endpoint_test *test)
686{
687 pci_endpoint_test_release_irq(test);
688 pci_endpoint_test_free_irq_vectors(test);
689 return true;
690}
691
692static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
693 int req_irq_type)
694{
695 struct pci_dev *pdev = test->pdev;
696 struct device *dev = &pdev->dev;
697
698 if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
699 dev_err(dev, "Invalid IRQ type option\n");
700 return false;
701 }
702
703 if (test->irq_type == req_irq_type)
704 return true;
705
706 pci_endpoint_test_release_irq(test);
707 pci_endpoint_test_free_irq_vectors(test);
708
709 if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
710 goto err;
711
712 if (!pci_endpoint_test_request_irq(test))
713 goto err;
714
715 return true;
716
717err:
718 pci_endpoint_test_free_irq_vectors(test);
719 return false;
720}
721
722static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
723 unsigned long arg)
724{
725 int ret = -EINVAL;
726 enum pci_barno bar;
727 struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
728 struct pci_dev *pdev = test->pdev;
729
730 mutex_lock(&test->mutex);
731 switch (cmd) {
732 case PCITEST_BAR:
733 bar = arg;
734 if (bar > BAR_5)
735 goto ret;
736 if (is_am654_pci_dev(pdev) && bar == BAR_0)
737 goto ret;
738 ret = pci_endpoint_test_bar(test, bar);
739 break;
740 case PCITEST_LEGACY_IRQ:
741 ret = pci_endpoint_test_legacy_irq(test);
742 break;
743 case PCITEST_MSI:
744 case PCITEST_MSIX:
745 ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
746 break;
747 case PCITEST_WRITE:
748 ret = pci_endpoint_test_write(test, arg);
749 break;
750 case PCITEST_READ:
751 ret = pci_endpoint_test_read(test, arg);
752 break;
753 case PCITEST_COPY:
754 ret = pci_endpoint_test_copy(test, arg);
755 break;
756 case PCITEST_SET_IRQTYPE:
757 ret = pci_endpoint_test_set_irq(test, arg);
758 break;
759 case PCITEST_GET_IRQTYPE:
760 ret = irq_type;
761 break;
762 case PCITEST_CLEAR_IRQ:
763 ret = pci_endpoint_test_clear_irq(test);
764 break;
765 }
766
767ret:
768 mutex_unlock(&test->mutex);
769 return ret;
770}
771
772static const struct file_operations pci_endpoint_test_fops = {
773 .owner = THIS_MODULE,
774 .unlocked_ioctl = pci_endpoint_test_ioctl,
775};
776
777static int pci_endpoint_test_probe(struct pci_dev *pdev,
778 const struct pci_device_id *ent)
779{
780 int err;
781 int id;
782 char name[24];
783 enum pci_barno bar;
784 void __iomem *base;
785 struct device *dev = &pdev->dev;
786 struct pci_endpoint_test *test;
787 struct pci_endpoint_test_data *data;
788 enum pci_barno test_reg_bar = BAR_0;
789 struct miscdevice *misc_device;
790
791 if (pci_is_bridge(pdev))
792 return -ENODEV;
793
794 test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
795 if (!test)
796 return -ENOMEM;
797
798 test->test_reg_bar = 0;
799 test->alignment = 0;
800 test->pdev = pdev;
801 test->irq_type = IRQ_TYPE_UNDEFINED;
802
803 if (no_msi)
804 irq_type = IRQ_TYPE_LEGACY;
805
806 data = (struct pci_endpoint_test_data *)ent->driver_data;
807 if (data) {
808 test_reg_bar = data->test_reg_bar;
809 test->test_reg_bar = test_reg_bar;
810 test->alignment = data->alignment;
811 irq_type = data->irq_type;
812 }
813
814 init_completion(&test->irq_raised);
815 mutex_init(&test->mutex);
816
817 if ((dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)) != 0) &&
818 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
819 dev_err(dev, "Cannot set DMA mask\n");
820 return -EINVAL;
821 }
822
823 err = pci_enable_device(pdev);
824 if (err) {
825 dev_err(dev, "Cannot enable PCI device\n");
826 return err;
827 }
828
829 err = pci_request_regions(pdev, DRV_MODULE_NAME);
830 if (err) {
831 dev_err(dev, "Cannot obtain PCI resources\n");
832 goto err_disable_pdev;
833 }
834
835 pci_set_master(pdev);
836
837 if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type)) {
838 err = -EINVAL;
839 goto err_disable_irq;
840 }
841
842 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
843 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
844 base = pci_ioremap_bar(pdev, bar);
845 if (!base) {
846 dev_err(dev, "Failed to read BAR%d\n", bar);
847 WARN_ON(bar == test_reg_bar);
848 }
849 test->bar[bar] = base;
850 }
851 }
852
853 test->base = test->bar[test_reg_bar];
854 if (!test->base) {
855 err = -ENOMEM;
856 dev_err(dev, "Cannot perform PCI test without BAR%d\n",
857 test_reg_bar);
858 goto err_iounmap;
859 }
860
861 pci_set_drvdata(pdev, test);
862
863 id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
864 if (id < 0) {
865 err = id;
866 dev_err(dev, "Unable to get id\n");
867 goto err_iounmap;
868 }
869
870 snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
871 test->name = kstrdup(name, GFP_KERNEL);
872 if (!test->name) {
873 err = -ENOMEM;
874 goto err_ida_remove;
875 }
876
877 if (!pci_endpoint_test_request_irq(test)) {
878 err = -EINVAL;
879 goto err_kfree_test_name;
880 }
881
882 misc_device = &test->miscdev;
883 misc_device->minor = MISC_DYNAMIC_MINOR;
884 misc_device->name = kstrdup(name, GFP_KERNEL);
885 if (!misc_device->name) {
886 err = -ENOMEM;
887 goto err_release_irq;
888 }
889 misc_device->parent = &pdev->dev;
890 misc_device->fops = &pci_endpoint_test_fops;
891
892 err = misc_register(misc_device);
893 if (err) {
894 dev_err(dev, "Failed to register device\n");
895 goto err_kfree_name;
896 }
897
898 return 0;
899
900err_kfree_name:
901 kfree(misc_device->name);
902
903err_release_irq:
904 pci_endpoint_test_release_irq(test);
905
906err_kfree_test_name:
907 kfree(test->name);
908
909err_ida_remove:
910 ida_simple_remove(&pci_endpoint_test_ida, id);
911
912err_iounmap:
913 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
914 if (test->bar[bar])
915 pci_iounmap(pdev, test->bar[bar]);
916 }
917
918err_disable_irq:
919 pci_endpoint_test_free_irq_vectors(test);
920 pci_release_regions(pdev);
921
922err_disable_pdev:
923 pci_disable_device(pdev);
924
925 return err;
926}
927
928static void pci_endpoint_test_remove(struct pci_dev *pdev)
929{
930 int id;
931 enum pci_barno bar;
932 struct pci_endpoint_test *test = pci_get_drvdata(pdev);
933 struct miscdevice *misc_device = &test->miscdev;
934
935 if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
936 return;
937 if (id < 0)
938 return;
939
940 misc_deregister(&test->miscdev);
941 kfree(misc_device->name);
942 kfree(test->name);
943 ida_simple_remove(&pci_endpoint_test_ida, id);
944 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
945 if (test->bar[bar])
946 pci_iounmap(pdev, test->bar[bar]);
947 }
948
949 pci_endpoint_test_release_irq(test);
950 pci_endpoint_test_free_irq_vectors(test);
951
952 pci_release_regions(pdev);
953 pci_disable_device(pdev);
954}
955
956static const struct pci_endpoint_test_data default_data = {
957 .test_reg_bar = BAR_0,
958 .alignment = SZ_4K,
959 .irq_type = IRQ_TYPE_MSI,
960};
961
962static const struct pci_endpoint_test_data am654_data = {
963 .test_reg_bar = BAR_2,
964 .alignment = SZ_64K,
965 .irq_type = IRQ_TYPE_MSI,
966};
967
968static const struct pci_endpoint_test_data j721e_data = {
969 .alignment = 256,
970 .irq_type = IRQ_TYPE_MSI,
971};
972
973static const struct pci_device_id pci_endpoint_test_tbl[] = {
974 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),
975 .driver_data = (kernel_ulong_t)&default_data,
976 },
977 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x),
978 .driver_data = (kernel_ulong_t)&default_data,
979 },
980 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0),
981 .driver_data = (kernel_ulong_t)&default_data,
982 },
983 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LS1088A),
984 .driver_data = (kernel_ulong_t)&default_data,
985 },
986 { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
987 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
988 .driver_data = (kernel_ulong_t)&am654_data
989 },
990 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
991 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
992 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
993 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),},
994 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
995 .driver_data = (kernel_ulong_t)&j721e_data,
996 },
997 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J7200),
998 .driver_data = (kernel_ulong_t)&j721e_data,
999 },
1000 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM64),
1001 .driver_data = (kernel_ulong_t)&j721e_data,
1002 },
1003 { }
1004};
1005MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
1006
1007static struct pci_driver pci_endpoint_test_driver = {
1008 .name = DRV_MODULE_NAME,
1009 .id_table = pci_endpoint_test_tbl,
1010 .probe = pci_endpoint_test_probe,
1011 .remove = pci_endpoint_test_remove,
1012 .sriov_configure = pci_sriov_configure_simple,
1013};
1014module_pci_driver(pci_endpoint_test_driver);
1015
1016MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
1017MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
1018MODULE_LICENSE("GPL v2");