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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Red Hat
4 *
5 * based in parts on udlfb.c:
6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it>
7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
9
10 */
11
12#include <linux/dma-buf.h>
13
14#include <drm/drm_atomic_helper.h>
15#include <drm/drm_crtc_helper.h>
16#include <drm/drm_damage_helper.h>
17#include <drm/drm_fourcc.h>
18#include <drm/drm_gem_framebuffer_helper.h>
19#include <drm/drm_gem_shmem_helper.h>
20#include <drm/drm_modeset_helper_vtables.h>
21#include <drm/drm_vblank.h>
22
23#include "udl_drv.h"
24
25#define UDL_COLOR_DEPTH_16BPP 0
26
27/*
28 * All DisplayLink bulk operations start with 0xAF, followed by specific code
29 * All operations are written to buffers which then later get sent to device
30 */
31static char *udl_set_register(char *buf, u8 reg, u8 val)
32{
33 *buf++ = 0xAF;
34 *buf++ = 0x20;
35 *buf++ = reg;
36 *buf++ = val;
37 return buf;
38}
39
40static char *udl_vidreg_lock(char *buf)
41{
42 return udl_set_register(buf, 0xFF, 0x00);
43}
44
45static char *udl_vidreg_unlock(char *buf)
46{
47 return udl_set_register(buf, 0xFF, 0xFF);
48}
49
50static char *udl_set_blank_mode(char *buf, u8 mode)
51{
52 return udl_set_register(buf, UDL_REG_BLANK_MODE, mode);
53}
54
55static char *udl_set_color_depth(char *buf, u8 selection)
56{
57 return udl_set_register(buf, 0x00, selection);
58}
59
60static char *udl_set_base16bpp(char *wrptr, u32 base)
61{
62 /* the base pointer is 16 bits wide, 0x20 is hi byte. */
63 wrptr = udl_set_register(wrptr, 0x20, base >> 16);
64 wrptr = udl_set_register(wrptr, 0x21, base >> 8);
65 return udl_set_register(wrptr, 0x22, base);
66}
67
68/*
69 * DisplayLink HW has separate 16bpp and 8bpp framebuffers.
70 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
71 */
72static char *udl_set_base8bpp(char *wrptr, u32 base)
73{
74 wrptr = udl_set_register(wrptr, 0x26, base >> 16);
75 wrptr = udl_set_register(wrptr, 0x27, base >> 8);
76 return udl_set_register(wrptr, 0x28, base);
77}
78
79static char *udl_set_register_16(char *wrptr, u8 reg, u16 value)
80{
81 wrptr = udl_set_register(wrptr, reg, value >> 8);
82 return udl_set_register(wrptr, reg+1, value);
83}
84
85/*
86 * This is kind of weird because the controller takes some
87 * register values in a different byte order than other registers.
88 */
89static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value)
90{
91 wrptr = udl_set_register(wrptr, reg, value);
92 return udl_set_register(wrptr, reg+1, value >> 8);
93}
94
95/*
96 * LFSR is linear feedback shift register. The reason we have this is
97 * because the display controller needs to minimize the clock depth of
98 * various counters used in the display path. So this code reverses the
99 * provided value into the lfsr16 value by counting backwards to get
100 * the value that needs to be set in the hardware comparator to get the
101 * same actual count. This makes sense once you read above a couple of
102 * times and think about it from a hardware perspective.
103 */
104static u16 udl_lfsr16(u16 actual_count)
105{
106 u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */
107
108 while (actual_count--) {
109 lv = ((lv << 1) |
110 (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1))
111 & 0xFFFF;
112 }
113
114 return (u16) lv;
115}
116
117/*
118 * This does LFSR conversion on the value that is to be written.
119 * See LFSR explanation above for more detail.
120 */
121static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value)
122{
123 return udl_set_register_16(wrptr, reg, udl_lfsr16(value));
124}
125
126/*
127 * This takes a standard fbdev screeninfo struct and all of its monitor mode
128 * details and converts them into the DisplayLink equivalent register commands.
129 ERR(vreg(dev, 0x00, (color_depth == 16) ? 0 : 1));
130 ERR(vreg_lfsr16(dev, 0x01, xDisplayStart));
131 ERR(vreg_lfsr16(dev, 0x03, xDisplayEnd));
132 ERR(vreg_lfsr16(dev, 0x05, yDisplayStart));
133 ERR(vreg_lfsr16(dev, 0x07, yDisplayEnd));
134 ERR(vreg_lfsr16(dev, 0x09, xEndCount));
135 ERR(vreg_lfsr16(dev, 0x0B, hSyncStart));
136 ERR(vreg_lfsr16(dev, 0x0D, hSyncEnd));
137 ERR(vreg_big_endian(dev, 0x0F, hPixels));
138 ERR(vreg_lfsr16(dev, 0x11, yEndCount));
139 ERR(vreg_lfsr16(dev, 0x13, vSyncStart));
140 ERR(vreg_lfsr16(dev, 0x15, vSyncEnd));
141 ERR(vreg_big_endian(dev, 0x17, vPixels));
142 ERR(vreg_little_endian(dev, 0x1B, pixelClock5KHz));
143
144 ERR(vreg(dev, 0x1F, 0));
145
146 ERR(vbuf(dev, WRITE_VIDREG_UNLOCK, DSIZEOF(WRITE_VIDREG_UNLOCK)));
147 */
148static char *udl_set_vid_cmds(char *wrptr, struct drm_display_mode *mode)
149{
150 u16 xds, yds;
151 u16 xde, yde;
152 u16 yec;
153
154 /* x display start */
155 xds = mode->crtc_htotal - mode->crtc_hsync_start;
156 wrptr = udl_set_register_lfsr16(wrptr, 0x01, xds);
157 /* x display end */
158 xde = xds + mode->crtc_hdisplay;
159 wrptr = udl_set_register_lfsr16(wrptr, 0x03, xde);
160
161 /* y display start */
162 yds = mode->crtc_vtotal - mode->crtc_vsync_start;
163 wrptr = udl_set_register_lfsr16(wrptr, 0x05, yds);
164 /* y display end */
165 yde = yds + mode->crtc_vdisplay;
166 wrptr = udl_set_register_lfsr16(wrptr, 0x07, yde);
167
168 /* x end count is active + blanking - 1 */
169 wrptr = udl_set_register_lfsr16(wrptr, 0x09,
170 mode->crtc_htotal - 1);
171
172 /* libdlo hardcodes hsync start to 1 */
173 wrptr = udl_set_register_lfsr16(wrptr, 0x0B, 1);
174
175 /* hsync end is width of sync pulse + 1 */
176 wrptr = udl_set_register_lfsr16(wrptr, 0x0D,
177 mode->crtc_hsync_end - mode->crtc_hsync_start + 1);
178
179 /* hpixels is active pixels */
180 wrptr = udl_set_register_16(wrptr, 0x0F, mode->hdisplay);
181
182 /* yendcount is vertical active + vertical blanking */
183 yec = mode->crtc_vtotal;
184 wrptr = udl_set_register_lfsr16(wrptr, 0x11, yec);
185
186 /* libdlo hardcodes vsync start to 0 */
187 wrptr = udl_set_register_lfsr16(wrptr, 0x13, 0);
188
189 /* vsync end is width of vsync pulse */
190 wrptr = udl_set_register_lfsr16(wrptr, 0x15, mode->crtc_vsync_end - mode->crtc_vsync_start);
191
192 /* vpixels is active pixels */
193 wrptr = udl_set_register_16(wrptr, 0x17, mode->crtc_vdisplay);
194
195 wrptr = udl_set_register_16be(wrptr, 0x1B,
196 mode->clock / 5);
197
198 return wrptr;
199}
200
201static char *udl_dummy_render(char *wrptr)
202{
203 *wrptr++ = 0xAF;
204 *wrptr++ = 0x6A; /* copy */
205 *wrptr++ = 0x00; /* from addr */
206 *wrptr++ = 0x00;
207 *wrptr++ = 0x00;
208 *wrptr++ = 0x01; /* one pixel */
209 *wrptr++ = 0x00; /* to address */
210 *wrptr++ = 0x00;
211 *wrptr++ = 0x00;
212 return wrptr;
213}
214
215static int udl_crtc_write_mode_to_hw(struct drm_crtc *crtc)
216{
217 struct drm_device *dev = crtc->dev;
218 struct udl_device *udl = to_udl(dev);
219 struct urb *urb;
220 char *buf;
221 int retval;
222
223 if (udl->mode_buf_len == 0) {
224 DRM_ERROR("No mode set\n");
225 return -EINVAL;
226 }
227
228 urb = udl_get_urb(dev);
229 if (!urb)
230 return -ENOMEM;
231
232 buf = (char *)urb->transfer_buffer;
233
234 memcpy(buf, udl->mode_buf, udl->mode_buf_len);
235 retval = udl_submit_urb(dev, urb, udl->mode_buf_len);
236 DRM_DEBUG("write mode info %d\n", udl->mode_buf_len);
237 return retval;
238}
239
240static long udl_log_cpp(unsigned int cpp)
241{
242 if (WARN_ON(!is_power_of_2(cpp)))
243 return -EINVAL;
244 return __ffs(cpp);
245}
246
247static int udl_aligned_damage_clip(struct drm_rect *clip, int x, int y,
248 int width, int height)
249{
250 int x1, x2;
251
252 if (WARN_ON_ONCE(x < 0) ||
253 WARN_ON_ONCE(y < 0) ||
254 WARN_ON_ONCE(width < 0) ||
255 WARN_ON_ONCE(height < 0))
256 return -EINVAL;
257
258 x1 = ALIGN_DOWN(x, sizeof(unsigned long));
259 x2 = ALIGN(width + (x - x1), sizeof(unsigned long)) + x1;
260
261 clip->x1 = x1;
262 clip->y1 = y;
263 clip->x2 = x2;
264 clip->y2 = y + height;
265
266 return 0;
267}
268
269static int udl_handle_damage(struct drm_framebuffer *fb, int x, int y,
270 int width, int height)
271{
272 struct drm_device *dev = fb->dev;
273 struct dma_buf_attachment *import_attach = fb->obj[0]->import_attach;
274 int i, ret, tmp_ret;
275 char *cmd;
276 struct urb *urb;
277 struct drm_rect clip;
278 int log_bpp;
279 void *vaddr;
280
281 ret = udl_log_cpp(fb->format->cpp[0]);
282 if (ret < 0)
283 return ret;
284 log_bpp = ret;
285
286 ret = udl_aligned_damage_clip(&clip, x, y, width, height);
287 if (ret)
288 return ret;
289 else if ((clip.x2 > fb->width) || (clip.y2 > fb->height))
290 return -EINVAL;
291
292 if (import_attach) {
293 ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
294 DMA_FROM_DEVICE);
295 if (ret)
296 return ret;
297 }
298
299 vaddr = drm_gem_shmem_vmap(fb->obj[0]);
300 if (IS_ERR(vaddr)) {
301 DRM_ERROR("failed to vmap fb\n");
302 goto out_dma_buf_end_cpu_access;
303 }
304
305 urb = udl_get_urb(dev);
306 if (!urb)
307 goto out_drm_gem_shmem_vunmap;
308 cmd = urb->transfer_buffer;
309
310 for (i = clip.y1; i < clip.y2; i++) {
311 const int line_offset = fb->pitches[0] * i;
312 const int byte_offset = line_offset + (clip.x1 << log_bpp);
313 const int dev_byte_offset = (fb->width * i + clip.x1) << log_bpp;
314 const int byte_width = (clip.x2 - clip.x1) << log_bpp;
315 ret = udl_render_hline(dev, log_bpp, &urb, (char *)vaddr,
316 &cmd, byte_offset, dev_byte_offset,
317 byte_width);
318 if (ret)
319 goto out_drm_gem_shmem_vunmap;
320 }
321
322 if (cmd > (char *)urb->transfer_buffer) {
323 /* Send partial buffer remaining before exiting */
324 int len;
325 if (cmd < (char *)urb->transfer_buffer + urb->transfer_buffer_length)
326 *cmd++ = 0xAF;
327 len = cmd - (char *)urb->transfer_buffer;
328 ret = udl_submit_urb(dev, urb, len);
329 } else {
330 udl_urb_completion(urb);
331 }
332
333 ret = 0;
334
335out_drm_gem_shmem_vunmap:
336 drm_gem_shmem_vunmap(fb->obj[0], vaddr);
337out_dma_buf_end_cpu_access:
338 if (import_attach) {
339 tmp_ret = dma_buf_end_cpu_access(import_attach->dmabuf,
340 DMA_FROM_DEVICE);
341 if (tmp_ret && !ret)
342 ret = tmp_ret; /* only update ret if not set yet */
343 }
344
345 return ret;
346}
347
348/*
349 * Simple display pipeline
350 */
351
352static const uint32_t udl_simple_display_pipe_formats[] = {
353 DRM_FORMAT_RGB565,
354 DRM_FORMAT_XRGB8888,
355};
356
357static enum drm_mode_status
358udl_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
359 const struct drm_display_mode *mode)
360{
361 return MODE_OK;
362}
363
364static void
365udl_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe,
366 struct drm_crtc_state *crtc_state,
367 struct drm_plane_state *plane_state)
368{
369 struct drm_crtc *crtc = &pipe->crtc;
370 struct drm_device *dev = crtc->dev;
371 struct drm_framebuffer *fb = plane_state->fb;
372 struct udl_device *udl = to_udl(dev);
373 struct drm_display_mode *mode = &crtc_state->mode;
374 char *buf;
375 char *wrptr;
376 int color_depth = UDL_COLOR_DEPTH_16BPP;
377
378 buf = (char *)udl->mode_buf;
379
380 /* This first section has to do with setting the base address on the
381 * controller associated with the display. There are 2 base
382 * pointers, currently, we only use the 16 bpp segment.
383 */
384 wrptr = udl_vidreg_lock(buf);
385 wrptr = udl_set_color_depth(wrptr, color_depth);
386 /* set base for 16bpp segment to 0 */
387 wrptr = udl_set_base16bpp(wrptr, 0);
388 /* set base for 8bpp segment to end of fb */
389 wrptr = udl_set_base8bpp(wrptr, 2 * mode->vdisplay * mode->hdisplay);
390
391 wrptr = udl_set_vid_cmds(wrptr, mode);
392 wrptr = udl_set_blank_mode(wrptr, UDL_BLANK_MODE_ON);
393 wrptr = udl_vidreg_unlock(wrptr);
394
395 wrptr = udl_dummy_render(wrptr);
396
397 udl->mode_buf_len = wrptr - buf;
398
399 udl_handle_damage(fb, 0, 0, fb->width, fb->height);
400
401 if (!crtc_state->mode_changed)
402 return;
403
404 /* enable display */
405 udl_crtc_write_mode_to_hw(crtc);
406}
407
408static void
409udl_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe)
410{
411 struct drm_crtc *crtc = &pipe->crtc;
412 struct drm_device *dev = crtc->dev;
413 struct urb *urb;
414 char *buf;
415
416 urb = udl_get_urb(dev);
417 if (!urb)
418 return;
419
420 buf = (char *)urb->transfer_buffer;
421 buf = udl_vidreg_lock(buf);
422 buf = udl_set_blank_mode(buf, UDL_BLANK_MODE_POWERDOWN);
423 buf = udl_vidreg_unlock(buf);
424 buf = udl_dummy_render(buf);
425
426 udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer);
427}
428
429static void
430udl_simple_display_pipe_update(struct drm_simple_display_pipe *pipe,
431 struct drm_plane_state *old_plane_state)
432{
433 struct drm_plane_state *state = pipe->plane.state;
434 struct drm_framebuffer *fb = state->fb;
435 struct drm_rect rect;
436
437 if (!fb)
438 return;
439
440 if (drm_atomic_helper_damage_merged(old_plane_state, state, &rect))
441 udl_handle_damage(fb, rect.x1, rect.y1, rect.x2 - rect.x1,
442 rect.y2 - rect.y1);
443}
444
445static const
446struct drm_simple_display_pipe_funcs udl_simple_display_pipe_funcs = {
447 .mode_valid = udl_simple_display_pipe_mode_valid,
448 .enable = udl_simple_display_pipe_enable,
449 .disable = udl_simple_display_pipe_disable,
450 .update = udl_simple_display_pipe_update,
451 .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
452};
453
454/*
455 * Modesetting
456 */
457
458static const struct drm_mode_config_funcs udl_mode_funcs = {
459 .fb_create = drm_gem_fb_create_with_dirty,
460 .atomic_check = drm_atomic_helper_check,
461 .atomic_commit = drm_atomic_helper_commit,
462};
463
464int udl_modeset_init(struct drm_device *dev)
465{
466 size_t format_count = ARRAY_SIZE(udl_simple_display_pipe_formats);
467 struct udl_device *udl = to_udl(dev);
468 struct drm_connector *connector;
469 int ret;
470
471 ret = drmm_mode_config_init(dev);
472 if (ret)
473 return ret;
474
475 dev->mode_config.min_width = 640;
476 dev->mode_config.min_height = 480;
477
478 dev->mode_config.max_width = 2048;
479 dev->mode_config.max_height = 2048;
480
481 dev->mode_config.prefer_shadow = 0;
482 dev->mode_config.preferred_depth = 16;
483
484 dev->mode_config.funcs = &udl_mode_funcs;
485
486 connector = udl_connector_init(dev);
487 if (IS_ERR(connector))
488 return PTR_ERR(connector);
489
490 format_count = ARRAY_SIZE(udl_simple_display_pipe_formats);
491
492 ret = drm_simple_display_pipe_init(dev, &udl->display_pipe,
493 &udl_simple_display_pipe_funcs,
494 udl_simple_display_pipe_formats,
495 format_count, NULL, connector);
496 if (ret)
497 return ret;
498
499 drm_mode_config_reset(dev);
500
501 return 0;
502}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Red Hat
4 *
5 * based in parts on udlfb.c:
6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it>
7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
9 */
10
11#include <linux/bitfield.h>
12
13#include <drm/drm_atomic.h>
14#include <drm/drm_atomic_helper.h>
15#include <drm/drm_crtc_helper.h>
16#include <drm/drm_damage_helper.h>
17#include <drm/drm_drv.h>
18#include <drm/drm_edid.h>
19#include <drm/drm_fourcc.h>
20#include <drm/drm_gem_atomic_helper.h>
21#include <drm/drm_gem_framebuffer_helper.h>
22#include <drm/drm_gem_shmem_helper.h>
23#include <drm/drm_modeset_helper_vtables.h>
24#include <drm/drm_plane_helper.h>
25#include <drm/drm_probe_helper.h>
26#include <drm/drm_vblank.h>
27
28#include "udl_drv.h"
29#include "udl_proto.h"
30
31/*
32 * All DisplayLink bulk operations start with 0xaf (UDL_MSG_BULK), followed by
33 * a specific command code. All operations are written to a command buffer, which
34 * the driver sends to the device.
35 */
36static char *udl_set_register(char *buf, u8 reg, u8 val)
37{
38 *buf++ = UDL_MSG_BULK;
39 *buf++ = UDL_CMD_WRITEREG;
40 *buf++ = reg;
41 *buf++ = val;
42
43 return buf;
44}
45
46static char *udl_vidreg_lock(char *buf)
47{
48 return udl_set_register(buf, UDL_REG_VIDREG, UDL_VIDREG_LOCK);
49}
50
51static char *udl_vidreg_unlock(char *buf)
52{
53 return udl_set_register(buf, UDL_REG_VIDREG, UDL_VIDREG_UNLOCK);
54}
55
56static char *udl_set_blank_mode(char *buf, u8 mode)
57{
58 return udl_set_register(buf, UDL_REG_BLANKMODE, mode);
59}
60
61static char *udl_set_color_depth(char *buf, u8 selection)
62{
63 return udl_set_register(buf, UDL_REG_COLORDEPTH, selection);
64}
65
66static char *udl_set_base16bpp(char *buf, u32 base)
67{
68 /* the base pointer is 24 bits wide, 0x20 is hi byte. */
69 u8 reg20 = FIELD_GET(UDL_BASE_ADDR2_MASK, base);
70 u8 reg21 = FIELD_GET(UDL_BASE_ADDR1_MASK, base);
71 u8 reg22 = FIELD_GET(UDL_BASE_ADDR0_MASK, base);
72
73 buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR2, reg20);
74 buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR1, reg21);
75 buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR0, reg22);
76
77 return buf;
78}
79
80/*
81 * DisplayLink HW has separate 16bpp and 8bpp framebuffers.
82 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
83 */
84static char *udl_set_base8bpp(char *buf, u32 base)
85{
86 /* the base pointer is 24 bits wide, 0x26 is hi byte. */
87 u8 reg26 = FIELD_GET(UDL_BASE_ADDR2_MASK, base);
88 u8 reg27 = FIELD_GET(UDL_BASE_ADDR1_MASK, base);
89 u8 reg28 = FIELD_GET(UDL_BASE_ADDR0_MASK, base);
90
91 buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR2, reg26);
92 buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR1, reg27);
93 buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR0, reg28);
94
95 return buf;
96}
97
98static char *udl_set_register_16(char *wrptr, u8 reg, u16 value)
99{
100 wrptr = udl_set_register(wrptr, reg, value >> 8);
101 return udl_set_register(wrptr, reg+1, value);
102}
103
104/*
105 * This is kind of weird because the controller takes some
106 * register values in a different byte order than other registers.
107 */
108static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value)
109{
110 wrptr = udl_set_register(wrptr, reg, value);
111 return udl_set_register(wrptr, reg+1, value >> 8);
112}
113
114/*
115 * LFSR is linear feedback shift register. The reason we have this is
116 * because the display controller needs to minimize the clock depth of
117 * various counters used in the display path. So this code reverses the
118 * provided value into the lfsr16 value by counting backwards to get
119 * the value that needs to be set in the hardware comparator to get the
120 * same actual count. This makes sense once you read above a couple of
121 * times and think about it from a hardware perspective.
122 */
123static u16 udl_lfsr16(u16 actual_count)
124{
125 u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */
126
127 while (actual_count--) {
128 lv = ((lv << 1) |
129 (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1))
130 & 0xFFFF;
131 }
132
133 return (u16) lv;
134}
135
136/*
137 * This does LFSR conversion on the value that is to be written.
138 * See LFSR explanation above for more detail.
139 */
140static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value)
141{
142 return udl_set_register_16(wrptr, reg, udl_lfsr16(value));
143}
144
145/*
146 * Takes a DRM display mode and converts it into the DisplayLink
147 * equivalent register commands.
148 */
149static char *udl_set_display_mode(char *buf, struct drm_display_mode *mode)
150{
151 u16 reg01 = mode->crtc_htotal - mode->crtc_hsync_start;
152 u16 reg03 = reg01 + mode->crtc_hdisplay;
153 u16 reg05 = mode->crtc_vtotal - mode->crtc_vsync_start;
154 u16 reg07 = reg05 + mode->crtc_vdisplay;
155 u16 reg09 = mode->crtc_htotal - 1;
156 u16 reg0b = 1; /* libdlo hardcodes hsync start to 1 */
157 u16 reg0d = mode->crtc_hsync_end - mode->crtc_hsync_start + 1;
158 u16 reg0f = mode->hdisplay;
159 u16 reg11 = mode->crtc_vtotal;
160 u16 reg13 = 0; /* libdlo hardcodes vsync start to 0 */
161 u16 reg15 = mode->crtc_vsync_end - mode->crtc_vsync_start;
162 u16 reg17 = mode->crtc_vdisplay;
163 u16 reg1b = mode->clock / 5;
164
165 buf = udl_set_register_lfsr16(buf, UDL_REG_XDISPLAYSTART, reg01);
166 buf = udl_set_register_lfsr16(buf, UDL_REG_XDISPLAYEND, reg03);
167 buf = udl_set_register_lfsr16(buf, UDL_REG_YDISPLAYSTART, reg05);
168 buf = udl_set_register_lfsr16(buf, UDL_REG_YDISPLAYEND, reg07);
169 buf = udl_set_register_lfsr16(buf, UDL_REG_XENDCOUNT, reg09);
170 buf = udl_set_register_lfsr16(buf, UDL_REG_HSYNCSTART, reg0b);
171 buf = udl_set_register_lfsr16(buf, UDL_REG_HSYNCEND, reg0d);
172 buf = udl_set_register_16(buf, UDL_REG_HPIXELS, reg0f);
173 buf = udl_set_register_lfsr16(buf, UDL_REG_YENDCOUNT, reg11);
174 buf = udl_set_register_lfsr16(buf, UDL_REG_VSYNCSTART, reg13);
175 buf = udl_set_register_lfsr16(buf, UDL_REG_VSYNCEND, reg15);
176 buf = udl_set_register_16(buf, UDL_REG_VPIXELS, reg17);
177 buf = udl_set_register_16be(buf, UDL_REG_PIXELCLOCK5KHZ, reg1b);
178
179 return buf;
180}
181
182static char *udl_dummy_render(char *wrptr)
183{
184 *wrptr++ = UDL_MSG_BULK;
185 *wrptr++ = UDL_CMD_WRITECOPY16;
186 *wrptr++ = 0x00; /* from addr */
187 *wrptr++ = 0x00;
188 *wrptr++ = 0x00;
189 *wrptr++ = 0x01; /* one pixel */
190 *wrptr++ = 0x00; /* to address */
191 *wrptr++ = 0x00;
192 *wrptr++ = 0x00;
193 return wrptr;
194}
195
196static long udl_log_cpp(unsigned int cpp)
197{
198 if (WARN_ON(!is_power_of_2(cpp)))
199 return -EINVAL;
200 return __ffs(cpp);
201}
202
203static int udl_handle_damage(struct drm_framebuffer *fb,
204 const struct iosys_map *map,
205 const struct drm_rect *clip)
206{
207 struct drm_device *dev = fb->dev;
208 void *vaddr = map->vaddr; /* TODO: Use mapping abstraction properly */
209 int i, ret;
210 char *cmd;
211 struct urb *urb;
212 int log_bpp;
213
214 ret = udl_log_cpp(fb->format->cpp[0]);
215 if (ret < 0)
216 return ret;
217 log_bpp = ret;
218
219 urb = udl_get_urb(dev);
220 if (!urb)
221 return -ENOMEM;
222 cmd = urb->transfer_buffer;
223
224 for (i = clip->y1; i < clip->y2; i++) {
225 const int line_offset = fb->pitches[0] * i;
226 const int byte_offset = line_offset + (clip->x1 << log_bpp);
227 const int dev_byte_offset = (fb->width * i + clip->x1) << log_bpp;
228 const int byte_width = drm_rect_width(clip) << log_bpp;
229 ret = udl_render_hline(dev, log_bpp, &urb, (char *)vaddr,
230 &cmd, byte_offset, dev_byte_offset,
231 byte_width);
232 if (ret)
233 return ret;
234 }
235
236 if (cmd > (char *)urb->transfer_buffer) {
237 /* Send partial buffer remaining before exiting */
238 int len;
239 if (cmd < (char *)urb->transfer_buffer + urb->transfer_buffer_length)
240 *cmd++ = UDL_MSG_BULK;
241 len = cmd - (char *)urb->transfer_buffer;
242 ret = udl_submit_urb(dev, urb, len);
243 } else {
244 udl_urb_completion(urb);
245 }
246
247 return 0;
248}
249
250/*
251 * Primary plane
252 */
253
254static const uint32_t udl_primary_plane_formats[] = {
255 DRM_FORMAT_RGB565,
256 DRM_FORMAT_XRGB8888,
257};
258
259static const uint64_t udl_primary_plane_fmtmods[] = {
260 DRM_FORMAT_MOD_LINEAR,
261 DRM_FORMAT_MOD_INVALID
262};
263
264static void udl_primary_plane_helper_atomic_update(struct drm_plane *plane,
265 struct drm_atomic_state *state)
266{
267 struct drm_device *dev = plane->dev;
268 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
269 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
270 struct drm_framebuffer *fb = plane_state->fb;
271 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
272 struct drm_atomic_helper_damage_iter iter;
273 struct drm_rect damage;
274 int ret, idx;
275
276 if (!fb)
277 return; /* no framebuffer; plane is disabled */
278
279 ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
280 if (ret)
281 return;
282
283 if (!drm_dev_enter(dev, &idx))
284 goto out_drm_gem_fb_end_cpu_access;
285
286 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
287 drm_atomic_for_each_plane_damage(&iter, &damage) {
288 udl_handle_damage(fb, &shadow_plane_state->data[0], &damage);
289 }
290
291 drm_dev_exit(idx);
292
293out_drm_gem_fb_end_cpu_access:
294 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
295}
296
297static const struct drm_plane_helper_funcs udl_primary_plane_helper_funcs = {
298 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
299 .atomic_check = drm_plane_helper_atomic_check,
300 .atomic_update = udl_primary_plane_helper_atomic_update,
301};
302
303static const struct drm_plane_funcs udl_primary_plane_funcs = {
304 .update_plane = drm_atomic_helper_update_plane,
305 .disable_plane = drm_atomic_helper_disable_plane,
306 .destroy = drm_plane_cleanup,
307 DRM_GEM_SHADOW_PLANE_FUNCS,
308};
309
310/*
311 * CRTC
312 */
313
314static int udl_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)
315{
316 struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
317
318 if (!new_crtc_state->enable)
319 return 0;
320
321 return drm_atomic_helper_check_crtc_primary_plane(new_crtc_state);
322}
323
324static void udl_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state)
325{
326 struct drm_device *dev = crtc->dev;
327 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
328 struct drm_display_mode *mode = &crtc_state->mode;
329 struct urb *urb;
330 char *buf;
331 int idx;
332
333 if (!drm_dev_enter(dev, &idx))
334 return;
335
336 urb = udl_get_urb(dev);
337 if (!urb)
338 goto out;
339
340 buf = (char *)urb->transfer_buffer;
341 buf = udl_vidreg_lock(buf);
342 buf = udl_set_color_depth(buf, UDL_COLORDEPTH_16BPP);
343 /* set base for 16bpp segment to 0 */
344 buf = udl_set_base16bpp(buf, 0);
345 /* set base for 8bpp segment to end of fb */
346 buf = udl_set_base8bpp(buf, 2 * mode->vdisplay * mode->hdisplay);
347 buf = udl_set_display_mode(buf, mode);
348 buf = udl_set_blank_mode(buf, UDL_BLANKMODE_ON);
349 buf = udl_vidreg_unlock(buf);
350 buf = udl_dummy_render(buf);
351
352 udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer);
353
354out:
355 drm_dev_exit(idx);
356}
357
358static void udl_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state)
359{
360 struct drm_device *dev = crtc->dev;
361 struct urb *urb;
362 char *buf;
363 int idx;
364
365 if (!drm_dev_enter(dev, &idx))
366 return;
367
368 urb = udl_get_urb(dev);
369 if (!urb)
370 goto out;
371
372 buf = (char *)urb->transfer_buffer;
373 buf = udl_vidreg_lock(buf);
374 buf = udl_set_blank_mode(buf, UDL_BLANKMODE_POWERDOWN);
375 buf = udl_vidreg_unlock(buf);
376 buf = udl_dummy_render(buf);
377
378 udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer);
379
380out:
381 drm_dev_exit(idx);
382}
383
384static const struct drm_crtc_helper_funcs udl_crtc_helper_funcs = {
385 .atomic_check = udl_crtc_helper_atomic_check,
386 .atomic_enable = udl_crtc_helper_atomic_enable,
387 .atomic_disable = udl_crtc_helper_atomic_disable,
388};
389
390static const struct drm_crtc_funcs udl_crtc_funcs = {
391 .reset = drm_atomic_helper_crtc_reset,
392 .destroy = drm_crtc_cleanup,
393 .set_config = drm_atomic_helper_set_config,
394 .page_flip = drm_atomic_helper_page_flip,
395 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
396 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
397};
398
399/*
400 * Encoder
401 */
402
403static const struct drm_encoder_funcs udl_encoder_funcs = {
404 .destroy = drm_encoder_cleanup,
405};
406
407/*
408 * Connector
409 */
410
411static int udl_connector_helper_get_modes(struct drm_connector *connector)
412{
413 struct udl_connector *udl_connector = to_udl_connector(connector);
414
415 drm_connector_update_edid_property(connector, udl_connector->edid);
416 if (udl_connector->edid)
417 return drm_add_edid_modes(connector, udl_connector->edid);
418
419 return 0;
420}
421
422static const struct drm_connector_helper_funcs udl_connector_helper_funcs = {
423 .get_modes = udl_connector_helper_get_modes,
424};
425
426static int udl_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len)
427{
428 struct udl_device *udl = data;
429 struct drm_device *dev = &udl->drm;
430 struct usb_device *udev = udl_to_usb_device(udl);
431 u8 *read_buff;
432 int ret;
433 size_t i;
434
435 read_buff = kmalloc(2, GFP_KERNEL);
436 if (!read_buff)
437 return -ENOMEM;
438
439 for (i = 0; i < len; i++) {
440 int bval = (i + block * EDID_LENGTH) << 8;
441
442 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
443 0x02, (0x80 | (0x02 << 5)), bval,
444 0xA1, read_buff, 2, USB_CTRL_GET_TIMEOUT);
445 if (ret < 0) {
446 drm_err(dev, "Read EDID byte %zu failed err %x\n", i, ret);
447 goto err_kfree;
448 } else if (ret < 1) {
449 ret = -EIO;
450 drm_err(dev, "Read EDID byte %zu failed\n", i);
451 goto err_kfree;
452 }
453
454 buf[i] = read_buff[1];
455 }
456
457 kfree(read_buff);
458
459 return 0;
460
461err_kfree:
462 kfree(read_buff);
463 return ret;
464}
465
466static enum drm_connector_status udl_connector_detect(struct drm_connector *connector, bool force)
467{
468 struct drm_device *dev = connector->dev;
469 struct udl_device *udl = to_udl(dev);
470 struct udl_connector *udl_connector = to_udl_connector(connector);
471 enum drm_connector_status status = connector_status_disconnected;
472 int idx;
473
474 /* cleanup previous EDID */
475 kfree(udl_connector->edid);
476 udl_connector->edid = NULL;
477
478 if (!drm_dev_enter(dev, &idx))
479 return connector_status_disconnected;
480
481 udl_connector->edid = drm_do_get_edid(connector, udl_get_edid_block, udl);
482 if (udl_connector->edid)
483 status = connector_status_connected;
484
485 drm_dev_exit(idx);
486
487 return status;
488}
489
490static void udl_connector_destroy(struct drm_connector *connector)
491{
492 struct udl_connector *udl_connector = to_udl_connector(connector);
493
494 drm_connector_cleanup(connector);
495 kfree(udl_connector->edid);
496 kfree(udl_connector);
497}
498
499static const struct drm_connector_funcs udl_connector_funcs = {
500 .reset = drm_atomic_helper_connector_reset,
501 .detect = udl_connector_detect,
502 .fill_modes = drm_helper_probe_single_connector_modes,
503 .destroy = udl_connector_destroy,
504 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
505 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
506};
507
508struct drm_connector *udl_connector_init(struct drm_device *dev)
509{
510 struct udl_connector *udl_connector;
511 struct drm_connector *connector;
512 int ret;
513
514 udl_connector = kzalloc(sizeof(*udl_connector), GFP_KERNEL);
515 if (!udl_connector)
516 return ERR_PTR(-ENOMEM);
517
518 connector = &udl_connector->connector;
519 ret = drm_connector_init(dev, connector, &udl_connector_funcs, DRM_MODE_CONNECTOR_VGA);
520 if (ret)
521 goto err_kfree;
522
523 drm_connector_helper_add(connector, &udl_connector_helper_funcs);
524
525 connector->polled = DRM_CONNECTOR_POLL_HPD |
526 DRM_CONNECTOR_POLL_CONNECT |
527 DRM_CONNECTOR_POLL_DISCONNECT;
528
529 return connector;
530
531err_kfree:
532 kfree(udl_connector);
533 return ERR_PTR(ret);
534}
535
536/*
537 * Modesetting
538 */
539
540static enum drm_mode_status udl_mode_config_mode_valid(struct drm_device *dev,
541 const struct drm_display_mode *mode)
542{
543 struct udl_device *udl = to_udl(dev);
544
545 if (udl->sku_pixel_limit) {
546 if (mode->vdisplay * mode->hdisplay > udl->sku_pixel_limit)
547 return MODE_MEM;
548 }
549
550 return MODE_OK;
551}
552
553static const struct drm_mode_config_funcs udl_mode_config_funcs = {
554 .fb_create = drm_gem_fb_create_with_dirty,
555 .mode_valid = udl_mode_config_mode_valid,
556 .atomic_check = drm_atomic_helper_check,
557 .atomic_commit = drm_atomic_helper_commit,
558};
559
560int udl_modeset_init(struct drm_device *dev)
561{
562 struct udl_device *udl = to_udl(dev);
563 struct drm_plane *primary_plane;
564 struct drm_crtc *crtc;
565 struct drm_encoder *encoder;
566 struct drm_connector *connector;
567 int ret;
568
569 ret = drmm_mode_config_init(dev);
570 if (ret)
571 return ret;
572
573 dev->mode_config.min_width = 640;
574 dev->mode_config.min_height = 480;
575 dev->mode_config.max_width = 2048;
576 dev->mode_config.max_height = 2048;
577 dev->mode_config.preferred_depth = 16;
578 dev->mode_config.funcs = &udl_mode_config_funcs;
579
580 primary_plane = &udl->primary_plane;
581 ret = drm_universal_plane_init(dev, primary_plane, 0,
582 &udl_primary_plane_funcs,
583 udl_primary_plane_formats,
584 ARRAY_SIZE(udl_primary_plane_formats),
585 udl_primary_plane_fmtmods,
586 DRM_PLANE_TYPE_PRIMARY, NULL);
587 if (ret)
588 return ret;
589 drm_plane_helper_add(primary_plane, &udl_primary_plane_helper_funcs);
590 drm_plane_enable_fb_damage_clips(primary_plane);
591
592 crtc = &udl->crtc;
593 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL,
594 &udl_crtc_funcs, NULL);
595 if (ret)
596 return ret;
597 drm_crtc_helper_add(crtc, &udl_crtc_helper_funcs);
598
599 encoder = &udl->encoder;
600 ret = drm_encoder_init(dev, encoder, &udl_encoder_funcs, DRM_MODE_ENCODER_DAC, NULL);
601 if (ret)
602 return ret;
603 encoder->possible_crtcs = drm_crtc_mask(crtc);
604
605 connector = udl_connector_init(dev);
606 if (IS_ERR(connector))
607 return PTR_ERR(connector);
608 ret = drm_connector_attach_encoder(connector, encoder);
609 if (ret)
610 return ret;
611
612 drm_mode_config_reset(dev);
613
614 return 0;
615}