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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef AST_DRAM_TABLES_H
3#define AST_DRAM_TABLES_H
4
5/* DRAM timing tables */
6struct ast_dramstruct {
7 u16 index;
8 u32 data;
9};
10
11static const struct ast_dramstruct ast2000_dram_table_data[] = {
12 { 0x0108, 0x00000000 },
13 { 0x0120, 0x00004a21 },
14 { 0xFF00, 0x00000043 },
15 { 0x0000, 0xFFFFFFFF },
16 { 0x0004, 0x00000089 },
17 { 0x0008, 0x22331353 },
18 { 0x000C, 0x0d07000b },
19 { 0x0010, 0x11113333 },
20 { 0x0020, 0x00110350 },
21 { 0x0028, 0x1e0828f0 },
22 { 0x0024, 0x00000001 },
23 { 0x001C, 0x00000000 },
24 { 0x0014, 0x00000003 },
25 { 0xFF00, 0x00000043 },
26 { 0x0018, 0x00000131 },
27 { 0x0014, 0x00000001 },
28 { 0xFF00, 0x00000043 },
29 { 0x0018, 0x00000031 },
30 { 0x0014, 0x00000001 },
31 { 0xFF00, 0x00000043 },
32 { 0x0028, 0x1e0828f1 },
33 { 0x0024, 0x00000003 },
34 { 0x002C, 0x1f0f28fb },
35 { 0x0030, 0xFFFFFE01 },
36 { 0xFFFF, 0xFFFFFFFF }
37};
38
39static const struct ast_dramstruct ast1100_dram_table_data[] = {
40 { 0x2000, 0x1688a8a8 },
41 { 0x2020, 0x000041f0 },
42 { 0xFF00, 0x00000043 },
43 { 0x0000, 0xfc600309 },
44 { 0x006C, 0x00909090 },
45 { 0x0064, 0x00050000 },
46 { 0x0004, 0x00000585 },
47 { 0x0008, 0x0011030f },
48 { 0x0010, 0x22201724 },
49 { 0x0018, 0x1e29011a },
50 { 0x0020, 0x00c82222 },
51 { 0x0014, 0x01001523 },
52 { 0x001C, 0x1024010d },
53 { 0x0024, 0x00cb2522 },
54 { 0x0038, 0xffffff82 },
55 { 0x003C, 0x00000000 },
56 { 0x0040, 0x00000000 },
57 { 0x0044, 0x00000000 },
58 { 0x0048, 0x00000000 },
59 { 0x004C, 0x00000000 },
60 { 0x0050, 0x00000000 },
61 { 0x0054, 0x00000000 },
62 { 0x0058, 0x00000000 },
63 { 0x005C, 0x00000000 },
64 { 0x0060, 0x032aa02a },
65 { 0x0064, 0x002d3000 },
66 { 0x0068, 0x00000000 },
67 { 0x0070, 0x00000000 },
68 { 0x0074, 0x00000000 },
69 { 0x0078, 0x00000000 },
70 { 0x007C, 0x00000000 },
71 { 0x0034, 0x00000001 },
72 { 0xFF00, 0x00000043 },
73 { 0x002C, 0x00000732 },
74 { 0x0030, 0x00000040 },
75 { 0x0028, 0x00000005 },
76 { 0x0028, 0x00000007 },
77 { 0x0028, 0x00000003 },
78 { 0x0028, 0x00000001 },
79 { 0x000C, 0x00005a08 },
80 { 0x002C, 0x00000632 },
81 { 0x0028, 0x00000001 },
82 { 0x0030, 0x000003c0 },
83 { 0x0028, 0x00000003 },
84 { 0x0030, 0x00000040 },
85 { 0x0028, 0x00000003 },
86 { 0x000C, 0x00005a21 },
87 { 0x0034, 0x00007c03 },
88 { 0x0120, 0x00004c41 },
89 { 0xffff, 0xffffffff },
90};
91
92static const struct ast_dramstruct ast2100_dram_table_data[] = {
93 { 0x2000, 0x1688a8a8 },
94 { 0x2020, 0x00004120 },
95 { 0xFF00, 0x00000043 },
96 { 0x0000, 0xfc600309 },
97 { 0x006C, 0x00909090 },
98 { 0x0064, 0x00070000 },
99 { 0x0004, 0x00000489 },
100 { 0x0008, 0x0011030f },
101 { 0x0010, 0x32302926 },
102 { 0x0018, 0x274c0122 },
103 { 0x0020, 0x00ce2222 },
104 { 0x0014, 0x01001523 },
105 { 0x001C, 0x1024010d },
106 { 0x0024, 0x00cb2522 },
107 { 0x0038, 0xffffff82 },
108 { 0x003C, 0x00000000 },
109 { 0x0040, 0x00000000 },
110 { 0x0044, 0x00000000 },
111 { 0x0048, 0x00000000 },
112 { 0x004C, 0x00000000 },
113 { 0x0050, 0x00000000 },
114 { 0x0054, 0x00000000 },
115 { 0x0058, 0x00000000 },
116 { 0x005C, 0x00000000 },
117 { 0x0060, 0x0f2aa02a },
118 { 0x0064, 0x003f3005 },
119 { 0x0068, 0x02020202 },
120 { 0x0070, 0x00000000 },
121 { 0x0074, 0x00000000 },
122 { 0x0078, 0x00000000 },
123 { 0x007C, 0x00000000 },
124 { 0x0034, 0x00000001 },
125 { 0xFF00, 0x00000043 },
126 { 0x002C, 0x00000942 },
127 { 0x0030, 0x00000040 },
128 { 0x0028, 0x00000005 },
129 { 0x0028, 0x00000007 },
130 { 0x0028, 0x00000003 },
131 { 0x0028, 0x00000001 },
132 { 0x000C, 0x00005a08 },
133 { 0x002C, 0x00000842 },
134 { 0x0028, 0x00000001 },
135 { 0x0030, 0x000003c0 },
136 { 0x0028, 0x00000003 },
137 { 0x0030, 0x00000040 },
138 { 0x0028, 0x00000003 },
139 { 0x000C, 0x00005a21 },
140 { 0x0034, 0x00007c03 },
141 { 0x0120, 0x00005061 },
142 { 0xffff, 0xffffffff },
143};
144
145/*
146 * AST2500 DRAM settings modules
147 */
148#define REGTBL_NUM 17
149#define REGIDX_010 0
150#define REGIDX_014 1
151#define REGIDX_018 2
152#define REGIDX_020 3
153#define REGIDX_024 4
154#define REGIDX_02C 5
155#define REGIDX_030 6
156#define REGIDX_214 7
157#define REGIDX_2E0 8
158#define REGIDX_2E4 9
159#define REGIDX_2E8 10
160#define REGIDX_2EC 11
161#define REGIDX_2F0 12
162#define REGIDX_2F4 13
163#define REGIDX_2F8 14
164#define REGIDX_RFC 15
165#define REGIDX_PLL 16
166
167static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = {
168 0x64604D38, /* 0x010 */
169 0x29690599, /* 0x014 */
170 0x00000300, /* 0x018 */
171 0x00000000, /* 0x020 */
172 0x00000000, /* 0x024 */
173 0x02181E70, /* 0x02C */
174 0x00000040, /* 0x030 */
175 0x00000024, /* 0x214 */
176 0x02001300, /* 0x2E0 */
177 0x0E0000A0, /* 0x2E4 */
178 0x000E001B, /* 0x2E8 */
179 0x35B8C105, /* 0x2EC */
180 0x08090408, /* 0x2F0 */
181 0x9B000800, /* 0x2F4 */
182 0x0E400A00, /* 0x2F8 */
183 0x9971452F, /* tRFC */
184 0x000071C1 /* PLL */
185};
186
187static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = {
188 0x63604E37, /* 0x010 */
189 0xE97AFA99, /* 0x014 */
190 0x00019000, /* 0x018 */
191 0x08000000, /* 0x020 */
192 0x00000400, /* 0x024 */
193 0x00000410, /* 0x02C */
194 0x00000101, /* 0x030 */
195 0x00000024, /* 0x214 */
196 0x03002900, /* 0x2E0 */
197 0x0E0000A0, /* 0x2E4 */
198 0x000E001C, /* 0x2E8 */
199 0x35B8C106, /* 0x2EC */
200 0x08080607, /* 0x2F0 */
201 0x9B000900, /* 0x2F4 */
202 0x0E400A00, /* 0x2F8 */
203 0x99714545, /* tRFC */
204 0x000071C1 /* PLL */
205};
206
207#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef AST_DRAM_TABLES_H
3#define AST_DRAM_TABLES_H
4
5/* DRAM timing tables */
6struct ast_dramstruct {
7 u16 index;
8 u32 data;
9};
10
11static const struct ast_dramstruct ast2000_dram_table_data[] = {
12 { 0x0108, 0x00000000 },
13 { 0x0120, 0x00004a21 },
14 { 0xFF00, 0x00000043 },
15 { 0x0000, 0xFFFFFFFF },
16 { 0x0004, 0x00000089 },
17 { 0x0008, 0x22331353 },
18 { 0x000C, 0x0d07000b },
19 { 0x0010, 0x11113333 },
20 { 0x0020, 0x00110350 },
21 { 0x0028, 0x1e0828f0 },
22 { 0x0024, 0x00000001 },
23 { 0x001C, 0x00000000 },
24 { 0x0014, 0x00000003 },
25 { 0xFF00, 0x00000043 },
26 { 0x0018, 0x00000131 },
27 { 0x0014, 0x00000001 },
28 { 0xFF00, 0x00000043 },
29 { 0x0018, 0x00000031 },
30 { 0x0014, 0x00000001 },
31 { 0xFF00, 0x00000043 },
32 { 0x0028, 0x1e0828f1 },
33 { 0x0024, 0x00000003 },
34 { 0x002C, 0x1f0f28fb },
35 { 0x0030, 0xFFFFFE01 },
36 { 0xFFFF, 0xFFFFFFFF }
37};
38
39static const struct ast_dramstruct ast1100_dram_table_data[] = {
40 { 0x2000, 0x1688a8a8 },
41 { 0x2020, 0x000041f0 },
42 { 0xFF00, 0x00000043 },
43 { 0x0000, 0xfc600309 },
44 { 0x006C, 0x00909090 },
45 { 0x0064, 0x00050000 },
46 { 0x0004, 0x00000585 },
47 { 0x0008, 0x0011030f },
48 { 0x0010, 0x22201724 },
49 { 0x0018, 0x1e29011a },
50 { 0x0020, 0x00c82222 },
51 { 0x0014, 0x01001523 },
52 { 0x001C, 0x1024010d },
53 { 0x0024, 0x00cb2522 },
54 { 0x0038, 0xffffff82 },
55 { 0x003C, 0x00000000 },
56 { 0x0040, 0x00000000 },
57 { 0x0044, 0x00000000 },
58 { 0x0048, 0x00000000 },
59 { 0x004C, 0x00000000 },
60 { 0x0050, 0x00000000 },
61 { 0x0054, 0x00000000 },
62 { 0x0058, 0x00000000 },
63 { 0x005C, 0x00000000 },
64 { 0x0060, 0x032aa02a },
65 { 0x0064, 0x002d3000 },
66 { 0x0068, 0x00000000 },
67 { 0x0070, 0x00000000 },
68 { 0x0074, 0x00000000 },
69 { 0x0078, 0x00000000 },
70 { 0x007C, 0x00000000 },
71 { 0x0034, 0x00000001 },
72 { 0xFF00, 0x00000043 },
73 { 0x002C, 0x00000732 },
74 { 0x0030, 0x00000040 },
75 { 0x0028, 0x00000005 },
76 { 0x0028, 0x00000007 },
77 { 0x0028, 0x00000003 },
78 { 0x0028, 0x00000001 },
79 { 0x000C, 0x00005a08 },
80 { 0x002C, 0x00000632 },
81 { 0x0028, 0x00000001 },
82 { 0x0030, 0x000003c0 },
83 { 0x0028, 0x00000003 },
84 { 0x0030, 0x00000040 },
85 { 0x0028, 0x00000003 },
86 { 0x000C, 0x00005a21 },
87 { 0x0034, 0x00007c03 },
88 { 0x0120, 0x00004c41 },
89 { 0xffff, 0xffffffff },
90};
91
92static const struct ast_dramstruct ast2100_dram_table_data[] = {
93 { 0x2000, 0x1688a8a8 },
94 { 0x2020, 0x00004120 },
95 { 0xFF00, 0x00000043 },
96 { 0x0000, 0xfc600309 },
97 { 0x006C, 0x00909090 },
98 { 0x0064, 0x00070000 },
99 { 0x0004, 0x00000489 },
100 { 0x0008, 0x0011030f },
101 { 0x0010, 0x32302926 },
102 { 0x0018, 0x274c0122 },
103 { 0x0020, 0x00ce2222 },
104 { 0x0014, 0x01001523 },
105 { 0x001C, 0x1024010d },
106 { 0x0024, 0x00cb2522 },
107 { 0x0038, 0xffffff82 },
108 { 0x003C, 0x00000000 },
109 { 0x0040, 0x00000000 },
110 { 0x0044, 0x00000000 },
111 { 0x0048, 0x00000000 },
112 { 0x004C, 0x00000000 },
113 { 0x0050, 0x00000000 },
114 { 0x0054, 0x00000000 },
115 { 0x0058, 0x00000000 },
116 { 0x005C, 0x00000000 },
117 { 0x0060, 0x0f2aa02a },
118 { 0x0064, 0x003f3005 },
119 { 0x0068, 0x02020202 },
120 { 0x0070, 0x00000000 },
121 { 0x0074, 0x00000000 },
122 { 0x0078, 0x00000000 },
123 { 0x007C, 0x00000000 },
124 { 0x0034, 0x00000001 },
125 { 0xFF00, 0x00000043 },
126 { 0x002C, 0x00000942 },
127 { 0x0030, 0x00000040 },
128 { 0x0028, 0x00000005 },
129 { 0x0028, 0x00000007 },
130 { 0x0028, 0x00000003 },
131 { 0x0028, 0x00000001 },
132 { 0x000C, 0x00005a08 },
133 { 0x002C, 0x00000842 },
134 { 0x0028, 0x00000001 },
135 { 0x0030, 0x000003c0 },
136 { 0x0028, 0x00000003 },
137 { 0x0030, 0x00000040 },
138 { 0x0028, 0x00000003 },
139 { 0x000C, 0x00005a21 },
140 { 0x0034, 0x00007c03 },
141 { 0x0120, 0x00005061 },
142 { 0xffff, 0xffffffff },
143};
144
145/*
146 * AST2500 DRAM settings modules
147 */
148#define REGTBL_NUM 17
149#define REGIDX_010 0
150#define REGIDX_014 1
151#define REGIDX_018 2
152#define REGIDX_020 3
153#define REGIDX_024 4
154#define REGIDX_02C 5
155#define REGIDX_030 6
156#define REGIDX_214 7
157#define REGIDX_2E0 8
158#define REGIDX_2E4 9
159#define REGIDX_2E8 10
160#define REGIDX_2EC 11
161#define REGIDX_2F0 12
162#define REGIDX_2F4 13
163#define REGIDX_2F8 14
164#define REGIDX_RFC 15
165#define REGIDX_PLL 16
166
167static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = {
168 0x64604D38, /* 0x010 */
169 0x29690599, /* 0x014 */
170 0x00000300, /* 0x018 */
171 0x00000000, /* 0x020 */
172 0x00000000, /* 0x024 */
173 0x02181E70, /* 0x02C */
174 0x00000040, /* 0x030 */
175 0x00000024, /* 0x214 */
176 0x02001300, /* 0x2E0 */
177 0x0E0000A0, /* 0x2E4 */
178 0x000E001B, /* 0x2E8 */
179 0x35B8C105, /* 0x2EC */
180 0x08090408, /* 0x2F0 */
181 0x9B000800, /* 0x2F4 */
182 0x0E400A00, /* 0x2F8 */
183 0x9971452F, /* tRFC */
184 0x000071C1 /* PLL */
185};
186
187static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = {
188 0x63604E37, /* 0x010 */
189 0xE97AFA99, /* 0x014 */
190 0x00019000, /* 0x018 */
191 0x08000000, /* 0x020 */
192 0x00000400, /* 0x024 */
193 0x00000410, /* 0x02C */
194 0x00000101, /* 0x030 */
195 0x00000024, /* 0x214 */
196 0x03002900, /* 0x2E0 */
197 0x0E0000A0, /* 0x2E4 */
198 0x000E001C, /* 0x2E8 */
199 0x35B8C106, /* 0x2EC */
200 0x08080607, /* 0x2F0 */
201 0x9B000900, /* 0x2F4 */
202 0x0E400A00, /* 0x2F8 */
203 0x99714545, /* tRFC */
204 0x000071C1 /* PLL */
205};
206
207#endif