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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _TA_RAS_IF_H
25#define _TA_RAS_IF_H
26
27#define RAS_TA_HOST_IF_VER 0
28
29/* Responses have bit 31 set */
30#define RSP_ID_MASK (1U << 31)
31#define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)
32
33/* RAS related enumerations */
34/**********************************************************/
35enum ras_command {
36 TA_RAS_COMMAND__ENABLE_FEATURES = 0,
37 TA_RAS_COMMAND__DISABLE_FEATURES,
38 TA_RAS_COMMAND__TRIGGER_ERROR,
39};
40
41enum ta_ras_status
42{
43 TA_RAS_STATUS__SUCCESS = 0x00,
44 TA_RAS_STATUS__RESET_NEEDED = 0xA001,
45 TA_RAS_STATUS__ERROR_INVALID_PARAMETER = 0xA002,
46 TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE = 0xA003,
47 TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD = 0xA004,
48 TA_RAS_STATUS__ERROR_INJECTION_FAILED = 0xA005,
49 TA_RAS_STATUS__ERROR_ASD_READ_WRITE = 0xA006,
50 TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE = 0xA007,
51 TA_RAS_STATUS__ERROR_TIMEOUT = 0xA008,
52 TA_RAS_STATUS__ERROR_BLOCK_DISABLED = 0XA009,
53 TA_RAS_STATUS__ERROR_GENERIC = 0xA00A,
54 TA_RAS_STATUS__ERROR_RAS_MMHUB_INIT = 0xA00B,
55 TA_RAS_STATUS__ERROR_GET_DEV_INFO = 0xA00C,
56 TA_RAS_STATUS__ERROR_UNSUPPORTED_DEV = 0xA00D,
57 TA_RAS_STATUS__ERROR_NOT_INITIALIZED = 0xA00E,
58 TA_RAS_STATUS__ERROR_TEE_INTERNAL = 0xA00F
59};
60
61enum ta_ras_block {
62 TA_RAS_BLOCK__UMC = 0,
63 TA_RAS_BLOCK__SDMA,
64 TA_RAS_BLOCK__GFX,
65 TA_RAS_BLOCK__MMHUB,
66 TA_RAS_BLOCK__ATHUB,
67 TA_RAS_BLOCK__PCIE_BIF,
68 TA_RAS_BLOCK__HDP,
69 TA_RAS_BLOCK__XGMI_WAFL,
70 TA_RAS_BLOCK__DF,
71 TA_RAS_BLOCK__SMN,
72 TA_RAS_BLOCK__SEM,
73 TA_RAS_BLOCK__MP0,
74 TA_RAS_BLOCK__MP1,
75 TA_RAS_BLOCK__FUSE,
76 TA_NUM_BLOCK_MAX
77};
78
79enum ta_ras_error_type {
80 TA_RAS_ERROR__NONE = 0,
81 TA_RAS_ERROR__PARITY = 1,
82 TA_RAS_ERROR__SINGLE_CORRECTABLE = 2,
83 TA_RAS_ERROR__MULTI_UNCORRECTABLE = 4,
84 TA_RAS_ERROR__POISON = 8,
85};
86
87/* Input/output structures for RAS commands */
88/**********************************************************/
89
90struct ta_ras_enable_features_input {
91 enum ta_ras_block block_id;
92 enum ta_ras_error_type error_type;
93};
94
95struct ta_ras_disable_features_input {
96 enum ta_ras_block block_id;
97 enum ta_ras_error_type error_type;
98};
99
100struct ta_ras_trigger_error_input {
101 enum ta_ras_block block_id; // ras-block. i.e. umc, gfx
102 enum ta_ras_error_type inject_error_type; // type of error. i.e. single_correctable
103 uint32_t sub_block_index; // mem block. i.e. hbm, sram etc.
104 uint64_t address; // explicit address of error
105 uint64_t value; // method if error injection. i.e persistent, coherent etc.
106};
107
108struct ta_ras_output_flags
109{
110 uint8_t ras_init_success_flag;
111 uint8_t err_inject_switch_disable_flag;
112 uint8_t reg_access_failure_flag;
113};
114
115/* Common input structure for RAS callbacks */
116/**********************************************************/
117union ta_ras_cmd_input {
118 struct ta_ras_enable_features_input enable_features;
119 struct ta_ras_disable_features_input disable_features;
120 struct ta_ras_trigger_error_input trigger_error;
121
122 uint32_t reserve_pad[256];
123};
124
125union ta_ras_cmd_output
126{
127 struct ta_ras_output_flags flags;
128
129 uint32_t reserve_pad[256];
130};
131
132/* Shared Memory structures */
133/**********************************************************/
134struct ta_ras_shared_memory {
135 uint32_t cmd_id;
136 uint32_t resp_id;
137 uint32_t ras_status;
138 uint32_t if_version;
139 union ta_ras_cmd_input ras_in_message;
140 union ta_ras_cmd_output ras_out_message;
141};
142
143#endif // TL_RAS_IF_H_
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _TA_RAS_IF_H
25#define _TA_RAS_IF_H
26
27#define RAS_TA_HOST_IF_VER 0
28
29/* Responses have bit 31 set */
30#define RSP_ID_MASK (1U << 31)
31#define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)
32
33/* RAS related enumerations */
34/**********************************************************/
35enum ras_command {
36 TA_RAS_COMMAND__ENABLE_FEATURES = 0,
37 TA_RAS_COMMAND__DISABLE_FEATURES,
38 TA_RAS_COMMAND__TRIGGER_ERROR,
39};
40
41enum ta_ras_status {
42 TA_RAS_STATUS__SUCCESS = 0x0000,
43 TA_RAS_STATUS__RESET_NEEDED = 0xA001,
44 TA_RAS_STATUS__ERROR_INVALID_PARAMETER = 0xA002,
45 TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE = 0xA003,
46 TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD = 0xA004,
47 TA_RAS_STATUS__ERROR_INJECTION_FAILED = 0xA005,
48 TA_RAS_STATUS__ERROR_ASD_READ_WRITE = 0xA006,
49 TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE = 0xA007,
50 TA_RAS_STATUS__ERROR_TIMEOUT = 0xA008,
51 TA_RAS_STATUS__ERROR_BLOCK_DISABLED = 0XA009,
52 TA_RAS_STATUS__ERROR_GENERIC = 0xA00A,
53 TA_RAS_STATUS__ERROR_RAS_MMHUB_INIT = 0xA00B,
54 TA_RAS_STATUS__ERROR_GET_DEV_INFO = 0xA00C,
55 TA_RAS_STATUS__ERROR_UNSUPPORTED_DEV = 0xA00D,
56 TA_RAS_STATUS__ERROR_NOT_INITIALIZED = 0xA00E,
57 TA_RAS_STATUS__ERROR_TEE_INTERNAL = 0xA00F,
58 TA_RAS_STATUS__ERROR_UNSUPPORTED_FUNCTION = 0xA010,
59 TA_RAS_STATUS__ERROR_SYS_DRV_REG_ACCESS = 0xA011,
60 TA_RAS_STATUS__ERROR_RAS_READ_WRITE = 0xA012,
61 TA_RAS_STATUS__ERROR_NULL_PTR = 0xA013,
62 TA_RAS_STATUS__ERROR_UNSUPPORTED_IP = 0xA014,
63 TA_RAS_STATUS__ERROR_PCS_STATE_QUIET = 0xA015,
64 TA_RAS_STATUS__ERROR_PCS_STATE_ERROR = 0xA016,
65 TA_RAS_STATUS__ERROR_PCS_STATE_HANG = 0xA017,
66 TA_RAS_STATUS__ERROR_PCS_STATE_UNKNOWN = 0xA018,
67 TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ = 0xA019,
68 TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED = 0xA01A
69};
70
71enum ta_ras_block {
72 TA_RAS_BLOCK__UMC = 0,
73 TA_RAS_BLOCK__SDMA,
74 TA_RAS_BLOCK__GFX,
75 TA_RAS_BLOCK__MMHUB,
76 TA_RAS_BLOCK__ATHUB,
77 TA_RAS_BLOCK__PCIE_BIF,
78 TA_RAS_BLOCK__HDP,
79 TA_RAS_BLOCK__XGMI_WAFL,
80 TA_RAS_BLOCK__DF,
81 TA_RAS_BLOCK__SMN,
82 TA_RAS_BLOCK__SEM,
83 TA_RAS_BLOCK__MP0,
84 TA_RAS_BLOCK__MP1,
85 TA_RAS_BLOCK__FUSE,
86 TA_RAS_BLOCK__MCA,
87 TA_NUM_BLOCK_MAX
88};
89
90enum ta_ras_mca_block {
91 TA_RAS_MCA_BLOCK__MP0 = 0,
92 TA_RAS_MCA_BLOCK__MP1 = 1,
93 TA_RAS_MCA_BLOCK__MPIO = 2,
94 TA_RAS_MCA_BLOCK__IOHC = 3,
95 TA_MCA_NUM_BLOCK_MAX
96};
97
98enum ta_ras_error_type {
99 TA_RAS_ERROR__NONE = 0,
100 TA_RAS_ERROR__PARITY = 1,
101 TA_RAS_ERROR__SINGLE_CORRECTABLE = 2,
102 TA_RAS_ERROR__MULTI_UNCORRECTABLE = 4,
103 TA_RAS_ERROR__POISON = 8,
104};
105
106/* Input/output structures for RAS commands */
107/**********************************************************/
108
109struct ta_ras_enable_features_input {
110 enum ta_ras_block block_id;
111 enum ta_ras_error_type error_type;
112};
113
114struct ta_ras_disable_features_input {
115 enum ta_ras_block block_id;
116 enum ta_ras_error_type error_type;
117};
118
119struct ta_ras_trigger_error_input {
120 enum ta_ras_block block_id; // ras-block. i.e. umc, gfx
121 enum ta_ras_error_type inject_error_type; // type of error. i.e. single_correctable
122 uint32_t sub_block_index; // mem block. i.e. hbm, sram etc.
123 uint64_t address; // explicit address of error
124 uint64_t value; // method if error injection. i.e persistent, coherent etc.
125};
126
127struct ta_ras_init_flags {
128 uint8_t poison_mode_en;
129 uint8_t dgpu_mode;
130};
131
132struct ta_ras_output_flags {
133 uint8_t ras_init_success_flag;
134 uint8_t err_inject_switch_disable_flag;
135 uint8_t reg_access_failure_flag;
136};
137
138/* Common input structure for RAS callbacks */
139/**********************************************************/
140union ta_ras_cmd_input {
141 struct ta_ras_init_flags init_flags;
142 struct ta_ras_enable_features_input enable_features;
143 struct ta_ras_disable_features_input disable_features;
144 struct ta_ras_trigger_error_input trigger_error;
145
146 uint32_t reserve_pad[256];
147};
148
149union ta_ras_cmd_output {
150 struct ta_ras_output_flags flags;
151
152 uint32_t reserve_pad[256];
153};
154
155/* Shared Memory structures */
156/**********************************************************/
157struct ta_ras_shared_memory {
158 uint32_t cmd_id;
159 uint32_t resp_id;
160 uint32_t ras_status;
161 uint32_t if_version;
162 union ta_ras_cmd_input ras_in_message;
163 union ta_ras_cmd_output ras_out_message;
164};
165
166#endif // TL_RAS_IF_H_