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1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_psp.h"
25#include "amdgpu_ucode.h"
26#include "soc15_common.h"
27#include "psp_v13_0_4.h"
28
29#include "mp/mp_13_0_4_offset.h"
30#include "mp/mp_13_0_4_sh_mask.h"
31
32MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin");
33MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin");
34
35static int psp_v13_0_4_init_microcode(struct psp_context *psp)
36{
37 struct amdgpu_device *adev = psp->adev;
38 const char *chip_name;
39 char ucode_prefix[30];
40 int err = 0;
41
42 switch (adev->ip_versions[MP0_HWIP][0]) {
43 case IP_VERSION(13, 0, 4):
44 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
45 chip_name = ucode_prefix;
46 break;
47 default:
48 BUG();
49 }
50
51 switch (adev->ip_versions[MP0_HWIP][0]) {
52 case IP_VERSION(13, 0, 4):
53 err = psp_init_toc_microcode(psp, chip_name);
54 if (err)
55 return err;
56 err = psp_init_ta_microcode(psp, chip_name);
57 if (err)
58 return err;
59 break;
60 default:
61 BUG();
62 }
63
64 return 0;
65}
66
67static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp)
68{
69 struct amdgpu_device *adev = psp->adev;
70 uint32_t sol_reg;
71
72 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
73
74 return sol_reg != 0x0;
75}
76
77static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp)
78{
79 struct amdgpu_device *adev = psp->adev;
80
81 int ret;
82 int retry_loop;
83
84 for (retry_loop = 0; retry_loop < 10; retry_loop++) {
85 /* Wait for bootloader to signify that is
86 ready having bit 31 of C2PMSG_35 set to 1 */
87 ret = psp_wait_for(psp,
88 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
89 0x80000000,
90 0x80000000,
91 false);
92
93 if (ret == 0)
94 return 0;
95 }
96
97 return ret;
98}
99
100static int psp_v13_0_4_bootloader_load_component(struct psp_context *psp,
101 struct psp_bin_desc *bin_desc,
102 enum psp_bootloader_cmd bl_cmd)
103{
104 int ret;
105 uint32_t psp_gfxdrv_command_reg = 0;
106 struct amdgpu_device *adev = psp->adev;
107
108 /* Check tOS sign of life register to confirm sys driver and sOS
109 * are already been loaded.
110 */
111 if (psp_v13_0_4_is_sos_alive(psp))
112 return 0;
113
114 ret = psp_v13_0_4_wait_for_bootloader(psp);
115 if (ret)
116 return ret;
117
118 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
119
120 /* Copy PSP KDB binary to memory */
121 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
122
123 /* Provide the PSP KDB to bootloader */
124 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
125 (uint32_t)(psp->fw_pri_mc_addr >> 20));
126 psp_gfxdrv_command_reg = bl_cmd;
127 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
128 psp_gfxdrv_command_reg);
129
130 ret = psp_v13_0_4_wait_for_bootloader(psp);
131
132 return ret;
133}
134
135static int psp_v13_0_4_bootloader_load_kdb(struct psp_context *psp)
136{
137 return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
138}
139
140static int psp_v13_0_4_bootloader_load_spl(struct psp_context *psp)
141{
142 return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
143}
144
145static int psp_v13_0_4_bootloader_load_sysdrv(struct psp_context *psp)
146{
147 return psp_v13_0_4_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
148}
149
150static int psp_v13_0_4_bootloader_load_soc_drv(struct psp_context *psp)
151{
152 return psp_v13_0_4_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
153}
154
155static int psp_v13_0_4_bootloader_load_intf_drv(struct psp_context *psp)
156{
157 return psp_v13_0_4_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
158}
159
160static int psp_v13_0_4_bootloader_load_dbg_drv(struct psp_context *psp)
161{
162 return psp_v13_0_4_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
163}
164
165static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp)
166{
167 int ret;
168 unsigned int psp_gfxdrv_command_reg = 0;
169 struct amdgpu_device *adev = psp->adev;
170
171 /* Check sOS sign of life register to confirm sys driver and sOS
172 * are already been loaded.
173 */
174 if (psp_v13_0_4_is_sos_alive(psp))
175 return 0;
176
177 ret = psp_v13_0_4_wait_for_bootloader(psp);
178 if (ret)
179 return ret;
180
181 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
182
183 /* Copy Secure OS binary to PSP memory */
184 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
185
186 /* Provide the PSP secure OS to bootloader */
187 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
188 (uint32_t)(psp->fw_pri_mc_addr >> 20));
189 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
190 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
191 psp_gfxdrv_command_reg);
192
193 /* there might be handshake issue with hardware which needs delay */
194 mdelay(20);
195 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
196 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
197 0, true);
198
199 return ret;
200}
201
202static int psp_v13_0_4_ring_stop(struct psp_context *psp,
203 enum psp_ring_type ring_type)
204{
205 int ret = 0;
206 struct amdgpu_device *adev = psp->adev;
207
208 if (amdgpu_sriov_vf(adev)) {
209 /* Write the ring destroy command*/
210 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
211 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
212 /* there might be handshake issue with hardware which needs delay */
213 mdelay(20);
214 /* Wait for response flag (bit 31) */
215 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
216 0x80000000, 0x80000000, false);
217 } else {
218 /* Write the ring destroy command*/
219 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
220 GFX_CTRL_CMD_ID_DESTROY_RINGS);
221 /* there might be handshake issue with hardware which needs delay */
222 mdelay(20);
223 /* Wait for response flag (bit 31) */
224 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
225 0x80000000, 0x80000000, false);
226 }
227
228 return ret;
229}
230
231static int psp_v13_0_4_ring_create(struct psp_context *psp,
232 enum psp_ring_type ring_type)
233{
234 int ret = 0;
235 unsigned int psp_ring_reg = 0;
236 struct psp_ring *ring = &psp->km_ring;
237 struct amdgpu_device *adev = psp->adev;
238
239 if (amdgpu_sriov_vf(adev)) {
240 ret = psp_v13_0_4_ring_stop(psp, ring_type);
241 if (ret) {
242 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
243 return ret;
244 }
245
246 /* Write low address of the ring to C2PMSG_102 */
247 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
248 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
249 /* Write high address of the ring to C2PMSG_103 */
250 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
251 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
252
253 /* Write the ring initialization command to C2PMSG_101 */
254 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
255 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
256
257 /* there might be handshake issue with hardware which needs delay */
258 mdelay(20);
259
260 /* Wait for response flag (bit 31) in C2PMSG_101 */
261 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
262 0x80000000, 0x8000FFFF, false);
263
264 } else {
265 /* Wait for sOS ready for ring creation */
266 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
267 0x80000000, 0x80000000, false);
268 if (ret) {
269 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
270 return ret;
271 }
272
273 /* Write low address of the ring to C2PMSG_69 */
274 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
275 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
276 /* Write high address of the ring to C2PMSG_70 */
277 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
278 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
279 /* Write size of ring to C2PMSG_71 */
280 psp_ring_reg = ring->ring_size;
281 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
282 /* Write the ring initialization command to C2PMSG_64 */
283 psp_ring_reg = ring_type;
284 psp_ring_reg = psp_ring_reg << 16;
285 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
286
287 /* there might be handshake issue with hardware which needs delay */
288 mdelay(20);
289
290 /* Wait for response flag (bit 31) in C2PMSG_64 */
291 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
292 0x80000000, 0x8000FFFF, false);
293 }
294
295 return ret;
296}
297
298static int psp_v13_0_4_ring_destroy(struct psp_context *psp,
299 enum psp_ring_type ring_type)
300{
301 int ret = 0;
302 struct psp_ring *ring = &psp->km_ring;
303 struct amdgpu_device *adev = psp->adev;
304
305 ret = psp_v13_0_4_ring_stop(psp, ring_type);
306 if (ret)
307 DRM_ERROR("Fail to stop psp ring\n");
308
309 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
310 &ring->ring_mem_mc_addr,
311 (void **)&ring->ring_mem);
312
313 return ret;
314}
315
316static uint32_t psp_v13_0_4_ring_get_wptr(struct psp_context *psp)
317{
318 uint32_t data;
319 struct amdgpu_device *adev = psp->adev;
320
321 if (amdgpu_sriov_vf(adev))
322 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
323 else
324 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
325
326 return data;
327}
328
329static void psp_v13_0_4_ring_set_wptr(struct psp_context *psp, uint32_t value)
330{
331 struct amdgpu_device *adev = psp->adev;
332
333 if (amdgpu_sriov_vf(adev)) {
334 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
335 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
336 GFX_CTRL_CMD_ID_CONSUME_CMD);
337 } else
338 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
339}
340
341static const struct psp_funcs psp_v13_0_4_funcs = {
342 .init_microcode = psp_v13_0_4_init_microcode,
343 .bootloader_load_kdb = psp_v13_0_4_bootloader_load_kdb,
344 .bootloader_load_spl = psp_v13_0_4_bootloader_load_spl,
345 .bootloader_load_sysdrv = psp_v13_0_4_bootloader_load_sysdrv,
346 .bootloader_load_soc_drv = psp_v13_0_4_bootloader_load_soc_drv,
347 .bootloader_load_intf_drv = psp_v13_0_4_bootloader_load_intf_drv,
348 .bootloader_load_dbg_drv = psp_v13_0_4_bootloader_load_dbg_drv,
349 .bootloader_load_sos = psp_v13_0_4_bootloader_load_sos,
350 .ring_create = psp_v13_0_4_ring_create,
351 .ring_stop = psp_v13_0_4_ring_stop,
352 .ring_destroy = psp_v13_0_4_ring_destroy,
353 .ring_get_wptr = psp_v13_0_4_ring_get_wptr,
354 .ring_set_wptr = psp_v13_0_4_ring_set_wptr,
355};
356
357void psp_v13_0_4_set_psp_funcs(struct psp_context *psp)
358{
359 psp->funcs = &psp_v13_0_4_funcs;
360}