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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu.h"
25#include "gfxhub_v2_1.h"
26
27#include "gc/gc_10_3_0_offset.h"
28#include "gc/gc_10_3_0_sh_mask.h"
29#include "gc/gc_10_3_0_default.h"
30#include "navi10_enum.h"
31
32#include "soc15_common.h"
33
34u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)
35{
36 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
37
38 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
39 base <<= 24;
40
41 return base;
42}
43
44u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev)
45{
46 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
47}
48
49void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
50 uint64_t page_table_base)
51{
52 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
53
54 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
55 hub->ctx_addr_distance * vmid,
56 lower_32_bits(page_table_base));
57
58 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
59 hub->ctx_addr_distance * vmid,
60 upper_32_bits(page_table_base));
61}
62
63static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev)
64{
65 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
66
67 gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base);
68
69 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
70 (u32)(adev->gmc.gart_start >> 12));
71 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
72 (u32)(adev->gmc.gart_start >> 44));
73
74 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
75 (u32)(adev->gmc.gart_end >> 12));
76 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
77 (u32)(adev->gmc.gart_end >> 44));
78}
79
80static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev)
81{
82 uint64_t value;
83
84 /* Disable AGP. */
85 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
86 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0);
87 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF);
88
89 /* Program the system aperture low logical page number. */
90 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
91 adev->gmc.vram_start >> 18);
92 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
93 adev->gmc.vram_end >> 18);
94
95 /* Set default page address. */
96 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
97 + adev->vm_manager.vram_base_offset;
98 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
99 (u32)(value >> 12));
100 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
101 (u32)(value >> 44));
102
103 /* Program "protection fault". */
104 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
105 (u32)(adev->dummy_page_addr >> 12));
106 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
107 (u32)((u64)adev->dummy_page_addr >> 44));
108
109 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
110 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
111}
112
113
114static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev)
115{
116 uint32_t tmp;
117
118 /* Setup TLB control */
119 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
120
121 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
122 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
123 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
124 ENABLE_ADVANCED_DRIVER_MODEL, 1);
125 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
126 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
127 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
128 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
129 MTYPE, MTYPE_UC); /* UC, uncached */
130
131 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
132}
133
134static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev)
135{
136 uint32_t tmp;
137
138 /* These registers are not accessible to VF-SRIOV.
139 * The PF will program them instead.
140 */
141 if (amdgpu_sriov_vf(adev))
142 return;
143
144 /* Setup L2 cache */
145 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
146 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
147 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
148 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
149 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
150 /* XXX for emulation, Refer to closed source code.*/
151 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
152 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
153 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
154 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
155 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
156 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
157
158 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
159 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
160 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
161 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
162
163 tmp = mmGCVM_L2_CNTL3_DEFAULT;
164 if (adev->gmc.translate_further) {
165 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
166 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
167 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
168 } else {
169 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
170 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
171 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
172 }
173 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
174
175 tmp = mmGCVM_L2_CNTL4_DEFAULT;
176 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
177 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
178 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
179
180 tmp = mmGCVM_L2_CNTL5_DEFAULT;
181 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
182 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
183}
184
185static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev)
186{
187 uint32_t tmp;
188
189 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
190 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
191 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
192 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
193 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
194 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
195}
196
197static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)
198{
199 /* These registers are not accessible to VF-SRIOV.
200 * The PF will program them instead.
201 */
202 if (amdgpu_sriov_vf(adev))
203 return;
204
205 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
206 0xFFFFFFFF);
207 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
208 0x0000000F);
209
210 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
211 0);
212 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
213 0);
214
215 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
216 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
217
218}
219
220static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev)
221{
222 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
223 int i;
224 uint32_t tmp;
225
226 for (i = 0; i <= 14; i++) {
227 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
228 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
229 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
230 adev->vm_manager.num_level);
231 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
232 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
233 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
234 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
235 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
236 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
237 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
238 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
239 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
240 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
241 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
242 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
243 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
244 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
245 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
246 PAGE_TABLE_BLOCK_SIZE,
247 adev->vm_manager.block_size - 9);
248 /* Send no-retry XNACK on fault to suppress VM fault storm. */
249 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
250 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
251 !amdgpu_noretry);
252 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,
253 i * hub->ctx_distance, tmp);
254 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
255 i * hub->ctx_addr_distance, 0);
256 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
257 i * hub->ctx_addr_distance, 0);
258 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
259 i * hub->ctx_addr_distance,
260 lower_32_bits(adev->vm_manager.max_pfn - 1));
261 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
262 i * hub->ctx_addr_distance,
263 upper_32_bits(adev->vm_manager.max_pfn - 1));
264 }
265}
266
267static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev)
268{
269 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
270 unsigned i;
271
272 for (i = 0 ; i < 18; ++i) {
273 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
274 i * hub->eng_addr_distance, 0xffffffff);
275 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
276 i * hub->eng_addr_distance, 0x1f);
277 }
278}
279
280int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev)
281{
282 if (amdgpu_sriov_vf(adev)) {
283 /*
284 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
285 * VF copy registers so vbios post doesn't program them, for
286 * SRIOV driver need to program them
287 */
288 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE,
289 adev->gmc.vram_start >> 24);
290 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP,
291 adev->gmc.vram_end >> 24);
292 }
293
294 /* GART Enable. */
295 gfxhub_v2_1_init_gart_aperture_regs(adev);
296 gfxhub_v2_1_init_system_aperture_regs(adev);
297 gfxhub_v2_1_init_tlb_regs(adev);
298 gfxhub_v2_1_init_cache_regs(adev);
299
300 gfxhub_v2_1_enable_system_domain(adev);
301 gfxhub_v2_1_disable_identity_aperture(adev);
302 gfxhub_v2_1_setup_vmid_config(adev);
303 gfxhub_v2_1_program_invalidation(adev);
304
305 return 0;
306}
307
308void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev)
309{
310 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
311 u32 tmp;
312 u32 i;
313
314 /* Disable all tables */
315 for (i = 0; i < 16; i++)
316 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL,
317 i * hub->ctx_distance, 0);
318
319 /* Setup TLB control */
320 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
321 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
322 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
323 ENABLE_ADVANCED_DRIVER_MODEL, 0);
324 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
325
326 /* Setup L2 cache */
327 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
328 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
329}
330
331/**
332 * gfxhub_v2_1_set_fault_enable_default - update GART/VM fault handling
333 *
334 * @adev: amdgpu_device pointer
335 * @value: true redirects VM faults to the default page
336 */
337void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
338 bool value)
339{
340 u32 tmp;
341
342 /* These registers are not accessible to VF-SRIOV.
343 * The PF will program them instead.
344 */
345 if (amdgpu_sriov_vf(adev))
346 return;
347
348 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
349 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
350 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
351 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
352 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
353 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
354 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
355 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
356 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
357 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
358 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
359 value);
360 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
361 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
362 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
363 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
364 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
365 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
366 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
367 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
368 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
369 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
370 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
371 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
372 if (!value) {
373 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
374 CRASH_ON_NO_RETRY_FAULT, 1);
375 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
376 CRASH_ON_RETRY_FAULT, 1);
377 }
378 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
379}
380
381void gfxhub_v2_1_init(struct amdgpu_device *adev)
382{
383 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
384
385 hub->ctx0_ptb_addr_lo32 =
386 SOC15_REG_OFFSET(GC, 0,
387 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
388 hub->ctx0_ptb_addr_hi32 =
389 SOC15_REG_OFFSET(GC, 0,
390 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
391 hub->vm_inv_eng0_sem =
392 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
393 hub->vm_inv_eng0_req =
394 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
395 hub->vm_inv_eng0_ack =
396 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
397 hub->vm_context0_cntl =
398 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
399 hub->vm_l2_pro_fault_status =
400 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
401 hub->vm_l2_pro_fault_cntl =
402 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
403
404 hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL;
405 hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
406 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
407 hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ -
408 mmGCVM_INVALIDATE_ENG0_REQ;
409 hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
410 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
411}
412
413int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
414{
415 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL);
416 u32 max_region =
417 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
418 u32 max_num_physical_nodes = 0;
419 u32 max_physical_node_id = 0;
420
421 switch (adev->asic_type) {
422 case CHIP_SIENNA_CICHLID:
423 max_num_physical_nodes = 4;
424 max_physical_node_id = 3;
425 break;
426 default:
427 return -EINVAL;
428 }
429
430 /* PF_MAX_REGION=0 means xgmi is disabled */
431 if (max_region) {
432 adev->gmc.xgmi.num_physical_nodes = max_region + 1;
433 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
434 return -EINVAL;
435
436 adev->gmc.xgmi.physical_node_id =
437 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);
438 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
439 return -EINVAL;
440
441 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD(
442 RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE),
443 GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
444 }
445
446 return 0;
447}
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu.h"
25#include "gfxhub_v2_1.h"
26
27#include "gc/gc_10_3_0_offset.h"
28#include "gc/gc_10_3_0_sh_mask.h"
29#include "gc/gc_10_3_0_default.h"
30#include "navi10_enum.h"
31
32#include "soc15_common.h"
33
34#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP 0x16f8
35#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP_BASE_IDX 0
36
37static const char *gfxhub_client_ids[] = {
38 "CB/DB",
39 "Reserved",
40 "GE1",
41 "GE2",
42 "CPF",
43 "CPC",
44 "CPG",
45 "RLC",
46 "TCP",
47 "SQC (inst)",
48 "SQC (data)",
49 "SQG",
50 "Reserved",
51 "SDMA0",
52 "SDMA1",
53 "GCR",
54 "SDMA2",
55 "SDMA3",
56};
57
58static uint32_t gfxhub_v2_1_get_invalidate_req(unsigned int vmid,
59 uint32_t flush_type)
60{
61 u32 req = 0;
62
63 /* invalidate using legacy mode on vmid*/
64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
65 PER_VMID_INVALIDATE_REQ, 1 << vmid);
66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
70 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
71 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
72 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
73 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
74
75 return req;
76}
77
78static void
79gfxhub_v2_1_print_l2_protection_fault_status(struct amdgpu_device *adev,
80 uint32_t status)
81{
82 u32 cid = REG_GET_FIELD(status,
83 GCVM_L2_PROTECTION_FAULT_STATUS, CID);
84
85 dev_err(adev->dev,
86 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
87 status);
88 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
89 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],
90 cid);
91 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
92 REG_GET_FIELD(status,
93 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
94 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
95 REG_GET_FIELD(status,
96 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
97 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
98 REG_GET_FIELD(status,
99 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
100 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
101 REG_GET_FIELD(status,
102 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
103 dev_err(adev->dev, "\t RW: 0x%lx\n",
104 REG_GET_FIELD(status,
105 GCVM_L2_PROTECTION_FAULT_STATUS, RW));
106}
107
108static u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)
109{
110 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
111
112 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
113 base <<= 24;
114
115 return base;
116}
117
118static u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev)
119{
120 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
121}
122
123static void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
124 uint64_t page_table_base)
125{
126 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
127
128 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
129 hub->ctx_addr_distance * vmid,
130 lower_32_bits(page_table_base));
131
132 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
133 hub->ctx_addr_distance * vmid,
134 upper_32_bits(page_table_base));
135}
136
137static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev)
138{
139 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
140
141 gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base);
142
143 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
144 (u32)(adev->gmc.gart_start >> 12));
145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
146 (u32)(adev->gmc.gart_start >> 44));
147
148 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
149 (u32)(adev->gmc.gart_end >> 12));
150 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
151 (u32)(adev->gmc.gart_end >> 44));
152}
153
154static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev)
155{
156 uint64_t value;
157
158 /* Program the AGP BAR */
159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
160 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
161 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
162
163 /* Program the system aperture low logical page number. */
164 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
165 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
166 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
167 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
168
169 /* Set default page address. */
170 value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
171 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
172 (u32)(value >> 12));
173 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
174 (u32)(value >> 44));
175
176 /* Program "protection fault". */
177 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
178 (u32)(adev->dummy_page_addr >> 12));
179 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
180 (u32)((u64)adev->dummy_page_addr >> 44));
181
182 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
183 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
184}
185
186
187static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev)
188{
189 uint32_t tmp;
190
191 /* Setup TLB control */
192 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
193
194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
196 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
197 ENABLE_ADVANCED_DRIVER_MODEL, 1);
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
199 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
201 MTYPE, MTYPE_UC); /* UC, uncached */
202
203 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
204}
205
206static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev)
207{
208 uint32_t tmp;
209
210 /* These registers are not accessible to VF-SRIOV.
211 * The PF will program them instead.
212 */
213 if (amdgpu_sriov_vf(adev))
214 return;
215
216 /* Setup L2 cache */
217 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
218 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
219 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
220 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
221 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
222 /* XXX for emulation, Refer to closed source code.*/
223 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
224 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
225 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
226 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
227 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
228 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
229
230 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
231 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
232 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
233 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
234
235 tmp = mmGCVM_L2_CNTL3_DEFAULT;
236 if (adev->gmc.translate_further) {
237 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
238 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
239 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
240 } else {
241 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
242 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
243 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
244 }
245 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
246
247 tmp = mmGCVM_L2_CNTL4_DEFAULT;
248 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
249 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
250 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
251
252 tmp = mmGCVM_L2_CNTL5_DEFAULT;
253 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
254 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
255}
256
257static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev)
258{
259 uint32_t tmp;
260
261 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
262 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
263 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
264 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
265 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
266 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
267}
268
269static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)
270{
271 /* These registers are not accessible to VF-SRIOV.
272 * The PF will program them instead.
273 */
274 if (amdgpu_sriov_vf(adev))
275 return;
276
277 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
278 0xFFFFFFFF);
279 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
280 0x0000000F);
281
282 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
283 0);
284 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
285 0);
286
287 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
288 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
289
290}
291
292static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev)
293{
294 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
295 int i;
296 uint32_t tmp;
297
298 for (i = 0; i <= 14; i++) {
299 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
300 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
301 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
302 adev->vm_manager.num_level);
303 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
304 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
305 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
306 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
307 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
308 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
309 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
310 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
311 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
312 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
313 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
314 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
315 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
316 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
317 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
318 PAGE_TABLE_BLOCK_SIZE,
319 adev->vm_manager.block_size - 9);
320 /* Send no-retry XNACK on fault to suppress VM fault storm. */
321 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
322 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
323 !adev->gmc.noretry);
324 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,
325 i * hub->ctx_distance, tmp);
326 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
327 i * hub->ctx_addr_distance, 0);
328 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
329 i * hub->ctx_addr_distance, 0);
330 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
331 i * hub->ctx_addr_distance,
332 lower_32_bits(adev->vm_manager.max_pfn - 1));
333 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
334 i * hub->ctx_addr_distance,
335 upper_32_bits(adev->vm_manager.max_pfn - 1));
336 }
337
338 hub->vm_cntx_cntl = tmp;
339}
340
341static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev)
342{
343 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
344 unsigned i;
345
346 for (i = 0 ; i < 18; ++i) {
347 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
348 i * hub->eng_addr_distance, 0xffffffff);
349 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
350 i * hub->eng_addr_distance, 0x1f);
351 }
352}
353
354static int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev)
355{
356 if (amdgpu_sriov_vf(adev)) {
357 /*
358 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
359 * VF copy registers so vbios post doesn't program them, for
360 * SRIOV driver need to program them
361 */
362 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE,
363 adev->gmc.vram_start >> 24);
364 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP,
365 adev->gmc.vram_end >> 24);
366 }
367
368 /* GART Enable. */
369 gfxhub_v2_1_init_gart_aperture_regs(adev);
370 gfxhub_v2_1_init_system_aperture_regs(adev);
371 gfxhub_v2_1_init_tlb_regs(adev);
372 gfxhub_v2_1_init_cache_regs(adev);
373
374 gfxhub_v2_1_enable_system_domain(adev);
375 gfxhub_v2_1_disable_identity_aperture(adev);
376 gfxhub_v2_1_setup_vmid_config(adev);
377 gfxhub_v2_1_program_invalidation(adev);
378
379 return 0;
380}
381
382static void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev)
383{
384 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
385 u32 tmp;
386 u32 i;
387
388 /* Disable all tables */
389 for (i = 0; i < 16; i++)
390 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL,
391 i * hub->ctx_distance, 0);
392
393 /* Setup TLB control */
394 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
395 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
396 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
397 ENABLE_ADVANCED_DRIVER_MODEL, 0);
398 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
399
400 if (amdgpu_sriov_vf(adev))
401 return;
402
403 /* Setup L2 cache */
404 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
405 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
406}
407
408/**
409 * gfxhub_v2_1_set_fault_enable_default - update GART/VM fault handling
410 *
411 * @adev: amdgpu_device pointer
412 * @value: true redirects VM faults to the default page
413 */
414static void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
415 bool value)
416{
417 u32 tmp;
418
419 /* These registers are not accessible to VF-SRIOV.
420 * The PF will program them instead.
421 */
422 if (amdgpu_sriov_vf(adev))
423 return;
424
425 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
426 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
427 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
428 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
429 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
430 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
431 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
432 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
433 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
434 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
435 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
436 value);
437 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
438 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
439 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
440 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
441 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
442 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
443 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
444 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
445 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
446 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
447 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
448 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
449 if (!value) {
450 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
451 CRASH_ON_NO_RETRY_FAULT, 1);
452 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
453 CRASH_ON_RETRY_FAULT, 1);
454 }
455 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
456}
457
458static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = {
459 .print_l2_protection_fault_status = gfxhub_v2_1_print_l2_protection_fault_status,
460 .get_invalidate_req = gfxhub_v2_1_get_invalidate_req,
461};
462
463static void gfxhub_v2_1_init(struct amdgpu_device *adev)
464{
465 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
466
467 hub->ctx0_ptb_addr_lo32 =
468 SOC15_REG_OFFSET(GC, 0,
469 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
470 hub->ctx0_ptb_addr_hi32 =
471 SOC15_REG_OFFSET(GC, 0,
472 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
473 hub->vm_inv_eng0_sem =
474 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
475 hub->vm_inv_eng0_req =
476 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
477 hub->vm_inv_eng0_ack =
478 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
479 hub->vm_context0_cntl =
480 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
481 hub->vm_l2_pro_fault_status =
482 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
483 hub->vm_l2_pro_fault_cntl =
484 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
485
486 hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL;
487 hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
488 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
489 hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ -
490 mmGCVM_INVALIDATE_ENG0_REQ;
491 hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
492 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
493
494 hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
495 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
496 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
497 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
498 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
499 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
500 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
501
502 hub->vmhub_funcs = &gfxhub_v2_1_vmhub_funcs;
503}
504
505static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
506{
507 u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL);
508 u32 max_region =
509 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
510 u32 max_num_physical_nodes = 0;
511 u32 max_physical_node_id = 0;
512
513 switch (adev->ip_versions[XGMI_HWIP][0]) {
514 case IP_VERSION(4, 8, 0):
515 max_num_physical_nodes = 4;
516 max_physical_node_id = 3;
517 break;
518 default:
519 return -EINVAL;
520 }
521
522 /* PF_MAX_REGION=0 means xgmi is disabled */
523 if (max_region) {
524 adev->gmc.xgmi.num_physical_nodes = max_region + 1;
525 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
526 return -EINVAL;
527
528 adev->gmc.xgmi.physical_node_id =
529 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);
530 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
531 return -EINVAL;
532
533 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD(
534 RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE),
535 GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
536 }
537
538 return 0;
539}
540
541static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)
542{
543 int i;
544 u32 tmp = 0, disabled_sa = 0;
545 u32 efuse_setting, vbios_setting;
546
547 u32 max_sa_mask = amdgpu_gfx_create_bitmask(
548 adev->gfx.config.max_sh_per_se *
549 adev->gfx.config.max_shader_engines);
550
551 switch (adev->ip_versions[GC_HWIP][0]) {
552 case IP_VERSION(10, 3, 1):
553 case IP_VERSION(10, 3, 3):
554 /* Get SA disabled bitmap from eFuse setting */
555 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
556 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
557 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
558
559 /* Get SA disabled bitmap from VBIOS setting */
560 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
561 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
562 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
563
564 disabled_sa |= efuse_setting | vbios_setting;
565 /* Make sure not to report harvested SAs beyond the max SA count */
566 disabled_sa &= max_sa_mask;
567
568 for (i = 0; disabled_sa > 0; i++) {
569 if (disabled_sa & 1)
570 tmp |= 0x3 << (i * 2);
571 disabled_sa >>= 1;
572 }
573 disabled_sa = tmp;
574
575 WREG32_SOC15(GC, 0, mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP, disabled_sa);
576 break;
577 default:
578 break;
579 }
580}
581
582static void gfxhub_v2_1_save_regs(struct amdgpu_device *adev)
583{
584 int i;
585 adev->gmc.VM_L2_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
586 adev->gmc.VM_L2_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
587 adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_CNTL);
588 adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32);
589 adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32);
590 adev->gmc.VM_L2_PROTECTION_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
591 adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2);
592 adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3);
593 adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4);
594 adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32);
595 adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32);
596 adev->gmc.VM_DEBUG = RREG32_SOC15(GC, 0, mmGCVM_DEBUG);
597 adev->gmc.VM_L2_MM_GROUP_RT_CLASSES = RREG32_SOC15(GC, 0, mmGCVM_L2_MM_GROUP_RT_CLASSES);
598 adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID);
599 adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2 = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID2);
600 adev->gmc.VM_L2_CACHE_PARITY_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CACHE_PARITY_CNTL);
601 adev->gmc.VM_L2_IH_LOG_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_IH_LOG_CNTL);
602
603 for (i = 0; i <= 15; i++) {
604 adev->gmc.VM_CONTEXT_CNTL[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i);
605 adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, i * 2);
606 adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, i * 2);
607 adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, i * 2);
608 adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, i * 2);
609 adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, i * 2);
610 adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, i * 2);
611 }
612
613 adev->gmc.MC_VM_MX_L1_TLB_CNTL = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
614}
615
616static void gfxhub_v2_1_restore_regs(struct amdgpu_device *adev)
617{
618 int i;
619 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, adev->gmc.VM_L2_CNTL);
620 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, adev->gmc.VM_L2_CNTL2);
621 WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_CNTL, adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL);
622 WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32, adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32);
623 WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32, adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32);
624 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, adev->gmc.VM_L2_PROTECTION_FAULT_CNTL);
625 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2, adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2);
626 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3, adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3);
627 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4, adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4);
628 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32, adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32);
629 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32, adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32);
630 WREG32_SOC15(GC, 0, mmGCVM_DEBUG, adev->gmc.VM_DEBUG);
631 WREG32_SOC15(GC, 0, mmGCVM_L2_MM_GROUP_RT_CLASSES, adev->gmc.VM_L2_MM_GROUP_RT_CLASSES);
632 WREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID, adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID);
633 WREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID2, adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2);
634 WREG32_SOC15(GC, 0, mmGCVM_L2_CACHE_PARITY_CNTL, adev->gmc.VM_L2_CACHE_PARITY_CNTL);
635 WREG32_SOC15(GC, 0, mmGCVM_L2_IH_LOG_CNTL, adev->gmc.VM_L2_IH_LOG_CNTL);
636
637 for (i = 0; i <= 15; i++) {
638 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, adev->gmc.VM_CONTEXT_CNTL[i]);
639 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[i]);
640 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[i]);
641 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[i]);
642 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[i]);
643 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[i]);
644 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[i]);
645 }
646
647 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, adev->gmc.vram_start >> 24);
648 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, adev->gmc.vram_end >> 24);
649 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, adev->gmc.MC_VM_MX_L1_TLB_CNTL);
650}
651
652static void gfxhub_v2_1_halt(struct amdgpu_device *adev)
653{
654 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
655 int i;
656 uint32_t tmp;
657 int time = 1000;
658
659 gfxhub_v2_1_set_fault_enable_default(adev, false);
660
661 for (i = 0; i <= 14; i++) {
662 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
663 i * hub->ctx_addr_distance, ~0);
664 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
665 i * hub->ctx_addr_distance, ~0);
666 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
667 i * hub->ctx_addr_distance,
668 0);
669 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
670 i * hub->ctx_addr_distance,
671 0);
672 }
673 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
674 while ((tmp & (GRBM_STATUS2__EA_BUSY_MASK |
675 GRBM_STATUS2__EA_LINK_BUSY_MASK)) != 0 &&
676 time) {
677 udelay(100);
678 time--;
679 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
680 }
681
682 if (!time) {
683 DRM_WARN("failed to wait for GRBM(EA) idle\n");
684 }
685}
686
687const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
688 .get_fb_location = gfxhub_v2_1_get_fb_location,
689 .get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset,
690 .setup_vm_pt_regs = gfxhub_v2_1_setup_vm_pt_regs,
691 .gart_enable = gfxhub_v2_1_gart_enable,
692 .gart_disable = gfxhub_v2_1_gart_disable,
693 .set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default,
694 .init = gfxhub_v2_1_init,
695 .get_xgmi_info = gfxhub_v2_1_get_xgmi_info,
696 .utcl2_harvest = gfxhub_v2_1_utcl2_harvest,
697 .mode2_save_regs = gfxhub_v2_1_save_regs,
698 .mode2_restore_regs = gfxhub_v2_1_restore_regs,
699 .halt = gfxhub_v2_1_halt,
700};