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1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#ifndef _AMDGPU_RAS_H
25#define _AMDGPU_RAS_H
26
27#include <linux/debugfs.h>
28#include <linux/list.h>
29#include "amdgpu.h"
30#include "amdgpu_psp.h"
31#include "ta_ras_if.h"
32#include "amdgpu_ras_eeprom.h"
33
34enum amdgpu_ras_block {
35 AMDGPU_RAS_BLOCK__UMC = 0,
36 AMDGPU_RAS_BLOCK__SDMA,
37 AMDGPU_RAS_BLOCK__GFX,
38 AMDGPU_RAS_BLOCK__MMHUB,
39 AMDGPU_RAS_BLOCK__ATHUB,
40 AMDGPU_RAS_BLOCK__PCIE_BIF,
41 AMDGPU_RAS_BLOCK__HDP,
42 AMDGPU_RAS_BLOCK__XGMI_WAFL,
43 AMDGPU_RAS_BLOCK__DF,
44 AMDGPU_RAS_BLOCK__SMN,
45 AMDGPU_RAS_BLOCK__SEM,
46 AMDGPU_RAS_BLOCK__MP0,
47 AMDGPU_RAS_BLOCK__MP1,
48 AMDGPU_RAS_BLOCK__FUSE,
49
50 AMDGPU_RAS_BLOCK__LAST
51};
52
53#define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST
54#define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
55
56enum amdgpu_ras_gfx_subblock {
57 /* CPC */
58 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
59 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
60 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
61 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
62 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
63 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
64 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
65 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
66 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
67 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
68 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
69 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
70 /* CPF */
71 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
72 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
73 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
74 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
75 AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
76 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
77 /* CPG */
78 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
79 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
80 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
81 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
82 AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
83 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
84 /* GDS */
85 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
86 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
87 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
88 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
89 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
90 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
91 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
92 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
93 /* SPI */
94 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
95 /* SQ */
96 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
97 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
98 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
99 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
100 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
101 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
102 /* SQC (3 ranges) */
103 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
104 /* SQC range 0 */
105 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
106 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
107 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
108 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
109 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
110 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
111 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
112 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
113 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
114 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
115 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
116 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
117 /* SQC range 1 */
118 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
119 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
120 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
121 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
122 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
123 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
124 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
125 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
126 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
127 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
128 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
129 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
130 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
131 /* SQC range 2 */
132 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
133 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
134 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
135 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
136 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
137 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
138 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
139 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
140 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
141 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
142 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
143 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
144 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
145 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
146 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
147 /* TA */
148 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
149 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
150 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
151 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
152 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
153 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
154 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
155 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
156 /* TCA */
157 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
158 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
159 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
160 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
161 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
162 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
163 /* TCC (5 sub-ranges) */
164 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
165 /* TCC range 0 */
166 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
167 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
168 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
169 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
170 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
171 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
172 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
173 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
174 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
175 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
176 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
177 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
178 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
179 /* TCC range 1 */
180 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
181 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
182 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
183 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
184 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
185 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
186 /* TCC range 2 */
187 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
188 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
189 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
190 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
191 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
192 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
193 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
194 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
195 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
196 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
197 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
198 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
199 /* TCC range 3 */
200 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
201 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
202 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
203 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
204 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
205 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
206 /* TCC range 4 */
207 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
208 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
209 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
210 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
211 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
212 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
213 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
214 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
215 /* TCI */
216 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
217 /* TCP */
218 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
219 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
220 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
221 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
222 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
223 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
224 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
225 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
226 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
227 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
228 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
229 /* TD */
230 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
231 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
232 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
233 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
234 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
235 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
236 /* EA (3 sub-ranges) */
237 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
238 /* EA range 0 */
239 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
240 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
241 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
242 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
243 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
244 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
245 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
246 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
247 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
248 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
249 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
250 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
251 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
252 /* EA range 1 */
253 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
254 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
255 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
256 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
257 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
258 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
259 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
260 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
261 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
262 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
263 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
264 /* EA range 2 */
265 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
266 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
267 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
268 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
269 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
270 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
271 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
272 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
273 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
274 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
275 /* UTC VM L2 bank */
276 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
277 /* UTC VM walker */
278 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
279 /* UTC ATC L2 2MB cache */
280 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
281 /* UTC ATC L2 4KB cache */
282 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
283 AMDGPU_RAS_BLOCK__GFX_MAX
284};
285
286enum amdgpu_ras_error_type {
287 AMDGPU_RAS_ERROR__NONE = 0,
288 AMDGPU_RAS_ERROR__PARITY = 1,
289 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2,
290 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4,
291 AMDGPU_RAS_ERROR__POISON = 8,
292};
293
294enum amdgpu_ras_ret {
295 AMDGPU_RAS_SUCCESS = 0,
296 AMDGPU_RAS_FAIL,
297 AMDGPU_RAS_UE,
298 AMDGPU_RAS_CE,
299 AMDGPU_RAS_PT,
300};
301
302struct ras_common_if {
303 enum amdgpu_ras_block block;
304 enum amdgpu_ras_error_type type;
305 uint32_t sub_block_index;
306 /* block name */
307 char name[32];
308};
309
310struct amdgpu_ras {
311 /* ras infrastructure */
312 /* for ras itself. */
313 uint32_t hw_supported;
314 /* for IP to check its ras ability. */
315 uint32_t supported;
316 uint32_t features;
317 struct list_head head;
318 /* debugfs */
319 struct dentry *dir;
320 /* sysfs */
321 struct device_attribute features_attr;
322 struct bin_attribute badpages_attr;
323 /* block array */
324 struct ras_manager *objs;
325
326 /* gpu recovery */
327 struct work_struct recovery_work;
328 atomic_t in_recovery;
329 struct amdgpu_device *adev;
330 /* error handler data */
331 struct ras_err_handler_data *eh_data;
332 struct mutex recovery_lock;
333
334 uint32_t flags;
335 bool reboot;
336 struct amdgpu_ras_eeprom_control eeprom_control;
337
338 bool error_query_ready;
339};
340
341struct ras_fs_data {
342 char sysfs_name[32];
343 char debugfs_name[32];
344};
345
346struct ras_err_data {
347 unsigned long ue_count;
348 unsigned long ce_count;
349 unsigned long err_addr_cnt;
350 struct eeprom_table_record *err_addr;
351};
352
353struct ras_err_handler_data {
354 /* point to bad page records array */
355 struct eeprom_table_record *bps;
356 /* point to reserved bo array */
357 struct amdgpu_bo **bps_bo;
358 /* the count of entries */
359 int count;
360 /* the space can place new entries */
361 int space_left;
362 /* last reserved entry's index + 1 */
363 int last_reserved;
364};
365
366typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
367 void *err_data,
368 struct amdgpu_iv_entry *entry);
369
370struct ras_ih_data {
371 /* interrupt bottom half */
372 struct work_struct ih_work;
373 int inuse;
374 /* IP callback */
375 ras_ih_cb cb;
376 /* full of entries */
377 unsigned char *ring;
378 unsigned int ring_size;
379 unsigned int element_size;
380 unsigned int aligned_element_size;
381 unsigned int rptr;
382 unsigned int wptr;
383};
384
385struct ras_manager {
386 struct ras_common_if head;
387 /* reference count */
388 int use;
389 /* ras block link */
390 struct list_head node;
391 /* the device */
392 struct amdgpu_device *adev;
393 /* debugfs */
394 struct dentry *ent;
395 /* sysfs */
396 struct device_attribute sysfs_attr;
397 int attr_inuse;
398
399 /* fs node name */
400 struct ras_fs_data fs_data;
401
402 /* IH data */
403 struct ras_ih_data ih_data;
404
405 struct ras_err_data err_data;
406};
407
408struct ras_badpage {
409 unsigned int bp;
410 unsigned int size;
411 unsigned int flags;
412};
413
414/* interfaces for IP */
415struct ras_fs_if {
416 struct ras_common_if head;
417 char sysfs_name[32];
418 char debugfs_name[32];
419};
420
421struct ras_query_if {
422 struct ras_common_if head;
423 unsigned long ue_count;
424 unsigned long ce_count;
425};
426
427struct ras_inject_if {
428 struct ras_common_if head;
429 uint64_t address;
430 uint64_t value;
431};
432
433struct ras_cure_if {
434 struct ras_common_if head;
435 uint64_t address;
436};
437
438struct ras_ih_if {
439 struct ras_common_if head;
440 ras_ih_cb cb;
441};
442
443struct ras_dispatch_if {
444 struct ras_common_if head;
445 struct amdgpu_iv_entry *entry;
446};
447
448struct ras_debug_if {
449 union {
450 struct ras_common_if head;
451 struct ras_inject_if inject;
452 };
453 int op;
454};
455/* work flow
456 * vbios
457 * 1: ras feature enable (enabled by default)
458 * psp
459 * 2: ras framework init (in ip_init)
460 * IP
461 * 3: IH add
462 * 4: debugfs/sysfs create
463 * 5: query/inject
464 * 6: debugfs/sysfs remove
465 * 7: IH remove
466 * 8: feature disable
467 */
468
469#define amdgpu_ras_get_context(adev) ((adev)->psp.ras.ras)
470#define amdgpu_ras_set_context(adev, ras_con) ((adev)->psp.ras.ras = (ras_con))
471
472/* check if ras is supported on block, say, sdma, gfx */
473static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev,
474 unsigned int block)
475{
476 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
477
478 if (block >= AMDGPU_RAS_BLOCK_COUNT)
479 return 0;
480 return ras && (ras->supported & (1 << block));
481}
482
483int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
484int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
485 unsigned int block);
486
487void amdgpu_ras_resume(struct amdgpu_device *adev);
488void amdgpu_ras_suspend(struct amdgpu_device *adev);
489
490unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
491 bool is_ce);
492
493/* error handling functions */
494int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
495 struct eeprom_table_record *bps, int pages);
496
497int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev);
498
499static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
500{
501 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
502
503 /* save bad page to eeprom before gpu reset,
504 * i2c may be unstable in gpu reset
505 */
506 if (in_task())
507 amdgpu_ras_reserve_bad_pages(adev);
508
509 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
510 schedule_work(&ras->recovery_work);
511 return 0;
512}
513
514static inline enum ta_ras_block
515amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
516 switch (block) {
517 case AMDGPU_RAS_BLOCK__UMC:
518 return TA_RAS_BLOCK__UMC;
519 case AMDGPU_RAS_BLOCK__SDMA:
520 return TA_RAS_BLOCK__SDMA;
521 case AMDGPU_RAS_BLOCK__GFX:
522 return TA_RAS_BLOCK__GFX;
523 case AMDGPU_RAS_BLOCK__MMHUB:
524 return TA_RAS_BLOCK__MMHUB;
525 case AMDGPU_RAS_BLOCK__ATHUB:
526 return TA_RAS_BLOCK__ATHUB;
527 case AMDGPU_RAS_BLOCK__PCIE_BIF:
528 return TA_RAS_BLOCK__PCIE_BIF;
529 case AMDGPU_RAS_BLOCK__HDP:
530 return TA_RAS_BLOCK__HDP;
531 case AMDGPU_RAS_BLOCK__XGMI_WAFL:
532 return TA_RAS_BLOCK__XGMI_WAFL;
533 case AMDGPU_RAS_BLOCK__DF:
534 return TA_RAS_BLOCK__DF;
535 case AMDGPU_RAS_BLOCK__SMN:
536 return TA_RAS_BLOCK__SMN;
537 case AMDGPU_RAS_BLOCK__SEM:
538 return TA_RAS_BLOCK__SEM;
539 case AMDGPU_RAS_BLOCK__MP0:
540 return TA_RAS_BLOCK__MP0;
541 case AMDGPU_RAS_BLOCK__MP1:
542 return TA_RAS_BLOCK__MP1;
543 case AMDGPU_RAS_BLOCK__FUSE:
544 return TA_RAS_BLOCK__FUSE;
545 default:
546 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
547 return TA_RAS_BLOCK__UMC;
548 }
549}
550
551static inline enum ta_ras_error_type
552amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
553 switch (error) {
554 case AMDGPU_RAS_ERROR__NONE:
555 return TA_RAS_ERROR__NONE;
556 case AMDGPU_RAS_ERROR__PARITY:
557 return TA_RAS_ERROR__PARITY;
558 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
559 return TA_RAS_ERROR__SINGLE_CORRECTABLE;
560 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
561 return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
562 case AMDGPU_RAS_ERROR__POISON:
563 return TA_RAS_ERROR__POISON;
564 default:
565 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
566 return TA_RAS_ERROR__NONE;
567 }
568}
569
570/* called in ip_init and ip_fini */
571int amdgpu_ras_init(struct amdgpu_device *adev);
572int amdgpu_ras_fini(struct amdgpu_device *adev);
573int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
574int amdgpu_ras_late_init(struct amdgpu_device *adev,
575 struct ras_common_if *ras_block,
576 struct ras_fs_if *fs_info,
577 struct ras_ih_if *ih_info);
578void amdgpu_ras_late_fini(struct amdgpu_device *adev,
579 struct ras_common_if *ras_block,
580 struct ras_ih_if *ih_info);
581
582int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
583 struct ras_common_if *head, bool enable);
584
585int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
586 struct ras_common_if *head, bool enable);
587
588int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
589 struct ras_fs_if *head);
590
591int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
592 struct ras_common_if *head);
593
594void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
595 struct ras_fs_if *head);
596
597void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
598
599void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev,
600 struct ras_common_if *head);
601
602int amdgpu_ras_error_query(struct amdgpu_device *adev,
603 struct ras_query_if *info);
604
605int amdgpu_ras_error_inject(struct amdgpu_device *adev,
606 struct ras_inject_if *info);
607
608int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
609 struct ras_ih_if *info);
610
611int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
612 struct ras_ih_if *info);
613
614int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
615 struct ras_dispatch_if *info);
616
617struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
618 struct ras_common_if *head);
619
620extern atomic_t amdgpu_ras_in_intr;
621
622static inline bool amdgpu_ras_intr_triggered(void)
623{
624 return !!atomic_read(&amdgpu_ras_in_intr);
625}
626
627static inline void amdgpu_ras_intr_cleared(void)
628{
629 atomic_set(&amdgpu_ras_in_intr, 0);
630}
631
632void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
633
634void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
635
636bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
637#endif
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#ifndef _AMDGPU_RAS_H
25#define _AMDGPU_RAS_H
26
27#include <linux/debugfs.h>
28#include <linux/list.h>
29#include "ta_ras_if.h"
30#include "amdgpu_ras_eeprom.h"
31
32struct amdgpu_iv_entry;
33
34#define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0)
35
36enum amdgpu_ras_block {
37 AMDGPU_RAS_BLOCK__UMC = 0,
38 AMDGPU_RAS_BLOCK__SDMA,
39 AMDGPU_RAS_BLOCK__GFX,
40 AMDGPU_RAS_BLOCK__MMHUB,
41 AMDGPU_RAS_BLOCK__ATHUB,
42 AMDGPU_RAS_BLOCK__PCIE_BIF,
43 AMDGPU_RAS_BLOCK__HDP,
44 AMDGPU_RAS_BLOCK__XGMI_WAFL,
45 AMDGPU_RAS_BLOCK__DF,
46 AMDGPU_RAS_BLOCK__SMN,
47 AMDGPU_RAS_BLOCK__SEM,
48 AMDGPU_RAS_BLOCK__MP0,
49 AMDGPU_RAS_BLOCK__MP1,
50 AMDGPU_RAS_BLOCK__FUSE,
51 AMDGPU_RAS_BLOCK__MCA,
52 AMDGPU_RAS_BLOCK__VCN,
53 AMDGPU_RAS_BLOCK__JPEG,
54
55 AMDGPU_RAS_BLOCK__LAST
56};
57
58enum amdgpu_ras_mca_block {
59 AMDGPU_RAS_MCA_BLOCK__MP0 = 0,
60 AMDGPU_RAS_MCA_BLOCK__MP1,
61 AMDGPU_RAS_MCA_BLOCK__MPIO,
62 AMDGPU_RAS_MCA_BLOCK__IOHC,
63
64 AMDGPU_RAS_MCA_BLOCK__LAST
65};
66
67#define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST
68#define AMDGPU_RAS_MCA_BLOCK_COUNT AMDGPU_RAS_MCA_BLOCK__LAST
69#define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
70
71enum amdgpu_ras_gfx_subblock {
72 /* CPC */
73 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
74 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
75 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
76 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
77 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
78 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
79 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
80 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
81 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
82 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
83 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
84 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
85 /* CPF */
86 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
87 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
88 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
89 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
90 AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
91 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
92 /* CPG */
93 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
94 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
95 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
96 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
97 AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
98 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
99 /* GDS */
100 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
101 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
102 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
103 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
104 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
105 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
106 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
107 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
108 /* SPI */
109 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
110 /* SQ */
111 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
112 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
113 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
114 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
115 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
116 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
117 /* SQC (3 ranges) */
118 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
119 /* SQC range 0 */
120 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
121 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
122 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
123 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
124 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
125 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
126 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
127 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
128 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
129 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
130 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
131 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
132 /* SQC range 1 */
133 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
134 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
135 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
136 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
137 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
138 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
139 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
140 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
141 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
142 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
143 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
144 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
145 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
146 /* SQC range 2 */
147 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
148 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
149 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
150 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
151 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
152 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
153 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
154 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
155 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
156 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
157 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
158 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
159 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
160 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
161 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
162 /* TA */
163 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
164 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
165 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
166 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
167 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
168 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
169 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
170 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
171 /* TCA */
172 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
173 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
174 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
175 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
176 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
177 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
178 /* TCC (5 sub-ranges) */
179 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
180 /* TCC range 0 */
181 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
182 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
183 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
184 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
185 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
186 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
187 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
188 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
189 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
190 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
191 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
192 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
193 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
194 /* TCC range 1 */
195 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
196 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
197 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
198 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
199 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
200 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
201 /* TCC range 2 */
202 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
203 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
204 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
205 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
206 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
207 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
208 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
209 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
210 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
211 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
212 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
213 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
214 /* TCC range 3 */
215 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
216 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
217 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
218 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
219 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
220 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
221 /* TCC range 4 */
222 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
223 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
224 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
225 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
226 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
227 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
228 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
229 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
230 /* TCI */
231 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
232 /* TCP */
233 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
234 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
235 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
236 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
237 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
238 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
239 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
240 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
241 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
242 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
243 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
244 /* TD */
245 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
246 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
247 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
248 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
249 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
250 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
251 /* EA (3 sub-ranges) */
252 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
253 /* EA range 0 */
254 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
255 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
256 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
257 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
258 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
259 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
260 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
261 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
262 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
263 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
264 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
265 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
266 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
267 /* EA range 1 */
268 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
269 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
270 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
271 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
272 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
273 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
274 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
275 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
276 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
277 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
278 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
279 /* EA range 2 */
280 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
281 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
282 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
283 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
284 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
285 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
286 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
287 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
288 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
289 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
290 /* UTC VM L2 bank */
291 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
292 /* UTC VM walker */
293 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
294 /* UTC ATC L2 2MB cache */
295 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
296 /* UTC ATC L2 4KB cache */
297 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
298 AMDGPU_RAS_BLOCK__GFX_MAX
299};
300
301enum amdgpu_ras_error_type {
302 AMDGPU_RAS_ERROR__NONE = 0,
303 AMDGPU_RAS_ERROR__PARITY = 1,
304 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2,
305 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4,
306 AMDGPU_RAS_ERROR__POISON = 8,
307};
308
309enum amdgpu_ras_ret {
310 AMDGPU_RAS_SUCCESS = 0,
311 AMDGPU_RAS_FAIL,
312 AMDGPU_RAS_UE,
313 AMDGPU_RAS_CE,
314 AMDGPU_RAS_PT,
315};
316
317struct ras_common_if {
318 enum amdgpu_ras_block block;
319 enum amdgpu_ras_error_type type;
320 uint32_t sub_block_index;
321 char name[32];
322};
323
324#define MAX_UMC_CHANNEL_NUM 32
325
326struct ecc_info_per_ch {
327 uint16_t ce_count_lo_chip;
328 uint16_t ce_count_hi_chip;
329 uint64_t mca_umc_status;
330 uint64_t mca_umc_addr;
331 uint64_t mca_ceumc_addr;
332};
333
334struct umc_ecc_info {
335 struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];
336
337 /* Determine smu ecctable whether support
338 * record correctable error address
339 */
340 int record_ce_addr_supported;
341};
342
343struct amdgpu_ras {
344 /* ras infrastructure */
345 /* for ras itself. */
346 uint32_t features;
347 struct list_head head;
348 /* sysfs */
349 struct device_attribute features_attr;
350 struct bin_attribute badpages_attr;
351 struct dentry *de_ras_eeprom_table;
352 /* block array */
353 struct ras_manager *objs;
354
355 /* gpu recovery */
356 struct work_struct recovery_work;
357 atomic_t in_recovery;
358 struct amdgpu_device *adev;
359 /* error handler data */
360 struct ras_err_handler_data *eh_data;
361 struct mutex recovery_lock;
362
363 uint32_t flags;
364 bool reboot;
365 struct amdgpu_ras_eeprom_control eeprom_control;
366
367 bool error_query_ready;
368
369 /* bad page count threshold */
370 uint32_t bad_page_cnt_threshold;
371
372 /* disable ras error count harvest in recovery */
373 bool disable_ras_err_cnt_harvest;
374
375 /* is poison mode supported */
376 bool poison_supported;
377
378 /* RAS count errors delayed work */
379 struct delayed_work ras_counte_delay_work;
380 atomic_t ras_ue_count;
381 atomic_t ras_ce_count;
382
383 /* record umc error info queried from smu */
384 struct umc_ecc_info umc_ecc;
385
386 /* Indicates smu whether need update bad channel info */
387 bool update_channel_flag;
388};
389
390struct ras_fs_data {
391 char sysfs_name[32];
392 char debugfs_name[32];
393};
394
395struct ras_err_data {
396 unsigned long ue_count;
397 unsigned long ce_count;
398 unsigned long err_addr_cnt;
399 struct eeprom_table_record *err_addr;
400};
401
402struct ras_err_handler_data {
403 /* point to bad page records array */
404 struct eeprom_table_record *bps;
405 /* the count of entries */
406 int count;
407 /* the space can place new entries */
408 int space_left;
409};
410
411typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
412 void *err_data,
413 struct amdgpu_iv_entry *entry);
414
415struct ras_ih_data {
416 /* interrupt bottom half */
417 struct work_struct ih_work;
418 int inuse;
419 /* IP callback */
420 ras_ih_cb cb;
421 /* full of entries */
422 unsigned char *ring;
423 unsigned int ring_size;
424 unsigned int element_size;
425 unsigned int aligned_element_size;
426 unsigned int rptr;
427 unsigned int wptr;
428};
429
430struct ras_manager {
431 struct ras_common_if head;
432 /* reference count */
433 int use;
434 /* ras block link */
435 struct list_head node;
436 /* the device */
437 struct amdgpu_device *adev;
438 /* sysfs */
439 struct device_attribute sysfs_attr;
440 int attr_inuse;
441
442 /* fs node name */
443 struct ras_fs_data fs_data;
444
445 /* IH data */
446 struct ras_ih_data ih_data;
447
448 struct ras_err_data err_data;
449};
450
451struct ras_badpage {
452 unsigned int bp;
453 unsigned int size;
454 unsigned int flags;
455};
456
457/* interfaces for IP */
458struct ras_fs_if {
459 struct ras_common_if head;
460 const char* sysfs_name;
461 char debugfs_name[32];
462};
463
464struct ras_query_if {
465 struct ras_common_if head;
466 unsigned long ue_count;
467 unsigned long ce_count;
468};
469
470struct ras_inject_if {
471 struct ras_common_if head;
472 uint64_t address;
473 uint64_t value;
474};
475
476struct ras_cure_if {
477 struct ras_common_if head;
478 uint64_t address;
479};
480
481struct ras_ih_if {
482 struct ras_common_if head;
483 ras_ih_cb cb;
484};
485
486struct ras_dispatch_if {
487 struct ras_common_if head;
488 struct amdgpu_iv_entry *entry;
489};
490
491struct ras_debug_if {
492 union {
493 struct ras_common_if head;
494 struct ras_inject_if inject;
495 };
496 int op;
497};
498
499struct amdgpu_ras_block_object {
500 struct ras_common_if ras_comm;
501
502 int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
503 enum amdgpu_ras_block block, uint32_t sub_block_index);
504 int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
505 void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
506 ras_ih_cb ras_cb;
507 const struct amdgpu_ras_block_hw_ops *hw_ops;
508};
509
510struct amdgpu_ras_block_hw_ops {
511 int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
512 void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status);
513 void (*query_ras_error_status)(struct amdgpu_device *adev);
514 void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status);
515 void (*reset_ras_error_count)(struct amdgpu_device *adev);
516 void (*reset_ras_error_status)(struct amdgpu_device *adev);
517 bool (*query_poison_status)(struct amdgpu_device *adev);
518 bool (*handle_poison_consumption)(struct amdgpu_device *adev);
519};
520
521/* work flow
522 * vbios
523 * 1: ras feature enable (enabled by default)
524 * psp
525 * 2: ras framework init (in ip_init)
526 * IP
527 * 3: IH add
528 * 4: debugfs/sysfs create
529 * 5: query/inject
530 * 6: debugfs/sysfs remove
531 * 7: IH remove
532 * 8: feature disable
533 */
534
535
536int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
537
538void amdgpu_ras_resume(struct amdgpu_device *adev);
539void amdgpu_ras_suspend(struct amdgpu_device *adev);
540
541int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
542 unsigned long *ce_count,
543 unsigned long *ue_count);
544
545/* error handling functions */
546int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
547 struct eeprom_table_record *bps, int pages);
548
549int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev);
550
551static inline enum ta_ras_block
552amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
553 switch (block) {
554 case AMDGPU_RAS_BLOCK__UMC:
555 return TA_RAS_BLOCK__UMC;
556 case AMDGPU_RAS_BLOCK__SDMA:
557 return TA_RAS_BLOCK__SDMA;
558 case AMDGPU_RAS_BLOCK__GFX:
559 return TA_RAS_BLOCK__GFX;
560 case AMDGPU_RAS_BLOCK__MMHUB:
561 return TA_RAS_BLOCK__MMHUB;
562 case AMDGPU_RAS_BLOCK__ATHUB:
563 return TA_RAS_BLOCK__ATHUB;
564 case AMDGPU_RAS_BLOCK__PCIE_BIF:
565 return TA_RAS_BLOCK__PCIE_BIF;
566 case AMDGPU_RAS_BLOCK__HDP:
567 return TA_RAS_BLOCK__HDP;
568 case AMDGPU_RAS_BLOCK__XGMI_WAFL:
569 return TA_RAS_BLOCK__XGMI_WAFL;
570 case AMDGPU_RAS_BLOCK__DF:
571 return TA_RAS_BLOCK__DF;
572 case AMDGPU_RAS_BLOCK__SMN:
573 return TA_RAS_BLOCK__SMN;
574 case AMDGPU_RAS_BLOCK__SEM:
575 return TA_RAS_BLOCK__SEM;
576 case AMDGPU_RAS_BLOCK__MP0:
577 return TA_RAS_BLOCK__MP0;
578 case AMDGPU_RAS_BLOCK__MP1:
579 return TA_RAS_BLOCK__MP1;
580 case AMDGPU_RAS_BLOCK__FUSE:
581 return TA_RAS_BLOCK__FUSE;
582 case AMDGPU_RAS_BLOCK__MCA:
583 return TA_RAS_BLOCK__MCA;
584 default:
585 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
586 return TA_RAS_BLOCK__UMC;
587 }
588}
589
590static inline enum ta_ras_error_type
591amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
592 switch (error) {
593 case AMDGPU_RAS_ERROR__NONE:
594 return TA_RAS_ERROR__NONE;
595 case AMDGPU_RAS_ERROR__PARITY:
596 return TA_RAS_ERROR__PARITY;
597 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
598 return TA_RAS_ERROR__SINGLE_CORRECTABLE;
599 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
600 return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
601 case AMDGPU_RAS_ERROR__POISON:
602 return TA_RAS_ERROR__POISON;
603 default:
604 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
605 return TA_RAS_ERROR__NONE;
606 }
607}
608
609/* called in ip_init and ip_fini */
610int amdgpu_ras_init(struct amdgpu_device *adev);
611int amdgpu_ras_late_init(struct amdgpu_device *adev);
612int amdgpu_ras_fini(struct amdgpu_device *adev);
613int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
614
615int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
616 struct ras_common_if *ras_block);
617
618void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
619 struct ras_common_if *ras_block);
620
621int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
622 struct ras_common_if *head, bool enable);
623
624int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
625 struct ras_common_if *head, bool enable);
626
627int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
628 struct ras_common_if *head);
629
630int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
631 struct ras_common_if *head);
632
633void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
634
635int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
636 struct ras_query_if *info);
637
638int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
639 enum amdgpu_ras_block block);
640
641int amdgpu_ras_error_inject(struct amdgpu_device *adev,
642 struct ras_inject_if *info);
643
644int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
645 struct ras_common_if *head);
646
647int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
648 struct ras_common_if *head);
649
650int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
651 struct ras_dispatch_if *info);
652
653struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
654 struct ras_common_if *head);
655
656extern atomic_t amdgpu_ras_in_intr;
657
658static inline bool amdgpu_ras_intr_triggered(void)
659{
660 return !!atomic_read(&amdgpu_ras_in_intr);
661}
662
663static inline void amdgpu_ras_intr_cleared(void)
664{
665 atomic_set(&amdgpu_ras_in_intr, 0);
666}
667
668void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
669
670void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
671
672bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
673
674void amdgpu_release_ras_context(struct amdgpu_device *adev);
675
676int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
677
678const char *get_ras_block_str(struct ras_common_if *ras_block);
679
680bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev);
681
682int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block);
683
684int amdgpu_ras_reset_gpu(struct amdgpu_device *adev);
685
686struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev);
687
688int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con);
689
690int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
691 struct amdgpu_ras_block_object *ras_block_obj);
692void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev);
693#endif