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1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24/*
25 * GPU doorbell structures, functions & helpers
26 */
27struct amdgpu_doorbell {
28 /* doorbell mmio */
29 resource_size_t base;
30 resource_size_t size;
31 u32 __iomem *ptr;
32 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
33};
34
35/* Reserved doorbells for amdgpu (including multimedia).
36 * KFD can use all the rest in the 2M doorbell bar.
37 * For asic before vega10, doorbell is 32-bit, so the
38 * index/offset is in dword. For vega10 and after, doorbell
39 * can be 64-bit, so the index defined is in qword.
40 */
41struct amdgpu_doorbell_index {
42 uint32_t kiq;
43 uint32_t mec_ring0;
44 uint32_t mec_ring1;
45 uint32_t mec_ring2;
46 uint32_t mec_ring3;
47 uint32_t mec_ring4;
48 uint32_t mec_ring5;
49 uint32_t mec_ring6;
50 uint32_t mec_ring7;
51 uint32_t userqueue_start;
52 uint32_t userqueue_end;
53 uint32_t gfx_ring0;
54 uint32_t gfx_ring1;
55 uint32_t sdma_engine[8];
56 uint32_t mes_ring;
57 uint32_t ih;
58 union {
59 struct {
60 uint32_t vcn_ring0_1;
61 uint32_t vcn_ring2_3;
62 uint32_t vcn_ring4_5;
63 uint32_t vcn_ring6_7;
64 } vcn;
65 struct {
66 uint32_t uvd_ring0_1;
67 uint32_t uvd_ring2_3;
68 uint32_t uvd_ring4_5;
69 uint32_t uvd_ring6_7;
70 uint32_t vce_ring0_1;
71 uint32_t vce_ring2_3;
72 uint32_t vce_ring4_5;
73 uint32_t vce_ring6_7;
74 } uvd_vce;
75 };
76 uint32_t first_non_cp;
77 uint32_t last_non_cp;
78 uint32_t max_assignment;
79 /* Per engine SDMA doorbell size in dword */
80 uint32_t sdma_doorbell_range;
81};
82
83typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
84{
85 AMDGPU_DOORBELL_KIQ = 0x000,
86 AMDGPU_DOORBELL_HIQ = 0x001,
87 AMDGPU_DOORBELL_DIQ = 0x002,
88 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
89 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
90 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
91 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
92 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
93 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
94 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
95 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
96 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
97 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
98 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
99 AMDGPU_DOORBELL_IH = 0x1E8,
100 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
101 AMDGPU_DOORBELL_INVALID = 0xFFFF
102} AMDGPU_DOORBELL_ASSIGNMENT;
103
104typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
105{
106 /* Compute + GFX: 0~255 */
107 AMDGPU_VEGA20_DOORBELL_KIQ = 0x000,
108 AMDGPU_VEGA20_DOORBELL_HIQ = 0x001,
109 AMDGPU_VEGA20_DOORBELL_DIQ = 0x002,
110 AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003,
111 AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004,
112 AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005,
113 AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006,
114 AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007,
115 AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008,
116 AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009,
117 AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A,
118 AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B,
119 AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A,
120 AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B,
121 /* SDMA:256~335*/
122 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100,
123 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A,
124 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114,
125 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E,
126 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128,
127 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132,
128 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C,
129 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146,
130 /* IH: 376~391 */
131 AMDGPU_VEGA20_DOORBELL_IH = 0x178,
132 /* MMSCH: 392~407
133 * overlap the doorbell assignment with VCN as they are mutually exclusive
134 * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD
135 */
136 AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */
137 AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189,
138 AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A,
139 AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B,
140
141 AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */
142 AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D,
143 AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E,
144 AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F,
145
146 AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188,
147 AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189,
148 AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A,
149 AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B,
150
151 AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C,
152 AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D,
153 AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E,
154 AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F,
155
156 AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0,
157 AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7,
158
159 AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F,
160 AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF
161} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
162
163typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT
164{
165 /* Compute + GFX: 0~255 */
166 AMDGPU_NAVI10_DOORBELL_KIQ = 0x000,
167 AMDGPU_NAVI10_DOORBELL_HIQ = 0x001,
168 AMDGPU_NAVI10_DOORBELL_DIQ = 0x002,
169 AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003,
170 AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004,
171 AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005,
172 AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006,
173 AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007,
174 AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008,
175 AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009,
176 AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A,
177 AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00B,
178 AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A,
179 AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B,
180 AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C,
181 AMDGPU_NAVI10_DOORBELL_MES_RING = 0x090,
182 /* SDMA:256~335*/
183 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100,
184 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A,
185 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 0x114,
186 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 0x11E,
187 /* IH: 376~391 */
188 AMDGPU_NAVI10_DOORBELL_IH = 0x178,
189 /* MMSCH: 392~407
190 * overlap the doorbell assignment with VCN as they are mutually exclusive
191 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
192 */
193 AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
194 AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189,
195 AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A,
196 AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B,
197
198 AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 0x18C,
199 AMDGPU_NAVI10_DOORBELL64_VCNa_b = 0x18D,
200 AMDGPU_NAVI10_DOORBELL64_VCNc_d = 0x18E,
201 AMDGPU_NAVI10_DOORBELL64_VCNe_f = 0x18F,
202
203 AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0,
204 AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VCNe_f,
205
206 AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 0x18F,
207 AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF
208} AMDGPU_NAVI10_DOORBELL_ASSIGNMENT;
209
210/*
211 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
212 */
213typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
214{
215 /*
216 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
217 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
218 * Compute related doorbells are allocated from 0x00 to 0x8a
219 */
220
221
222 /* kernel scheduling */
223 AMDGPU_DOORBELL64_KIQ = 0x00,
224
225 /* HSA interface queue and debug queue */
226 AMDGPU_DOORBELL64_HIQ = 0x01,
227 AMDGPU_DOORBELL64_DIQ = 0x02,
228
229 /* Compute engines */
230 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
231 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
232 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
233 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
234 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
235 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
236 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
237 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
238
239 /* User queue doorbell range (128 doorbells) */
240 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
241 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
242
243 /* Graphics engine */
244 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
245
246 /*
247 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf
248 * Graphics voltage island aperture 1
249 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive
250 */
251
252 /* For vega10 sriov, the sdma doorbell must be fixed as follow
253 * to keep the same setting with host driver, or it will
254 * happen conflicts
255 */
256 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
257 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
258 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
259 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
260
261 /* Interrupt handler */
262 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
263 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
264 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
265
266 /* VCN engine use 32 bits doorbell */
267 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
268 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
269 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
270 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
271
272 /* overlap the doorbell assignment with VCN as they are mutually exclusive
273 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
274 */
275 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
276 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
277 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
278 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
279
280 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
281 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
282 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
283 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
284
285 AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0,
286 AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7,
287
288 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
289 AMDGPU_DOORBELL64_INVALID = 0xFFFF
290} AMDGPU_DOORBELL64_ASSIGNMENT;
291
292u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
293void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
294u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
295void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
296
297#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
298#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
299#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
300#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
301
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24/*
25 * GPU doorbell structures, functions & helpers
26 */
27struct amdgpu_doorbell {
28 /* doorbell mmio */
29 resource_size_t base;
30 resource_size_t size;
31 u32 __iomem *ptr;
32 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
33};
34
35/* Reserved doorbells for amdgpu (including multimedia).
36 * KFD can use all the rest in the 2M doorbell bar.
37 * For asic before vega10, doorbell is 32-bit, so the
38 * index/offset is in dword. For vega10 and after, doorbell
39 * can be 64-bit, so the index defined is in qword.
40 */
41struct amdgpu_doorbell_index {
42 uint32_t kiq;
43 uint32_t mec_ring0;
44 uint32_t mec_ring1;
45 uint32_t mec_ring2;
46 uint32_t mec_ring3;
47 uint32_t mec_ring4;
48 uint32_t mec_ring5;
49 uint32_t mec_ring6;
50 uint32_t mec_ring7;
51 uint32_t userqueue_start;
52 uint32_t userqueue_end;
53 uint32_t gfx_ring0;
54 uint32_t gfx_ring1;
55 uint32_t gfx_userqueue_start;
56 uint32_t gfx_userqueue_end;
57 uint32_t sdma_engine[8];
58 uint32_t mes_ring0;
59 uint32_t mes_ring1;
60 uint32_t ih;
61 union {
62 struct {
63 uint32_t vcn_ring0_1;
64 uint32_t vcn_ring2_3;
65 uint32_t vcn_ring4_5;
66 uint32_t vcn_ring6_7;
67 } vcn;
68 struct {
69 uint32_t uvd_ring0_1;
70 uint32_t uvd_ring2_3;
71 uint32_t uvd_ring4_5;
72 uint32_t uvd_ring6_7;
73 uint32_t vce_ring0_1;
74 uint32_t vce_ring2_3;
75 uint32_t vce_ring4_5;
76 uint32_t vce_ring6_7;
77 } uvd_vce;
78 };
79 uint32_t first_non_cp;
80 uint32_t last_non_cp;
81 uint32_t max_assignment;
82 /* Per engine SDMA doorbell size in dword */
83 uint32_t sdma_doorbell_range;
84};
85
86typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
87{
88 AMDGPU_DOORBELL_KIQ = 0x000,
89 AMDGPU_DOORBELL_HIQ = 0x001,
90 AMDGPU_DOORBELL_DIQ = 0x002,
91 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
92 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
93 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
94 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
95 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
96 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
97 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
98 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
99 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
100 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
101 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
102 AMDGPU_DOORBELL_IH = 0x1E8,
103 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
104 AMDGPU_DOORBELL_INVALID = 0xFFFF
105} AMDGPU_DOORBELL_ASSIGNMENT;
106
107typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT
108{
109 /* Compute + GFX: 0~255 */
110 AMDGPU_VEGA20_DOORBELL_KIQ = 0x000,
111 AMDGPU_VEGA20_DOORBELL_HIQ = 0x001,
112 AMDGPU_VEGA20_DOORBELL_DIQ = 0x002,
113 AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003,
114 AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004,
115 AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005,
116 AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006,
117 AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007,
118 AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008,
119 AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009,
120 AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A,
121 AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B,
122 AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A,
123 AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B,
124 /* SDMA:256~335*/
125 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100,
126 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A,
127 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114,
128 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E,
129 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128,
130 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132,
131 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C,
132 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146,
133 /* IH: 376~391 */
134 AMDGPU_VEGA20_DOORBELL_IH = 0x178,
135 /* MMSCH: 392~407
136 * overlap the doorbell assignment with VCN as they are mutually exclusive
137 * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD
138 */
139 AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */
140 AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189,
141 AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A,
142 AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B,
143
144 AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */
145 AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D,
146 AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E,
147 AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F,
148
149 AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188,
150 AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189,
151 AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A,
152 AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B,
153
154 AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C,
155 AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D,
156 AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E,
157 AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F,
158
159 AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0,
160 AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7,
161
162 AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F,
163 AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF
164} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
165
166typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT
167{
168 /* Compute + GFX: 0~255 */
169 AMDGPU_NAVI10_DOORBELL_KIQ = 0x000,
170 AMDGPU_NAVI10_DOORBELL_HIQ = 0x001,
171 AMDGPU_NAVI10_DOORBELL_DIQ = 0x002,
172 AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003,
173 AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004,
174 AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005,
175 AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006,
176 AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007,
177 AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008,
178 AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009,
179 AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A,
180 AMDGPU_NAVI10_DOORBELL_MES_RING0 = 0x00B,
181 AMDGPU_NAVI10_DOORBELL_MES_RING1 = 0x00C,
182 AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00D,
183 AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A,
184 AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B,
185 AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C,
186 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START = 0x08D,
187 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END = 0x0FF,
188
189 /* SDMA:256~335*/
190 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100,
191 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A,
192 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2 = 0x114,
193 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3 = 0x11E,
194 /* IH: 376~391 */
195 AMDGPU_NAVI10_DOORBELL_IH = 0x178,
196 /* MMSCH: 392~407
197 * overlap the doorbell assignment with VCN as they are mutually exclusive
198 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
199 */
200 AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
201 AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189,
202 AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A,
203 AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B,
204
205 AMDGPU_NAVI10_DOORBELL64_VCN8_9 = 0x18C,
206 AMDGPU_NAVI10_DOORBELL64_VCNa_b = 0x18D,
207 AMDGPU_NAVI10_DOORBELL64_VCNc_d = 0x18E,
208 AMDGPU_NAVI10_DOORBELL64_VCNe_f = 0x18F,
209
210 AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0,
211 AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VCNe_f,
212
213 AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 0x18F,
214 AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF
215} AMDGPU_NAVI10_DOORBELL_ASSIGNMENT;
216
217/*
218 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
219 */
220typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
221{
222 /*
223 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
224 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
225 * Compute related doorbells are allocated from 0x00 to 0x8a
226 */
227
228
229 /* kernel scheduling */
230 AMDGPU_DOORBELL64_KIQ = 0x00,
231
232 /* HSA interface queue and debug queue */
233 AMDGPU_DOORBELL64_HIQ = 0x01,
234 AMDGPU_DOORBELL64_DIQ = 0x02,
235
236 /* Compute engines */
237 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
238 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
239 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
240 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
241 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
242 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
243 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
244 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
245
246 /* User queue doorbell range (128 doorbells) */
247 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
248 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
249
250 /* Graphics engine */
251 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
252
253 /*
254 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf
255 * Graphics voltage island aperture 1
256 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive
257 */
258
259 /* For vega10 sriov, the sdma doorbell must be fixed as follow
260 * to keep the same setting with host driver, or it will
261 * happen conflicts
262 */
263 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
264 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
265 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
266 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
267
268 /* Interrupt handler */
269 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
270 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
271 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
272
273 /* VCN engine use 32 bits doorbell */
274 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
275 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
276 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
277 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
278
279 /* overlap the doorbell assignment with VCN as they are mutually exclusive
280 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
281 */
282 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
283 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
284 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
285 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
286
287 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
288 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
289 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
290 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
291
292 AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0,
293 AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7,
294
295 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
296 AMDGPU_DOORBELL64_INVALID = 0xFFFF
297} AMDGPU_DOORBELL64_ASSIGNMENT;
298
299u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
300void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
301u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
302void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
303
304#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
305#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
306#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
307#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
308