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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Xilinx gpio driver for xps/axi_gpio IP.
4 *
5 * Copyright 2008 - 2013 Xilinx, Inc.
6 */
7
8#include <linux/bitops.h>
9#include <linux/init.h>
10#include <linux/errno.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/of_platform.h>
14#include <linux/io.h>
15#include <linux/gpio/driver.h>
16#include <linux/slab.h>
17
18/* Register Offset Definitions */
19#define XGPIO_DATA_OFFSET (0x0) /* Data register */
20#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
21
22#define XGPIO_CHANNEL_OFFSET 0x8
23
24/* Read/Write access to the GPIO registers */
25#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
26# define xgpio_readreg(offset) readl(offset)
27# define xgpio_writereg(offset, val) writel(val, offset)
28#else
29# define xgpio_readreg(offset) __raw_readl(offset)
30# define xgpio_writereg(offset, val) __raw_writel(val, offset)
31#endif
32
33/**
34 * struct xgpio_instance - Stores information about GPIO device
35 * @gc: GPIO chip
36 * @regs: register block
37 * @gpio_width: GPIO width for every channel
38 * @gpio_state: GPIO state shadow register
39 * @gpio_dir: GPIO direction shadow register
40 * @gpio_lock: Lock used for synchronization
41 */
42struct xgpio_instance {
43 struct gpio_chip gc;
44 void __iomem *regs;
45 unsigned int gpio_width[2];
46 u32 gpio_state[2];
47 u32 gpio_dir[2];
48 spinlock_t gpio_lock[2];
49};
50
51static inline int xgpio_index(struct xgpio_instance *chip, int gpio)
52{
53 if (gpio >= chip->gpio_width[0])
54 return 1;
55
56 return 0;
57}
58
59static inline int xgpio_regoffset(struct xgpio_instance *chip, int gpio)
60{
61 if (xgpio_index(chip, gpio))
62 return XGPIO_CHANNEL_OFFSET;
63
64 return 0;
65}
66
67static inline int xgpio_offset(struct xgpio_instance *chip, int gpio)
68{
69 if (xgpio_index(chip, gpio))
70 return gpio - chip->gpio_width[0];
71
72 return gpio;
73}
74
75/**
76 * xgpio_get - Read the specified signal of the GPIO device.
77 * @gc: Pointer to gpio_chip device structure.
78 * @gpio: GPIO signal number.
79 *
80 * This function reads the specified signal of the GPIO device.
81 *
82 * Return:
83 * 0 if direction of GPIO signals is set as input otherwise it
84 * returns negative error value.
85 */
86static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
87{
88 struct xgpio_instance *chip = gpiochip_get_data(gc);
89 u32 val;
90
91 val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET +
92 xgpio_regoffset(chip, gpio));
93
94 return !!(val & BIT(xgpio_offset(chip, gpio)));
95}
96
97/**
98 * xgpio_set - Write the specified signal of the GPIO device.
99 * @gc: Pointer to gpio_chip device structure.
100 * @gpio: GPIO signal number.
101 * @val: Value to be written to specified signal.
102 *
103 * This function writes the specified value in to the specified signal of the
104 * GPIO device.
105 */
106static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
107{
108 unsigned long flags;
109 struct xgpio_instance *chip = gpiochip_get_data(gc);
110 int index = xgpio_index(chip, gpio);
111 int offset = xgpio_offset(chip, gpio);
112
113 spin_lock_irqsave(&chip->gpio_lock[index], flags);
114
115 /* Write to GPIO signal and set its direction to output */
116 if (val)
117 chip->gpio_state[index] |= BIT(offset);
118 else
119 chip->gpio_state[index] &= ~BIT(offset);
120
121 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
122 xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
123
124 spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
125}
126
127/**
128 * xgpio_set_multiple - Write the specified signals of the GPIO device.
129 * @gc: Pointer to gpio_chip device structure.
130 * @mask: Mask of the GPIOS to modify.
131 * @bits: Value to be wrote on each GPIO
132 *
133 * This function writes the specified values into the specified signals of the
134 * GPIO devices.
135 */
136static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
137 unsigned long *bits)
138{
139 unsigned long flags;
140 struct xgpio_instance *chip = gpiochip_get_data(gc);
141 int index = xgpio_index(chip, 0);
142 int offset, i;
143
144 spin_lock_irqsave(&chip->gpio_lock[index], flags);
145
146 /* Write to GPIO signals */
147 for (i = 0; i < gc->ngpio; i++) {
148 if (*mask == 0)
149 break;
150 /* Once finished with an index write it out to the register */
151 if (index != xgpio_index(chip, i)) {
152 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
153 index * XGPIO_CHANNEL_OFFSET,
154 chip->gpio_state[index]);
155 spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
156 index = xgpio_index(chip, i);
157 spin_lock_irqsave(&chip->gpio_lock[index], flags);
158 }
159 if (__test_and_clear_bit(i, mask)) {
160 offset = xgpio_offset(chip, i);
161 if (test_bit(i, bits))
162 chip->gpio_state[index] |= BIT(offset);
163 else
164 chip->gpio_state[index] &= ~BIT(offset);
165 }
166 }
167
168 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
169 index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]);
170
171 spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
172}
173
174/**
175 * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
176 * @gc: Pointer to gpio_chip device structure.
177 * @gpio: GPIO signal number.
178 *
179 * Return:
180 * 0 - if direction of GPIO signals is set as input
181 * otherwise it returns negative error value.
182 */
183static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
184{
185 unsigned long flags;
186 struct xgpio_instance *chip = gpiochip_get_data(gc);
187 int index = xgpio_index(chip, gpio);
188 int offset = xgpio_offset(chip, gpio);
189
190 spin_lock_irqsave(&chip->gpio_lock[index], flags);
191
192 /* Set the GPIO bit in shadow register and set direction as input */
193 chip->gpio_dir[index] |= BIT(offset);
194 xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
195 xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
196
197 spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
198
199 return 0;
200}
201
202/**
203 * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
204 * @gc: Pointer to gpio_chip device structure.
205 * @gpio: GPIO signal number.
206 * @val: Value to be written to specified signal.
207 *
208 * This function sets the direction of specified GPIO signal as output.
209 *
210 * Return:
211 * If all GPIO signals of GPIO chip is configured as input then it returns
212 * error otherwise it returns 0.
213 */
214static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
215{
216 unsigned long flags;
217 struct xgpio_instance *chip = gpiochip_get_data(gc);
218 int index = xgpio_index(chip, gpio);
219 int offset = xgpio_offset(chip, gpio);
220
221 spin_lock_irqsave(&chip->gpio_lock[index], flags);
222
223 /* Write state of GPIO signal */
224 if (val)
225 chip->gpio_state[index] |= BIT(offset);
226 else
227 chip->gpio_state[index] &= ~BIT(offset);
228 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
229 xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
230
231 /* Clear the GPIO bit in shadow register and set direction as output */
232 chip->gpio_dir[index] &= ~BIT(offset);
233 xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
234 xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
235
236 spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
237
238 return 0;
239}
240
241/**
242 * xgpio_save_regs - Set initial values of GPIO pins
243 * @chip: Pointer to GPIO instance
244 */
245static void xgpio_save_regs(struct xgpio_instance *chip)
246{
247 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET, chip->gpio_state[0]);
248 xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]);
249
250 if (!chip->gpio_width[1])
251 return;
252
253 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET,
254 chip->gpio_state[1]);
255 xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET,
256 chip->gpio_dir[1]);
257}
258
259/**
260 * xgpio_of_probe - Probe method for the GPIO device.
261 * @pdev: pointer to the platform device
262 *
263 * Return:
264 * It returns 0, if the driver is bound to the GPIO device, or
265 * a negative value if there is an error.
266 */
267static int xgpio_probe(struct platform_device *pdev)
268{
269 struct xgpio_instance *chip;
270 int status = 0;
271 struct device_node *np = pdev->dev.of_node;
272 u32 is_dual;
273
274 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
275 if (!chip)
276 return -ENOMEM;
277
278 platform_set_drvdata(pdev, chip);
279
280 /* Update GPIO state shadow register with default value */
281 of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0]);
282
283 /* Update GPIO direction shadow register with default value */
284 if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0]))
285 chip->gpio_dir[0] = 0xFFFFFFFF;
286
287 /*
288 * Check device node and parent device node for device width
289 * and assume default width of 32
290 */
291 if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0]))
292 chip->gpio_width[0] = 32;
293
294 spin_lock_init(&chip->gpio_lock[0]);
295
296 if (of_property_read_u32(np, "xlnx,is-dual", &is_dual))
297 is_dual = 0;
298
299 if (is_dual) {
300 /* Update GPIO state shadow register with default value */
301 of_property_read_u32(np, "xlnx,dout-default-2",
302 &chip->gpio_state[1]);
303
304 /* Update GPIO direction shadow register with default value */
305 if (of_property_read_u32(np, "xlnx,tri-default-2",
306 &chip->gpio_dir[1]))
307 chip->gpio_dir[1] = 0xFFFFFFFF;
308
309 /*
310 * Check device node and parent device node for device width
311 * and assume default width of 32
312 */
313 if (of_property_read_u32(np, "xlnx,gpio2-width",
314 &chip->gpio_width[1]))
315 chip->gpio_width[1] = 32;
316
317 spin_lock_init(&chip->gpio_lock[1]);
318 }
319
320 chip->gc.base = -1;
321 chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1];
322 chip->gc.parent = &pdev->dev;
323 chip->gc.direction_input = xgpio_dir_in;
324 chip->gc.direction_output = xgpio_dir_out;
325 chip->gc.get = xgpio_get;
326 chip->gc.set = xgpio_set;
327 chip->gc.set_multiple = xgpio_set_multiple;
328
329 chip->gc.label = dev_name(&pdev->dev);
330
331 chip->regs = devm_platform_ioremap_resource(pdev, 0);
332 if (IS_ERR(chip->regs)) {
333 dev_err(&pdev->dev, "failed to ioremap memory resource\n");
334 return PTR_ERR(chip->regs);
335 }
336
337 xgpio_save_regs(chip);
338
339 status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
340 if (status) {
341 dev_err(&pdev->dev, "failed to add GPIO chip\n");
342 return status;
343 }
344
345 return 0;
346}
347
348static const struct of_device_id xgpio_of_match[] = {
349 { .compatible = "xlnx,xps-gpio-1.00.a", },
350 { /* end of list */ },
351};
352
353MODULE_DEVICE_TABLE(of, xgpio_of_match);
354
355static struct platform_driver xgpio_plat_driver = {
356 .probe = xgpio_probe,
357 .driver = {
358 .name = "gpio-xilinx",
359 .of_match_table = xgpio_of_match,
360 },
361};
362
363static int __init xgpio_init(void)
364{
365 return platform_driver_register(&xgpio_plat_driver);
366}
367
368subsys_initcall(xgpio_init);
369
370static void __exit xgpio_exit(void)
371{
372 platform_driver_unregister(&xgpio_plat_driver);
373}
374module_exit(xgpio_exit);
375
376MODULE_AUTHOR("Xilinx, Inc.");
377MODULE_DESCRIPTION("Xilinx GPIO driver");
378MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Xilinx gpio driver for xps/axi_gpio IP.
4 *
5 * Copyright 2008 - 2013 Xilinx, Inc.
6 */
7
8#include <linux/bitmap.h>
9#include <linux/bitops.h>
10#include <linux/clk.h>
11#include <linux/errno.h>
12#include <linux/gpio/driver.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/module.h>
18#include <linux/of_device.h>
19#include <linux/of_platform.h>
20#include <linux/pm_runtime.h>
21#include <linux/slab.h>
22
23/* Register Offset Definitions */
24#define XGPIO_DATA_OFFSET (0x0) /* Data register */
25#define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
26
27#define XGPIO_CHANNEL0_OFFSET 0x0
28#define XGPIO_CHANNEL1_OFFSET 0x8
29
30#define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */
31#define XGPIO_GIER_IE BIT(31)
32#define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */
33#define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */
34
35/* Read/Write access to the GPIO registers */
36#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
37# define xgpio_readreg(offset) readl(offset)
38# define xgpio_writereg(offset, val) writel(val, offset)
39#else
40# define xgpio_readreg(offset) __raw_readl(offset)
41# define xgpio_writereg(offset, val) __raw_writel(val, offset)
42#endif
43
44/**
45 * struct xgpio_instance - Stores information about GPIO device
46 * @gc: GPIO chip
47 * @regs: register block
48 * @hw_map: GPIO pin mapping on hardware side
49 * @sw_map: GPIO pin mapping on software side
50 * @state: GPIO write state shadow register
51 * @last_irq_read: GPIO read state register from last interrupt
52 * @dir: GPIO direction shadow register
53 * @gpio_lock: Lock used for synchronization
54 * @irq: IRQ used by GPIO device
55 * @irqchip: IRQ chip
56 * @enable: GPIO IRQ enable/disable bitfield
57 * @rising_edge: GPIO IRQ rising edge enable/disable bitfield
58 * @falling_edge: GPIO IRQ falling edge enable/disable bitfield
59 * @clk: clock resource for this driver
60 */
61struct xgpio_instance {
62 struct gpio_chip gc;
63 void __iomem *regs;
64 DECLARE_BITMAP(hw_map, 64);
65 DECLARE_BITMAP(sw_map, 64);
66 DECLARE_BITMAP(state, 64);
67 DECLARE_BITMAP(last_irq_read, 64);
68 DECLARE_BITMAP(dir, 64);
69 spinlock_t gpio_lock; /* For serializing operations */
70 int irq;
71 struct irq_chip irqchip;
72 DECLARE_BITMAP(enable, 64);
73 DECLARE_BITMAP(rising_edge, 64);
74 DECLARE_BITMAP(falling_edge, 64);
75 struct clk *clk;
76};
77
78static inline int xgpio_from_bit(struct xgpio_instance *chip, int bit)
79{
80 return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64);
81}
82
83static inline int xgpio_to_bit(struct xgpio_instance *chip, int gpio)
84{
85 return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64);
86}
87
88static inline u32 xgpio_get_value32(const unsigned long *map, int bit)
89{
90 const size_t index = BIT_WORD(bit);
91 const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
92
93 return (map[index] >> offset) & 0xFFFFFFFFul;
94}
95
96static inline void xgpio_set_value32(unsigned long *map, int bit, u32 v)
97{
98 const size_t index = BIT_WORD(bit);
99 const unsigned long offset = (bit % BITS_PER_LONG) & BIT(5);
100
101 map[index] &= ~(0xFFFFFFFFul << offset);
102 map[index] |= (unsigned long)v << offset;
103}
104
105static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch)
106{
107 switch (ch) {
108 case 0:
109 return XGPIO_CHANNEL0_OFFSET;
110 case 1:
111 return XGPIO_CHANNEL1_OFFSET;
112 default:
113 return -EINVAL;
114 }
115}
116
117static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
118{
119 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
120
121 xgpio_set_value32(a, bit, xgpio_readreg(addr));
122}
123
124static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
125{
126 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
127
128 xgpio_writereg(addr, xgpio_get_value32(a, bit));
129}
130
131static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
132{
133 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
134
135 for (bit = 0; bit <= lastbit ; bit += 32)
136 xgpio_read_ch(chip, reg, bit, a);
137}
138
139static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
140{
141 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1);
142
143 for (bit = 0; bit <= lastbit ; bit += 32)
144 xgpio_write_ch(chip, reg, bit, a);
145}
146
147/**
148 * xgpio_get - Read the specified signal of the GPIO device.
149 * @gc: Pointer to gpio_chip device structure.
150 * @gpio: GPIO signal number.
151 *
152 * This function reads the specified signal of the GPIO device.
153 *
154 * Return:
155 * 0 if direction of GPIO signals is set as input otherwise it
156 * returns negative error value.
157 */
158static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
159{
160 struct xgpio_instance *chip = gpiochip_get_data(gc);
161 int bit = xgpio_to_bit(chip, gpio);
162 DECLARE_BITMAP(state, 64);
163
164 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state);
165
166 return test_bit(bit, state);
167}
168
169/**
170 * xgpio_set - Write the specified signal of the GPIO device.
171 * @gc: Pointer to gpio_chip device structure.
172 * @gpio: GPIO signal number.
173 * @val: Value to be written to specified signal.
174 *
175 * This function writes the specified value in to the specified signal of the
176 * GPIO device.
177 */
178static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
179{
180 unsigned long flags;
181 struct xgpio_instance *chip = gpiochip_get_data(gc);
182 int bit = xgpio_to_bit(chip, gpio);
183
184 spin_lock_irqsave(&chip->gpio_lock, flags);
185
186 /* Write to GPIO signal and set its direction to output */
187 __assign_bit(bit, chip->state, val);
188
189 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
190
191 spin_unlock_irqrestore(&chip->gpio_lock, flags);
192}
193
194/**
195 * xgpio_set_multiple - Write the specified signals of the GPIO device.
196 * @gc: Pointer to gpio_chip device structure.
197 * @mask: Mask of the GPIOS to modify.
198 * @bits: Value to be wrote on each GPIO
199 *
200 * This function writes the specified values into the specified signals of the
201 * GPIO devices.
202 */
203static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
204 unsigned long *bits)
205{
206 DECLARE_BITMAP(hw_mask, 64);
207 DECLARE_BITMAP(hw_bits, 64);
208 DECLARE_BITMAP(state, 64);
209 unsigned long flags;
210 struct xgpio_instance *chip = gpiochip_get_data(gc);
211
212 bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64);
213 bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64);
214
215 spin_lock_irqsave(&chip->gpio_lock, flags);
216
217 bitmap_replace(state, chip->state, hw_bits, hw_mask, 64);
218
219 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state);
220
221 bitmap_copy(chip->state, state, 64);
222
223 spin_unlock_irqrestore(&chip->gpio_lock, flags);
224}
225
226/**
227 * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
228 * @gc: Pointer to gpio_chip device structure.
229 * @gpio: GPIO signal number.
230 *
231 * Return:
232 * 0 - if direction of GPIO signals is set as input
233 * otherwise it returns negative error value.
234 */
235static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
236{
237 unsigned long flags;
238 struct xgpio_instance *chip = gpiochip_get_data(gc);
239 int bit = xgpio_to_bit(chip, gpio);
240
241 spin_lock_irqsave(&chip->gpio_lock, flags);
242
243 /* Set the GPIO bit in shadow register and set direction as input */
244 __set_bit(bit, chip->dir);
245 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
246
247 spin_unlock_irqrestore(&chip->gpio_lock, flags);
248
249 return 0;
250}
251
252/**
253 * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
254 * @gc: Pointer to gpio_chip device structure.
255 * @gpio: GPIO signal number.
256 * @val: Value to be written to specified signal.
257 *
258 * This function sets the direction of specified GPIO signal as output.
259 *
260 * Return:
261 * If all GPIO signals of GPIO chip is configured as input then it returns
262 * error otherwise it returns 0.
263 */
264static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
265{
266 unsigned long flags;
267 struct xgpio_instance *chip = gpiochip_get_data(gc);
268 int bit = xgpio_to_bit(chip, gpio);
269
270 spin_lock_irqsave(&chip->gpio_lock, flags);
271
272 /* Write state of GPIO signal */
273 __assign_bit(bit, chip->state, val);
274 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
275
276 /* Clear the GPIO bit in shadow register and set direction as output */
277 __clear_bit(bit, chip->dir);
278 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
279
280 spin_unlock_irqrestore(&chip->gpio_lock, flags);
281
282 return 0;
283}
284
285/**
286 * xgpio_save_regs - Set initial values of GPIO pins
287 * @chip: Pointer to GPIO instance
288 */
289static void xgpio_save_regs(struct xgpio_instance *chip)
290{
291 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state);
292 xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir);
293}
294
295static int xgpio_request(struct gpio_chip *chip, unsigned int offset)
296{
297 int ret;
298
299 ret = pm_runtime_get_sync(chip->parent);
300 /*
301 * If the device is already active pm_runtime_get() will return 1 on
302 * success, but gpio_request still needs to return 0.
303 */
304 return ret < 0 ? ret : 0;
305}
306
307static void xgpio_free(struct gpio_chip *chip, unsigned int offset)
308{
309 pm_runtime_put(chip->parent);
310}
311
312static int __maybe_unused xgpio_suspend(struct device *dev)
313{
314 struct xgpio_instance *gpio = dev_get_drvdata(dev);
315 struct irq_data *data = irq_get_irq_data(gpio->irq);
316
317 if (!data) {
318 dev_dbg(dev, "IRQ not connected\n");
319 return pm_runtime_force_suspend(dev);
320 }
321
322 if (!irqd_is_wakeup_set(data))
323 return pm_runtime_force_suspend(dev);
324
325 return 0;
326}
327
328/**
329 * xgpio_remove - Remove method for the GPIO device.
330 * @pdev: pointer to the platform device
331 *
332 * This function remove gpiochips and frees all the allocated resources.
333 *
334 * Return: 0 always
335 */
336static int xgpio_remove(struct platform_device *pdev)
337{
338 struct xgpio_instance *gpio = platform_get_drvdata(pdev);
339
340 pm_runtime_get_sync(&pdev->dev);
341 pm_runtime_put_noidle(&pdev->dev);
342 pm_runtime_disable(&pdev->dev);
343 clk_disable_unprepare(gpio->clk);
344
345 return 0;
346}
347
348/**
349 * xgpio_irq_ack - Acknowledge a child GPIO interrupt.
350 * @irq_data: per IRQ and chip data passed down to chip functions
351 * This currently does nothing, but irq_ack is unconditionally called by
352 * handle_edge_irq and therefore must be defined.
353 */
354static void xgpio_irq_ack(struct irq_data *irq_data)
355{
356}
357
358static int __maybe_unused xgpio_resume(struct device *dev)
359{
360 struct xgpio_instance *gpio = dev_get_drvdata(dev);
361 struct irq_data *data = irq_get_irq_data(gpio->irq);
362
363 if (!data) {
364 dev_dbg(dev, "IRQ not connected\n");
365 return pm_runtime_force_resume(dev);
366 }
367
368 if (!irqd_is_wakeup_set(data))
369 return pm_runtime_force_resume(dev);
370
371 return 0;
372}
373
374static int __maybe_unused xgpio_runtime_suspend(struct device *dev)
375{
376 struct xgpio_instance *gpio = dev_get_drvdata(dev);
377
378 clk_disable(gpio->clk);
379
380 return 0;
381}
382
383static int __maybe_unused xgpio_runtime_resume(struct device *dev)
384{
385 struct xgpio_instance *gpio = dev_get_drvdata(dev);
386
387 return clk_enable(gpio->clk);
388}
389
390static const struct dev_pm_ops xgpio_dev_pm_ops = {
391 SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume)
392 SET_RUNTIME_PM_OPS(xgpio_runtime_suspend,
393 xgpio_runtime_resume, NULL)
394};
395
396/**
397 * xgpio_irq_mask - Write the specified signal of the GPIO device.
398 * @irq_data: per IRQ and chip data passed down to chip functions
399 */
400static void xgpio_irq_mask(struct irq_data *irq_data)
401{
402 unsigned long flags;
403 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
404 int irq_offset = irqd_to_hwirq(irq_data);
405 int bit = xgpio_to_bit(chip, irq_offset);
406 u32 mask = BIT(bit / 32), temp;
407
408 spin_lock_irqsave(&chip->gpio_lock, flags);
409
410 __clear_bit(bit, chip->enable);
411
412 if (xgpio_get_value32(chip->enable, bit) == 0) {
413 /* Disable per channel interrupt */
414 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
415 temp &= ~mask;
416 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);
417 }
418 spin_unlock_irqrestore(&chip->gpio_lock, flags);
419}
420
421/**
422 * xgpio_irq_unmask - Write the specified signal of the GPIO device.
423 * @irq_data: per IRQ and chip data passed down to chip functions
424 */
425static void xgpio_irq_unmask(struct irq_data *irq_data)
426{
427 unsigned long flags;
428 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
429 int irq_offset = irqd_to_hwirq(irq_data);
430 int bit = xgpio_to_bit(chip, irq_offset);
431 u32 old_enable = xgpio_get_value32(chip->enable, bit);
432 u32 mask = BIT(bit / 32), val;
433
434 spin_lock_irqsave(&chip->gpio_lock, flags);
435
436 __set_bit(bit, chip->enable);
437
438 if (old_enable == 0) {
439 /* Clear any existing per-channel interrupts */
440 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
441 val &= mask;
442 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);
443
444 /* Update GPIO IRQ read data before enabling interrupt*/
445 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read);
446
447 /* Enable per channel interrupt */
448 val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
449 val |= mask;
450 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);
451 }
452
453 spin_unlock_irqrestore(&chip->gpio_lock, flags);
454}
455
456/**
457 * xgpio_set_irq_type - Write the specified signal of the GPIO device.
458 * @irq_data: Per IRQ and chip data passed down to chip functions
459 * @type: Interrupt type that is to be set for the gpio pin
460 *
461 * Return:
462 * 0 if interrupt type is supported otherwise -EINVAL
463 */
464static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
465{
466 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
467 int irq_offset = irqd_to_hwirq(irq_data);
468 int bit = xgpio_to_bit(chip, irq_offset);
469
470 /*
471 * The Xilinx GPIO hardware provides a single interrupt status
472 * indication for any state change in a given GPIO channel (bank).
473 * Therefore, only rising edge or falling edge triggers are
474 * supported.
475 */
476 switch (type & IRQ_TYPE_SENSE_MASK) {
477 case IRQ_TYPE_EDGE_BOTH:
478 __set_bit(bit, chip->rising_edge);
479 __set_bit(bit, chip->falling_edge);
480 break;
481 case IRQ_TYPE_EDGE_RISING:
482 __set_bit(bit, chip->rising_edge);
483 __clear_bit(bit, chip->falling_edge);
484 break;
485 case IRQ_TYPE_EDGE_FALLING:
486 __clear_bit(bit, chip->rising_edge);
487 __set_bit(bit, chip->falling_edge);
488 break;
489 default:
490 return -EINVAL;
491 }
492
493 irq_set_handler_locked(irq_data, handle_edge_irq);
494 return 0;
495}
496
497/**
498 * xgpio_irqhandler - Gpio interrupt service routine
499 * @desc: Pointer to interrupt description
500 */
501static void xgpio_irqhandler(struct irq_desc *desc)
502{
503 struct xgpio_instance *chip = irq_desc_get_handler_data(desc);
504 struct gpio_chip *gc = &chip->gc;
505 struct irq_chip *irqchip = irq_desc_get_chip(desc);
506 DECLARE_BITMAP(rising, 64);
507 DECLARE_BITMAP(falling, 64);
508 DECLARE_BITMAP(all, 64);
509 int irq_offset;
510 u32 status;
511 u32 bit;
512
513 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
514 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);
515
516 chained_irq_enter(irqchip, desc);
517
518 spin_lock(&chip->gpio_lock);
519
520 xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, all);
521
522 bitmap_complement(rising, chip->last_irq_read, 64);
523 bitmap_and(rising, rising, all, 64);
524 bitmap_and(rising, rising, chip->enable, 64);
525 bitmap_and(rising, rising, chip->rising_edge, 64);
526
527 bitmap_complement(falling, all, 64);
528 bitmap_and(falling, falling, chip->last_irq_read, 64);
529 bitmap_and(falling, falling, chip->enable, 64);
530 bitmap_and(falling, falling, chip->falling_edge, 64);
531
532 bitmap_copy(chip->last_irq_read, all, 64);
533 bitmap_or(all, rising, falling, 64);
534
535 spin_unlock(&chip->gpio_lock);
536
537 dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);
538
539 for_each_set_bit(bit, all, 64) {
540 irq_offset = xgpio_from_bit(chip, bit);
541 generic_handle_domain_irq(gc->irq.domain, irq_offset);
542 }
543
544 chained_irq_exit(irqchip, desc);
545}
546
547/**
548 * xgpio_probe - Probe method for the GPIO device.
549 * @pdev: pointer to the platform device
550 *
551 * Return:
552 * It returns 0, if the driver is bound to the GPIO device, or
553 * a negative value if there is an error.
554 */
555static int xgpio_probe(struct platform_device *pdev)
556{
557 struct xgpio_instance *chip;
558 int status = 0;
559 struct device_node *np = pdev->dev.of_node;
560 u32 is_dual = 0;
561 u32 cells = 2;
562 u32 width[2];
563 u32 state[2];
564 u32 dir[2];
565 struct gpio_irq_chip *girq;
566 u32 temp;
567
568 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
569 if (!chip)
570 return -ENOMEM;
571
572 platform_set_drvdata(pdev, chip);
573
574 /* First, check if the device is dual-channel */
575 of_property_read_u32(np, "xlnx,is-dual", &is_dual);
576
577 /* Setup defaults */
578 memset32(width, 0, ARRAY_SIZE(width));
579 memset32(state, 0, ARRAY_SIZE(state));
580 memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir));
581
582 /* Update GPIO state shadow register with default value */
583 of_property_read_u32(np, "xlnx,dout-default", &state[0]);
584 of_property_read_u32(np, "xlnx,dout-default-2", &state[1]);
585
586 bitmap_from_arr32(chip->state, state, 64);
587
588 /* Update GPIO direction shadow register with default value */
589 of_property_read_u32(np, "xlnx,tri-default", &dir[0]);
590 of_property_read_u32(np, "xlnx,tri-default-2", &dir[1]);
591
592 bitmap_from_arr32(chip->dir, dir, 64);
593
594 /* Update cells with gpio-cells value */
595 if (of_property_read_u32(np, "#gpio-cells", &cells))
596 dev_dbg(&pdev->dev, "Missing gpio-cells property\n");
597
598 if (cells != 2) {
599 dev_err(&pdev->dev, "#gpio-cells mismatch\n");
600 return -EINVAL;
601 }
602
603 /*
604 * Check device node and parent device node for device width
605 * and assume default width of 32
606 */
607 if (of_property_read_u32(np, "xlnx,gpio-width", &width[0]))
608 width[0] = 32;
609
610 if (width[0] > 32)
611 return -EINVAL;
612
613 if (is_dual && of_property_read_u32(np, "xlnx,gpio2-width", &width[1]))
614 width[1] = 32;
615
616 if (width[1] > 32)
617 return -EINVAL;
618
619 /* Setup software pin mapping */
620 bitmap_set(chip->sw_map, 0, width[0] + width[1]);
621
622 /* Setup hardware pin mapping */
623 bitmap_set(chip->hw_map, 0, width[0]);
624 bitmap_set(chip->hw_map, 32, width[1]);
625
626 spin_lock_init(&chip->gpio_lock);
627
628 chip->gc.base = -1;
629 chip->gc.ngpio = bitmap_weight(chip->hw_map, 64);
630 chip->gc.parent = &pdev->dev;
631 chip->gc.direction_input = xgpio_dir_in;
632 chip->gc.direction_output = xgpio_dir_out;
633 chip->gc.of_gpio_n_cells = cells;
634 chip->gc.get = xgpio_get;
635 chip->gc.set = xgpio_set;
636 chip->gc.request = xgpio_request;
637 chip->gc.free = xgpio_free;
638 chip->gc.set_multiple = xgpio_set_multiple;
639
640 chip->gc.label = dev_name(&pdev->dev);
641
642 chip->regs = devm_platform_ioremap_resource(pdev, 0);
643 if (IS_ERR(chip->regs)) {
644 dev_err(&pdev->dev, "failed to ioremap memory resource\n");
645 return PTR_ERR(chip->regs);
646 }
647
648 chip->clk = devm_clk_get_optional(&pdev->dev, NULL);
649 if (IS_ERR(chip->clk))
650 return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n");
651
652 status = clk_prepare_enable(chip->clk);
653 if (status < 0) {
654 dev_err(&pdev->dev, "Failed to prepare clk\n");
655 return status;
656 }
657 pm_runtime_get_noresume(&pdev->dev);
658 pm_runtime_set_active(&pdev->dev);
659 pm_runtime_enable(&pdev->dev);
660
661 xgpio_save_regs(chip);
662
663 chip->irq = platform_get_irq_optional(pdev, 0);
664 if (chip->irq <= 0)
665 goto skip_irq;
666
667 chip->irqchip.name = "gpio-xilinx";
668 chip->irqchip.irq_ack = xgpio_irq_ack;
669 chip->irqchip.irq_mask = xgpio_irq_mask;
670 chip->irqchip.irq_unmask = xgpio_irq_unmask;
671 chip->irqchip.irq_set_type = xgpio_set_irq_type;
672
673 /* Disable per-channel interrupts */
674 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0);
675 /* Clear any existing per-channel interrupts */
676 temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
677 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp);
678 /* Enable global interrupts */
679 xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);
680
681 girq = &chip->gc.irq;
682 girq->chip = &chip->irqchip;
683 girq->parent_handler = xgpio_irqhandler;
684 girq->num_parents = 1;
685 girq->parents = devm_kcalloc(&pdev->dev, 1,
686 sizeof(*girq->parents),
687 GFP_KERNEL);
688 if (!girq->parents) {
689 status = -ENOMEM;
690 goto err_pm_put;
691 }
692 girq->parents[0] = chip->irq;
693 girq->default_type = IRQ_TYPE_NONE;
694 girq->handler = handle_bad_irq;
695
696skip_irq:
697 status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
698 if (status) {
699 dev_err(&pdev->dev, "failed to add GPIO chip\n");
700 goto err_pm_put;
701 }
702
703 pm_runtime_put(&pdev->dev);
704 return 0;
705
706err_pm_put:
707 pm_runtime_disable(&pdev->dev);
708 pm_runtime_put_noidle(&pdev->dev);
709 clk_disable_unprepare(chip->clk);
710 return status;
711}
712
713static const struct of_device_id xgpio_of_match[] = {
714 { .compatible = "xlnx,xps-gpio-1.00.a", },
715 { /* end of list */ },
716};
717
718MODULE_DEVICE_TABLE(of, xgpio_of_match);
719
720static struct platform_driver xgpio_plat_driver = {
721 .probe = xgpio_probe,
722 .remove = xgpio_remove,
723 .driver = {
724 .name = "gpio-xilinx",
725 .of_match_table = xgpio_of_match,
726 .pm = &xgpio_dev_pm_ops,
727 },
728};
729
730static int __init xgpio_init(void)
731{
732 return platform_driver_register(&xgpio_plat_driver);
733}
734
735subsys_initcall(xgpio_init);
736
737static void __exit xgpio_exit(void)
738{
739 platform_driver_unregister(&xgpio_plat_driver);
740}
741module_exit(xgpio_exit);
742
743MODULE_AUTHOR("Xilinx, Inc.");
744MODULE_DESCRIPTION("Xilinx GPIO driver");
745MODULE_LICENSE("GPL");