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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
4 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 *
7 * Simple multiplexer clock implementation
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/module.h>
12#include <linux/slab.h>
13#include <linux/io.h>
14#include <linux/err.h>
15
16/*
17 * DOC: basic adjustable multiplexer clock that cannot gate
18 *
19 * Traits of this clock:
20 * prepare - clk_prepare only ensures that parents are prepared
21 * enable - clk_enable only ensures that parents are enabled
22 * rate - rate is only affected by parent switching. No clk_set_rate support
23 * parent - parent is adjustable through clk_set_parent
24 */
25
26static inline u32 clk_mux_readl(struct clk_mux *mux)
27{
28 if (mux->flags & CLK_MUX_BIG_ENDIAN)
29 return ioread32be(mux->reg);
30
31 return readl(mux->reg);
32}
33
34static inline void clk_mux_writel(struct clk_mux *mux, u32 val)
35{
36 if (mux->flags & CLK_MUX_BIG_ENDIAN)
37 iowrite32be(val, mux->reg);
38 else
39 writel(val, mux->reg);
40}
41
42int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
43 unsigned int val)
44{
45 int num_parents = clk_hw_get_num_parents(hw);
46
47 if (table) {
48 int i;
49
50 for (i = 0; i < num_parents; i++)
51 if (table[i] == val)
52 return i;
53 return -EINVAL;
54 }
55
56 if (val && (flags & CLK_MUX_INDEX_BIT))
57 val = ffs(val) - 1;
58
59 if (val && (flags & CLK_MUX_INDEX_ONE))
60 val--;
61
62 if (val >= num_parents)
63 return -EINVAL;
64
65 return val;
66}
67EXPORT_SYMBOL_GPL(clk_mux_val_to_index);
68
69unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
70{
71 unsigned int val = index;
72
73 if (table) {
74 val = table[index];
75 } else {
76 if (flags & CLK_MUX_INDEX_BIT)
77 val = 1 << index;
78
79 if (flags & CLK_MUX_INDEX_ONE)
80 val++;
81 }
82
83 return val;
84}
85EXPORT_SYMBOL_GPL(clk_mux_index_to_val);
86
87static u8 clk_mux_get_parent(struct clk_hw *hw)
88{
89 struct clk_mux *mux = to_clk_mux(hw);
90 u32 val;
91
92 val = clk_mux_readl(mux) >> mux->shift;
93 val &= mux->mask;
94
95 return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
96}
97
98static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
99{
100 struct clk_mux *mux = to_clk_mux(hw);
101 u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
102 unsigned long flags = 0;
103 u32 reg;
104
105 if (mux->lock)
106 spin_lock_irqsave(mux->lock, flags);
107 else
108 __acquire(mux->lock);
109
110 if (mux->flags & CLK_MUX_HIWORD_MASK) {
111 reg = mux->mask << (mux->shift + 16);
112 } else {
113 reg = clk_mux_readl(mux);
114 reg &= ~(mux->mask << mux->shift);
115 }
116 val = val << mux->shift;
117 reg |= val;
118 clk_mux_writel(mux, reg);
119
120 if (mux->lock)
121 spin_unlock_irqrestore(mux->lock, flags);
122 else
123 __release(mux->lock);
124
125 return 0;
126}
127
128static int clk_mux_determine_rate(struct clk_hw *hw,
129 struct clk_rate_request *req)
130{
131 struct clk_mux *mux = to_clk_mux(hw);
132
133 return clk_mux_determine_rate_flags(hw, req, mux->flags);
134}
135
136const struct clk_ops clk_mux_ops = {
137 .get_parent = clk_mux_get_parent,
138 .set_parent = clk_mux_set_parent,
139 .determine_rate = clk_mux_determine_rate,
140};
141EXPORT_SYMBOL_GPL(clk_mux_ops);
142
143const struct clk_ops clk_mux_ro_ops = {
144 .get_parent = clk_mux_get_parent,
145};
146EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
147
148struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
149 const char *name, u8 num_parents,
150 const char * const *parent_names,
151 const struct clk_hw **parent_hws,
152 const struct clk_parent_data *parent_data,
153 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
154 u8 clk_mux_flags, u32 *table, spinlock_t *lock)
155{
156 struct clk_mux *mux;
157 struct clk_hw *hw;
158 struct clk_init_data init = {};
159 u8 width = 0;
160 int ret = -EINVAL;
161
162 if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
163 width = fls(mask) - ffs(mask) + 1;
164 if (width + shift > 16) {
165 pr_err("mux value exceeds LOWORD field\n");
166 return ERR_PTR(-EINVAL);
167 }
168 }
169
170 /* allocate the mux */
171 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
172 if (!mux)
173 return ERR_PTR(-ENOMEM);
174
175 init.name = name;
176 if (clk_mux_flags & CLK_MUX_READ_ONLY)
177 init.ops = &clk_mux_ro_ops;
178 else
179 init.ops = &clk_mux_ops;
180 init.flags = flags;
181 init.parent_names = parent_names;
182 init.parent_data = parent_data;
183 init.parent_hws = parent_hws;
184 init.num_parents = num_parents;
185
186 /* struct clk_mux assignments */
187 mux->reg = reg;
188 mux->shift = shift;
189 mux->mask = mask;
190 mux->flags = clk_mux_flags;
191 mux->lock = lock;
192 mux->table = table;
193 mux->hw.init = &init;
194
195 hw = &mux->hw;
196 if (dev || !np)
197 ret = clk_hw_register(dev, hw);
198 else if (np)
199 ret = of_clk_hw_register(np, hw);
200 if (ret) {
201 kfree(mux);
202 hw = ERR_PTR(ret);
203 }
204
205 return hw;
206}
207EXPORT_SYMBOL_GPL(__clk_hw_register_mux);
208
209struct clk *clk_register_mux_table(struct device *dev, const char *name,
210 const char * const *parent_names, u8 num_parents,
211 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
212 u8 clk_mux_flags, u32 *table, spinlock_t *lock)
213{
214 struct clk_hw *hw;
215
216 hw = clk_hw_register_mux_table(dev, name, parent_names,
217 num_parents, flags, reg, shift, mask,
218 clk_mux_flags, table, lock);
219 if (IS_ERR(hw))
220 return ERR_CAST(hw);
221 return hw->clk;
222}
223EXPORT_SYMBOL_GPL(clk_register_mux_table);
224
225void clk_unregister_mux(struct clk *clk)
226{
227 struct clk_mux *mux;
228 struct clk_hw *hw;
229
230 hw = __clk_get_hw(clk);
231 if (!hw)
232 return;
233
234 mux = to_clk_mux(hw);
235
236 clk_unregister(clk);
237 kfree(mux);
238}
239EXPORT_SYMBOL_GPL(clk_unregister_mux);
240
241void clk_hw_unregister_mux(struct clk_hw *hw)
242{
243 struct clk_mux *mux;
244
245 mux = to_clk_mux(hw);
246
247 clk_hw_unregister(hw);
248 kfree(mux);
249}
250EXPORT_SYMBOL_GPL(clk_hw_unregister_mux);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
4 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 *
7 * Simple multiplexer clock implementation
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/device.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/io.h>
15#include <linux/err.h>
16
17/*
18 * DOC: basic adjustable multiplexer clock that cannot gate
19 *
20 * Traits of this clock:
21 * prepare - clk_prepare only ensures that parents are prepared
22 * enable - clk_enable only ensures that parents are enabled
23 * rate - rate is only affected by parent switching. No clk_set_rate support
24 * parent - parent is adjustable through clk_set_parent
25 */
26
27static inline u32 clk_mux_readl(struct clk_mux *mux)
28{
29 if (mux->flags & CLK_MUX_BIG_ENDIAN)
30 return ioread32be(mux->reg);
31
32 return readl(mux->reg);
33}
34
35static inline void clk_mux_writel(struct clk_mux *mux, u32 val)
36{
37 if (mux->flags & CLK_MUX_BIG_ENDIAN)
38 iowrite32be(val, mux->reg);
39 else
40 writel(val, mux->reg);
41}
42
43int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,
44 unsigned int val)
45{
46 int num_parents = clk_hw_get_num_parents(hw);
47
48 if (table) {
49 int i;
50
51 for (i = 0; i < num_parents; i++)
52 if (table[i] == val)
53 return i;
54 return -EINVAL;
55 }
56
57 if (val && (flags & CLK_MUX_INDEX_BIT))
58 val = ffs(val) - 1;
59
60 if (val && (flags & CLK_MUX_INDEX_ONE))
61 val--;
62
63 if (val >= num_parents)
64 return -EINVAL;
65
66 return val;
67}
68EXPORT_SYMBOL_GPL(clk_mux_val_to_index);
69
70unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index)
71{
72 unsigned int val = index;
73
74 if (table) {
75 val = table[index];
76 } else {
77 if (flags & CLK_MUX_INDEX_BIT)
78 val = 1 << index;
79
80 if (flags & CLK_MUX_INDEX_ONE)
81 val++;
82 }
83
84 return val;
85}
86EXPORT_SYMBOL_GPL(clk_mux_index_to_val);
87
88static u8 clk_mux_get_parent(struct clk_hw *hw)
89{
90 struct clk_mux *mux = to_clk_mux(hw);
91 u32 val;
92
93 val = clk_mux_readl(mux) >> mux->shift;
94 val &= mux->mask;
95
96 return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
97}
98
99static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
100{
101 struct clk_mux *mux = to_clk_mux(hw);
102 u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
103 unsigned long flags = 0;
104 u32 reg;
105
106 if (mux->lock)
107 spin_lock_irqsave(mux->lock, flags);
108 else
109 __acquire(mux->lock);
110
111 if (mux->flags & CLK_MUX_HIWORD_MASK) {
112 reg = mux->mask << (mux->shift + 16);
113 } else {
114 reg = clk_mux_readl(mux);
115 reg &= ~(mux->mask << mux->shift);
116 }
117 val = val << mux->shift;
118 reg |= val;
119 clk_mux_writel(mux, reg);
120
121 if (mux->lock)
122 spin_unlock_irqrestore(mux->lock, flags);
123 else
124 __release(mux->lock);
125
126 return 0;
127}
128
129static int clk_mux_determine_rate(struct clk_hw *hw,
130 struct clk_rate_request *req)
131{
132 struct clk_mux *mux = to_clk_mux(hw);
133
134 return clk_mux_determine_rate_flags(hw, req, mux->flags);
135}
136
137const struct clk_ops clk_mux_ops = {
138 .get_parent = clk_mux_get_parent,
139 .set_parent = clk_mux_set_parent,
140 .determine_rate = clk_mux_determine_rate,
141};
142EXPORT_SYMBOL_GPL(clk_mux_ops);
143
144const struct clk_ops clk_mux_ro_ops = {
145 .get_parent = clk_mux_get_parent,
146};
147EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
148
149struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
150 const char *name, u8 num_parents,
151 const char * const *parent_names,
152 const struct clk_hw **parent_hws,
153 const struct clk_parent_data *parent_data,
154 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
155 u8 clk_mux_flags, const u32 *table, spinlock_t *lock)
156{
157 struct clk_mux *mux;
158 struct clk_hw *hw;
159 struct clk_init_data init = {};
160 int ret = -EINVAL;
161
162 if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
163 u8 width = fls(mask) - ffs(mask) + 1;
164
165 if (width + shift > 16) {
166 pr_err("mux value exceeds LOWORD field\n");
167 return ERR_PTR(-EINVAL);
168 }
169 }
170
171 /* allocate the mux */
172 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
173 if (!mux)
174 return ERR_PTR(-ENOMEM);
175
176 init.name = name;
177 if (clk_mux_flags & CLK_MUX_READ_ONLY)
178 init.ops = &clk_mux_ro_ops;
179 else
180 init.ops = &clk_mux_ops;
181 init.flags = flags;
182 init.parent_names = parent_names;
183 init.parent_data = parent_data;
184 init.parent_hws = parent_hws;
185 init.num_parents = num_parents;
186
187 /* struct clk_mux assignments */
188 mux->reg = reg;
189 mux->shift = shift;
190 mux->mask = mask;
191 mux->flags = clk_mux_flags;
192 mux->lock = lock;
193 mux->table = table;
194 mux->hw.init = &init;
195
196 hw = &mux->hw;
197 if (dev || !np)
198 ret = clk_hw_register(dev, hw);
199 else if (np)
200 ret = of_clk_hw_register(np, hw);
201 if (ret) {
202 kfree(mux);
203 hw = ERR_PTR(ret);
204 }
205
206 return hw;
207}
208EXPORT_SYMBOL_GPL(__clk_hw_register_mux);
209
210static void devm_clk_hw_release_mux(struct device *dev, void *res)
211{
212 clk_hw_unregister_mux(*(struct clk_hw **)res);
213}
214
215struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
216 const char *name, u8 num_parents,
217 const char * const *parent_names,
218 const struct clk_hw **parent_hws,
219 const struct clk_parent_data *parent_data,
220 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
221 u8 clk_mux_flags, const u32 *table, spinlock_t *lock)
222{
223 struct clk_hw **ptr, *hw;
224
225 ptr = devres_alloc(devm_clk_hw_release_mux, sizeof(*ptr), GFP_KERNEL);
226 if (!ptr)
227 return ERR_PTR(-ENOMEM);
228
229 hw = __clk_hw_register_mux(dev, np, name, num_parents, parent_names, parent_hws,
230 parent_data, flags, reg, shift, mask,
231 clk_mux_flags, table, lock);
232
233 if (!IS_ERR(hw)) {
234 *ptr = hw;
235 devres_add(dev, ptr);
236 } else {
237 devres_free(ptr);
238 }
239
240 return hw;
241}
242EXPORT_SYMBOL_GPL(__devm_clk_hw_register_mux);
243
244struct clk *clk_register_mux_table(struct device *dev, const char *name,
245 const char * const *parent_names, u8 num_parents,
246 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
247 u8 clk_mux_flags, const u32 *table, spinlock_t *lock)
248{
249 struct clk_hw *hw;
250
251 hw = clk_hw_register_mux_table(dev, name, parent_names,
252 num_parents, flags, reg, shift, mask,
253 clk_mux_flags, table, lock);
254 if (IS_ERR(hw))
255 return ERR_CAST(hw);
256 return hw->clk;
257}
258EXPORT_SYMBOL_GPL(clk_register_mux_table);
259
260void clk_unregister_mux(struct clk *clk)
261{
262 struct clk_mux *mux;
263 struct clk_hw *hw;
264
265 hw = __clk_get_hw(clk);
266 if (!hw)
267 return;
268
269 mux = to_clk_mux(hw);
270
271 clk_unregister(clk);
272 kfree(mux);
273}
274EXPORT_SYMBOL_GPL(clk_unregister_mux);
275
276void clk_hw_unregister_mux(struct clk_hw *hw)
277{
278 struct clk_mux *mux;
279
280 mux = to_clk_mux(hw);
281
282 clk_hw_unregister(hw);
283 kfree(mux);
284}
285EXPORT_SYMBOL_GPL(clk_hw_unregister_mux);