1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * sata_inic162x.c - Driver for Initio 162x SATA controllers
  4 *
  5 * Copyright 2006  SUSE Linux Products GmbH
  6 * Copyright 2006  Tejun Heo <teheo@novell.com>
  7 *
  8 * **** WARNING ****
  9 *
 10 * This driver never worked properly and unfortunately data corruption is
 11 * relatively common.  There isn't anyone working on the driver and there's
 12 * no support from the vendor.  Do not use this driver in any production
 13 * environment.
 14 *
 15 * http://thread.gmane.org/gmane.linux.debian.devel.bugs.rc/378525/focus=54491
 16 * https://bugzilla.kernel.org/show_bug.cgi?id=60565
 17 *
 18 * *****************
 19 *
 20 * This controller is eccentric and easily locks up if something isn't
 21 * right.  Documentation is available at initio's website but it only
 22 * documents registers (not programming model).
 23 *
 24 * This driver has interesting history.  The first version was written
 25 * from the documentation and a 2.4 IDE driver posted on a Taiwan
 26 * company, which didn't use any IDMA features and couldn't handle
 27 * LBA48.  The resulting driver couldn't handle LBA48 devices either
 28 * making it pretty useless.
 29 *
 30 * After a while, initio picked the driver up, renamed it to
 31 * sata_initio162x, updated it to use IDMA for ATA DMA commands and
 32 * posted it on their website.  It only used ATA_PROT_DMA for IDMA and
 33 * attaching both devices and issuing IDMA and !IDMA commands
 34 * simultaneously broke it due to PIRQ masking interaction but it did
 35 * show how to use the IDMA (ADMA + some initio specific twists)
 36 * engine.
 37 *
 38 * Then, I picked up their changes again and here's the usable driver
 39 * which uses IDMA for everything.  Everything works now including
 40 * LBA48, CD/DVD burning, suspend/resume and hotplug.  There are some
 41 * issues tho.  Result Tf is not resported properly, NCQ isn't
 42 * supported yet and CD/DVD writing works with DMA assisted PIO
 43 * protocol (which, for native SATA devices, shouldn't cause any
 44 * noticeable difference).
 45 *
 46 * Anyways, so, here's finally a working driver for inic162x.  Enjoy!
 47 *
 48 * initio: If you guys wanna improve the driver regarding result TF
 49 * access and other stuff, please feel free to contact me.  I'll be
 50 * happy to assist.
 51 */
 52
 53#include <linux/gfp.h>
 54#include <linux/kernel.h>
 55#include <linux/module.h>
 56#include <linux/pci.h>
 57#include <scsi/scsi_host.h>
 58#include <linux/libata.h>
 59#include <linux/blkdev.h>
 60#include <scsi/scsi_device.h>
 61
 62#define DRV_NAME	"sata_inic162x"
 63#define DRV_VERSION	"0.4"
 64
 65enum {
 66	MMIO_BAR_PCI		= 5,
 67	MMIO_BAR_CARDBUS	= 1,
 68
 69	NR_PORTS		= 2,
 70
 71	IDMA_CPB_TBL_SIZE	= 4 * 32,
 72
 73	INIC_DMA_BOUNDARY	= 0xffffff,
 74
 75	HOST_ACTRL		= 0x08,
 76	HOST_CTL		= 0x7c,
 77	HOST_STAT		= 0x7e,
 78	HOST_IRQ_STAT		= 0xbc,
 79	HOST_IRQ_MASK		= 0xbe,
 80
 81	PORT_SIZE		= 0x40,
 82
 83	/* registers for ATA TF operation */
 84	PORT_TF_DATA		= 0x00,
 85	PORT_TF_FEATURE		= 0x01,
 86	PORT_TF_NSECT		= 0x02,
 87	PORT_TF_LBAL		= 0x03,
 88	PORT_TF_LBAM		= 0x04,
 89	PORT_TF_LBAH		= 0x05,
 90	PORT_TF_DEVICE		= 0x06,
 91	PORT_TF_COMMAND		= 0x07,
 92	PORT_TF_ALT_STAT	= 0x08,
 93	PORT_IRQ_STAT		= 0x09,
 94	PORT_IRQ_MASK		= 0x0a,
 95	PORT_PRD_CTL		= 0x0b,
 96	PORT_PRD_ADDR		= 0x0c,
 97	PORT_PRD_XFERLEN	= 0x10,
 98	PORT_CPB_CPBLAR		= 0x18,
 99	PORT_CPB_PTQFIFO	= 0x1c,
100
101	/* IDMA register */
102	PORT_IDMA_CTL		= 0x14,
103	PORT_IDMA_STAT		= 0x16,
104
105	PORT_RPQ_FIFO		= 0x1e,
106	PORT_RPQ_CNT		= 0x1f,
107
108	PORT_SCR		= 0x20,
109
110	/* HOST_CTL bits */
111	HCTL_LEDEN		= (1 << 3),  /* enable LED operation */
112	HCTL_IRQOFF		= (1 << 8),  /* global IRQ off */
113	HCTL_FTHD0		= (1 << 10), /* fifo threshold 0 */
114	HCTL_FTHD1		= (1 << 11), /* fifo threshold 1*/
115	HCTL_PWRDWN		= (1 << 12), /* power down PHYs */
116	HCTL_SOFTRST		= (1 << 13), /* global reset (no phy reset) */
117	HCTL_RPGSEL		= (1 << 15), /* register page select */
118
119	HCTL_KNOWN_BITS		= HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
120				  HCTL_RPGSEL,
121
122	/* HOST_IRQ_(STAT|MASK) bits */
123	HIRQ_PORT0		= (1 << 0),
124	HIRQ_PORT1		= (1 << 1),
125	HIRQ_SOFT		= (1 << 14),
126	HIRQ_GLOBAL		= (1 << 15), /* STAT only */
127
128	/* PORT_IRQ_(STAT|MASK) bits */
129	PIRQ_OFFLINE		= (1 << 0),  /* device unplugged */
130	PIRQ_ONLINE		= (1 << 1),  /* device plugged */
131	PIRQ_COMPLETE		= (1 << 2),  /* completion interrupt */
132	PIRQ_FATAL		= (1 << 3),  /* fatal error */
133	PIRQ_ATA		= (1 << 4),  /* ATA interrupt */
134	PIRQ_REPLY		= (1 << 5),  /* reply FIFO not empty */
135	PIRQ_PENDING		= (1 << 7),  /* port IRQ pending (STAT only) */
136
137	PIRQ_ERR		= PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
138	PIRQ_MASK_DEFAULT	= PIRQ_REPLY | PIRQ_ATA,
139	PIRQ_MASK_FREEZE	= 0xff,
140
141	/* PORT_PRD_CTL bits */
142	PRD_CTL_START		= (1 << 0),
143	PRD_CTL_WR		= (1 << 3),
144	PRD_CTL_DMAEN		= (1 << 7),  /* DMA enable */
145
146	/* PORT_IDMA_CTL bits */
147	IDMA_CTL_RST_ATA	= (1 << 2),  /* hardreset ATA bus */
148	IDMA_CTL_RST_IDMA	= (1 << 5),  /* reset IDMA machinery */
149	IDMA_CTL_GO		= (1 << 7),  /* IDMA mode go */
150	IDMA_CTL_ATA_NIEN	= (1 << 8),  /* ATA IRQ disable */
151
152	/* PORT_IDMA_STAT bits */
153	IDMA_STAT_PERR		= (1 << 0),  /* PCI ERROR MODE */
154	IDMA_STAT_CPBERR	= (1 << 1),  /* ADMA CPB error */
155	IDMA_STAT_LGCY		= (1 << 3),  /* ADMA legacy */
156	IDMA_STAT_UIRQ		= (1 << 4),  /* ADMA unsolicited irq */
157	IDMA_STAT_STPD		= (1 << 5),  /* ADMA stopped */
158	IDMA_STAT_PSD		= (1 << 6),  /* ADMA pause */
159	IDMA_STAT_DONE		= (1 << 7),  /* ADMA done */
160
161	IDMA_STAT_ERR		= IDMA_STAT_PERR | IDMA_STAT_CPBERR,
162
163	/* CPB Control Flags*/
164	CPB_CTL_VALID		= (1 << 0),  /* CPB valid */
165	CPB_CTL_QUEUED		= (1 << 1),  /* queued command */
166	CPB_CTL_DATA		= (1 << 2),  /* data, rsvd in datasheet */
167	CPB_CTL_IEN		= (1 << 3),  /* PCI interrupt enable */
168	CPB_CTL_DEVDIR		= (1 << 4),  /* device direction control */
169
170	/* CPB Response Flags */
171	CPB_RESP_DONE		= (1 << 0),  /* ATA command complete */
172	CPB_RESP_REL		= (1 << 1),  /* ATA release */
173	CPB_RESP_IGNORED	= (1 << 2),  /* CPB ignored */
174	CPB_RESP_ATA_ERR	= (1 << 3),  /* ATA command error */
175	CPB_RESP_SPURIOUS	= (1 << 4),  /* ATA spurious interrupt error */
176	CPB_RESP_UNDERFLOW	= (1 << 5),  /* APRD deficiency length error */
177	CPB_RESP_OVERFLOW	= (1 << 6),  /* APRD exccess length error */
178	CPB_RESP_CPB_ERR	= (1 << 7),  /* CPB error flag */
179
180	/* PRD Control Flags */
181	PRD_DRAIN		= (1 << 1),  /* ignore data excess */
182	PRD_CDB			= (1 << 2),  /* atapi packet command pointer */
183	PRD_DIRECT_INTR		= (1 << 3),  /* direct interrupt */
184	PRD_DMA			= (1 << 4),  /* data transfer method */
185	PRD_WRITE		= (1 << 5),  /* data dir, rsvd in datasheet */
186	PRD_IOM			= (1 << 6),  /* io/memory transfer */
187	PRD_END			= (1 << 7),  /* APRD chain end */
188};
189
190/* Comman Parameter Block */
191struct inic_cpb {
192	u8		resp_flags;	/* Response Flags */
193	u8		error;		/* ATA Error */
194	u8		status;		/* ATA Status */
195	u8		ctl_flags;	/* Control Flags */
196	__le32		len;		/* Total Transfer Length */
197	__le32		prd;		/* First PRD pointer */
198	u8		rsvd[4];
199	/* 16 bytes */
200	u8		feature;	/* ATA Feature */
201	u8		hob_feature;	/* ATA Ex. Feature */
202	u8		device;		/* ATA Device/Head */
203	u8		mirctl;		/* Mirror Control */
204	u8		nsect;		/* ATA Sector Count */
205	u8		hob_nsect;	/* ATA Ex. Sector Count */
206	u8		lbal;		/* ATA Sector Number */
207	u8		hob_lbal;	/* ATA Ex. Sector Number */
208	u8		lbam;		/* ATA Cylinder Low */
209	u8		hob_lbam;	/* ATA Ex. Cylinder Low */
210	u8		lbah;		/* ATA Cylinder High */
211	u8		hob_lbah;	/* ATA Ex. Cylinder High */
212	u8		command;	/* ATA Command */
213	u8		ctl;		/* ATA Control */
214	u8		slave_error;	/* Slave ATA Error */
215	u8		slave_status;	/* Slave ATA Status */
216	/* 32 bytes */
217} __packed;
218
219/* Physical Region Descriptor */
220struct inic_prd {
221	__le32		mad;		/* Physical Memory Address */
222	__le16		len;		/* Transfer Length */
223	u8		rsvd;
224	u8		flags;		/* Control Flags */
225} __packed;
226
227struct inic_pkt {
228	struct inic_cpb	cpb;
229	struct inic_prd	prd[LIBATA_MAX_PRD + 1];	/* + 1 for cdb */
230	u8		cdb[ATAPI_CDB_LEN];
231} __packed;
232
233struct inic_host_priv {
234	void __iomem	*mmio_base;
235	u16		cached_hctl;
236};
237
238struct inic_port_priv {
239	struct inic_pkt	*pkt;
240	dma_addr_t	pkt_dma;
241	u32		*cpb_tbl;
242	dma_addr_t	cpb_tbl_dma;
243};
244
245static struct scsi_host_template inic_sht = {
246	ATA_BASE_SHT(DRV_NAME),
247	.sg_tablesize		= LIBATA_MAX_PRD, /* maybe it can be larger? */
248
249	/*
250	 * This controller is braindamaged.  dma_boundary is 0xffff like others
251	 * but it will lock up the whole machine HARD if 65536 byte PRD entry
252	 * is fed.  Reduce maximum segment size.
253	 */
254	.dma_boundary		= INIC_DMA_BOUNDARY,
255	.max_segment_size	= 65536 - 512,
256};
257
258static const int scr_map[] = {
259	[SCR_STATUS]	= 0,
260	[SCR_ERROR]	= 1,
261	[SCR_CONTROL]	= 2,
262};
263
264static void __iomem *inic_port_base(struct ata_port *ap)
265{
266	struct inic_host_priv *hpriv = ap->host->private_data;
267
268	return hpriv->mmio_base + ap->port_no * PORT_SIZE;
269}
270
271static void inic_reset_port(void __iomem *port_base)
272{
273	void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
274
275	/* stop IDMA engine */
276	readw(idma_ctl); /* flush */
277	msleep(1);
278
279	/* mask IRQ and assert reset */
280	writew(IDMA_CTL_RST_IDMA, idma_ctl);
281	readw(idma_ctl); /* flush */
282	msleep(1);
283
284	/* release reset */
285	writew(0, idma_ctl);
286
287	/* clear irq */
288	writeb(0xff, port_base + PORT_IRQ_STAT);
289}
290
291static int inic_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
292{
293	void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
294
295	if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
296		return -EINVAL;
297
298	*val = readl(scr_addr + scr_map[sc_reg] * 4);
299
300	/* this controller has stuck DIAG.N, ignore it */
301	if (sc_reg == SCR_ERROR)
302		*val &= ~SERR_PHYRDY_CHG;
303	return 0;
304}
305
306static int inic_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
307{
308	void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
309
310	if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
311		return -EINVAL;
312
313	writel(val, scr_addr + scr_map[sc_reg] * 4);
314	return 0;
315}
316
317static void inic_stop_idma(struct ata_port *ap)
318{
319	void __iomem *port_base = inic_port_base(ap);
320
321	readb(port_base + PORT_RPQ_FIFO);
322	readb(port_base + PORT_RPQ_CNT);
323	writew(0, port_base + PORT_IDMA_CTL);
324}
325
326static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat)
327{
328	struct ata_eh_info *ehi = &ap->link.eh_info;
329	struct inic_port_priv *pp = ap->private_data;
330	struct inic_cpb *cpb = &pp->pkt->cpb;
331	bool freeze = false;
332
333	ata_ehi_clear_desc(ehi);
334	ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x",
335			  irq_stat, idma_stat);
336
337	inic_stop_idma(ap);
338
339	if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
340		ata_ehi_push_desc(ehi, "hotplug");
341		ata_ehi_hotplugged(ehi);
342		freeze = true;
343	}
344
345	if (idma_stat & IDMA_STAT_PERR) {
346		ata_ehi_push_desc(ehi, "PCI error");
347		freeze = true;
348	}
349
350	if (idma_stat & IDMA_STAT_CPBERR) {
351		ata_ehi_push_desc(ehi, "CPB error");
352
353		if (cpb->resp_flags & CPB_RESP_IGNORED) {
354			__ata_ehi_push_desc(ehi, " ignored");
355			ehi->err_mask |= AC_ERR_INVALID;
356			freeze = true;
357		}
358
359		if (cpb->resp_flags & CPB_RESP_ATA_ERR)
360			ehi->err_mask |= AC_ERR_DEV;
361
362		if (cpb->resp_flags & CPB_RESP_SPURIOUS) {
363			__ata_ehi_push_desc(ehi, " spurious-intr");
364			ehi->err_mask |= AC_ERR_HSM;
365			freeze = true;
366		}
367
368		if (cpb->resp_flags &
369		    (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) {
370			__ata_ehi_push_desc(ehi, " data-over/underflow");
371			ehi->err_mask |= AC_ERR_HSM;
372			freeze = true;
373		}
374	}
375
376	if (freeze)
377		ata_port_freeze(ap);
378	else
379		ata_port_abort(ap);
380}
381
382static void inic_host_intr(struct ata_port *ap)
383{
384	void __iomem *port_base = inic_port_base(ap);
385	struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
386	u8 irq_stat;
387	u16 idma_stat;
388
389	/* read and clear IRQ status */
390	irq_stat = readb(port_base + PORT_IRQ_STAT);
391	writeb(irq_stat, port_base + PORT_IRQ_STAT);
392	idma_stat = readw(port_base + PORT_IDMA_STAT);
393
394	if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR)))
395		inic_host_err_intr(ap, irq_stat, idma_stat);
396
397	if (unlikely(!qc))
398		goto spurious;
399
400	if (likely(idma_stat & IDMA_STAT_DONE)) {
401		inic_stop_idma(ap);
402
403		/* Depending on circumstances, device error
404		 * isn't reported by IDMA, check it explicitly.
405		 */
406		if (unlikely(readb(port_base + PORT_TF_COMMAND) &
407			     (ATA_DF | ATA_ERR)))
408			qc->err_mask |= AC_ERR_DEV;
409
410		ata_qc_complete(qc);
411		return;
412	}
413
414 spurious:
415	ata_port_warn(ap, "unhandled interrupt: cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n",
416		      qc ? qc->tf.command : 0xff, irq_stat, idma_stat);
417}
418
419static irqreturn_t inic_interrupt(int irq, void *dev_instance)
420{
421	struct ata_host *host = dev_instance;
422	struct inic_host_priv *hpriv = host->private_data;
423	u16 host_irq_stat;
424	int i, handled = 0;
425
426	host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT);
427
428	if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
429		goto out;
430
431	spin_lock(&host->lock);
432
433	for (i = 0; i < NR_PORTS; i++)
434		if (host_irq_stat & (HIRQ_PORT0 << i)) {
435			inic_host_intr(host->ports[i]);
436			handled++;
437		}
438
439	spin_unlock(&host->lock);
440
441 out:
442	return IRQ_RETVAL(handled);
443}
444
445static int inic_check_atapi_dma(struct ata_queued_cmd *qc)
446{
447	/* For some reason ATAPI_PROT_DMA doesn't work for some
448	 * commands including writes and other misc ops.  Use PIO
449	 * protocol instead, which BTW is driven by the DMA engine
450	 * anyway, so it shouldn't make much difference for native
451	 * SATA devices.
452	 */
453	if (atapi_cmd_type(qc->cdb[0]) == READ)
454		return 0;
455	return 1;
456}
457
458static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc)
459{
460	struct scatterlist *sg;
461	unsigned int si;
462	u8 flags = 0;
463
464	if (qc->tf.flags & ATA_TFLAG_WRITE)
465		flags |= PRD_WRITE;
466
467	if (ata_is_dma(qc->tf.protocol))
468		flags |= PRD_DMA;
469
470	for_each_sg(qc->sg, sg, qc->n_elem, si) {
471		prd->mad = cpu_to_le32(sg_dma_address(sg));
472		prd->len = cpu_to_le16(sg_dma_len(sg));
473		prd->flags = flags;
474		prd++;
475	}
476
477	WARN_ON(!si);
478	prd[-1].flags |= PRD_END;
479}
480
481static enum ata_completion_errors inic_qc_prep(struct ata_queued_cmd *qc)
482{
483	struct inic_port_priv *pp = qc->ap->private_data;
484	struct inic_pkt *pkt = pp->pkt;
485	struct inic_cpb *cpb = &pkt->cpb;
486	struct inic_prd *prd = pkt->prd;
487	bool is_atapi = ata_is_atapi(qc->tf.protocol);
488	bool is_data = ata_is_data(qc->tf.protocol);
489	unsigned int cdb_len = 0;
490
491	VPRINTK("ENTER\n");
492
493	if (is_atapi)
494		cdb_len = qc->dev->cdb_len;
495
496	/* prepare packet, based on initio driver */
497	memset(pkt, 0, sizeof(struct inic_pkt));
498
499	cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN;
500	if (is_atapi || is_data)
501		cpb->ctl_flags |= CPB_CTL_DATA;
502
503	cpb->len = cpu_to_le32(qc->nbytes + cdb_len);
504	cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd));
505
506	cpb->device = qc->tf.device;
507	cpb->feature = qc->tf.feature;
508	cpb->nsect = qc->tf.nsect;
509	cpb->lbal = qc->tf.lbal;
510	cpb->lbam = qc->tf.lbam;
511	cpb->lbah = qc->tf.lbah;
512
513	if (qc->tf.flags & ATA_TFLAG_LBA48) {
514		cpb->hob_feature = qc->tf.hob_feature;
515		cpb->hob_nsect = qc->tf.hob_nsect;
516		cpb->hob_lbal = qc->tf.hob_lbal;
517		cpb->hob_lbam = qc->tf.hob_lbam;
518		cpb->hob_lbah = qc->tf.hob_lbah;
519	}
520
521	cpb->command = qc->tf.command;
522	/* don't load ctl - dunno why.  it's like that in the initio driver */
523
524	/* setup PRD for CDB */
525	if (is_atapi) {
526		memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN);
527		prd->mad = cpu_to_le32(pp->pkt_dma +
528				       offsetof(struct inic_pkt, cdb));
529		prd->len = cpu_to_le16(cdb_len);
530		prd->flags = PRD_CDB | PRD_WRITE;
531		if (!is_data)
532			prd->flags |= PRD_END;
533		prd++;
534	}
535
536	/* setup sg table */
537	if (is_data)
538		inic_fill_sg(prd, qc);
539
540	pp->cpb_tbl[0] = pp->pkt_dma;
541
542	return AC_ERR_OK;
543}
544
545static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
546{
547	struct ata_port *ap = qc->ap;
548	void __iomem *port_base = inic_port_base(ap);
549
550	/* fire up the ADMA engine */
551	writew(HCTL_FTHD0 | HCTL_LEDEN, port_base + HOST_CTL);
552	writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL);
553	writeb(0, port_base + PORT_CPB_PTQFIFO);
554
555	return 0;
556}
557
558static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
559{
560	void __iomem *port_base = inic_port_base(ap);
561
562	tf->feature	= readb(port_base + PORT_TF_FEATURE);
563	tf->nsect	= readb(port_base + PORT_TF_NSECT);
564	tf->lbal	= readb(port_base + PORT_TF_LBAL);
565	tf->lbam	= readb(port_base + PORT_TF_LBAM);
566	tf->lbah	= readb(port_base + PORT_TF_LBAH);
567	tf->device	= readb(port_base + PORT_TF_DEVICE);
568	tf->command	= readb(port_base + PORT_TF_COMMAND);
569}
570
571static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc)
572{
573	struct ata_taskfile *rtf = &qc->result_tf;
574	struct ata_taskfile tf;
575
576	/* FIXME: Except for status and error, result TF access
577	 * doesn't work.  I tried reading from BAR0/2, CPB and BAR5.
578	 * None works regardless of which command interface is used.
579	 * For now return true iff status indicates device error.
580	 * This means that we're reporting bogus sector for RW
581	 * failures.  Eeekk....
582	 */
583	inic_tf_read(qc->ap, &tf);
584
585	if (!(tf.command & ATA_ERR))
586		return false;
587
588	rtf->command = tf.command;
589	rtf->feature = tf.feature;
590	return true;
591}
592
593static void inic_freeze(struct ata_port *ap)
594{
595	void __iomem *port_base = inic_port_base(ap);
596
597	writeb(PIRQ_MASK_FREEZE, port_base + PORT_IRQ_MASK);
598	writeb(0xff, port_base + PORT_IRQ_STAT);
599}
600
601static void inic_thaw(struct ata_port *ap)
602{
603	void __iomem *port_base = inic_port_base(ap);
604
605	writeb(0xff, port_base + PORT_IRQ_STAT);
606	writeb(PIRQ_MASK_DEFAULT, port_base + PORT_IRQ_MASK);
607}
608
609static int inic_check_ready(struct ata_link *link)
610{
611	void __iomem *port_base = inic_port_base(link->ap);
612
613	return ata_check_ready(readb(port_base + PORT_TF_COMMAND));
614}
615
616/*
617 * SRST and SControl hardreset don't give valid signature on this
618 * controller.  Only controller specific hardreset mechanism works.
619 */
620static int inic_hardreset(struct ata_link *link, unsigned int *class,
621			  unsigned long deadline)
622{
623	struct ata_port *ap = link->ap;
624	void __iomem *port_base = inic_port_base(ap);
625	void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
626	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
627	int rc;
628
629	/* hammer it into sane state */
630	inic_reset_port(port_base);
631
632	writew(IDMA_CTL_RST_ATA, idma_ctl);
633	readw(idma_ctl);	/* flush */
634	ata_msleep(ap, 1);
635	writew(0, idma_ctl);
636
637	rc = sata_link_resume(link, timing, deadline);
638	if (rc) {
639		ata_link_warn(link,
640			      "failed to resume link after reset (errno=%d)\n",
641			      rc);
642		return rc;
643	}
644
645	*class = ATA_DEV_NONE;
646	if (ata_link_online(link)) {
647		struct ata_taskfile tf;
648
649		/* wait for link to become ready */
650		rc = ata_wait_after_reset(link, deadline, inic_check_ready);
651		/* link occupied, -ENODEV too is an error */
652		if (rc) {
653			ata_link_warn(link,
654				      "device not ready after hardreset (errno=%d)\n",
655				      rc);
656			return rc;
657		}
658
659		inic_tf_read(ap, &tf);
660		*class = ata_dev_classify(&tf);
661	}
662
663	return 0;
664}
665
666static void inic_error_handler(struct ata_port *ap)
667{
668	void __iomem *port_base = inic_port_base(ap);
669
670	inic_reset_port(port_base);
671	ata_std_error_handler(ap);
672}
673
674static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
675{
676	/* make DMA engine forget about the failed command */
677	if (qc->flags & ATA_QCFLAG_FAILED)
678		inic_reset_port(inic_port_base(qc->ap));
679}
680
681static void init_port(struct ata_port *ap)
682{
683	void __iomem *port_base = inic_port_base(ap);
684	struct inic_port_priv *pp = ap->private_data;
685
686	/* clear packet and CPB table */
687	memset(pp->pkt, 0, sizeof(struct inic_pkt));
688	memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE);
689
690	/* setup CPB lookup table addresses */
691	writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR);
692}
693
694static int inic_port_resume(struct ata_port *ap)
695{
696	init_port(ap);
697	return 0;
698}
699
700static int inic_port_start(struct ata_port *ap)
701{
702	struct device *dev = ap->host->dev;
703	struct inic_port_priv *pp;
704
705	/* alloc and initialize private data */
706	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
707	if (!pp)
708		return -ENOMEM;
709	ap->private_data = pp;
710
711	/* Alloc resources */
712	pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt),
713				      &pp->pkt_dma, GFP_KERNEL);
714	if (!pp->pkt)
715		return -ENOMEM;
716
717	pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE,
718					  &pp->cpb_tbl_dma, GFP_KERNEL);
719	if (!pp->cpb_tbl)
720		return -ENOMEM;
721
722	init_port(ap);
723
724	return 0;
725}
726
727static struct ata_port_operations inic_port_ops = {
728	.inherits		= &sata_port_ops,
729
730	.check_atapi_dma	= inic_check_atapi_dma,
731	.qc_prep		= inic_qc_prep,
732	.qc_issue		= inic_qc_issue,
733	.qc_fill_rtf		= inic_qc_fill_rtf,
734
735	.freeze			= inic_freeze,
736	.thaw			= inic_thaw,
737	.hardreset		= inic_hardreset,
738	.error_handler		= inic_error_handler,
739	.post_internal_cmd	= inic_post_internal_cmd,
740
741	.scr_read		= inic_scr_read,
742	.scr_write		= inic_scr_write,
743
744	.port_resume		= inic_port_resume,
745	.port_start		= inic_port_start,
746};
747
748static const struct ata_port_info inic_port_info = {
749	.flags			= ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
750	.pio_mask		= ATA_PIO4,
751	.mwdma_mask		= ATA_MWDMA2,
752	.udma_mask		= ATA_UDMA6,
753	.port_ops		= &inic_port_ops
754};
755
756static int init_controller(void __iomem *mmio_base, u16 hctl)
757{
758	int i;
759	u16 val;
760
761	hctl &= ~HCTL_KNOWN_BITS;
762
763	/* Soft reset whole controller.  Spec says reset duration is 3
764	 * PCI clocks, be generous and give it 10ms.
765	 */
766	writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
767	readw(mmio_base + HOST_CTL); /* flush */
768
769	for (i = 0; i < 10; i++) {
770		msleep(1);
771		val = readw(mmio_base + HOST_CTL);
772		if (!(val & HCTL_SOFTRST))
773			break;
774	}
775
776	if (val & HCTL_SOFTRST)
777		return -EIO;
778
779	/* mask all interrupts and reset ports */
780	for (i = 0; i < NR_PORTS; i++) {
781		void __iomem *port_base = mmio_base + i * PORT_SIZE;
782
783		writeb(0xff, port_base + PORT_IRQ_MASK);
784		inic_reset_port(port_base);
785	}
786
787	/* port IRQ is masked now, unmask global IRQ */
788	writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
789	val = readw(mmio_base + HOST_IRQ_MASK);
790	val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
791	writew(val, mmio_base + HOST_IRQ_MASK);
792
793	return 0;
794}
795
796#ifdef CONFIG_PM_SLEEP
797static int inic_pci_device_resume(struct pci_dev *pdev)
798{
799	struct ata_host *host = pci_get_drvdata(pdev);
800	struct inic_host_priv *hpriv = host->private_data;
801	int rc;
802
803	rc = ata_pci_device_do_resume(pdev);
804	if (rc)
805		return rc;
806
807	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
808		rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
809		if (rc)
810			return rc;
811	}
812
813	ata_host_resume(host);
814
815	return 0;
816}
817#endif
818
819static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
820{
821	const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
822	struct ata_host *host;
823	struct inic_host_priv *hpriv;
824	void __iomem * const *iomap;
825	int mmio_bar;
826	int i, rc;
827
828	ata_print_version_once(&pdev->dev, DRV_VERSION);
829
830	dev_alert(&pdev->dev, "inic162x support is broken with common data corruption issues and will be disabled by default, contact linux-ide@vger.kernel.org if in production use\n");
831
832	/* alloc host */
833	host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
834	hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
835	if (!host || !hpriv)
836		return -ENOMEM;
837
838	host->private_data = hpriv;
839
840	/* Acquire resources and fill host.  Note that PCI and cardbus
841	 * use different BARs.
842	 */
843	rc = pcim_enable_device(pdev);
844	if (rc)
845		return rc;
846
847	if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM)
848		mmio_bar = MMIO_BAR_PCI;
849	else
850		mmio_bar = MMIO_BAR_CARDBUS;
851
852	rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME);
853	if (rc)
854		return rc;
855	host->iomap = iomap = pcim_iomap_table(pdev);
856	hpriv->mmio_base = iomap[mmio_bar];
857	hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL);
858
859	for (i = 0; i < NR_PORTS; i++) {
860		struct ata_port *ap = host->ports[i];
861
862		ata_port_pbar_desc(ap, mmio_bar, -1, "mmio");
863		ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port");
864	}
865
866	/* Set dma_mask.  This devices doesn't support 64bit addressing. */
867	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
868	if (rc) {
869		dev_err(&pdev->dev, "32-bit DMA enable failed\n");
870		return rc;
871	}
872
873	rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
874	if (rc) {
875		dev_err(&pdev->dev, "failed to initialize controller\n");
876		return rc;
877	}
878
879	pci_set_master(pdev);
880	return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
881				 &inic_sht);
882}
883
884static const struct pci_device_id inic_pci_tbl[] = {
885	{ PCI_VDEVICE(INIT, 0x1622), },
886	{ },
887};
888
889static struct pci_driver inic_pci_driver = {
890	.name 		= DRV_NAME,
891	.id_table	= inic_pci_tbl,
892#ifdef CONFIG_PM_SLEEP
893	.suspend	= ata_pci_device_suspend,
894	.resume		= inic_pci_device_resume,
895#endif
896	.probe 		= inic_init_one,
897	.remove		= ata_pci_remove_one,
898};
899
900module_pci_driver(inic_pci_driver);
901
902MODULE_AUTHOR("Tejun Heo");
903MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
904MODULE_LICENSE("GPL v2");
905MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
906MODULE_VERSION(DRV_VERSION);