Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2
3/*
4 * acard-ahci.c - ACard AHCI SATA support
5 *
6 * Maintained by: Tejun Heo <tj@kernel.org>
7 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * on emails.
9 *
10 * Copyright 2010 Red Hat, Inc.
11 *
12 * libata documentation is available via 'make {ps|pdf}docs',
13 * as Documentation/driver-api/libata.rst
14 *
15 * AHCI hardware documentation:
16 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
17 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
27#include <linux/device.h>
28#include <linux/dmi.h>
29#include <linux/gfp.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_cmnd.h>
32#include <linux/libata.h>
33#include "ahci.h"
34
35#define DRV_NAME "acard-ahci"
36#define DRV_VERSION "1.0"
37
38/*
39 Received FIS structure limited to 80h.
40*/
41
42#define ACARD_AHCI_RX_FIS_SZ 128
43
44enum {
45 AHCI_PCI_BAR = 5,
46};
47
48enum board_ids {
49 board_acard_ahci,
50};
51
52struct acard_sg {
53 __le32 addr;
54 __le32 addr_hi;
55 __le32 reserved;
56 __le32 size; /* bit 31 (EOT) max==0x10000 (64k) */
57};
58
59static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc);
60static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
61static int acard_ahci_port_start(struct ata_port *ap);
62static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
63
64#ifdef CONFIG_PM_SLEEP
65static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
66static int acard_ahci_pci_device_resume(struct pci_dev *pdev);
67#endif
68
69static struct scsi_host_template acard_ahci_sht = {
70 AHCI_SHT("acard-ahci"),
71};
72
73static struct ata_port_operations acard_ops = {
74 .inherits = &ahci_ops,
75 .qc_prep = acard_ahci_qc_prep,
76 .qc_fill_rtf = acard_ahci_qc_fill_rtf,
77 .port_start = acard_ahci_port_start,
78};
79
80#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
81
82static const struct ata_port_info acard_ahci_port_info[] = {
83 [board_acard_ahci] =
84 {
85 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
86 .flags = AHCI_FLAG_COMMON,
87 .pio_mask = ATA_PIO4,
88 .udma_mask = ATA_UDMA6,
89 .port_ops = &acard_ops,
90 },
91};
92
93static const struct pci_device_id acard_ahci_pci_tbl[] = {
94 /* ACard */
95 { PCI_VDEVICE(ARTOP, 0x000d), board_acard_ahci }, /* ATP8620 */
96
97 { } /* terminate list */
98};
99
100static struct pci_driver acard_ahci_pci_driver = {
101 .name = DRV_NAME,
102 .id_table = acard_ahci_pci_tbl,
103 .probe = acard_ahci_init_one,
104 .remove = ata_pci_remove_one,
105#ifdef CONFIG_PM_SLEEP
106 .suspend = acard_ahci_pci_device_suspend,
107 .resume = acard_ahci_pci_device_resume,
108#endif
109};
110
111#ifdef CONFIG_PM_SLEEP
112static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
113{
114 struct ata_host *host = pci_get_drvdata(pdev);
115 struct ahci_host_priv *hpriv = host->private_data;
116 void __iomem *mmio = hpriv->mmio;
117 u32 ctl;
118
119 if (mesg.event & PM_EVENT_SUSPEND &&
120 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
121 dev_err(&pdev->dev,
122 "BIOS update required for suspend/resume\n");
123 return -EIO;
124 }
125
126 if (mesg.event & PM_EVENT_SLEEP) {
127 /* AHCI spec rev1.1 section 8.3.3:
128 * Software must disable interrupts prior to requesting a
129 * transition of the HBA to D3 state.
130 */
131 ctl = readl(mmio + HOST_CTL);
132 ctl &= ~HOST_IRQ_EN;
133 writel(ctl, mmio + HOST_CTL);
134 readl(mmio + HOST_CTL); /* flush */
135 }
136
137 return ata_pci_device_suspend(pdev, mesg);
138}
139
140static int acard_ahci_pci_device_resume(struct pci_dev *pdev)
141{
142 struct ata_host *host = pci_get_drvdata(pdev);
143 int rc;
144
145 rc = ata_pci_device_do_resume(pdev);
146 if (rc)
147 return rc;
148
149 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
150 rc = ahci_reset_controller(host);
151 if (rc)
152 return rc;
153
154 ahci_init_controller(host);
155 }
156
157 ata_host_resume(host);
158
159 return 0;
160}
161#endif
162
163static void acard_ahci_pci_print_info(struct ata_host *host)
164{
165 struct pci_dev *pdev = to_pci_dev(host->dev);
166 u16 cc;
167 const char *scc_s;
168
169 pci_read_config_word(pdev, 0x0a, &cc);
170 if (cc == PCI_CLASS_STORAGE_IDE)
171 scc_s = "IDE";
172 else if (cc == PCI_CLASS_STORAGE_SATA)
173 scc_s = "SATA";
174 else if (cc == PCI_CLASS_STORAGE_RAID)
175 scc_s = "RAID";
176 else
177 scc_s = "unknown";
178
179 ahci_print_info(host, scc_s);
180}
181
182static unsigned int acard_ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
183{
184 struct scatterlist *sg;
185 struct acard_sg *acard_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
186 unsigned int si, last_si = 0;
187
188 VPRINTK("ENTER\n");
189
190 /*
191 * Next, the S/G list.
192 */
193 for_each_sg(qc->sg, sg, qc->n_elem, si) {
194 dma_addr_t addr = sg_dma_address(sg);
195 u32 sg_len = sg_dma_len(sg);
196
197 /*
198 * ACard note:
199 * We must set an end-of-table (EOT) bit,
200 * and the segment cannot exceed 64k (0x10000)
201 */
202 acard_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
203 acard_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
204 acard_sg[si].size = cpu_to_le32(sg_len);
205 last_si = si;
206 }
207
208 acard_sg[last_si].size |= cpu_to_le32(1 << 31); /* set EOT */
209
210 return si;
211}
212
213static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc)
214{
215 struct ata_port *ap = qc->ap;
216 struct ahci_port_priv *pp = ap->private_data;
217 int is_atapi = ata_is_atapi(qc->tf.protocol);
218 void *cmd_tbl;
219 u32 opts;
220 const u32 cmd_fis_len = 5; /* five dwords */
221
222 /*
223 * Fill in command table information. First, the header,
224 * a SATA Register - Host to Device command FIS.
225 */
226 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
227
228 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
229 if (is_atapi) {
230 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
231 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
232 }
233
234 if (qc->flags & ATA_QCFLAG_DMAMAP)
235 acard_ahci_fill_sg(qc, cmd_tbl);
236
237 /*
238 * Fill in command slot information.
239 *
240 * ACard note: prd table length not filled in
241 */
242 opts = cmd_fis_len | (qc->dev->link->pmp << 12);
243 if (qc->tf.flags & ATA_TFLAG_WRITE)
244 opts |= AHCI_CMD_WRITE;
245 if (is_atapi)
246 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
247
248 ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
249
250 return AC_ERR_OK;
251}
252
253static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
254{
255 struct ahci_port_priv *pp = qc->ap->private_data;
256 u8 *rx_fis = pp->rx_fis;
257
258 if (pp->fbs_enabled)
259 rx_fis += qc->dev->link->pmp * ACARD_AHCI_RX_FIS_SZ;
260
261 /*
262 * After a successful execution of an ATA PIO data-in command,
263 * the device doesn't send D2H Reg FIS to update the TF and
264 * the host should take TF and E_Status from the preceding PIO
265 * Setup FIS.
266 */
267 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
268 !(qc->flags & ATA_QCFLAG_FAILED)) {
269 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
270 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
271 } else
272 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
273
274 return true;
275}
276
277static int acard_ahci_port_start(struct ata_port *ap)
278{
279 struct ahci_host_priv *hpriv = ap->host->private_data;
280 struct device *dev = ap->host->dev;
281 struct ahci_port_priv *pp;
282 void *mem;
283 dma_addr_t mem_dma;
284 size_t dma_sz, rx_fis_sz;
285
286 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
287 if (!pp)
288 return -ENOMEM;
289
290 /* check FBS capability */
291 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
292 void __iomem *port_mmio = ahci_port_base(ap);
293 u32 cmd = readl(port_mmio + PORT_CMD);
294 if (cmd & PORT_CMD_FBSCP)
295 pp->fbs_supported = true;
296 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
297 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
298 ap->port_no);
299 pp->fbs_supported = true;
300 } else
301 dev_warn(dev, "port %d is not capable of FBS\n",
302 ap->port_no);
303 }
304
305 if (pp->fbs_supported) {
306 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
307 rx_fis_sz = ACARD_AHCI_RX_FIS_SZ * 16;
308 } else {
309 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
310 rx_fis_sz = ACARD_AHCI_RX_FIS_SZ;
311 }
312
313 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
314 if (!mem)
315 return -ENOMEM;
316
317 /*
318 * First item in chunk of DMA memory: 32-slot command table,
319 * 32 bytes each in size
320 */
321 pp->cmd_slot = mem;
322 pp->cmd_slot_dma = mem_dma;
323
324 mem += AHCI_CMD_SLOT_SZ;
325 mem_dma += AHCI_CMD_SLOT_SZ;
326
327 /*
328 * Second item: Received-FIS area
329 */
330 pp->rx_fis = mem;
331 pp->rx_fis_dma = mem_dma;
332
333 mem += rx_fis_sz;
334 mem_dma += rx_fis_sz;
335
336 /*
337 * Third item: data area for storing a single command
338 * and its scatter-gather table
339 */
340 pp->cmd_tbl = mem;
341 pp->cmd_tbl_dma = mem_dma;
342
343 /*
344 * Save off initial list of interrupts to be enabled.
345 * This could be changed later
346 */
347 pp->intr_mask = DEF_PORT_IRQ;
348
349 ap->private_data = pp;
350
351 /* engage engines, captain */
352 return ahci_port_resume(ap);
353}
354
355static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
356{
357 unsigned int board_id = ent->driver_data;
358 struct ata_port_info pi = acard_ahci_port_info[board_id];
359 const struct ata_port_info *ppi[] = { &pi, NULL };
360 struct device *dev = &pdev->dev;
361 struct ahci_host_priv *hpriv;
362 struct ata_host *host;
363 int n_ports, i, rc;
364
365 VPRINTK("ENTER\n");
366
367 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
368
369 ata_print_version_once(&pdev->dev, DRV_VERSION);
370
371 /* acquire resources */
372 rc = pcim_enable_device(pdev);
373 if (rc)
374 return rc;
375
376 /* AHCI controllers often implement SFF compatible interface.
377 * Grab all PCI BARs just in case.
378 */
379 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
380 if (rc == -EBUSY)
381 pcim_pin_device(pdev);
382 if (rc)
383 return rc;
384
385 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
386 if (!hpriv)
387 return -ENOMEM;
388
389 hpriv->irq = pdev->irq;
390 hpriv->flags |= (unsigned long)pi.private_data;
391
392 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
393 pci_enable_msi(pdev);
394
395 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
396
397 /* save initial config */
398 ahci_save_initial_config(&pdev->dev, hpriv);
399
400 /* prepare host */
401 if (hpriv->cap & HOST_CAP_NCQ)
402 pi.flags |= ATA_FLAG_NCQ;
403
404 if (hpriv->cap & HOST_CAP_PMP)
405 pi.flags |= ATA_FLAG_PMP;
406
407 ahci_set_em_messages(hpriv, &pi);
408
409 /* CAP.NP sometimes indicate the index of the last enabled
410 * port, at other times, that of the last possible port, so
411 * determining the maximum port number requires looking at
412 * both CAP.NP and port_map.
413 */
414 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
415
416 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
417 if (!host)
418 return -ENOMEM;
419 host->private_data = hpriv;
420
421 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
422 host->flags |= ATA_HOST_PARALLEL_SCAN;
423 else
424 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
425
426 for (i = 0; i < host->n_ports; i++) {
427 struct ata_port *ap = host->ports[i];
428
429 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
430 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
431 0x100 + ap->port_no * 0x80, "port");
432
433 /* set initial link pm policy */
434 /*
435 ap->pm_policy = NOT_AVAILABLE;
436 */
437 /* disabled/not-implemented port */
438 if (!(hpriv->port_map & (1 << i)))
439 ap->ops = &ata_dummy_port_ops;
440 }
441
442 /* initialize adapter */
443 rc = dma_set_mask_and_coherent(&pdev->dev,
444 DMA_BIT_MASK((hpriv->cap & HOST_CAP_64) ? 64 : 32));
445 if (rc) {
446 dev_err(&pdev->dev, "DMA enable failed\n");
447 return rc;
448 }
449
450 rc = ahci_reset_controller(host);
451 if (rc)
452 return rc;
453
454 ahci_init_controller(host);
455 acard_ahci_pci_print_info(host);
456
457 pci_set_master(pdev);
458 return ahci_host_activate(host, &acard_ahci_sht);
459}
460
461module_pci_driver(acard_ahci_pci_driver);
462
463MODULE_AUTHOR("Jeff Garzik");
464MODULE_DESCRIPTION("ACard AHCI SATA low-level driver");
465MODULE_LICENSE("GPL");
466MODULE_DEVICE_TABLE(pci, acard_ahci_pci_tbl);
467MODULE_VERSION(DRV_VERSION);
1// SPDX-License-Identifier: GPL-2.0-or-later
2
3/*
4 * acard-ahci.c - ACard AHCI SATA support
5 *
6 * Maintained by: Tejun Heo <tj@kernel.org>
7 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * on emails.
9 *
10 * Copyright 2010 Red Hat, Inc.
11 *
12 * libata documentation is available via 'make {ps|pdf}docs',
13 * as Documentation/driver-api/libata.rst
14 *
15 * AHCI hardware documentation:
16 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
17 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
27#include <linux/device.h>
28#include <linux/dmi.h>
29#include <linux/gfp.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_cmnd.h>
32#include <linux/libata.h>
33#include "ahci.h"
34
35#define DRV_NAME "acard-ahci"
36#define DRV_VERSION "1.0"
37
38/*
39 Received FIS structure limited to 80h.
40*/
41
42#define ACARD_AHCI_RX_FIS_SZ 128
43
44enum {
45 AHCI_PCI_BAR = 5,
46};
47
48enum board_ids {
49 board_acard_ahci,
50};
51
52struct acard_sg {
53 __le32 addr;
54 __le32 addr_hi;
55 __le32 reserved;
56 __le32 size; /* bit 31 (EOT) max==0x10000 (64k) */
57};
58
59static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc);
60static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
61static int acard_ahci_port_start(struct ata_port *ap);
62static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
63
64#ifdef CONFIG_PM_SLEEP
65static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
66static int acard_ahci_pci_device_resume(struct pci_dev *pdev);
67#endif
68
69static struct scsi_host_template acard_ahci_sht = {
70 AHCI_SHT("acard-ahci"),
71};
72
73static struct ata_port_operations acard_ops = {
74 .inherits = &ahci_ops,
75 .qc_prep = acard_ahci_qc_prep,
76 .qc_fill_rtf = acard_ahci_qc_fill_rtf,
77 .port_start = acard_ahci_port_start,
78};
79
80#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
81
82static const struct ata_port_info acard_ahci_port_info[] = {
83 [board_acard_ahci] =
84 {
85 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
86 .flags = AHCI_FLAG_COMMON,
87 .pio_mask = ATA_PIO4,
88 .udma_mask = ATA_UDMA6,
89 .port_ops = &acard_ops,
90 },
91};
92
93static const struct pci_device_id acard_ahci_pci_tbl[] = {
94 /* ACard */
95 { PCI_VDEVICE(ARTOP, 0x000d), board_acard_ahci }, /* ATP8620 */
96
97 { } /* terminate list */
98};
99
100static struct pci_driver acard_ahci_pci_driver = {
101 .name = DRV_NAME,
102 .id_table = acard_ahci_pci_tbl,
103 .probe = acard_ahci_init_one,
104 .remove = ata_pci_remove_one,
105#ifdef CONFIG_PM_SLEEP
106 .suspend = acard_ahci_pci_device_suspend,
107 .resume = acard_ahci_pci_device_resume,
108#endif
109};
110
111#ifdef CONFIG_PM_SLEEP
112static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
113{
114 struct ata_host *host = pci_get_drvdata(pdev);
115 struct ahci_host_priv *hpriv = host->private_data;
116 void __iomem *mmio = hpriv->mmio;
117 u32 ctl;
118
119 if (mesg.event & PM_EVENT_SUSPEND &&
120 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
121 dev_err(&pdev->dev,
122 "BIOS update required for suspend/resume\n");
123 return -EIO;
124 }
125
126 if (mesg.event & PM_EVENT_SLEEP) {
127 /* AHCI spec rev1.1 section 8.3.3:
128 * Software must disable interrupts prior to requesting a
129 * transition of the HBA to D3 state.
130 */
131 ctl = readl(mmio + HOST_CTL);
132 ctl &= ~HOST_IRQ_EN;
133 writel(ctl, mmio + HOST_CTL);
134 readl(mmio + HOST_CTL); /* flush */
135 }
136
137 return ata_pci_device_suspend(pdev, mesg);
138}
139
140static int acard_ahci_pci_device_resume(struct pci_dev *pdev)
141{
142 struct ata_host *host = pci_get_drvdata(pdev);
143 int rc;
144
145 rc = ata_pci_device_do_resume(pdev);
146 if (rc)
147 return rc;
148
149 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
150 rc = ahci_reset_controller(host);
151 if (rc)
152 return rc;
153
154 ahci_init_controller(host);
155 }
156
157 ata_host_resume(host);
158
159 return 0;
160}
161#endif
162
163static void acard_ahci_pci_print_info(struct ata_host *host)
164{
165 struct pci_dev *pdev = to_pci_dev(host->dev);
166 u16 cc;
167 const char *scc_s;
168
169 pci_read_config_word(pdev, 0x0a, &cc);
170 if (cc == PCI_CLASS_STORAGE_IDE)
171 scc_s = "IDE";
172 else if (cc == PCI_CLASS_STORAGE_SATA)
173 scc_s = "SATA";
174 else if (cc == PCI_CLASS_STORAGE_RAID)
175 scc_s = "RAID";
176 else
177 scc_s = "unknown";
178
179 ahci_print_info(host, scc_s);
180}
181
182static unsigned int acard_ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
183{
184 struct scatterlist *sg;
185 struct acard_sg *acard_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
186 unsigned int si, last_si = 0;
187
188 /*
189 * Next, the S/G list.
190 */
191 for_each_sg(qc->sg, sg, qc->n_elem, si) {
192 dma_addr_t addr = sg_dma_address(sg);
193 u32 sg_len = sg_dma_len(sg);
194
195 /*
196 * ACard note:
197 * We must set an end-of-table (EOT) bit,
198 * and the segment cannot exceed 64k (0x10000)
199 */
200 acard_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
201 acard_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
202 acard_sg[si].size = cpu_to_le32(sg_len);
203 last_si = si;
204 }
205
206 acard_sg[last_si].size |= cpu_to_le32(1 << 31); /* set EOT */
207
208 return si;
209}
210
211static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc)
212{
213 struct ata_port *ap = qc->ap;
214 struct ahci_port_priv *pp = ap->private_data;
215 int is_atapi = ata_is_atapi(qc->tf.protocol);
216 void *cmd_tbl;
217 u32 opts;
218 const u32 cmd_fis_len = 5; /* five dwords */
219
220 /*
221 * Fill in command table information. First, the header,
222 * a SATA Register - Host to Device command FIS.
223 */
224 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
225
226 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
227 if (is_atapi) {
228 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
229 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
230 }
231
232 if (qc->flags & ATA_QCFLAG_DMAMAP)
233 acard_ahci_fill_sg(qc, cmd_tbl);
234
235 /*
236 * Fill in command slot information.
237 *
238 * ACard note: prd table length not filled in
239 */
240 opts = cmd_fis_len | (qc->dev->link->pmp << 12);
241 if (qc->tf.flags & ATA_TFLAG_WRITE)
242 opts |= AHCI_CMD_WRITE;
243 if (is_atapi)
244 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
245
246 ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
247
248 return AC_ERR_OK;
249}
250
251static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
252{
253 struct ahci_port_priv *pp = qc->ap->private_data;
254 u8 *rx_fis = pp->rx_fis;
255
256 if (pp->fbs_enabled)
257 rx_fis += qc->dev->link->pmp * ACARD_AHCI_RX_FIS_SZ;
258
259 /*
260 * After a successful execution of an ATA PIO data-in command,
261 * the device doesn't send D2H Reg FIS to update the TF and
262 * the host should take TF and E_Status from the preceding PIO
263 * Setup FIS.
264 */
265 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
266 !(qc->flags & ATA_QCFLAG_FAILED)) {
267 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
268 qc->result_tf.status = (rx_fis + RX_FIS_PIO_SETUP)[15];
269 } else
270 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
271
272 return true;
273}
274
275static int acard_ahci_port_start(struct ata_port *ap)
276{
277 struct ahci_host_priv *hpriv = ap->host->private_data;
278 struct device *dev = ap->host->dev;
279 struct ahci_port_priv *pp;
280 void *mem;
281 dma_addr_t mem_dma;
282 size_t dma_sz, rx_fis_sz;
283
284 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
285 if (!pp)
286 return -ENOMEM;
287
288 /* check FBS capability */
289 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
290 void __iomem *port_mmio = ahci_port_base(ap);
291 u32 cmd = readl(port_mmio + PORT_CMD);
292 if (cmd & PORT_CMD_FBSCP)
293 pp->fbs_supported = true;
294 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
295 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
296 ap->port_no);
297 pp->fbs_supported = true;
298 } else
299 dev_warn(dev, "port %d is not capable of FBS\n",
300 ap->port_no);
301 }
302
303 if (pp->fbs_supported) {
304 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
305 rx_fis_sz = ACARD_AHCI_RX_FIS_SZ * 16;
306 } else {
307 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
308 rx_fis_sz = ACARD_AHCI_RX_FIS_SZ;
309 }
310
311 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
312 if (!mem)
313 return -ENOMEM;
314
315 /*
316 * First item in chunk of DMA memory: 32-slot command table,
317 * 32 bytes each in size
318 */
319 pp->cmd_slot = mem;
320 pp->cmd_slot_dma = mem_dma;
321
322 mem += AHCI_CMD_SLOT_SZ;
323 mem_dma += AHCI_CMD_SLOT_SZ;
324
325 /*
326 * Second item: Received-FIS area
327 */
328 pp->rx_fis = mem;
329 pp->rx_fis_dma = mem_dma;
330
331 mem += rx_fis_sz;
332 mem_dma += rx_fis_sz;
333
334 /*
335 * Third item: data area for storing a single command
336 * and its scatter-gather table
337 */
338 pp->cmd_tbl = mem;
339 pp->cmd_tbl_dma = mem_dma;
340
341 /*
342 * Save off initial list of interrupts to be enabled.
343 * This could be changed later
344 */
345 pp->intr_mask = DEF_PORT_IRQ;
346
347 ap->private_data = pp;
348
349 /* engage engines, captain */
350 return ahci_port_resume(ap);
351}
352
353static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
354{
355 unsigned int board_id = ent->driver_data;
356 struct ata_port_info pi = acard_ahci_port_info[board_id];
357 const struct ata_port_info *ppi[] = { &pi, NULL };
358 struct device *dev = &pdev->dev;
359 struct ahci_host_priv *hpriv;
360 struct ata_host *host;
361 int n_ports, i, rc;
362
363 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
364
365 ata_print_version_once(&pdev->dev, DRV_VERSION);
366
367 /* acquire resources */
368 rc = pcim_enable_device(pdev);
369 if (rc)
370 return rc;
371
372 /* AHCI controllers often implement SFF compatible interface.
373 * Grab all PCI BARs just in case.
374 */
375 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
376 if (rc == -EBUSY)
377 pcim_pin_device(pdev);
378 if (rc)
379 return rc;
380
381 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
382 if (!hpriv)
383 return -ENOMEM;
384
385 hpriv->irq = pdev->irq;
386 hpriv->flags |= (unsigned long)pi.private_data;
387
388 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
389 pci_enable_msi(pdev);
390
391 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
392
393 /* save initial config */
394 ahci_save_initial_config(&pdev->dev, hpriv);
395
396 /* prepare host */
397 if (hpriv->cap & HOST_CAP_NCQ)
398 pi.flags |= ATA_FLAG_NCQ;
399
400 if (hpriv->cap & HOST_CAP_PMP)
401 pi.flags |= ATA_FLAG_PMP;
402
403 ahci_set_em_messages(hpriv, &pi);
404
405 /* CAP.NP sometimes indicate the index of the last enabled
406 * port, at other times, that of the last possible port, so
407 * determining the maximum port number requires looking at
408 * both CAP.NP and port_map.
409 */
410 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
411
412 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
413 if (!host)
414 return -ENOMEM;
415 host->private_data = hpriv;
416
417 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
418 host->flags |= ATA_HOST_PARALLEL_SCAN;
419 else
420 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
421
422 for (i = 0; i < host->n_ports; i++) {
423 struct ata_port *ap = host->ports[i];
424
425 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
426 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
427 0x100 + ap->port_no * 0x80, "port");
428
429 /* set initial link pm policy */
430 /*
431 ap->pm_policy = NOT_AVAILABLE;
432 */
433 /* disabled/not-implemented port */
434 if (!(hpriv->port_map & (1 << i)))
435 ap->ops = &ata_dummy_port_ops;
436 }
437
438 /* initialize adapter */
439 rc = dma_set_mask_and_coherent(&pdev->dev,
440 DMA_BIT_MASK((hpriv->cap & HOST_CAP_64) ? 64 : 32));
441 if (rc) {
442 dev_err(&pdev->dev, "DMA enable failed\n");
443 return rc;
444 }
445
446 rc = ahci_reset_controller(host);
447 if (rc)
448 return rc;
449
450 ahci_init_controller(host);
451 acard_ahci_pci_print_info(host);
452
453 pci_set_master(pdev);
454 return ahci_host_activate(host, &acard_ahci_sht);
455}
456
457module_pci_driver(acard_ahci_pci_driver);
458
459MODULE_AUTHOR("Jeff Garzik");
460MODULE_DESCRIPTION("ACard AHCI SATA low-level driver");
461MODULE_LICENSE("GPL");
462MODULE_DEVICE_TABLE(pci, acard_ahci_pci_tbl);
463MODULE_VERSION(DRV_VERSION);