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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
4 *
5 * (C) Copyright 2014, 2015 Linaro Ltd.
6 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
7 *
8 * CPPC describes a few methods for controlling CPU performance using
9 * information from a per CPU table called CPC. This table is described in
10 * the ACPI v5.0+ specification. The table consists of a list of
11 * registers which may be memory mapped or hardware registers and also may
12 * include some static integer values.
13 *
14 * CPU performance is on an abstract continuous scale as against a discretized
15 * P-state scale which is tied to CPU frequency only. In brief, the basic
16 * operation involves:
17 *
18 * - OS makes a CPU performance request. (Can provide min and max bounds)
19 *
20 * - Platform (such as BMC) is free to optimize request within requested bounds
21 * depending on power/thermal budgets etc.
22 *
23 * - Platform conveys its decision back to OS
24 *
25 * The communication between OS and platform occurs through another medium
26 * called (PCC) Platform Communication Channel. This is a generic mailbox like
27 * mechanism which includes doorbell semantics to indicate register updates.
28 * See drivers/mailbox/pcc.c for details on PCC.
29 *
30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
31 * above specifications.
32 */
33
34#define pr_fmt(fmt) "ACPI CPPC: " fmt
35
36#include <linux/cpufreq.h>
37#include <linux/delay.h>
38#include <linux/iopoll.h>
39#include <linux/ktime.h>
40#include <linux/rwsem.h>
41#include <linux/wait.h>
42
43#include <acpi/cppc_acpi.h>
44
45struct cppc_pcc_data {
46 struct mbox_chan *pcc_channel;
47 void __iomem *pcc_comm_addr;
48 bool pcc_channel_acquired;
49 unsigned int deadline_us;
50 unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
51
52 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */
53 bool platform_owns_pcc; /* Ownership of PCC subspace */
54 unsigned int pcc_write_cnt; /* Running count of PCC write commands */
55
56 /*
57 * Lock to provide controlled access to the PCC channel.
58 *
59 * For performance critical usecases(currently cppc_set_perf)
60 * We need to take read_lock and check if channel belongs to OSPM
61 * before reading or writing to PCC subspace
62 * We need to take write_lock before transferring the channel
63 * ownership to the platform via a Doorbell
64 * This allows us to batch a number of CPPC requests if they happen
65 * to originate in about the same time
66 *
67 * For non-performance critical usecases(init)
68 * Take write_lock for all purposes which gives exclusive access
69 */
70 struct rw_semaphore pcc_lock;
71
72 /* Wait queue for CPUs whose requests were batched */
73 wait_queue_head_t pcc_write_wait_q;
74 ktime_t last_cmd_cmpl_time;
75 ktime_t last_mpar_reset;
76 int mpar_count;
77 int refcount;
78};
79
80/* Array to represent the PCC channel per subspace ID */
81static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
82/* The cpu_pcc_subspace_idx contains per CPU subspace ID */
83static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
84
85/*
86 * The cpc_desc structure contains the ACPI register details
87 * as described in the per CPU _CPC tables. The details
88 * include the type of register (e.g. PCC, System IO, FFH etc.)
89 * and destination addresses which lets us READ/WRITE CPU performance
90 * information using the appropriate I/O methods.
91 */
92static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
93
94/* pcc mapped address + header size + offset within PCC subspace */
95#define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
96 0x8 + (offs))
97
98/* Check if a CPC register is in PCC */
99#define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
100 (cpc)->cpc_entry.reg.space_id == \
101 ACPI_ADR_SPACE_PLATFORM_COMM)
102
103/* Evalutes to True if reg is a NULL register descriptor */
104#define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \
105 (reg)->address == 0 && \
106 (reg)->bit_width == 0 && \
107 (reg)->bit_offset == 0 && \
108 (reg)->access_width == 0)
109
110/* Evalutes to True if an optional cpc field is supported */
111#define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
112 !!(cpc)->cpc_entry.int_value : \
113 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
114/*
115 * Arbitrary Retries in case the remote processor is slow to respond
116 * to PCC commands. Keeping it high enough to cover emulators where
117 * the processors run painfully slow.
118 */
119#define NUM_RETRIES 500ULL
120
121struct cppc_attr {
122 struct attribute attr;
123 ssize_t (*show)(struct kobject *kobj,
124 struct attribute *attr, char *buf);
125 ssize_t (*store)(struct kobject *kobj,
126 struct attribute *attr, const char *c, ssize_t count);
127};
128
129#define define_one_cppc_ro(_name) \
130static struct cppc_attr _name = \
131__ATTR(_name, 0444, show_##_name, NULL)
132
133#define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
134
135#define show_cppc_data(access_fn, struct_name, member_name) \
136 static ssize_t show_##member_name(struct kobject *kobj, \
137 struct attribute *attr, char *buf) \
138 { \
139 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
140 struct struct_name st_name = {0}; \
141 int ret; \
142 \
143 ret = access_fn(cpc_ptr->cpu_id, &st_name); \
144 if (ret) \
145 return ret; \
146 \
147 return scnprintf(buf, PAGE_SIZE, "%llu\n", \
148 (u64)st_name.member_name); \
149 } \
150 define_one_cppc_ro(member_name)
151
152show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
153show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
154show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
155show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
156show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
157show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
158
159show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
160show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
161
162static ssize_t show_feedback_ctrs(struct kobject *kobj,
163 struct attribute *attr, char *buf)
164{
165 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
166 struct cppc_perf_fb_ctrs fb_ctrs = {0};
167 int ret;
168
169 ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
170 if (ret)
171 return ret;
172
173 return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
174 fb_ctrs.reference, fb_ctrs.delivered);
175}
176define_one_cppc_ro(feedback_ctrs);
177
178static struct attribute *cppc_attrs[] = {
179 &feedback_ctrs.attr,
180 &reference_perf.attr,
181 &wraparound_time.attr,
182 &highest_perf.attr,
183 &lowest_perf.attr,
184 &lowest_nonlinear_perf.attr,
185 &nominal_perf.attr,
186 &nominal_freq.attr,
187 &lowest_freq.attr,
188 NULL
189};
190
191static struct kobj_type cppc_ktype = {
192 .sysfs_ops = &kobj_sysfs_ops,
193 .default_attrs = cppc_attrs,
194};
195
196static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
197{
198 int ret, status;
199 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
200 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
201 pcc_ss_data->pcc_comm_addr;
202
203 if (!pcc_ss_data->platform_owns_pcc)
204 return 0;
205
206 /*
207 * Poll PCC status register every 3us(delay_us) for maximum of
208 * deadline_us(timeout_us) until PCC command complete bit is set(cond)
209 */
210 ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
211 status & PCC_CMD_COMPLETE_MASK, 3,
212 pcc_ss_data->deadline_us);
213
214 if (likely(!ret)) {
215 pcc_ss_data->platform_owns_pcc = false;
216 if (chk_err_bit && (status & PCC_ERROR_MASK))
217 ret = -EIO;
218 }
219
220 if (unlikely(ret))
221 pr_err("PCC check channel failed for ss: %d. ret=%d\n",
222 pcc_ss_id, ret);
223
224 return ret;
225}
226
227/*
228 * This function transfers the ownership of the PCC to the platform
229 * So it must be called while holding write_lock(pcc_lock)
230 */
231static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
232{
233 int ret = -EIO, i;
234 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
235 struct acpi_pcct_shared_memory *generic_comm_base =
236 (struct acpi_pcct_shared_memory *)pcc_ss_data->pcc_comm_addr;
237 unsigned int time_delta;
238
239 /*
240 * For CMD_WRITE we know for a fact the caller should have checked
241 * the channel before writing to PCC space
242 */
243 if (cmd == CMD_READ) {
244 /*
245 * If there are pending cpc_writes, then we stole the channel
246 * before write completion, so first send a WRITE command to
247 * platform
248 */
249 if (pcc_ss_data->pending_pcc_write_cmd)
250 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
251
252 ret = check_pcc_chan(pcc_ss_id, false);
253 if (ret)
254 goto end;
255 } else /* CMD_WRITE */
256 pcc_ss_data->pending_pcc_write_cmd = FALSE;
257
258 /*
259 * Handle the Minimum Request Turnaround Time(MRTT)
260 * "The minimum amount of time that OSPM must wait after the completion
261 * of a command before issuing the next command, in microseconds"
262 */
263 if (pcc_ss_data->pcc_mrtt) {
264 time_delta = ktime_us_delta(ktime_get(),
265 pcc_ss_data->last_cmd_cmpl_time);
266 if (pcc_ss_data->pcc_mrtt > time_delta)
267 udelay(pcc_ss_data->pcc_mrtt - time_delta);
268 }
269
270 /*
271 * Handle the non-zero Maximum Periodic Access Rate(MPAR)
272 * "The maximum number of periodic requests that the subspace channel can
273 * support, reported in commands per minute. 0 indicates no limitation."
274 *
275 * This parameter should be ideally zero or large enough so that it can
276 * handle maximum number of requests that all the cores in the system can
277 * collectively generate. If it is not, we will follow the spec and just
278 * not send the request to the platform after hitting the MPAR limit in
279 * any 60s window
280 */
281 if (pcc_ss_data->pcc_mpar) {
282 if (pcc_ss_data->mpar_count == 0) {
283 time_delta = ktime_ms_delta(ktime_get(),
284 pcc_ss_data->last_mpar_reset);
285 if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
286 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
287 pcc_ss_id);
288 ret = -EIO;
289 goto end;
290 }
291 pcc_ss_data->last_mpar_reset = ktime_get();
292 pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
293 }
294 pcc_ss_data->mpar_count--;
295 }
296
297 /* Write to the shared comm region. */
298 writew_relaxed(cmd, &generic_comm_base->command);
299
300 /* Flip CMD COMPLETE bit */
301 writew_relaxed(0, &generic_comm_base->status);
302
303 pcc_ss_data->platform_owns_pcc = true;
304
305 /* Ring doorbell */
306 ret = mbox_send_message(pcc_ss_data->pcc_channel, &cmd);
307 if (ret < 0) {
308 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
309 pcc_ss_id, cmd, ret);
310 goto end;
311 }
312
313 /* wait for completion and check for PCC errro bit */
314 ret = check_pcc_chan(pcc_ss_id, true);
315
316 if (pcc_ss_data->pcc_mrtt)
317 pcc_ss_data->last_cmd_cmpl_time = ktime_get();
318
319 if (pcc_ss_data->pcc_channel->mbox->txdone_irq)
320 mbox_chan_txdone(pcc_ss_data->pcc_channel, ret);
321 else
322 mbox_client_txdone(pcc_ss_data->pcc_channel, ret);
323
324end:
325 if (cmd == CMD_WRITE) {
326 if (unlikely(ret)) {
327 for_each_possible_cpu(i) {
328 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
329 if (!desc)
330 continue;
331
332 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
333 desc->write_cmd_status = ret;
334 }
335 }
336 pcc_ss_data->pcc_write_cnt++;
337 wake_up_all(&pcc_ss_data->pcc_write_wait_q);
338 }
339
340 return ret;
341}
342
343static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
344{
345 if (ret < 0)
346 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
347 *(u16 *)msg, ret);
348 else
349 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
350 *(u16 *)msg, ret);
351}
352
353static struct mbox_client cppc_mbox_cl = {
354 .tx_done = cppc_chan_tx_done,
355 .knows_txdone = true,
356};
357
358static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
359{
360 int result = -EFAULT;
361 acpi_status status = AE_OK;
362 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
363 struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
364 struct acpi_buffer state = {0, NULL};
365 union acpi_object *psd = NULL;
366 struct acpi_psd_package *pdomain;
367
368 status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
369 &buffer, ACPI_TYPE_PACKAGE);
370 if (status == AE_NOT_FOUND) /* _PSD is optional */
371 return 0;
372 if (ACPI_FAILURE(status))
373 return -ENODEV;
374
375 psd = buffer.pointer;
376 if (!psd || psd->package.count != 1) {
377 pr_debug("Invalid _PSD data\n");
378 goto end;
379 }
380
381 pdomain = &(cpc_ptr->domain_info);
382
383 state.length = sizeof(struct acpi_psd_package);
384 state.pointer = pdomain;
385
386 status = acpi_extract_package(&(psd->package.elements[0]),
387 &format, &state);
388 if (ACPI_FAILURE(status)) {
389 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
390 goto end;
391 }
392
393 if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
394 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
395 goto end;
396 }
397
398 if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
399 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
400 goto end;
401 }
402
403 if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
404 pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
405 pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
406 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
407 goto end;
408 }
409
410 result = 0;
411end:
412 kfree(buffer.pointer);
413 return result;
414}
415
416/**
417 * acpi_get_psd_map - Map the CPUs in a common freq domain.
418 * @all_cpu_data: Ptrs to CPU specific CPPC data including PSD info.
419 *
420 * Return: 0 for success or negative value for err.
421 */
422int acpi_get_psd_map(struct cppc_cpudata **all_cpu_data)
423{
424 int count_target;
425 int retval = 0;
426 unsigned int i, j;
427 cpumask_var_t covered_cpus;
428 struct cppc_cpudata *pr, *match_pr;
429 struct acpi_psd_package *pdomain;
430 struct acpi_psd_package *match_pdomain;
431 struct cpc_desc *cpc_ptr, *match_cpc_ptr;
432
433 if (!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL))
434 return -ENOMEM;
435
436 /*
437 * Now that we have _PSD data from all CPUs, let's setup P-state
438 * domain info.
439 */
440 for_each_possible_cpu(i) {
441 if (cpumask_test_cpu(i, covered_cpus))
442 continue;
443
444 pr = all_cpu_data[i];
445 cpc_ptr = per_cpu(cpc_desc_ptr, i);
446 if (!cpc_ptr) {
447 retval = -EFAULT;
448 goto err_ret;
449 }
450
451 pdomain = &(cpc_ptr->domain_info);
452 cpumask_set_cpu(i, pr->shared_cpu_map);
453 cpumask_set_cpu(i, covered_cpus);
454 if (pdomain->num_processors <= 1)
455 continue;
456
457 /* Validate the Domain info */
458 count_target = pdomain->num_processors;
459 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
460 pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
461 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
462 pr->shared_type = CPUFREQ_SHARED_TYPE_HW;
463 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
464 pr->shared_type = CPUFREQ_SHARED_TYPE_ANY;
465
466 for_each_possible_cpu(j) {
467 if (i == j)
468 continue;
469
470 match_cpc_ptr = per_cpu(cpc_desc_ptr, j);
471 if (!match_cpc_ptr) {
472 retval = -EFAULT;
473 goto err_ret;
474 }
475
476 match_pdomain = &(match_cpc_ptr->domain_info);
477 if (match_pdomain->domain != pdomain->domain)
478 continue;
479
480 /* Here i and j are in the same domain */
481 if (match_pdomain->num_processors != count_target) {
482 retval = -EFAULT;
483 goto err_ret;
484 }
485
486 if (pdomain->coord_type != match_pdomain->coord_type) {
487 retval = -EFAULT;
488 goto err_ret;
489 }
490
491 cpumask_set_cpu(j, covered_cpus);
492 cpumask_set_cpu(j, pr->shared_cpu_map);
493 }
494
495 for_each_cpu(j, pr->shared_cpu_map) {
496 if (i == j)
497 continue;
498
499 match_pr = all_cpu_data[j];
500 match_pr->shared_type = pr->shared_type;
501 cpumask_copy(match_pr->shared_cpu_map,
502 pr->shared_cpu_map);
503 }
504 }
505 goto out;
506
507err_ret:
508 for_each_possible_cpu(i) {
509 pr = all_cpu_data[i];
510
511 /* Assume no coordination on any error parsing domain info */
512 cpumask_clear(pr->shared_cpu_map);
513 cpumask_set_cpu(i, pr->shared_cpu_map);
514 pr->shared_type = CPUFREQ_SHARED_TYPE_ALL;
515 }
516out:
517 free_cpumask_var(covered_cpus);
518 return retval;
519}
520EXPORT_SYMBOL_GPL(acpi_get_psd_map);
521
522static int register_pcc_channel(int pcc_ss_idx)
523{
524 struct acpi_pcct_hw_reduced *cppc_ss;
525 u64 usecs_lat;
526
527 if (pcc_ss_idx >= 0) {
528 pcc_data[pcc_ss_idx]->pcc_channel =
529 pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
530
531 if (IS_ERR(pcc_data[pcc_ss_idx]->pcc_channel)) {
532 pr_err("Failed to find PCC channel for subspace %d\n",
533 pcc_ss_idx);
534 return -ENODEV;
535 }
536
537 /*
538 * The PCC mailbox controller driver should
539 * have parsed the PCCT (global table of all
540 * PCC channels) and stored pointers to the
541 * subspace communication region in con_priv.
542 */
543 cppc_ss = (pcc_data[pcc_ss_idx]->pcc_channel)->con_priv;
544
545 if (!cppc_ss) {
546 pr_err("No PCC subspace found for %d CPPC\n",
547 pcc_ss_idx);
548 return -ENODEV;
549 }
550
551 /*
552 * cppc_ss->latency is just a Nominal value. In reality
553 * the remote processor could be much slower to reply.
554 * So add an arbitrary amount of wait on top of Nominal.
555 */
556 usecs_lat = NUM_RETRIES * cppc_ss->latency;
557 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
558 pcc_data[pcc_ss_idx]->pcc_mrtt = cppc_ss->min_turnaround_time;
559 pcc_data[pcc_ss_idx]->pcc_mpar = cppc_ss->max_access_rate;
560 pcc_data[pcc_ss_idx]->pcc_nominal = cppc_ss->latency;
561
562 pcc_data[pcc_ss_idx]->pcc_comm_addr =
563 acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length);
564 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
565 pr_err("Failed to ioremap PCC comm region mem for %d\n",
566 pcc_ss_idx);
567 return -ENOMEM;
568 }
569
570 /* Set flag so that we don't come here for each CPU. */
571 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
572 }
573
574 return 0;
575}
576
577/**
578 * cpc_ffh_supported() - check if FFH reading supported
579 *
580 * Check if the architecture has support for functional fixed hardware
581 * read/write capability.
582 *
583 * Return: true for supported, false for not supported
584 */
585bool __weak cpc_ffh_supported(void)
586{
587 return false;
588}
589
590/**
591 * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
592 *
593 * Check and allocate the cppc_pcc_data memory.
594 * In some processor configurations it is possible that same subspace
595 * is shared between multiple CPUs. This is seen especially in CPUs
596 * with hardware multi-threading support.
597 *
598 * Return: 0 for success, errno for failure
599 */
600static int pcc_data_alloc(int pcc_ss_id)
601{
602 if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
603 return -EINVAL;
604
605 if (pcc_data[pcc_ss_id]) {
606 pcc_data[pcc_ss_id]->refcount++;
607 } else {
608 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
609 GFP_KERNEL);
610 if (!pcc_data[pcc_ss_id])
611 return -ENOMEM;
612 pcc_data[pcc_ss_id]->refcount++;
613 }
614
615 return 0;
616}
617
618/* Check if CPPC revision + num_ent combination is supported */
619static bool is_cppc_supported(int revision, int num_ent)
620{
621 int expected_num_ent;
622
623 switch (revision) {
624 case CPPC_V2_REV:
625 expected_num_ent = CPPC_V2_NUM_ENT;
626 break;
627 case CPPC_V3_REV:
628 expected_num_ent = CPPC_V3_NUM_ENT;
629 break;
630 default:
631 pr_debug("Firmware exports unsupported CPPC revision: %d\n",
632 revision);
633 return false;
634 }
635
636 if (expected_num_ent != num_ent) {
637 pr_debug("Firmware exports %d entries. Expected: %d for CPPC rev:%d\n",
638 num_ent, expected_num_ent, revision);
639 return false;
640 }
641
642 return true;
643}
644
645/*
646 * An example CPC table looks like the following.
647 *
648 * Name(_CPC, Package()
649 * {
650 * 17,
651 * NumEntries
652 * 1,
653 * // Revision
654 * ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
655 * // Highest Performance
656 * ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
657 * // Nominal Performance
658 * ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
659 * // Lowest Nonlinear Performance
660 * ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
661 * // Lowest Performance
662 * ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
663 * // Guaranteed Performance Register
664 * ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
665 * // Desired Performance Register
666 * ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)},
667 * ..
668 * ..
669 * ..
670 *
671 * }
672 * Each Register() encodes how to access that specific register.
673 * e.g. a sample PCC entry has the following encoding:
674 *
675 * Register (
676 * PCC,
677 * AddressSpaceKeyword
678 * 8,
679 * //RegisterBitWidth
680 * 8,
681 * //RegisterBitOffset
682 * 0x30,
683 * //RegisterAddress
684 * 9
685 * //AccessSize (subspace ID)
686 * 0
687 * )
688 * }
689 */
690
691/**
692 * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
693 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
694 *
695 * Return: 0 for success or negative value for err.
696 */
697int acpi_cppc_processor_probe(struct acpi_processor *pr)
698{
699 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
700 union acpi_object *out_obj, *cpc_obj;
701 struct cpc_desc *cpc_ptr;
702 struct cpc_reg *gas_t;
703 struct device *cpu_dev;
704 acpi_handle handle = pr->handle;
705 unsigned int num_ent, i, cpc_rev;
706 int pcc_subspace_id = -1;
707 acpi_status status;
708 int ret = -EFAULT;
709
710 /* Parse the ACPI _CPC table for this CPU. */
711 status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
712 ACPI_TYPE_PACKAGE);
713 if (ACPI_FAILURE(status)) {
714 ret = -ENODEV;
715 goto out_buf_free;
716 }
717
718 out_obj = (union acpi_object *) output.pointer;
719
720 cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
721 if (!cpc_ptr) {
722 ret = -ENOMEM;
723 goto out_buf_free;
724 }
725
726 /* First entry is NumEntries. */
727 cpc_obj = &out_obj->package.elements[0];
728 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
729 num_ent = cpc_obj->integer.value;
730 } else {
731 pr_debug("Unexpected entry type(%d) for NumEntries\n",
732 cpc_obj->type);
733 goto out_free;
734 }
735 cpc_ptr->num_entries = num_ent;
736
737 /* Second entry should be revision. */
738 cpc_obj = &out_obj->package.elements[1];
739 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
740 cpc_rev = cpc_obj->integer.value;
741 } else {
742 pr_debug("Unexpected entry type(%d) for Revision\n",
743 cpc_obj->type);
744 goto out_free;
745 }
746 cpc_ptr->version = cpc_rev;
747
748 if (!is_cppc_supported(cpc_rev, num_ent))
749 goto out_free;
750
751 /* Iterate through remaining entries in _CPC */
752 for (i = 2; i < num_ent; i++) {
753 cpc_obj = &out_obj->package.elements[i];
754
755 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
756 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
757 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
758 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
759 gas_t = (struct cpc_reg *)
760 cpc_obj->buffer.pointer;
761
762 /*
763 * The PCC Subspace index is encoded inside
764 * the CPC table entries. The same PCC index
765 * will be used for all the PCC entries,
766 * so extract it only once.
767 */
768 if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
769 if (pcc_subspace_id < 0) {
770 pcc_subspace_id = gas_t->access_width;
771 if (pcc_data_alloc(pcc_subspace_id))
772 goto out_free;
773 } else if (pcc_subspace_id != gas_t->access_width) {
774 pr_debug("Mismatched PCC ids.\n");
775 goto out_free;
776 }
777 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
778 if (gas_t->address) {
779 void __iomem *addr;
780
781 addr = ioremap(gas_t->address, gas_t->bit_width/8);
782 if (!addr)
783 goto out_free;
784 cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
785 }
786 } else {
787 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
788 /* Support only PCC ,SYS MEM and FFH type regs */
789 pr_debug("Unsupported register type: %d\n", gas_t->space_id);
790 goto out_free;
791 }
792 }
793
794 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
795 memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
796 } else {
797 pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id);
798 goto out_free;
799 }
800 }
801 per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
802
803 /*
804 * Initialize the remaining cpc_regs as unsupported.
805 * Example: In case FW exposes CPPC v2, the below loop will initialize
806 * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
807 */
808 for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
809 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
810 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
811 }
812
813
814 /* Store CPU Logical ID */
815 cpc_ptr->cpu_id = pr->id;
816
817 /* Parse PSD data for this CPU */
818 ret = acpi_get_psd(cpc_ptr, handle);
819 if (ret)
820 goto out_free;
821
822 /* Register PCC channel once for all PCC subspace ID. */
823 if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
824 ret = register_pcc_channel(pcc_subspace_id);
825 if (ret)
826 goto out_free;
827
828 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
829 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
830 }
831
832 /* Everything looks okay */
833 pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
834
835 /* Add per logical CPU nodes for reading its feedback counters. */
836 cpu_dev = get_cpu_device(pr->id);
837 if (!cpu_dev) {
838 ret = -EINVAL;
839 goto out_free;
840 }
841
842 /* Plug PSD data into this CPU's CPC descriptor. */
843 per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
844
845 ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
846 "acpi_cppc");
847 if (ret) {
848 per_cpu(cpc_desc_ptr, pr->id) = NULL;
849 kobject_put(&cpc_ptr->kobj);
850 goto out_free;
851 }
852
853 kfree(output.pointer);
854 return 0;
855
856out_free:
857 /* Free all the mapped sys mem areas for this CPU */
858 for (i = 2; i < cpc_ptr->num_entries; i++) {
859 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
860
861 if (addr)
862 iounmap(addr);
863 }
864 kfree(cpc_ptr);
865
866out_buf_free:
867 kfree(output.pointer);
868 return ret;
869}
870EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
871
872/**
873 * acpi_cppc_processor_exit - Cleanup CPC structs.
874 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
875 *
876 * Return: Void
877 */
878void acpi_cppc_processor_exit(struct acpi_processor *pr)
879{
880 struct cpc_desc *cpc_ptr;
881 unsigned int i;
882 void __iomem *addr;
883 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
884
885 if (pcc_ss_id >=0 && pcc_data[pcc_ss_id]) {
886 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
887 pcc_data[pcc_ss_id]->refcount--;
888 if (!pcc_data[pcc_ss_id]->refcount) {
889 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
890 kfree(pcc_data[pcc_ss_id]);
891 pcc_data[pcc_ss_id] = NULL;
892 }
893 }
894 }
895
896 cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
897 if (!cpc_ptr)
898 return;
899
900 /* Free all the mapped sys mem areas for this CPU */
901 for (i = 2; i < cpc_ptr->num_entries; i++) {
902 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
903 if (addr)
904 iounmap(addr);
905 }
906
907 kobject_put(&cpc_ptr->kobj);
908 kfree(cpc_ptr);
909}
910EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
911
912/**
913 * cpc_read_ffh() - Read FFH register
914 * @cpunum: CPU number to read
915 * @reg: cppc register information
916 * @val: place holder for return value
917 *
918 * Read bit_width bits from a specified address and bit_offset
919 *
920 * Return: 0 for success and error code
921 */
922int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
923{
924 return -ENOTSUPP;
925}
926
927/**
928 * cpc_write_ffh() - Write FFH register
929 * @cpunum: CPU number to write
930 * @reg: cppc register information
931 * @val: value to write
932 *
933 * Write value of bit_width bits to a specified address and bit_offset
934 *
935 * Return: 0 for success and error code
936 */
937int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
938{
939 return -ENOTSUPP;
940}
941
942/*
943 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
944 * as fast as possible. We have already mapped the PCC subspace during init, so
945 * we can directly write to it.
946 */
947
948static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
949{
950 int ret_val = 0;
951 void __iomem *vaddr = 0;
952 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
953 struct cpc_reg *reg = ®_res->cpc_entry.reg;
954
955 if (reg_res->type == ACPI_TYPE_INTEGER) {
956 *val = reg_res->cpc_entry.int_value;
957 return ret_val;
958 }
959
960 *val = 0;
961 if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
962 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
963 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
964 vaddr = reg_res->sys_mem_vaddr;
965 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
966 return cpc_read_ffh(cpu, reg, val);
967 else
968 return acpi_os_read_memory((acpi_physical_address)reg->address,
969 val, reg->bit_width);
970
971 switch (reg->bit_width) {
972 case 8:
973 *val = readb_relaxed(vaddr);
974 break;
975 case 16:
976 *val = readw_relaxed(vaddr);
977 break;
978 case 32:
979 *val = readl_relaxed(vaddr);
980 break;
981 case 64:
982 *val = readq_relaxed(vaddr);
983 break;
984 default:
985 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
986 reg->bit_width, pcc_ss_id);
987 ret_val = -EFAULT;
988 }
989
990 return ret_val;
991}
992
993static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
994{
995 int ret_val = 0;
996 void __iomem *vaddr = 0;
997 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
998 struct cpc_reg *reg = ®_res->cpc_entry.reg;
999
1000 if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
1001 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1002 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1003 vaddr = reg_res->sys_mem_vaddr;
1004 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1005 return cpc_write_ffh(cpu, reg, val);
1006 else
1007 return acpi_os_write_memory((acpi_physical_address)reg->address,
1008 val, reg->bit_width);
1009
1010 switch (reg->bit_width) {
1011 case 8:
1012 writeb_relaxed(val, vaddr);
1013 break;
1014 case 16:
1015 writew_relaxed(val, vaddr);
1016 break;
1017 case 32:
1018 writel_relaxed(val, vaddr);
1019 break;
1020 case 64:
1021 writeq_relaxed(val, vaddr);
1022 break;
1023 default:
1024 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
1025 reg->bit_width, pcc_ss_id);
1026 ret_val = -EFAULT;
1027 break;
1028 }
1029
1030 return ret_val;
1031}
1032
1033/**
1034 * cppc_get_desired_perf - Get the value of desired performance register.
1035 * @cpunum: CPU from which to get desired performance.
1036 * @desired_perf: address of a variable to store the returned desired performance
1037 *
1038 * Return: 0 for success, -EIO otherwise.
1039 */
1040int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
1041{
1042 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1043 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1044 struct cpc_register_resource *desired_reg;
1045 struct cppc_pcc_data *pcc_ss_data = NULL;
1046
1047 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1048
1049 if (CPC_IN_PCC(desired_reg)) {
1050 int ret = 0;
1051
1052 if (pcc_ss_id < 0)
1053 return -EIO;
1054
1055 pcc_ss_data = pcc_data[pcc_ss_id];
1056
1057 down_write(&pcc_ss_data->pcc_lock);
1058
1059 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
1060 cpc_read(cpunum, desired_reg, desired_perf);
1061 else
1062 ret = -EIO;
1063
1064 up_write(&pcc_ss_data->pcc_lock);
1065
1066 return ret;
1067 }
1068
1069 cpc_read(cpunum, desired_reg, desired_perf);
1070
1071 return 0;
1072}
1073EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
1074
1075/**
1076 * cppc_get_perf_caps - Get a CPU's performance capabilities.
1077 * @cpunum: CPU from which to get capabilities info.
1078 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1079 *
1080 * Return: 0 for success with perf_caps populated else -ERRNO.
1081 */
1082int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1083{
1084 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1085 struct cpc_register_resource *highest_reg, *lowest_reg,
1086 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
1087 *low_freq_reg = NULL, *nom_freq_reg = NULL;
1088 u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
1089 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1090 struct cppc_pcc_data *pcc_ss_data = NULL;
1091 int ret = 0, regs_in_pcc = 0;
1092
1093 if (!cpc_desc) {
1094 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1095 return -ENODEV;
1096 }
1097
1098 highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1099 lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1100 lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1101 nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1102 low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
1103 nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
1104 guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
1105
1106 /* Are any of the regs PCC ?*/
1107 if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
1108 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
1109 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
1110 if (pcc_ss_id < 0) {
1111 pr_debug("Invalid pcc_ss_id\n");
1112 return -ENODEV;
1113 }
1114 pcc_ss_data = pcc_data[pcc_ss_id];
1115 regs_in_pcc = 1;
1116 down_write(&pcc_ss_data->pcc_lock);
1117 /* Ring doorbell once to update PCC subspace */
1118 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1119 ret = -EIO;
1120 goto out_err;
1121 }
1122 }
1123
1124 cpc_read(cpunum, highest_reg, &high);
1125 perf_caps->highest_perf = high;
1126
1127 cpc_read(cpunum, lowest_reg, &low);
1128 perf_caps->lowest_perf = low;
1129
1130 cpc_read(cpunum, nominal_reg, &nom);
1131 perf_caps->nominal_perf = nom;
1132
1133 if (guaranteed_reg->type != ACPI_TYPE_BUFFER ||
1134 IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
1135 perf_caps->guaranteed_perf = 0;
1136 } else {
1137 cpc_read(cpunum, guaranteed_reg, &guaranteed);
1138 perf_caps->guaranteed_perf = guaranteed;
1139 }
1140
1141 cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1142 perf_caps->lowest_nonlinear_perf = min_nonlinear;
1143
1144 if (!high || !low || !nom || !min_nonlinear)
1145 ret = -EFAULT;
1146
1147 /* Read optional lowest and nominal frequencies if present */
1148 if (CPC_SUPPORTED(low_freq_reg))
1149 cpc_read(cpunum, low_freq_reg, &low_f);
1150
1151 if (CPC_SUPPORTED(nom_freq_reg))
1152 cpc_read(cpunum, nom_freq_reg, &nom_f);
1153
1154 perf_caps->lowest_freq = low_f;
1155 perf_caps->nominal_freq = nom_f;
1156
1157
1158out_err:
1159 if (regs_in_pcc)
1160 up_write(&pcc_ss_data->pcc_lock);
1161 return ret;
1162}
1163EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1164
1165/**
1166 * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
1167 * @cpunum: CPU from which to read counters.
1168 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1169 *
1170 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1171 */
1172int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1173{
1174 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1175 struct cpc_register_resource *delivered_reg, *reference_reg,
1176 *ref_perf_reg, *ctr_wrap_reg;
1177 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1178 struct cppc_pcc_data *pcc_ss_data = NULL;
1179 u64 delivered, reference, ref_perf, ctr_wrap_time;
1180 int ret = 0, regs_in_pcc = 0;
1181
1182 if (!cpc_desc) {
1183 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1184 return -ENODEV;
1185 }
1186
1187 delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1188 reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1189 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1190 ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1191
1192 /*
1193 * If reference perf register is not supported then we should
1194 * use the nominal perf value
1195 */
1196 if (!CPC_SUPPORTED(ref_perf_reg))
1197 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1198
1199 /* Are any of the regs PCC ?*/
1200 if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1201 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1202 if (pcc_ss_id < 0) {
1203 pr_debug("Invalid pcc_ss_id\n");
1204 return -ENODEV;
1205 }
1206 pcc_ss_data = pcc_data[pcc_ss_id];
1207 down_write(&pcc_ss_data->pcc_lock);
1208 regs_in_pcc = 1;
1209 /* Ring doorbell once to update PCC subspace */
1210 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1211 ret = -EIO;
1212 goto out_err;
1213 }
1214 }
1215
1216 cpc_read(cpunum, delivered_reg, &delivered);
1217 cpc_read(cpunum, reference_reg, &reference);
1218 cpc_read(cpunum, ref_perf_reg, &ref_perf);
1219
1220 /*
1221 * Per spec, if ctr_wrap_time optional register is unsupported, then the
1222 * performance counters are assumed to never wrap during the lifetime of
1223 * platform
1224 */
1225 ctr_wrap_time = (u64)(~((u64)0));
1226 if (CPC_SUPPORTED(ctr_wrap_reg))
1227 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1228
1229 if (!delivered || !reference || !ref_perf) {
1230 ret = -EFAULT;
1231 goto out_err;
1232 }
1233
1234 perf_fb_ctrs->delivered = delivered;
1235 perf_fb_ctrs->reference = reference;
1236 perf_fb_ctrs->reference_perf = ref_perf;
1237 perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1238out_err:
1239 if (regs_in_pcc)
1240 up_write(&pcc_ss_data->pcc_lock);
1241 return ret;
1242}
1243EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1244
1245/**
1246 * cppc_set_perf - Set a CPU's performance controls.
1247 * @cpu: CPU for which to set performance controls.
1248 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1249 *
1250 * Return: 0 for success, -ERRNO otherwise.
1251 */
1252int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1253{
1254 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1255 struct cpc_register_resource *desired_reg;
1256 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1257 struct cppc_pcc_data *pcc_ss_data = NULL;
1258 int ret = 0;
1259
1260 if (!cpc_desc) {
1261 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1262 return -ENODEV;
1263 }
1264
1265 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1266
1267 /*
1268 * This is Phase-I where we want to write to CPC registers
1269 * -> We want all CPUs to be able to execute this phase in parallel
1270 *
1271 * Since read_lock can be acquired by multiple CPUs simultaneously we
1272 * achieve that goal here
1273 */
1274 if (CPC_IN_PCC(desired_reg)) {
1275 if (pcc_ss_id < 0) {
1276 pr_debug("Invalid pcc_ss_id\n");
1277 return -ENODEV;
1278 }
1279 pcc_ss_data = pcc_data[pcc_ss_id];
1280 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
1281 if (pcc_ss_data->platform_owns_pcc) {
1282 ret = check_pcc_chan(pcc_ss_id, false);
1283 if (ret) {
1284 up_read(&pcc_ss_data->pcc_lock);
1285 return ret;
1286 }
1287 }
1288 /*
1289 * Update the pending_write to make sure a PCC CMD_READ will not
1290 * arrive and steal the channel during the switch to write lock
1291 */
1292 pcc_ss_data->pending_pcc_write_cmd = true;
1293 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
1294 cpc_desc->write_cmd_status = 0;
1295 }
1296
1297 /*
1298 * Skip writing MIN/MAX until Linux knows how to come up with
1299 * useful values.
1300 */
1301 cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1302
1303 if (CPC_IN_PCC(desired_reg))
1304 up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */
1305 /*
1306 * This is Phase-II where we transfer the ownership of PCC to Platform
1307 *
1308 * Short Summary: Basically if we think of a group of cppc_set_perf
1309 * requests that happened in short overlapping interval. The last CPU to
1310 * come out of Phase-I will enter Phase-II and ring the doorbell.
1311 *
1312 * We have the following requirements for Phase-II:
1313 * 1. We want to execute Phase-II only when there are no CPUs
1314 * currently executing in Phase-I
1315 * 2. Once we start Phase-II we want to avoid all other CPUs from
1316 * entering Phase-I.
1317 * 3. We want only one CPU among all those who went through Phase-I
1318 * to run phase-II
1319 *
1320 * If write_trylock fails to get the lock and doesn't transfer the
1321 * PCC ownership to the platform, then one of the following will be TRUE
1322 * 1. There is at-least one CPU in Phase-I which will later execute
1323 * write_trylock, so the CPUs in Phase-I will be responsible for
1324 * executing the Phase-II.
1325 * 2. Some other CPU has beaten this CPU to successfully execute the
1326 * write_trylock and has already acquired the write_lock. We know for a
1327 * fact it (other CPU acquiring the write_lock) couldn't have happened
1328 * before this CPU's Phase-I as we held the read_lock.
1329 * 3. Some other CPU executing pcc CMD_READ has stolen the
1330 * down_write, in which case, send_pcc_cmd will check for pending
1331 * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1332 * So this CPU can be certain that its request will be delivered
1333 * So in all cases, this CPU knows that its request will be delivered
1334 * by another CPU and can return
1335 *
1336 * After getting the down_write we still need to check for
1337 * pending_pcc_write_cmd to take care of the following scenario
1338 * The thread running this code could be scheduled out between
1339 * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1340 * could have delivered the request to Platform by triggering the
1341 * doorbell and transferred the ownership of PCC to platform. So this
1342 * avoids triggering an unnecessary doorbell and more importantly before
1343 * triggering the doorbell it makes sure that the PCC channel ownership
1344 * is still with OSPM.
1345 * pending_pcc_write_cmd can also be cleared by a different CPU, if
1346 * there was a pcc CMD_READ waiting on down_write and it steals the lock
1347 * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this
1348 * case during a CMD_READ and if there are pending writes it delivers
1349 * the write command before servicing the read command
1350 */
1351 if (CPC_IN_PCC(desired_reg)) {
1352 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
1353 /* Update only if there are pending write commands */
1354 if (pcc_ss_data->pending_pcc_write_cmd)
1355 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1356 up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */
1357 } else
1358 /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1359 wait_event(pcc_ss_data->pcc_write_wait_q,
1360 cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
1361
1362 /* send_pcc_cmd updates the status in case of failure */
1363 ret = cpc_desc->write_cmd_status;
1364 }
1365 return ret;
1366}
1367EXPORT_SYMBOL_GPL(cppc_set_perf);
1368
1369/**
1370 * cppc_get_transition_latency - returns frequency transition latency in ns
1371 *
1372 * ACPI CPPC does not explicitly specifiy how a platform can specify the
1373 * transition latency for perfromance change requests. The closest we have
1374 * is the timing information from the PCCT tables which provides the info
1375 * on the number and frequency of PCC commands the platform can handle.
1376 */
1377unsigned int cppc_get_transition_latency(int cpu_num)
1378{
1379 /*
1380 * Expected transition latency is based on the PCCT timing values
1381 * Below are definition from ACPI spec:
1382 * pcc_nominal- Expected latency to process a command, in microseconds
1383 * pcc_mpar - The maximum number of periodic requests that the subspace
1384 * channel can support, reported in commands per minute. 0
1385 * indicates no limitation.
1386 * pcc_mrtt - The minimum amount of time that OSPM must wait after the
1387 * completion of a command before issuing the next command,
1388 * in microseconds.
1389 */
1390 unsigned int latency_ns = 0;
1391 struct cpc_desc *cpc_desc;
1392 struct cpc_register_resource *desired_reg;
1393 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
1394 struct cppc_pcc_data *pcc_ss_data;
1395
1396 cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1397 if (!cpc_desc)
1398 return CPUFREQ_ETERNAL;
1399
1400 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1401 if (!CPC_IN_PCC(desired_reg))
1402 return CPUFREQ_ETERNAL;
1403
1404 if (pcc_ss_id < 0)
1405 return CPUFREQ_ETERNAL;
1406
1407 pcc_ss_data = pcc_data[pcc_ss_id];
1408 if (pcc_ss_data->pcc_mpar)
1409 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
1410
1411 latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
1412 latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
1413
1414 return latency_ns;
1415}
1416EXPORT_SYMBOL_GPL(cppc_get_transition_latency);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
4 *
5 * (C) Copyright 2014, 2015 Linaro Ltd.
6 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
7 *
8 * CPPC describes a few methods for controlling CPU performance using
9 * information from a per CPU table called CPC. This table is described in
10 * the ACPI v5.0+ specification. The table consists of a list of
11 * registers which may be memory mapped or hardware registers and also may
12 * include some static integer values.
13 *
14 * CPU performance is on an abstract continuous scale as against a discretized
15 * P-state scale which is tied to CPU frequency only. In brief, the basic
16 * operation involves:
17 *
18 * - OS makes a CPU performance request. (Can provide min and max bounds)
19 *
20 * - Platform (such as BMC) is free to optimize request within requested bounds
21 * depending on power/thermal budgets etc.
22 *
23 * - Platform conveys its decision back to OS
24 *
25 * The communication between OS and platform occurs through another medium
26 * called (PCC) Platform Communication Channel. This is a generic mailbox like
27 * mechanism which includes doorbell semantics to indicate register updates.
28 * See drivers/mailbox/pcc.c for details on PCC.
29 *
30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
31 * above specifications.
32 */
33
34#define pr_fmt(fmt) "ACPI CPPC: " fmt
35
36#include <linux/delay.h>
37#include <linux/iopoll.h>
38#include <linux/ktime.h>
39#include <linux/rwsem.h>
40#include <linux/wait.h>
41#include <linux/topology.h>
42
43#include <acpi/cppc_acpi.h>
44
45struct cppc_pcc_data {
46 struct pcc_mbox_chan *pcc_channel;
47 void __iomem *pcc_comm_addr;
48 bool pcc_channel_acquired;
49 unsigned int deadline_us;
50 unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
51
52 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */
53 bool platform_owns_pcc; /* Ownership of PCC subspace */
54 unsigned int pcc_write_cnt; /* Running count of PCC write commands */
55
56 /*
57 * Lock to provide controlled access to the PCC channel.
58 *
59 * For performance critical usecases(currently cppc_set_perf)
60 * We need to take read_lock and check if channel belongs to OSPM
61 * before reading or writing to PCC subspace
62 * We need to take write_lock before transferring the channel
63 * ownership to the platform via a Doorbell
64 * This allows us to batch a number of CPPC requests if they happen
65 * to originate in about the same time
66 *
67 * For non-performance critical usecases(init)
68 * Take write_lock for all purposes which gives exclusive access
69 */
70 struct rw_semaphore pcc_lock;
71
72 /* Wait queue for CPUs whose requests were batched */
73 wait_queue_head_t pcc_write_wait_q;
74 ktime_t last_cmd_cmpl_time;
75 ktime_t last_mpar_reset;
76 int mpar_count;
77 int refcount;
78};
79
80/* Array to represent the PCC channel per subspace ID */
81static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
82/* The cpu_pcc_subspace_idx contains per CPU subspace ID */
83static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
84
85/*
86 * The cpc_desc structure contains the ACPI register details
87 * as described in the per CPU _CPC tables. The details
88 * include the type of register (e.g. PCC, System IO, FFH etc.)
89 * and destination addresses which lets us READ/WRITE CPU performance
90 * information using the appropriate I/O methods.
91 */
92static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
93
94/* pcc mapped address + header size + offset within PCC subspace */
95#define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
96 0x8 + (offs))
97
98/* Check if a CPC register is in PCC */
99#define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
100 (cpc)->cpc_entry.reg.space_id == \
101 ACPI_ADR_SPACE_PLATFORM_COMM)
102
103/* Check if a CPC register is in SystemMemory */
104#define CPC_IN_SYSTEM_MEMORY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
105 (cpc)->cpc_entry.reg.space_id == \
106 ACPI_ADR_SPACE_SYSTEM_MEMORY)
107
108/* Check if a CPC register is in SystemIo */
109#define CPC_IN_SYSTEM_IO(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
110 (cpc)->cpc_entry.reg.space_id == \
111 ACPI_ADR_SPACE_SYSTEM_IO)
112
113/* Evaluates to True if reg is a NULL register descriptor */
114#define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \
115 (reg)->address == 0 && \
116 (reg)->bit_width == 0 && \
117 (reg)->bit_offset == 0 && \
118 (reg)->access_width == 0)
119
120/* Evaluates to True if an optional cpc field is supported */
121#define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
122 !!(cpc)->cpc_entry.int_value : \
123 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
124/*
125 * Arbitrary Retries in case the remote processor is slow to respond
126 * to PCC commands. Keeping it high enough to cover emulators where
127 * the processors run painfully slow.
128 */
129#define NUM_RETRIES 500ULL
130
131#define OVER_16BTS_MASK ~0xFFFFULL
132
133#define define_one_cppc_ro(_name) \
134static struct kobj_attribute _name = \
135__ATTR(_name, 0444, show_##_name, NULL)
136
137#define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
138
139#define show_cppc_data(access_fn, struct_name, member_name) \
140 static ssize_t show_##member_name(struct kobject *kobj, \
141 struct kobj_attribute *attr, char *buf) \
142 { \
143 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
144 struct struct_name st_name = {0}; \
145 int ret; \
146 \
147 ret = access_fn(cpc_ptr->cpu_id, &st_name); \
148 if (ret) \
149 return ret; \
150 \
151 return sysfs_emit(buf, "%llu\n", \
152 (u64)st_name.member_name); \
153 } \
154 define_one_cppc_ro(member_name)
155
156show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
157show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
158show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
159show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
160show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
161show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
162
163show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
164show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
165
166static ssize_t show_feedback_ctrs(struct kobject *kobj,
167 struct kobj_attribute *attr, char *buf)
168{
169 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
170 struct cppc_perf_fb_ctrs fb_ctrs = {0};
171 int ret;
172
173 ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
174 if (ret)
175 return ret;
176
177 return sysfs_emit(buf, "ref:%llu del:%llu\n",
178 fb_ctrs.reference, fb_ctrs.delivered);
179}
180define_one_cppc_ro(feedback_ctrs);
181
182static struct attribute *cppc_attrs[] = {
183 &feedback_ctrs.attr,
184 &reference_perf.attr,
185 &wraparound_time.attr,
186 &highest_perf.attr,
187 &lowest_perf.attr,
188 &lowest_nonlinear_perf.attr,
189 &nominal_perf.attr,
190 &nominal_freq.attr,
191 &lowest_freq.attr,
192 NULL
193};
194ATTRIBUTE_GROUPS(cppc);
195
196static struct kobj_type cppc_ktype = {
197 .sysfs_ops = &kobj_sysfs_ops,
198 .default_groups = cppc_groups,
199};
200
201static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
202{
203 int ret, status;
204 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
205 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
206 pcc_ss_data->pcc_comm_addr;
207
208 if (!pcc_ss_data->platform_owns_pcc)
209 return 0;
210
211 /*
212 * Poll PCC status register every 3us(delay_us) for maximum of
213 * deadline_us(timeout_us) until PCC command complete bit is set(cond)
214 */
215 ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
216 status & PCC_CMD_COMPLETE_MASK, 3,
217 pcc_ss_data->deadline_us);
218
219 if (likely(!ret)) {
220 pcc_ss_data->platform_owns_pcc = false;
221 if (chk_err_bit && (status & PCC_ERROR_MASK))
222 ret = -EIO;
223 }
224
225 if (unlikely(ret))
226 pr_err("PCC check channel failed for ss: %d. ret=%d\n",
227 pcc_ss_id, ret);
228
229 return ret;
230}
231
232/*
233 * This function transfers the ownership of the PCC to the platform
234 * So it must be called while holding write_lock(pcc_lock)
235 */
236static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
237{
238 int ret = -EIO, i;
239 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
240 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
241 pcc_ss_data->pcc_comm_addr;
242 unsigned int time_delta;
243
244 /*
245 * For CMD_WRITE we know for a fact the caller should have checked
246 * the channel before writing to PCC space
247 */
248 if (cmd == CMD_READ) {
249 /*
250 * If there are pending cpc_writes, then we stole the channel
251 * before write completion, so first send a WRITE command to
252 * platform
253 */
254 if (pcc_ss_data->pending_pcc_write_cmd)
255 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
256
257 ret = check_pcc_chan(pcc_ss_id, false);
258 if (ret)
259 goto end;
260 } else /* CMD_WRITE */
261 pcc_ss_data->pending_pcc_write_cmd = FALSE;
262
263 /*
264 * Handle the Minimum Request Turnaround Time(MRTT)
265 * "The minimum amount of time that OSPM must wait after the completion
266 * of a command before issuing the next command, in microseconds"
267 */
268 if (pcc_ss_data->pcc_mrtt) {
269 time_delta = ktime_us_delta(ktime_get(),
270 pcc_ss_data->last_cmd_cmpl_time);
271 if (pcc_ss_data->pcc_mrtt > time_delta)
272 udelay(pcc_ss_data->pcc_mrtt - time_delta);
273 }
274
275 /*
276 * Handle the non-zero Maximum Periodic Access Rate(MPAR)
277 * "The maximum number of periodic requests that the subspace channel can
278 * support, reported in commands per minute. 0 indicates no limitation."
279 *
280 * This parameter should be ideally zero or large enough so that it can
281 * handle maximum number of requests that all the cores in the system can
282 * collectively generate. If it is not, we will follow the spec and just
283 * not send the request to the platform after hitting the MPAR limit in
284 * any 60s window
285 */
286 if (pcc_ss_data->pcc_mpar) {
287 if (pcc_ss_data->mpar_count == 0) {
288 time_delta = ktime_ms_delta(ktime_get(),
289 pcc_ss_data->last_mpar_reset);
290 if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
291 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
292 pcc_ss_id);
293 ret = -EIO;
294 goto end;
295 }
296 pcc_ss_data->last_mpar_reset = ktime_get();
297 pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
298 }
299 pcc_ss_data->mpar_count--;
300 }
301
302 /* Write to the shared comm region. */
303 writew_relaxed(cmd, &generic_comm_base->command);
304
305 /* Flip CMD COMPLETE bit */
306 writew_relaxed(0, &generic_comm_base->status);
307
308 pcc_ss_data->platform_owns_pcc = true;
309
310 /* Ring doorbell */
311 ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd);
312 if (ret < 0) {
313 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
314 pcc_ss_id, cmd, ret);
315 goto end;
316 }
317
318 /* wait for completion and check for PCC error bit */
319 ret = check_pcc_chan(pcc_ss_id, true);
320
321 if (pcc_ss_data->pcc_mrtt)
322 pcc_ss_data->last_cmd_cmpl_time = ktime_get();
323
324 if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq)
325 mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret);
326 else
327 mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);
328
329end:
330 if (cmd == CMD_WRITE) {
331 if (unlikely(ret)) {
332 for_each_possible_cpu(i) {
333 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
334
335 if (!desc)
336 continue;
337
338 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
339 desc->write_cmd_status = ret;
340 }
341 }
342 pcc_ss_data->pcc_write_cnt++;
343 wake_up_all(&pcc_ss_data->pcc_write_wait_q);
344 }
345
346 return ret;
347}
348
349static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
350{
351 if (ret < 0)
352 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
353 *(u16 *)msg, ret);
354 else
355 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
356 *(u16 *)msg, ret);
357}
358
359static struct mbox_client cppc_mbox_cl = {
360 .tx_done = cppc_chan_tx_done,
361 .knows_txdone = true,
362};
363
364static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
365{
366 int result = -EFAULT;
367 acpi_status status = AE_OK;
368 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
369 struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
370 struct acpi_buffer state = {0, NULL};
371 union acpi_object *psd = NULL;
372 struct acpi_psd_package *pdomain;
373
374 status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
375 &buffer, ACPI_TYPE_PACKAGE);
376 if (status == AE_NOT_FOUND) /* _PSD is optional */
377 return 0;
378 if (ACPI_FAILURE(status))
379 return -ENODEV;
380
381 psd = buffer.pointer;
382 if (!psd || psd->package.count != 1) {
383 pr_debug("Invalid _PSD data\n");
384 goto end;
385 }
386
387 pdomain = &(cpc_ptr->domain_info);
388
389 state.length = sizeof(struct acpi_psd_package);
390 state.pointer = pdomain;
391
392 status = acpi_extract_package(&(psd->package.elements[0]),
393 &format, &state);
394 if (ACPI_FAILURE(status)) {
395 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
396 goto end;
397 }
398
399 if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
400 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
401 goto end;
402 }
403
404 if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
405 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
406 goto end;
407 }
408
409 if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
410 pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
411 pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
412 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
413 goto end;
414 }
415
416 result = 0;
417end:
418 kfree(buffer.pointer);
419 return result;
420}
421
422bool acpi_cpc_valid(void)
423{
424 struct cpc_desc *cpc_ptr;
425 int cpu;
426
427 if (acpi_disabled)
428 return false;
429
430 for_each_present_cpu(cpu) {
431 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
432 if (!cpc_ptr)
433 return false;
434 }
435
436 return true;
437}
438EXPORT_SYMBOL_GPL(acpi_cpc_valid);
439
440bool cppc_allow_fast_switch(void)
441{
442 struct cpc_register_resource *desired_reg;
443 struct cpc_desc *cpc_ptr;
444 int cpu;
445
446 for_each_possible_cpu(cpu) {
447 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
448 desired_reg = &cpc_ptr->cpc_regs[DESIRED_PERF];
449 if (!CPC_IN_SYSTEM_MEMORY(desired_reg) &&
450 !CPC_IN_SYSTEM_IO(desired_reg))
451 return false;
452 }
453
454 return true;
455}
456EXPORT_SYMBOL_GPL(cppc_allow_fast_switch);
457
458/**
459 * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
460 * @cpu: Find all CPUs that share a domain with cpu.
461 * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
462 *
463 * Return: 0 for success or negative value for err.
464 */
465int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
466{
467 struct cpc_desc *cpc_ptr, *match_cpc_ptr;
468 struct acpi_psd_package *match_pdomain;
469 struct acpi_psd_package *pdomain;
470 int count_target, i;
471
472 /*
473 * Now that we have _PSD data from all CPUs, let's setup P-state
474 * domain info.
475 */
476 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
477 if (!cpc_ptr)
478 return -EFAULT;
479
480 pdomain = &(cpc_ptr->domain_info);
481 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
482 if (pdomain->num_processors <= 1)
483 return 0;
484
485 /* Validate the Domain info */
486 count_target = pdomain->num_processors;
487 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
488 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
489 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
490 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
491 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
492 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
493
494 for_each_possible_cpu(i) {
495 if (i == cpu)
496 continue;
497
498 match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
499 if (!match_cpc_ptr)
500 goto err_fault;
501
502 match_pdomain = &(match_cpc_ptr->domain_info);
503 if (match_pdomain->domain != pdomain->domain)
504 continue;
505
506 /* Here i and cpu are in the same domain */
507 if (match_pdomain->num_processors != count_target)
508 goto err_fault;
509
510 if (pdomain->coord_type != match_pdomain->coord_type)
511 goto err_fault;
512
513 cpumask_set_cpu(i, cpu_data->shared_cpu_map);
514 }
515
516 return 0;
517
518err_fault:
519 /* Assume no coordination on any error parsing domain info */
520 cpumask_clear(cpu_data->shared_cpu_map);
521 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
522 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
523
524 return -EFAULT;
525}
526EXPORT_SYMBOL_GPL(acpi_get_psd_map);
527
528static int register_pcc_channel(int pcc_ss_idx)
529{
530 struct pcc_mbox_chan *pcc_chan;
531 u64 usecs_lat;
532
533 if (pcc_ss_idx >= 0) {
534 pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
535
536 if (IS_ERR(pcc_chan)) {
537 pr_err("Failed to find PCC channel for subspace %d\n",
538 pcc_ss_idx);
539 return -ENODEV;
540 }
541
542 pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan;
543 /*
544 * cppc_ss->latency is just a Nominal value. In reality
545 * the remote processor could be much slower to reply.
546 * So add an arbitrary amount of wait on top of Nominal.
547 */
548 usecs_lat = NUM_RETRIES * pcc_chan->latency;
549 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
550 pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time;
551 pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
552 pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
553
554 pcc_data[pcc_ss_idx]->pcc_comm_addr =
555 acpi_os_ioremap(pcc_chan->shmem_base_addr,
556 pcc_chan->shmem_size);
557 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
558 pr_err("Failed to ioremap PCC comm region mem for %d\n",
559 pcc_ss_idx);
560 return -ENOMEM;
561 }
562
563 /* Set flag so that we don't come here for each CPU. */
564 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
565 }
566
567 return 0;
568}
569
570/**
571 * cpc_ffh_supported() - check if FFH reading supported
572 *
573 * Check if the architecture has support for functional fixed hardware
574 * read/write capability.
575 *
576 * Return: true for supported, false for not supported
577 */
578bool __weak cpc_ffh_supported(void)
579{
580 return false;
581}
582
583/**
584 * cpc_supported_by_cpu() - check if CPPC is supported by CPU
585 *
586 * Check if the architectural support for CPPC is present even
587 * if the _OSC hasn't prescribed it
588 *
589 * Return: true for supported, false for not supported
590 */
591bool __weak cpc_supported_by_cpu(void)
592{
593 return false;
594}
595
596/**
597 * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
598 *
599 * Check and allocate the cppc_pcc_data memory.
600 * In some processor configurations it is possible that same subspace
601 * is shared between multiple CPUs. This is seen especially in CPUs
602 * with hardware multi-threading support.
603 *
604 * Return: 0 for success, errno for failure
605 */
606static int pcc_data_alloc(int pcc_ss_id)
607{
608 if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
609 return -EINVAL;
610
611 if (pcc_data[pcc_ss_id]) {
612 pcc_data[pcc_ss_id]->refcount++;
613 } else {
614 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
615 GFP_KERNEL);
616 if (!pcc_data[pcc_ss_id])
617 return -ENOMEM;
618 pcc_data[pcc_ss_id]->refcount++;
619 }
620
621 return 0;
622}
623
624/*
625 * An example CPC table looks like the following.
626 *
627 * Name (_CPC, Package() {
628 * 17, // NumEntries
629 * 1, // Revision
630 * ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)}, // Highest Performance
631 * ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)}, // Nominal Performance
632 * ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)}, // Lowest Nonlinear Performance
633 * ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)}, // Lowest Performance
634 * ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)}, // Guaranteed Performance Register
635 * ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)}, // Desired Performance Register
636 * ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)},
637 * ...
638 * ...
639 * ...
640 * }
641 * Each Register() encodes how to access that specific register.
642 * e.g. a sample PCC entry has the following encoding:
643 *
644 * Register (
645 * PCC, // AddressSpaceKeyword
646 * 8, // RegisterBitWidth
647 * 8, // RegisterBitOffset
648 * 0x30, // RegisterAddress
649 * 9, // AccessSize (subspace ID)
650 * )
651 */
652
653#ifndef arch_init_invariance_cppc
654static inline void arch_init_invariance_cppc(void) { }
655#endif
656
657/**
658 * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
659 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
660 *
661 * Return: 0 for success or negative value for err.
662 */
663int acpi_cppc_processor_probe(struct acpi_processor *pr)
664{
665 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
666 union acpi_object *out_obj, *cpc_obj;
667 struct cpc_desc *cpc_ptr;
668 struct cpc_reg *gas_t;
669 struct device *cpu_dev;
670 acpi_handle handle = pr->handle;
671 unsigned int num_ent, i, cpc_rev;
672 int pcc_subspace_id = -1;
673 acpi_status status;
674 int ret = -ENODATA;
675
676 if (!osc_sb_cppc2_support_acked) {
677 pr_debug("CPPC v2 _OSC not acked\n");
678 if (!cpc_supported_by_cpu())
679 return -ENODEV;
680 }
681
682 /* Parse the ACPI _CPC table for this CPU. */
683 status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
684 ACPI_TYPE_PACKAGE);
685 if (ACPI_FAILURE(status)) {
686 ret = -ENODEV;
687 goto out_buf_free;
688 }
689
690 out_obj = (union acpi_object *) output.pointer;
691
692 cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
693 if (!cpc_ptr) {
694 ret = -ENOMEM;
695 goto out_buf_free;
696 }
697
698 /* First entry is NumEntries. */
699 cpc_obj = &out_obj->package.elements[0];
700 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
701 num_ent = cpc_obj->integer.value;
702 if (num_ent <= 1) {
703 pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n",
704 num_ent, pr->id);
705 goto out_free;
706 }
707 } else {
708 pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n",
709 cpc_obj->type, pr->id);
710 goto out_free;
711 }
712
713 /* Second entry should be revision. */
714 cpc_obj = &out_obj->package.elements[1];
715 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
716 cpc_rev = cpc_obj->integer.value;
717 } else {
718 pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n",
719 cpc_obj->type, pr->id);
720 goto out_free;
721 }
722
723 if (cpc_rev < CPPC_V2_REV) {
724 pr_debug("Unsupported _CPC Revision (%d) for CPU:%d\n", cpc_rev,
725 pr->id);
726 goto out_free;
727 }
728
729 /*
730 * Disregard _CPC if the number of entries in the return pachage is not
731 * as expected, but support future revisions being proper supersets of
732 * the v3 and only causing more entries to be returned by _CPC.
733 */
734 if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) ||
735 (cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) ||
736 (cpc_rev > CPPC_V3_REV && num_ent <= CPPC_V3_NUM_ENT)) {
737 pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n",
738 num_ent, pr->id);
739 goto out_free;
740 }
741 if (cpc_rev > CPPC_V3_REV) {
742 num_ent = CPPC_V3_NUM_ENT;
743 cpc_rev = CPPC_V3_REV;
744 }
745
746 cpc_ptr->num_entries = num_ent;
747 cpc_ptr->version = cpc_rev;
748
749 /* Iterate through remaining entries in _CPC */
750 for (i = 2; i < num_ent; i++) {
751 cpc_obj = &out_obj->package.elements[i];
752
753 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
754 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
755 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
756 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
757 gas_t = (struct cpc_reg *)
758 cpc_obj->buffer.pointer;
759
760 /*
761 * The PCC Subspace index is encoded inside
762 * the CPC table entries. The same PCC index
763 * will be used for all the PCC entries,
764 * so extract it only once.
765 */
766 if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
767 if (pcc_subspace_id < 0) {
768 pcc_subspace_id = gas_t->access_width;
769 if (pcc_data_alloc(pcc_subspace_id))
770 goto out_free;
771 } else if (pcc_subspace_id != gas_t->access_width) {
772 pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
773 pr->id);
774 goto out_free;
775 }
776 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
777 if (gas_t->address) {
778 void __iomem *addr;
779
780 if (!osc_cpc_flexible_adr_space_confirmed) {
781 pr_debug("Flexible address space capability not supported\n");
782 if (!cpc_supported_by_cpu())
783 goto out_free;
784 }
785
786 addr = ioremap(gas_t->address, gas_t->bit_width/8);
787 if (!addr)
788 goto out_free;
789 cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
790 }
791 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
792 if (gas_t->access_width < 1 || gas_t->access_width > 3) {
793 /*
794 * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.
795 * SystemIO doesn't implement 64-bit
796 * registers.
797 */
798 pr_debug("Invalid access width %d for SystemIO register in _CPC\n",
799 gas_t->access_width);
800 goto out_free;
801 }
802 if (gas_t->address & OVER_16BTS_MASK) {
803 /* SystemIO registers use 16-bit integer addresses */
804 pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n",
805 gas_t->address);
806 goto out_free;
807 }
808 if (!osc_cpc_flexible_adr_space_confirmed) {
809 pr_debug("Flexible address space capability not supported\n");
810 if (!cpc_supported_by_cpu())
811 goto out_free;
812 }
813 } else {
814 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
815 /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
816 pr_debug("Unsupported register type (%d) in _CPC\n",
817 gas_t->space_id);
818 goto out_free;
819 }
820 }
821
822 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
823 memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
824 } else {
825 pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n",
826 i, pr->id);
827 goto out_free;
828 }
829 }
830 per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
831
832 /*
833 * Initialize the remaining cpc_regs as unsupported.
834 * Example: In case FW exposes CPPC v2, the below loop will initialize
835 * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
836 */
837 for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
838 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
839 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
840 }
841
842
843 /* Store CPU Logical ID */
844 cpc_ptr->cpu_id = pr->id;
845
846 /* Parse PSD data for this CPU */
847 ret = acpi_get_psd(cpc_ptr, handle);
848 if (ret)
849 goto out_free;
850
851 /* Register PCC channel once for all PCC subspace ID. */
852 if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
853 ret = register_pcc_channel(pcc_subspace_id);
854 if (ret)
855 goto out_free;
856
857 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
858 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
859 }
860
861 /* Everything looks okay */
862 pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
863
864 /* Add per logical CPU nodes for reading its feedback counters. */
865 cpu_dev = get_cpu_device(pr->id);
866 if (!cpu_dev) {
867 ret = -EINVAL;
868 goto out_free;
869 }
870
871 /* Plug PSD data into this CPU's CPC descriptor. */
872 per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
873
874 ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
875 "acpi_cppc");
876 if (ret) {
877 per_cpu(cpc_desc_ptr, pr->id) = NULL;
878 kobject_put(&cpc_ptr->kobj);
879 goto out_free;
880 }
881
882 arch_init_invariance_cppc();
883
884 kfree(output.pointer);
885 return 0;
886
887out_free:
888 /* Free all the mapped sys mem areas for this CPU */
889 for (i = 2; i < cpc_ptr->num_entries; i++) {
890 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
891
892 if (addr)
893 iounmap(addr);
894 }
895 kfree(cpc_ptr);
896
897out_buf_free:
898 kfree(output.pointer);
899 return ret;
900}
901EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
902
903/**
904 * acpi_cppc_processor_exit - Cleanup CPC structs.
905 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
906 *
907 * Return: Void
908 */
909void acpi_cppc_processor_exit(struct acpi_processor *pr)
910{
911 struct cpc_desc *cpc_ptr;
912 unsigned int i;
913 void __iomem *addr;
914 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
915
916 if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
917 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
918 pcc_data[pcc_ss_id]->refcount--;
919 if (!pcc_data[pcc_ss_id]->refcount) {
920 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
921 kfree(pcc_data[pcc_ss_id]);
922 pcc_data[pcc_ss_id] = NULL;
923 }
924 }
925 }
926
927 cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
928 if (!cpc_ptr)
929 return;
930
931 /* Free all the mapped sys mem areas for this CPU */
932 for (i = 2; i < cpc_ptr->num_entries; i++) {
933 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
934 if (addr)
935 iounmap(addr);
936 }
937
938 kobject_put(&cpc_ptr->kobj);
939 kfree(cpc_ptr);
940}
941EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
942
943/**
944 * cpc_read_ffh() - Read FFH register
945 * @cpunum: CPU number to read
946 * @reg: cppc register information
947 * @val: place holder for return value
948 *
949 * Read bit_width bits from a specified address and bit_offset
950 *
951 * Return: 0 for success and error code
952 */
953int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
954{
955 return -ENOTSUPP;
956}
957
958/**
959 * cpc_write_ffh() - Write FFH register
960 * @cpunum: CPU number to write
961 * @reg: cppc register information
962 * @val: value to write
963 *
964 * Write value of bit_width bits to a specified address and bit_offset
965 *
966 * Return: 0 for success and error code
967 */
968int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
969{
970 return -ENOTSUPP;
971}
972
973/*
974 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
975 * as fast as possible. We have already mapped the PCC subspace during init, so
976 * we can directly write to it.
977 */
978
979static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
980{
981 void __iomem *vaddr = NULL;
982 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
983 struct cpc_reg *reg = ®_res->cpc_entry.reg;
984
985 if (reg_res->type == ACPI_TYPE_INTEGER) {
986 *val = reg_res->cpc_entry.int_value;
987 return 0;
988 }
989
990 *val = 0;
991
992 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
993 u32 width = 8 << (reg->access_width - 1);
994 u32 val_u32;
995 acpi_status status;
996
997 status = acpi_os_read_port((acpi_io_address)reg->address,
998 &val_u32, width);
999 if (ACPI_FAILURE(status)) {
1000 pr_debug("Error: Failed to read SystemIO port %llx\n",
1001 reg->address);
1002 return -EFAULT;
1003 }
1004
1005 *val = val_u32;
1006 return 0;
1007 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
1008 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1009 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1010 vaddr = reg_res->sys_mem_vaddr;
1011 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1012 return cpc_read_ffh(cpu, reg, val);
1013 else
1014 return acpi_os_read_memory((acpi_physical_address)reg->address,
1015 val, reg->bit_width);
1016
1017 switch (reg->bit_width) {
1018 case 8:
1019 *val = readb_relaxed(vaddr);
1020 break;
1021 case 16:
1022 *val = readw_relaxed(vaddr);
1023 break;
1024 case 32:
1025 *val = readl_relaxed(vaddr);
1026 break;
1027 case 64:
1028 *val = readq_relaxed(vaddr);
1029 break;
1030 default:
1031 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
1032 reg->bit_width, pcc_ss_id);
1033 return -EFAULT;
1034 }
1035
1036 return 0;
1037}
1038
1039static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
1040{
1041 int ret_val = 0;
1042 void __iomem *vaddr = NULL;
1043 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1044 struct cpc_reg *reg = ®_res->cpc_entry.reg;
1045
1046 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1047 u32 width = 8 << (reg->access_width - 1);
1048 acpi_status status;
1049
1050 status = acpi_os_write_port((acpi_io_address)reg->address,
1051 (u32)val, width);
1052 if (ACPI_FAILURE(status)) {
1053 pr_debug("Error: Failed to write SystemIO port %llx\n",
1054 reg->address);
1055 return -EFAULT;
1056 }
1057
1058 return 0;
1059 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
1060 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1061 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1062 vaddr = reg_res->sys_mem_vaddr;
1063 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1064 return cpc_write_ffh(cpu, reg, val);
1065 else
1066 return acpi_os_write_memory((acpi_physical_address)reg->address,
1067 val, reg->bit_width);
1068
1069 switch (reg->bit_width) {
1070 case 8:
1071 writeb_relaxed(val, vaddr);
1072 break;
1073 case 16:
1074 writew_relaxed(val, vaddr);
1075 break;
1076 case 32:
1077 writel_relaxed(val, vaddr);
1078 break;
1079 case 64:
1080 writeq_relaxed(val, vaddr);
1081 break;
1082 default:
1083 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
1084 reg->bit_width, pcc_ss_id);
1085 ret_val = -EFAULT;
1086 break;
1087 }
1088
1089 return ret_val;
1090}
1091
1092static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf)
1093{
1094 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1095 struct cpc_register_resource *reg;
1096
1097 if (!cpc_desc) {
1098 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1099 return -ENODEV;
1100 }
1101
1102 reg = &cpc_desc->cpc_regs[reg_idx];
1103
1104 if (CPC_IN_PCC(reg)) {
1105 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1106 struct cppc_pcc_data *pcc_ss_data = NULL;
1107 int ret = 0;
1108
1109 if (pcc_ss_id < 0)
1110 return -EIO;
1111
1112 pcc_ss_data = pcc_data[pcc_ss_id];
1113
1114 down_write(&pcc_ss_data->pcc_lock);
1115
1116 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
1117 cpc_read(cpunum, reg, perf);
1118 else
1119 ret = -EIO;
1120
1121 up_write(&pcc_ss_data->pcc_lock);
1122
1123 return ret;
1124 }
1125
1126 cpc_read(cpunum, reg, perf);
1127
1128 return 0;
1129}
1130
1131/**
1132 * cppc_get_desired_perf - Get the desired performance register value.
1133 * @cpunum: CPU from which to get desired performance.
1134 * @desired_perf: Return address.
1135 *
1136 * Return: 0 for success, -EIO otherwise.
1137 */
1138int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
1139{
1140 return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf);
1141}
1142EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
1143
1144/**
1145 * cppc_get_nominal_perf - Get the nominal performance register value.
1146 * @cpunum: CPU from which to get nominal performance.
1147 * @nominal_perf: Return address.
1148 *
1149 * Return: 0 for success, -EIO otherwise.
1150 */
1151int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
1152{
1153 return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
1154}
1155
1156/**
1157 * cppc_get_perf_caps - Get a CPU's performance capabilities.
1158 * @cpunum: CPU from which to get capabilities info.
1159 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1160 *
1161 * Return: 0 for success with perf_caps populated else -ERRNO.
1162 */
1163int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1164{
1165 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1166 struct cpc_register_resource *highest_reg, *lowest_reg,
1167 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
1168 *low_freq_reg = NULL, *nom_freq_reg = NULL;
1169 u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
1170 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1171 struct cppc_pcc_data *pcc_ss_data = NULL;
1172 int ret = 0, regs_in_pcc = 0;
1173
1174 if (!cpc_desc) {
1175 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1176 return -ENODEV;
1177 }
1178
1179 highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1180 lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1181 lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1182 nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1183 low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
1184 nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
1185 guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
1186
1187 /* Are any of the regs PCC ?*/
1188 if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
1189 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
1190 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
1191 if (pcc_ss_id < 0) {
1192 pr_debug("Invalid pcc_ss_id\n");
1193 return -ENODEV;
1194 }
1195 pcc_ss_data = pcc_data[pcc_ss_id];
1196 regs_in_pcc = 1;
1197 down_write(&pcc_ss_data->pcc_lock);
1198 /* Ring doorbell once to update PCC subspace */
1199 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1200 ret = -EIO;
1201 goto out_err;
1202 }
1203 }
1204
1205 cpc_read(cpunum, highest_reg, &high);
1206 perf_caps->highest_perf = high;
1207
1208 cpc_read(cpunum, lowest_reg, &low);
1209 perf_caps->lowest_perf = low;
1210
1211 cpc_read(cpunum, nominal_reg, &nom);
1212 perf_caps->nominal_perf = nom;
1213
1214 if (guaranteed_reg->type != ACPI_TYPE_BUFFER ||
1215 IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
1216 perf_caps->guaranteed_perf = 0;
1217 } else {
1218 cpc_read(cpunum, guaranteed_reg, &guaranteed);
1219 perf_caps->guaranteed_perf = guaranteed;
1220 }
1221
1222 cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1223 perf_caps->lowest_nonlinear_perf = min_nonlinear;
1224
1225 if (!high || !low || !nom || !min_nonlinear)
1226 ret = -EFAULT;
1227
1228 /* Read optional lowest and nominal frequencies if present */
1229 if (CPC_SUPPORTED(low_freq_reg))
1230 cpc_read(cpunum, low_freq_reg, &low_f);
1231
1232 if (CPC_SUPPORTED(nom_freq_reg))
1233 cpc_read(cpunum, nom_freq_reg, &nom_f);
1234
1235 perf_caps->lowest_freq = low_f;
1236 perf_caps->nominal_freq = nom_f;
1237
1238
1239out_err:
1240 if (regs_in_pcc)
1241 up_write(&pcc_ss_data->pcc_lock);
1242 return ret;
1243}
1244EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1245
1246/**
1247 * cppc_perf_ctrs_in_pcc - Check if any perf counters are in a PCC region.
1248 *
1249 * CPPC has flexibility about how CPU performance counters are accessed.
1250 * One of the choices is PCC regions, which can have a high access latency. This
1251 * routine allows callers of cppc_get_perf_ctrs() to know this ahead of time.
1252 *
1253 * Return: true if any of the counters are in PCC regions, false otherwise
1254 */
1255bool cppc_perf_ctrs_in_pcc(void)
1256{
1257 int cpu;
1258
1259 for_each_present_cpu(cpu) {
1260 struct cpc_register_resource *ref_perf_reg;
1261 struct cpc_desc *cpc_desc;
1262
1263 cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1264
1265 if (CPC_IN_PCC(&cpc_desc->cpc_regs[DELIVERED_CTR]) ||
1266 CPC_IN_PCC(&cpc_desc->cpc_regs[REFERENCE_CTR]) ||
1267 CPC_IN_PCC(&cpc_desc->cpc_regs[CTR_WRAP_TIME]))
1268 return true;
1269
1270
1271 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1272
1273 /*
1274 * If reference perf register is not supported then we should
1275 * use the nominal perf value
1276 */
1277 if (!CPC_SUPPORTED(ref_perf_reg))
1278 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1279
1280 if (CPC_IN_PCC(ref_perf_reg))
1281 return true;
1282 }
1283
1284 return false;
1285}
1286EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc);
1287
1288/**
1289 * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
1290 * @cpunum: CPU from which to read counters.
1291 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1292 *
1293 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1294 */
1295int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1296{
1297 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1298 struct cpc_register_resource *delivered_reg, *reference_reg,
1299 *ref_perf_reg, *ctr_wrap_reg;
1300 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1301 struct cppc_pcc_data *pcc_ss_data = NULL;
1302 u64 delivered, reference, ref_perf, ctr_wrap_time;
1303 int ret = 0, regs_in_pcc = 0;
1304
1305 if (!cpc_desc) {
1306 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1307 return -ENODEV;
1308 }
1309
1310 delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1311 reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1312 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1313 ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1314
1315 /*
1316 * If reference perf register is not supported then we should
1317 * use the nominal perf value
1318 */
1319 if (!CPC_SUPPORTED(ref_perf_reg))
1320 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1321
1322 /* Are any of the regs PCC ?*/
1323 if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1324 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1325 if (pcc_ss_id < 0) {
1326 pr_debug("Invalid pcc_ss_id\n");
1327 return -ENODEV;
1328 }
1329 pcc_ss_data = pcc_data[pcc_ss_id];
1330 down_write(&pcc_ss_data->pcc_lock);
1331 regs_in_pcc = 1;
1332 /* Ring doorbell once to update PCC subspace */
1333 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1334 ret = -EIO;
1335 goto out_err;
1336 }
1337 }
1338
1339 cpc_read(cpunum, delivered_reg, &delivered);
1340 cpc_read(cpunum, reference_reg, &reference);
1341 cpc_read(cpunum, ref_perf_reg, &ref_perf);
1342
1343 /*
1344 * Per spec, if ctr_wrap_time optional register is unsupported, then the
1345 * performance counters are assumed to never wrap during the lifetime of
1346 * platform
1347 */
1348 ctr_wrap_time = (u64)(~((u64)0));
1349 if (CPC_SUPPORTED(ctr_wrap_reg))
1350 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1351
1352 if (!delivered || !reference || !ref_perf) {
1353 ret = -EFAULT;
1354 goto out_err;
1355 }
1356
1357 perf_fb_ctrs->delivered = delivered;
1358 perf_fb_ctrs->reference = reference;
1359 perf_fb_ctrs->reference_perf = ref_perf;
1360 perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1361out_err:
1362 if (regs_in_pcc)
1363 up_write(&pcc_ss_data->pcc_lock);
1364 return ret;
1365}
1366EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1367
1368/**
1369 * cppc_set_enable - Set to enable CPPC on the processor by writing the
1370 * Continuous Performance Control package EnableRegister field.
1371 * @cpu: CPU for which to enable CPPC register.
1372 * @enable: 0 - disable, 1 - enable CPPC feature on the processor.
1373 *
1374 * Return: 0 for success, -ERRNO or -EIO otherwise.
1375 */
1376int cppc_set_enable(int cpu, bool enable)
1377{
1378 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1379 struct cpc_register_resource *enable_reg;
1380 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1381 struct cppc_pcc_data *pcc_ss_data = NULL;
1382 int ret = -EINVAL;
1383
1384 if (!cpc_desc) {
1385 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1386 return -EINVAL;
1387 }
1388
1389 enable_reg = &cpc_desc->cpc_regs[ENABLE];
1390
1391 if (CPC_IN_PCC(enable_reg)) {
1392
1393 if (pcc_ss_id < 0)
1394 return -EIO;
1395
1396 ret = cpc_write(cpu, enable_reg, enable);
1397 if (ret)
1398 return ret;
1399
1400 pcc_ss_data = pcc_data[pcc_ss_id];
1401
1402 down_write(&pcc_ss_data->pcc_lock);
1403 /* after writing CPC, transfer the ownership of PCC to platfrom */
1404 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1405 up_write(&pcc_ss_data->pcc_lock);
1406 return ret;
1407 }
1408
1409 return cpc_write(cpu, enable_reg, enable);
1410}
1411EXPORT_SYMBOL_GPL(cppc_set_enable);
1412
1413/**
1414 * cppc_set_perf - Set a CPU's performance controls.
1415 * @cpu: CPU for which to set performance controls.
1416 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1417 *
1418 * Return: 0 for success, -ERRNO otherwise.
1419 */
1420int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1421{
1422 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1423 struct cpc_register_resource *desired_reg;
1424 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1425 struct cppc_pcc_data *pcc_ss_data = NULL;
1426 int ret = 0;
1427
1428 if (!cpc_desc) {
1429 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1430 return -ENODEV;
1431 }
1432
1433 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1434
1435 /*
1436 * This is Phase-I where we want to write to CPC registers
1437 * -> We want all CPUs to be able to execute this phase in parallel
1438 *
1439 * Since read_lock can be acquired by multiple CPUs simultaneously we
1440 * achieve that goal here
1441 */
1442 if (CPC_IN_PCC(desired_reg)) {
1443 if (pcc_ss_id < 0) {
1444 pr_debug("Invalid pcc_ss_id\n");
1445 return -ENODEV;
1446 }
1447 pcc_ss_data = pcc_data[pcc_ss_id];
1448 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
1449 if (pcc_ss_data->platform_owns_pcc) {
1450 ret = check_pcc_chan(pcc_ss_id, false);
1451 if (ret) {
1452 up_read(&pcc_ss_data->pcc_lock);
1453 return ret;
1454 }
1455 }
1456 /*
1457 * Update the pending_write to make sure a PCC CMD_READ will not
1458 * arrive and steal the channel during the switch to write lock
1459 */
1460 pcc_ss_data->pending_pcc_write_cmd = true;
1461 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
1462 cpc_desc->write_cmd_status = 0;
1463 }
1464
1465 /*
1466 * Skip writing MIN/MAX until Linux knows how to come up with
1467 * useful values.
1468 */
1469 cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1470
1471 if (CPC_IN_PCC(desired_reg))
1472 up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */
1473 /*
1474 * This is Phase-II where we transfer the ownership of PCC to Platform
1475 *
1476 * Short Summary: Basically if we think of a group of cppc_set_perf
1477 * requests that happened in short overlapping interval. The last CPU to
1478 * come out of Phase-I will enter Phase-II and ring the doorbell.
1479 *
1480 * We have the following requirements for Phase-II:
1481 * 1. We want to execute Phase-II only when there are no CPUs
1482 * currently executing in Phase-I
1483 * 2. Once we start Phase-II we want to avoid all other CPUs from
1484 * entering Phase-I.
1485 * 3. We want only one CPU among all those who went through Phase-I
1486 * to run phase-II
1487 *
1488 * If write_trylock fails to get the lock and doesn't transfer the
1489 * PCC ownership to the platform, then one of the following will be TRUE
1490 * 1. There is at-least one CPU in Phase-I which will later execute
1491 * write_trylock, so the CPUs in Phase-I will be responsible for
1492 * executing the Phase-II.
1493 * 2. Some other CPU has beaten this CPU to successfully execute the
1494 * write_trylock and has already acquired the write_lock. We know for a
1495 * fact it (other CPU acquiring the write_lock) couldn't have happened
1496 * before this CPU's Phase-I as we held the read_lock.
1497 * 3. Some other CPU executing pcc CMD_READ has stolen the
1498 * down_write, in which case, send_pcc_cmd will check for pending
1499 * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1500 * So this CPU can be certain that its request will be delivered
1501 * So in all cases, this CPU knows that its request will be delivered
1502 * by another CPU and can return
1503 *
1504 * After getting the down_write we still need to check for
1505 * pending_pcc_write_cmd to take care of the following scenario
1506 * The thread running this code could be scheduled out between
1507 * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1508 * could have delivered the request to Platform by triggering the
1509 * doorbell and transferred the ownership of PCC to platform. So this
1510 * avoids triggering an unnecessary doorbell and more importantly before
1511 * triggering the doorbell it makes sure that the PCC channel ownership
1512 * is still with OSPM.
1513 * pending_pcc_write_cmd can also be cleared by a different CPU, if
1514 * there was a pcc CMD_READ waiting on down_write and it steals the lock
1515 * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
1516 * case during a CMD_READ and if there are pending writes it delivers
1517 * the write command before servicing the read command
1518 */
1519 if (CPC_IN_PCC(desired_reg)) {
1520 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
1521 /* Update only if there are pending write commands */
1522 if (pcc_ss_data->pending_pcc_write_cmd)
1523 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1524 up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */
1525 } else
1526 /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1527 wait_event(pcc_ss_data->pcc_write_wait_q,
1528 cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
1529
1530 /* send_pcc_cmd updates the status in case of failure */
1531 ret = cpc_desc->write_cmd_status;
1532 }
1533 return ret;
1534}
1535EXPORT_SYMBOL_GPL(cppc_set_perf);
1536
1537/**
1538 * cppc_get_transition_latency - returns frequency transition latency in ns
1539 *
1540 * ACPI CPPC does not explicitly specify how a platform can specify the
1541 * transition latency for performance change requests. The closest we have
1542 * is the timing information from the PCCT tables which provides the info
1543 * on the number and frequency of PCC commands the platform can handle.
1544 *
1545 * If desired_reg is in the SystemMemory or SystemIo ACPI address space,
1546 * then assume there is no latency.
1547 */
1548unsigned int cppc_get_transition_latency(int cpu_num)
1549{
1550 /*
1551 * Expected transition latency is based on the PCCT timing values
1552 * Below are definition from ACPI spec:
1553 * pcc_nominal- Expected latency to process a command, in microseconds
1554 * pcc_mpar - The maximum number of periodic requests that the subspace
1555 * channel can support, reported in commands per minute. 0
1556 * indicates no limitation.
1557 * pcc_mrtt - The minimum amount of time that OSPM must wait after the
1558 * completion of a command before issuing the next command,
1559 * in microseconds.
1560 */
1561 unsigned int latency_ns = 0;
1562 struct cpc_desc *cpc_desc;
1563 struct cpc_register_resource *desired_reg;
1564 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
1565 struct cppc_pcc_data *pcc_ss_data;
1566
1567 cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1568 if (!cpc_desc)
1569 return CPUFREQ_ETERNAL;
1570
1571 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1572 if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg))
1573 return 0;
1574 else if (!CPC_IN_PCC(desired_reg))
1575 return CPUFREQ_ETERNAL;
1576
1577 if (pcc_ss_id < 0)
1578 return CPUFREQ_ETERNAL;
1579
1580 pcc_ss_data = pcc_data[pcc_ss_id];
1581 if (pcc_ss_data->pcc_mpar)
1582 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
1583
1584 latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
1585 latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
1586
1587 return latency_ns;
1588}
1589EXPORT_SYMBOL_GPL(cppc_get_transition_latency);