1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2012 Regents of the University of California
  4 */
  5
  6#include <asm/thread_info.h>
  7#include <asm/asm-offsets.h>
  8#include <asm/asm.h>
  9#include <linux/init.h>
 10#include <linux/linkage.h>
 11#include <asm/thread_info.h>
 12#include <asm/page.h>
 
 13#include <asm/csr.h>
 
 14#include <asm/hwcap.h>
 15#include <asm/image.h>
 
 
 16
 17__HEAD
 18ENTRY(_start)
 19	/*
 20	 * Image header expected by Linux boot-loaders. The image header data
 21	 * structure is described in asm/image.h.
 22	 * Do not modify it without modifying the structure and all bootloaders
 23	 * that expects this header format!!
 24	 */
 
 
 
 
 
 
 
 25	/* jump to start kernel */
 26	j _start_kernel
 27	/* reserved */
 28	.word 0
 
 29	.balign 8
 
 
 
 
 30#if __riscv_xlen == 64
 31	/* Image load offset(2MB) from start of RAM */
 32	.dword 0x200000
 33#else
 34	/* Image load offset(4MB) from start of RAM */
 35	.dword 0x400000
 36#endif
 
 37	/* Effective size of kernel image */
 38	.dword _end - _start
 39	.dword __HEAD_FLAGS
 40	.word RISCV_HEADER_VERSION
 41	.word 0
 42	.dword 0
 43	.ascii RISCV_IMAGE_MAGIC
 44	.balign 4
 45	.ascii RISCV_IMAGE_MAGIC2
 
 
 
 
 
 
 46	.word 0
 
 47
 48.align 2
 49#ifdef CONFIG_MMU
 50relocate:
 
 51	/* Relocate return address */
 52	li a1, PAGE_OFFSET
 
 
 53	la a2, _start
 54	sub a1, a1, a2
 55	add ra, ra, a1
 56
 57	/* Point stvec to virtual address of intruction after satp write */
 58	la a2, 1f
 59	add a2, a2, a1
 60	csrw CSR_TVEC, a2
 61
 62	/* Compute satp for kernel page tables, but don't load it yet */
 63	srl a2, a0, PAGE_SHIFT
 64	li a1, SATP_MODE
 
 65	or a2, a2, a1
 66
 67	/*
 68	 * Load trampoline page directory, which will cause us to trap to
 69	 * stvec if VA != PA, or simply fall through if VA == PA.  We need a
 70	 * full fence here because setup_vm() just wrote these PTEs and we need
 71	 * to ensure the new translations are in use.
 72	 */
 73	la a0, trampoline_pg_dir
 
 74	srl a0, a0, PAGE_SHIFT
 75	or a0, a0, a1
 76	sfence.vma
 77	csrw CSR_SATP, a0
 78.align 2
 791:
 80	/* Set trap vector to spin forever to help debug */
 81	la a0, .Lsecondary_park
 82	csrw CSR_TVEC, a0
 83
 84	/* Reload the global pointer */
 85.option push
 86.option norelax
 87	la gp, __global_pointer$
 88.option pop
 89
 90	/*
 91	 * Switch to kernel page tables.  A full fence is necessary in order to
 92	 * avoid using the trampoline translations, which are only correct for
 93	 * the first superpage.  Fetching the fence is guarnteed to work
 94	 * because that first superpage is translated the same way.
 95	 */
 96	csrw CSR_SATP, a2
 97	sfence.vma
 98
 99	ret
100#endif /* CONFIG_MMU */
101#ifdef CONFIG_SMP
102	.global secondary_start_sbi
103secondary_start_sbi:
104	/* Mask all interrupts */
105	csrw CSR_IE, zero
106	csrw CSR_IP, zero
107
108	/* Load the global pointer */
109	.option push
110	.option norelax
111		la gp, __global_pointer$
112	.option pop
113
114	/*
115	 * Disable FPU to detect illegal usage of
116	 * floating point in kernel space
117	 */
118	li t0, SR_FS
119	csrc CSR_STATUS, t0
120
121	/* Set trap vector to spin forever to help debug */
122	la a3, .Lsecondary_park
123	csrw CSR_TVEC, a3
124
125	slli a3, a0, LGREG
126	la a4, __cpu_up_stack_pointer
127	la a5, __cpu_up_task_pointer
128	add a4, a3, a4
129	add a5, a3, a5
130	REG_L sp, (a4)
131	REG_L tp, (a5)
 
 
132
133	.global secondary_start_common
134secondary_start_common:
135
136#ifdef CONFIG_MMU
137	/* Enable virtual memory and relocate to virtual address */
138	la a0, swapper_pg_dir
139	call relocate
 
140#endif
141	call setup_trap_vector
142	tail smp_callin
143#endif /* CONFIG_SMP */
144
145.align 2
146setup_trap_vector:
147	/* Set trap vector to exception handler */
148	la a0, handle_exception
149	csrw CSR_TVEC, a0
150
151	/*
152	 * Set sup0 scratch register to 0, indicating to exception vector that
153	 * we are presently executing in kernel.
154	 */
155	csrw CSR_SCRATCH, zero
156	ret
157
 
158.Lsecondary_park:
159	/* We lack SMP support or have too many harts, so park this hart */
160	wfi
161	j .Lsecondary_park
162
163END(_start)
164
165	__INIT
166ENTRY(_start_kernel)
167	/* Mask all interrupts */
168	csrw CSR_IE, zero
169	csrw CSR_IP, zero
170
171#ifdef CONFIG_RISCV_M_MODE
172	/* flush the instruction cache */
173	fence.i
174
175	/* Reset all registers except ra, a0, a1 */
176	call reset_regs
177
178	/*
179	 * Setup a PMP to permit access to all of memory.  Some machines may
180	 * not implement PMPs, so we set up a quick trap handler to just skip
181	 * touching the PMPs on any trap.
182	 */
183	la a0, pmp_done
184	csrw CSR_TVEC, a0
185
186	li a0, -1
187	csrw CSR_PMPADDR0, a0
188	li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X)
189	csrw CSR_PMPCFG0, a0
190.align 2
191pmp_done:
192
193	/*
194	 * The hartid in a0 is expected later on, and we have no firmware
195	 * to hand it to us.
196	 */
197	csrr a0, CSR_MHARTID
198#endif /* CONFIG_RISCV_M_MODE */
199
200	/* Load the global pointer */
201.option push
202.option norelax
203	la gp, __global_pointer$
204.option pop
205
206	/*
207	 * Disable FPU to detect illegal usage of
208	 * floating point in kernel space
209	 */
210	li t0, SR_FS
211	csrc CSR_STATUS, t0
212
213#ifdef CONFIG_SMP
214	li t0, CONFIG_NR_CPUS
215	blt a0, t0, .Lgood_cores
216	tail .Lsecondary_park
217.Lgood_cores:
218#endif
219
 
 
220	/* Pick one hart to run the main boot sequence */
221	la a3, hart_lottery
222	li a2, 1
223	amoadd.w a3, a2, (a3)
224	bnez a3, .Lsecondary_start
225
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
226	/* Clear BSS for flat non-ELF images */
227	la a3, __bss_start
228	la a4, __bss_stop
229	ble a4, a3, clear_bss_done
230clear_bss:
231	REG_S zero, (a3)
232	add a3, a3, RISCV_SZPTR
233	blt a3, a4, clear_bss
234clear_bss_done:
235
236	/* Save hart ID and DTB physical address */
237	mv s0, a0
238	mv s1, a1
 
239	la a2, boot_cpu_hartid
 
240	REG_S a0, (a2)
241
242	/* Initialize page tables and relocate to virtual addresses */
 
243	la sp, init_thread_union + THREAD_SIZE
 
 
 
 
 
244	mv a0, s1
 
245	call setup_vm
246#ifdef CONFIG_MMU
247	la a0, early_pg_dir
248	call relocate
 
249#endif /* CONFIG_MMU */
250
251	call setup_trap_vector
252	/* Restore C environment */
253	la tp, init_task
254	sw zero, TASK_TI_CPU(tp)
255	la sp, init_thread_union + THREAD_SIZE
256
257#ifdef CONFIG_KASAN
258	call kasan_early_init
259#endif
260	/* Start the kernel */
261	call soc_early_init
262	call parse_dtb
263	tail start_kernel
264
 
265.Lsecondary_start:
266#ifdef CONFIG_SMP
267	/* Set trap vector to spin forever to help debug */
268	la a3, .Lsecondary_park
269	csrw CSR_TVEC, a3
270
271	slli a3, a0, LGREG
272	la a1, __cpu_up_stack_pointer
273	la a2, __cpu_up_task_pointer
 
 
274	add a1, a3, a1
275	add a2, a3, a2
276
277	/*
278	 * This hart didn't win the lottery, so we wait for the winning hart to
279	 * get far enough along the boot process that it should continue.
280	 */
281.Lwait_for_cpu_up:
282	/* FIXME: We should WFI to save some energy here. */
283	REG_L sp, (a1)
284	REG_L tp, (a2)
285	beqz sp, .Lwait_for_cpu_up
286	beqz tp, .Lwait_for_cpu_up
287	fence
288
289	tail secondary_start_common
290#endif
291
292END(_start_kernel)
293
294#ifdef CONFIG_RISCV_M_MODE
295ENTRY(reset_regs)
296	li	sp, 0
297	li	gp, 0
298	li	tp, 0
299	li	t0, 0
300	li	t1, 0
301	li	t2, 0
302	li	s0, 0
303	li	s1, 0
304	li	a2, 0
305	li	a3, 0
306	li	a4, 0
307	li	a5, 0
308	li	a6, 0
309	li	a7, 0
310	li	s2, 0
311	li	s3, 0
312	li	s4, 0
313	li	s5, 0
314	li	s6, 0
315	li	s7, 0
316	li	s8, 0
317	li	s9, 0
318	li	s10, 0
319	li	s11, 0
320	li	t3, 0
321	li	t4, 0
322	li	t5, 0
323	li	t6, 0
324	csrw	CSR_SCRATCH, 0
325
326#ifdef CONFIG_FPU
327	csrr	t0, CSR_MISA
328	andi	t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
329	beqz	t0, .Lreset_regs_done
330
331	li	t1, SR_FS
332	csrs	CSR_STATUS, t1
333	fmv.s.x	f0, zero
334	fmv.s.x	f1, zero
335	fmv.s.x	f2, zero
336	fmv.s.x	f3, zero
337	fmv.s.x	f4, zero
338	fmv.s.x	f5, zero
339	fmv.s.x	f6, zero
340	fmv.s.x	f7, zero
341	fmv.s.x	f8, zero
342	fmv.s.x	f9, zero
343	fmv.s.x	f10, zero
344	fmv.s.x	f11, zero
345	fmv.s.x	f12, zero
346	fmv.s.x	f13, zero
347	fmv.s.x	f14, zero
348	fmv.s.x	f15, zero
349	fmv.s.x	f16, zero
350	fmv.s.x	f17, zero
351	fmv.s.x	f18, zero
352	fmv.s.x	f19, zero
353	fmv.s.x	f20, zero
354	fmv.s.x	f21, zero
355	fmv.s.x	f22, zero
356	fmv.s.x	f23, zero
357	fmv.s.x	f24, zero
358	fmv.s.x	f25, zero
359	fmv.s.x	f26, zero
360	fmv.s.x	f27, zero
361	fmv.s.x	f28, zero
362	fmv.s.x	f29, zero
363	fmv.s.x	f30, zero
364	fmv.s.x	f31, zero
365	csrw	fcsr, 0
366	/* note that the caller must clear SR_FS */
367#endif /* CONFIG_FPU */
368.Lreset_regs_done:
369	ret
370END(reset_regs)
371#endif /* CONFIG_RISCV_M_MODE */
372
373__PAGE_ALIGNED_BSS
374	/* Empty zero page */
375	.balign PAGE_SIZE

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2012 Regents of the University of California
  4 */
  5
 
  6#include <asm/asm-offsets.h>
  7#include <asm/asm.h>
  8#include <linux/init.h>
  9#include <linux/linkage.h>
 10#include <asm/thread_info.h>
 11#include <asm/page.h>
 12#include <asm/pgtable.h>
 13#include <asm/csr.h>
 14#include <asm/cpu_ops_sbi.h>
 15#include <asm/hwcap.h>
 16#include <asm/image.h>
 17#include <asm/xip_fixup.h>
 18#include "efi-header.S"
 19
 20__HEAD
 21ENTRY(_start)
 22	/*
 23	 * Image header expected by Linux boot-loaders. The image header data
 24	 * structure is described in asm/image.h.
 25	 * Do not modify it without modifying the structure and all bootloaders
 26	 * that expects this header format!!
 27	 */
 28#ifdef CONFIG_EFI
 29	/*
 30	 * This instruction decodes to "MZ" ASCII required by UEFI.
 31	 */
 32	c.li s4,-13
 33	j _start_kernel
 34#else
 35	/* jump to start kernel */
 36	j _start_kernel
 37	/* reserved */
 38	.word 0
 39#endif
 40	.balign 8
 41#ifdef CONFIG_RISCV_M_MODE
 42	/* Image load offset (0MB) from start of RAM for M-mode */
 43	.dword 0
 44#else
 45#if __riscv_xlen == 64
 46	/* Image load offset(2MB) from start of RAM */
 47	.dword 0x200000
 48#else
 49	/* Image load offset(4MB) from start of RAM */
 50	.dword 0x400000
 51#endif
 52#endif
 53	/* Effective size of kernel image */
 54	.dword _end - _start
 55	.dword __HEAD_FLAGS
 56	.word RISCV_HEADER_VERSION
 57	.word 0
 58	.dword 0
 59	.ascii RISCV_IMAGE_MAGIC
 60	.balign 4
 61	.ascii RISCV_IMAGE_MAGIC2
 62#ifdef CONFIG_EFI
 63	.word pe_head_start - _start
 64pe_head_start:
 65
 66	__EFI_PE_HEADER
 67#else
 68	.word 0
 69#endif
 70
 71.align 2
 72#ifdef CONFIG_MMU
 73	.global relocate_enable_mmu
 74relocate_enable_mmu:
 75	/* Relocate return address */
 76	la a1, kernel_map
 77	XIP_FIXUP_OFFSET a1
 78	REG_L a1, KERNEL_MAP_VIRT_ADDR(a1)
 79	la a2, _start
 80	sub a1, a1, a2
 81	add ra, ra, a1
 82
 83	/* Point stvec to virtual address of intruction after satp write */
 84	la a2, 1f
 85	add a2, a2, a1
 86	csrw CSR_TVEC, a2
 87
 88	/* Compute satp for kernel page tables, but don't load it yet */
 89	srl a2, a0, PAGE_SHIFT
 90	la a1, satp_mode
 91	REG_L a1, 0(a1)
 92	or a2, a2, a1
 93
 94	/*
 95	 * Load trampoline page directory, which will cause us to trap to
 96	 * stvec if VA != PA, or simply fall through if VA == PA.  We need a
 97	 * full fence here because setup_vm() just wrote these PTEs and we need
 98	 * to ensure the new translations are in use.
 99	 */
100	la a0, trampoline_pg_dir
101	XIP_FIXUP_OFFSET a0
102	srl a0, a0, PAGE_SHIFT
103	or a0, a0, a1
104	sfence.vma
105	csrw CSR_SATP, a0
106.align 2
1071:
108	/* Set trap vector to spin forever to help debug */
109	la a0, .Lsecondary_park
110	csrw CSR_TVEC, a0
111
112	/* Reload the global pointer */
113.option push
114.option norelax
115	la gp, __global_pointer$
116.option pop
117
118	/*
119	 * Switch to kernel page tables.  A full fence is necessary in order to
120	 * avoid using the trampoline translations, which are only correct for
121	 * the first superpage.  Fetching the fence is guaranteed to work
122	 * because that first superpage is translated the same way.
123	 */
124	csrw CSR_SATP, a2
125	sfence.vma
126
127	ret
128#endif /* CONFIG_MMU */
129#ifdef CONFIG_SMP
130	.global secondary_start_sbi
131secondary_start_sbi:
132	/* Mask all interrupts */
133	csrw CSR_IE, zero
134	csrw CSR_IP, zero
135
136	/* Load the global pointer */
137	.option push
138	.option norelax
139		la gp, __global_pointer$
140	.option pop
141
142	/*
143	 * Disable FPU to detect illegal usage of
144	 * floating point in kernel space
145	 */
146	li t0, SR_FS
147	csrc CSR_STATUS, t0
148
149	/* Set trap vector to spin forever to help debug */
150	la a3, .Lsecondary_park
151	csrw CSR_TVEC, a3
152
153	/* a0 contains the hartid & a1 contains boot data */
154	li a2, SBI_HART_BOOT_TASK_PTR_OFFSET
155	XIP_FIXUP_OFFSET a2
156	add a2, a2, a1
157	REG_L tp, (a2)
158	li a3, SBI_HART_BOOT_STACK_PTR_OFFSET
159	XIP_FIXUP_OFFSET a3
160	add a3, a3, a1
161	REG_L sp, (a3)
162
163.Lsecondary_start_common:
 
164
165#ifdef CONFIG_MMU
166	/* Enable virtual memory and relocate to virtual address */
167	la a0, swapper_pg_dir
168	XIP_FIXUP_OFFSET a0
169	call relocate_enable_mmu
170#endif
171	call setup_trap_vector
172	tail smp_callin
173#endif /* CONFIG_SMP */
174
175.align 2
176setup_trap_vector:
177	/* Set trap vector to exception handler */
178	la a0, handle_exception
179	csrw CSR_TVEC, a0
180
181	/*
182	 * Set sup0 scratch register to 0, indicating to exception vector that
183	 * we are presently executing in kernel.
184	 */
185	csrw CSR_SCRATCH, zero
186	ret
187
188.align 2
189.Lsecondary_park:
190	/* We lack SMP support or have too many harts, so park this hart */
191	wfi
192	j .Lsecondary_park
193
194END(_start)
195
 
196ENTRY(_start_kernel)
197	/* Mask all interrupts */
198	csrw CSR_IE, zero
199	csrw CSR_IP, zero
200
201#ifdef CONFIG_RISCV_M_MODE
202	/* flush the instruction cache */
203	fence.i
204
205	/* Reset all registers except ra, a0, a1 */
206	call reset_regs
207
208	/*
209	 * Setup a PMP to permit access to all of memory.  Some machines may
210	 * not implement PMPs, so we set up a quick trap handler to just skip
211	 * touching the PMPs on any trap.
212	 */
213	la a0, pmp_done
214	csrw CSR_TVEC, a0
215
216	li a0, -1
217	csrw CSR_PMPADDR0, a0
218	li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X)
219	csrw CSR_PMPCFG0, a0
220.align 2
221pmp_done:
222
223	/*
224	 * The hartid in a0 is expected later on, and we have no firmware
225	 * to hand it to us.
226	 */
227	csrr a0, CSR_MHARTID
228#endif /* CONFIG_RISCV_M_MODE */
229
230	/* Load the global pointer */
231.option push
232.option norelax
233	la gp, __global_pointer$
234.option pop
235
236	/*
237	 * Disable FPU to detect illegal usage of
238	 * floating point in kernel space
239	 */
240	li t0, SR_FS
241	csrc CSR_STATUS, t0
242
243#ifdef CONFIG_RISCV_BOOT_SPINWAIT
244	li t0, CONFIG_NR_CPUS
245	blt a0, t0, .Lgood_cores
246	tail .Lsecondary_park
247.Lgood_cores:
 
248
249	/* The lottery system is only required for spinwait booting method */
250#ifndef CONFIG_XIP_KERNEL
251	/* Pick one hart to run the main boot sequence */
252	la a3, hart_lottery
253	li a2, 1
254	amoadd.w a3, a2, (a3)
255	bnez a3, .Lsecondary_start
256
257#else
258	/* hart_lottery in flash contains a magic number */
259	la a3, hart_lottery
260	mv a2, a3
261	XIP_FIXUP_OFFSET a2
262	XIP_FIXUP_FLASH_OFFSET a3
263	lw t1, (a3)
264	amoswap.w t0, t1, (a2)
265	/* first time here if hart_lottery in RAM is not set */
266	beq t0, t1, .Lsecondary_start
267
268#endif /* CONFIG_XIP */
269#endif /* CONFIG_RISCV_BOOT_SPINWAIT */
270
271#ifdef CONFIG_XIP_KERNEL
272	la sp, _end + THREAD_SIZE
273	XIP_FIXUP_OFFSET sp
274	mv s0, a0
275	call __copy_data
276
277	/* Restore a0 copy */
278	mv a0, s0
279#endif
280
281#ifndef CONFIG_XIP_KERNEL
282	/* Clear BSS for flat non-ELF images */
283	la a3, __bss_start
284	la a4, __bss_stop
285	ble a4, a3, clear_bss_done
286clear_bss:
287	REG_S zero, (a3)
288	add a3, a3, RISCV_SZPTR
289	blt a3, a4, clear_bss
290clear_bss_done:
291#endif
292	/* Save hart ID and DTB physical address */
293	mv s0, a0
294	mv s1, a1
295
296	la a2, boot_cpu_hartid
297	XIP_FIXUP_OFFSET a2
298	REG_S a0, (a2)
299
300	/* Initialize page tables and relocate to virtual addresses */
301	la tp, init_task
302	la sp, init_thread_union + THREAD_SIZE
303	XIP_FIXUP_OFFSET sp
304#ifdef CONFIG_BUILTIN_DTB
305	la a0, __dtb_start
306	XIP_FIXUP_OFFSET a0
307#else
308	mv a0, s1
309#endif /* CONFIG_BUILTIN_DTB */
310	call setup_vm
311#ifdef CONFIG_MMU
312	la a0, early_pg_dir
313	XIP_FIXUP_OFFSET a0
314	call relocate_enable_mmu
315#endif /* CONFIG_MMU */
316
317	call setup_trap_vector
318	/* Restore C environment */
319	la tp, init_task
 
320	la sp, init_thread_union + THREAD_SIZE
321
322#ifdef CONFIG_KASAN
323	call kasan_early_init
324#endif
325	/* Start the kernel */
326	call soc_early_init
 
327	tail start_kernel
328
329#ifdef CONFIG_RISCV_BOOT_SPINWAIT
330.Lsecondary_start:
 
331	/* Set trap vector to spin forever to help debug */
332	la a3, .Lsecondary_park
333	csrw CSR_TVEC, a3
334
335	slli a3, a0, LGREG
336	la a1, __cpu_spinwait_stack_pointer
337	XIP_FIXUP_OFFSET a1
338	la a2, __cpu_spinwait_task_pointer
339	XIP_FIXUP_OFFSET a2
340	add a1, a3, a1
341	add a2, a3, a2
342
343	/*
344	 * This hart didn't win the lottery, so we wait for the winning hart to
345	 * get far enough along the boot process that it should continue.
346	 */
347.Lwait_for_cpu_up:
348	/* FIXME: We should WFI to save some energy here. */
349	REG_L sp, (a1)
350	REG_L tp, (a2)
351	beqz sp, .Lwait_for_cpu_up
352	beqz tp, .Lwait_for_cpu_up
353	fence
354
355	tail .Lsecondary_start_common
356#endif /* CONFIG_RISCV_BOOT_SPINWAIT */
357
358END(_start_kernel)
359
360#ifdef CONFIG_RISCV_M_MODE
361ENTRY(reset_regs)
362	li	sp, 0
363	li	gp, 0
364	li	tp, 0
365	li	t0, 0
366	li	t1, 0
367	li	t2, 0
368	li	s0, 0
369	li	s1, 0
370	li	a2, 0
371	li	a3, 0
372	li	a4, 0
373	li	a5, 0
374	li	a6, 0
375	li	a7, 0
376	li	s2, 0
377	li	s3, 0
378	li	s4, 0
379	li	s5, 0
380	li	s6, 0
381	li	s7, 0
382	li	s8, 0
383	li	s9, 0
384	li	s10, 0
385	li	s11, 0
386	li	t3, 0
387	li	t4, 0
388	li	t5, 0
389	li	t6, 0
390	csrw	CSR_SCRATCH, 0
391
392#ifdef CONFIG_FPU
393	csrr	t0, CSR_MISA
394	andi	t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
395	beqz	t0, .Lreset_regs_done
396
397	li	t1, SR_FS
398	csrs	CSR_STATUS, t1
399	fmv.s.x	f0, zero
400	fmv.s.x	f1, zero
401	fmv.s.x	f2, zero
402	fmv.s.x	f3, zero
403	fmv.s.x	f4, zero
404	fmv.s.x	f5, zero
405	fmv.s.x	f6, zero
406	fmv.s.x	f7, zero
407	fmv.s.x	f8, zero
408	fmv.s.x	f9, zero
409	fmv.s.x	f10, zero
410	fmv.s.x	f11, zero
411	fmv.s.x	f12, zero
412	fmv.s.x	f13, zero
413	fmv.s.x	f14, zero
414	fmv.s.x	f15, zero
415	fmv.s.x	f16, zero
416	fmv.s.x	f17, zero
417	fmv.s.x	f18, zero
418	fmv.s.x	f19, zero
419	fmv.s.x	f20, zero
420	fmv.s.x	f21, zero
421	fmv.s.x	f22, zero
422	fmv.s.x	f23, zero
423	fmv.s.x	f24, zero
424	fmv.s.x	f25, zero
425	fmv.s.x	f26, zero
426	fmv.s.x	f27, zero
427	fmv.s.x	f28, zero
428	fmv.s.x	f29, zero
429	fmv.s.x	f30, zero
430	fmv.s.x	f31, zero
431	csrw	fcsr, 0
432	/* note that the caller must clear SR_FS */
433#endif /* CONFIG_FPU */
434.Lreset_regs_done:
435	ret
436END(reset_regs)
437#endif /* CONFIG_RISCV_M_MODE */