1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * 
   4 * Common boot and setup code.
   5 *
   6 * Copyright (C) 2001 PPC64 Team, IBM Corp
   7 */
   8
   9#include <linux/export.h>
  10#include <linux/string.h>
  11#include <linux/sched.h>
  12#include <linux/init.h>
  13#include <linux/kernel.h>
  14#include <linux/reboot.h>
  15#include <linux/delay.h>
  16#include <linux/initrd.h>
  17#include <linux/seq_file.h>
  18#include <linux/ioport.h>
  19#include <linux/console.h>
  20#include <linux/utsname.h>
  21#include <linux/tty.h>
  22#include <linux/root_dev.h>
  23#include <linux/notifier.h>
  24#include <linux/cpu.h>
  25#include <linux/unistd.h>
  26#include <linux/serial.h>
  27#include <linux/serial_8250.h>
  28#include <linux/memblock.h>
  29#include <linux/pci.h>
  30#include <linux/lockdep.h>
  31#include <linux/memory.h>
  32#include <linux/nmi.h>
  33#include <linux/pgtable.h>
 
 
  34
  35#include <asm/debugfs.h>
 
  36#include <asm/io.h>
  37#include <asm/kdump.h>
  38#include <asm/prom.h>
  39#include <asm/processor.h>
  40#include <asm/smp.h>
  41#include <asm/elf.h>
  42#include <asm/machdep.h>
  43#include <asm/paca.h>
  44#include <asm/time.h>
  45#include <asm/cputable.h>
  46#include <asm/dt_cpu_ftrs.h>
  47#include <asm/sections.h>
  48#include <asm/btext.h>
  49#include <asm/nvram.h>
  50#include <asm/setup.h>
  51#include <asm/rtas.h>
  52#include <asm/iommu.h>
  53#include <asm/serial.h>
  54#include <asm/cache.h>
  55#include <asm/page.h>
  56#include <asm/mmu.h>
  57#include <asm/firmware.h>
  58#include <asm/xmon.h>
  59#include <asm/udbg.h>
  60#include <asm/kexec.h>
  61#include <asm/code-patching.h>
  62#include <asm/livepatch.h>
  63#include <asm/opal.h>
  64#include <asm/cputhreads.h>
  65#include <asm/hw_irq.h>
  66#include <asm/feature-fixups.h>
  67#include <asm/kup.h>
  68#include <asm/early_ioremap.h>
 
  69
  70#include "setup.h"
  71
  72int spinning_secondaries;
  73u64 ppc64_pft_size;
  74
  75struct ppc64_caches ppc64_caches = {
  76	.l1d = {
  77		.block_size = 0x40,
  78		.log_block_size = 6,
  79	},
  80	.l1i = {
  81		.block_size = 0x40,
  82		.log_block_size = 6
  83	},
  84};
  85EXPORT_SYMBOL_GPL(ppc64_caches);
  86
  87#if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
  88void __init setup_tlb_core_data(void)
  89{
  90	int cpu;
  91
  92	BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
  93
  94	for_each_possible_cpu(cpu) {
  95		int first = cpu_first_thread_sibling(cpu);
  96
  97		/*
  98		 * If we boot via kdump on a non-primary thread,
  99		 * make sure we point at the thread that actually
 100		 * set up this TLB.
 101		 */
 102		if (cpu_first_thread_sibling(boot_cpuid) == first)
 103			first = boot_cpuid;
 104
 105		paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd;
 106
 107		/*
 108		 * If we have threads, we need either tlbsrx.
 109		 * or e6500 tablewalk mode, or else TLB handlers
 110		 * will be racy and could produce duplicate entries.
 111		 * Should we panic instead?
 112		 */
 113		WARN_ONCE(smt_enabled_at_boot >= 2 &&
 114			  !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
 115			  book3e_htw_mode != PPC_HTW_E6500,
 116			  "%s: unsupported MMU configuration\n", __func__);
 117	}
 118}
 119#endif
 120
 121#ifdef CONFIG_SMP
 122
 123static char *smt_enabled_cmdline;
 124
 125/* Look for ibm,smt-enabled OF option */
 126void __init check_smt_enabled(void)
 127{
 128	struct device_node *dn;
 129	const char *smt_option;
 130
 131	/* Default to enabling all threads */
 132	smt_enabled_at_boot = threads_per_core;
 133
 134	/* Allow the command line to overrule the OF option */
 135	if (smt_enabled_cmdline) {
 136		if (!strcmp(smt_enabled_cmdline, "on"))
 137			smt_enabled_at_boot = threads_per_core;
 138		else if (!strcmp(smt_enabled_cmdline, "off"))
 139			smt_enabled_at_boot = 0;
 140		else {
 141			int smt;
 142			int rc;
 143
 144			rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
 145			if (!rc)
 146				smt_enabled_at_boot =
 147					min(threads_per_core, smt);
 148		}
 149	} else {
 150		dn = of_find_node_by_path("/options");
 151		if (dn) {
 152			smt_option = of_get_property(dn, "ibm,smt-enabled",
 153						     NULL);
 154
 155			if (smt_option) {
 156				if (!strcmp(smt_option, "on"))
 157					smt_enabled_at_boot = threads_per_core;
 158				else if (!strcmp(smt_option, "off"))
 159					smt_enabled_at_boot = 0;
 160			}
 161
 162			of_node_put(dn);
 163		}
 164	}
 165}
 166
 167/* Look for smt-enabled= cmdline option */
 168static int __init early_smt_enabled(char *p)
 169{
 170	smt_enabled_cmdline = p;
 171	return 0;
 172}
 173early_param("smt-enabled", early_smt_enabled);
 174
 175#endif /* CONFIG_SMP */
 176
 177/** Fix up paca fields required for the boot cpu */
 178static void __init fixup_boot_paca(void)
 179{
 180	/* The boot cpu is started */
 181	get_paca()->cpu_start = 1;
 
 
 
 
 
 
 
 
 
 
 182	/* Allow percpu accesses to work until we setup percpu data */
 183	get_paca()->data_offset = 0;
 184	/* Mark interrupts disabled in PACA */
 185	irq_soft_mask_set(IRQS_DISABLED);
 
 
 186}
 187
 188static void __init configure_exceptions(void)
 189{
 190	/*
 191	 * Setup the trampolines from the lowmem exception vectors
 192	 * to the kdump kernel when not using a relocatable kernel.
 193	 */
 194	setup_kdump_trampoline();
 195
 196	/* Under a PAPR hypervisor, we need hypercalls */
 197	if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 198		/* Enable AIL if possible */
 199		if (!pseries_enable_reloc_on_exc()) {
 200			init_task.thread.fscr &= ~FSCR_SCV;
 201			cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_SCV;
 202		}
 203
 204		/*
 205		 * Tell the hypervisor that we want our exceptions to
 206		 * be taken in little endian mode.
 207		 *
 208		 * We don't call this for big endian as our calling convention
 209		 * makes us always enter in BE, and the call may fail under
 210		 * some circumstances with kdump.
 211		 */
 212#ifdef __LITTLE_ENDIAN__
 213		pseries_little_endian_exceptions();
 214#endif
 215	} else {
 216		/* Set endian mode using OPAL */
 217		if (firmware_has_feature(FW_FEATURE_OPAL))
 218			opal_configure_cores();
 219
 220		/* AIL on native is done in cpu_ready_for_interrupts() */
 221	}
 222}
 223
 224static void cpu_ready_for_interrupts(void)
 225{
 226	/*
 227	 * Enable AIL if supported, and we are in hypervisor mode. This
 228	 * is called once for every processor.
 229	 *
 230	 * If we are not in hypervisor mode the job is done once for
 231	 * the whole partition in configure_exceptions().
 232	 */
 233	if (cpu_has_feature(CPU_FTR_HVMODE) &&
 234	    cpu_has_feature(CPU_FTR_ARCH_207S)) {
 235		unsigned long lpcr = mfspr(SPRN_LPCR);
 236		mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 237	}
 238
 239	/*
 240	 * Set HFSCR:TM based on CPU features:
 241	 * In the special case of TM no suspend (P9N DD2.1), Linux is
 242	 * told TM is off via the dt-ftrs but told to (partially) use
 243	 * it via OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED. So HFSCR[TM]
 244	 * will be off from dt-ftrs but we need to turn it on for the
 245	 * no suspend case.
 246	 */
 247	if (cpu_has_feature(CPU_FTR_HVMODE)) {
 248		if (cpu_has_feature(CPU_FTR_TM_COMP))
 249			mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) | HFSCR_TM);
 250		else
 251			mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
 252	}
 253
 254	/* Set IR and DR in PACA MSR */
 255	get_paca()->kernel_msr = MSR_KERNEL;
 256}
 257
 258unsigned long spr_default_dscr = 0;
 259
 260void __init record_spr_defaults(void)
 261{
 262	if (early_cpu_has_feature(CPU_FTR_DSCR))
 263		spr_default_dscr = mfspr(SPRN_DSCR);
 264}
 265
 266/*
 267 * Early initialization entry point. This is called by head.S
 268 * with MMU translation disabled. We rely on the "feature" of
 269 * the CPU that ignores the top 2 bits of the address in real
 270 * mode so we can access kernel globals normally provided we
 271 * only toy with things in the RMO region. From here, we do
 272 * some early parsing of the device-tree to setup out MEMBLOCK
 273 * data structures, and allocate & initialize the hash table
 274 * and segment tables so we can start running with translation
 275 * enabled.
 276 *
 277 * It is this function which will call the probe() callback of
 278 * the various platform types and copy the matching one to the
 279 * global ppc_md structure. Your platform can eventually do
 280 * some very early initializations from the probe() routine, but
 281 * this is not recommended, be very careful as, for example, the
 282 * device-tree is not accessible via normal means at this point.
 283 */
 284
 285void __init __nostackprotector early_setup(unsigned long dt_ptr)
 286{
 287	static __initdata struct paca_struct boot_paca;
 288
 289	/* -------- printk is _NOT_ safe to use here ! ------- */
 290
 291	/*
 292	 * Assume we're on cpu 0 for now.
 293	 *
 294	 * We need to load a PACA very early for a few reasons.
 295	 *
 296	 * The stack protector canary is stored in the paca, so as soon as we
 297	 * call any stack protected code we need r13 pointing somewhere valid.
 298	 *
 299	 * If we are using kcov it will call in_task() in its instrumentation,
 300	 * which relies on the current task from the PACA.
 301	 *
 302	 * dt_cpu_ftrs_init() calls into generic OF/fdt code, as well as
 303	 * printk(), which can trigger both stack protector and kcov.
 304	 *
 305	 * percpu variables and spin locks also use the paca.
 306	 *
 307	 * So set up a temporary paca. It will be replaced below once we know
 308	 * what CPU we are on.
 309	 */
 310	initialise_paca(&boot_paca, 0);
 311	setup_paca(&boot_paca);
 312	fixup_boot_paca();
 
 313
 314	/* -------- printk is now safe to use ------- */
 315
 
 
 
 316	/* Try new device tree based feature discovery ... */
 317	if (!dt_cpu_ftrs_init(__va(dt_ptr)))
 318		/* Otherwise use the old style CPU table */
 319		identify_cpu(0, mfspr(SPRN_PVR));
 320
 321	/* Enable early debugging if any specified (see udbg.h) */
 322	udbg_early_init();
 323
 324	udbg_printf(" -> %s(), dt_ptr: 0x%lx\n", __func__, dt_ptr);
 325
 326	/*
 327	 * Do early initialization using the flattened device
 328	 * tree, such as retrieving the physical memory map or
 329	 * calculating/retrieving the hash table size.
 330	 */
 331	early_init_devtree(__va(dt_ptr));
 332
 333	/* Now we know the logical id of our boot cpu, setup the paca. */
 334	if (boot_cpuid != 0) {
 335		/* Poison paca_ptrs[0] again if it's not the boot cpu */
 336		memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0]));
 337	}
 338	setup_paca(paca_ptrs[boot_cpuid]);
 339	fixup_boot_paca();
 340
 341	/*
 342	 * Configure exception handlers. This include setting up trampolines
 343	 * if needed, setting exception endian mode, etc...
 344	 */
 345	configure_exceptions();
 346
 347	/*
 348	 * Configure Kernel Userspace Protection. This needs to happen before
 349	 * feature fixups for platforms that implement this using features.
 350	 */
 351	setup_kup();
 352
 353	/* Apply all the dynamic patching */
 354	apply_feature_fixups();
 355	setup_feature_keys();
 356
 357	early_ioremap_setup();
 358
 359	/* Initialize the hash table or TLB handling */
 360	early_init_mmu();
 361
 
 
 362	/*
 363	 * After firmware and early platform setup code has set things up,
 364	 * we note the SPR values for configurable control/performance
 365	 * registers, and use those as initial defaults.
 366	 */
 367	record_spr_defaults();
 368
 369	/*
 370	 * At this point, we can let interrupts switch to virtual mode
 371	 * (the MMU has been setup), so adjust the MSR in the PACA to
 372	 * have IR and DR set and enable AIL if it exists
 373	 */
 374	cpu_ready_for_interrupts();
 375
 376	/*
 377	 * We enable ftrace here, but since we only support DYNAMIC_FTRACE, it
 378	 * will only actually get enabled on the boot cpu much later once
 379	 * ftrace itself has been initialized.
 380	 */
 381	this_cpu_enable_ftrace();
 382
 383	udbg_printf(" <- %s()\n", __func__);
 384
 385#ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
 386	/*
 387	 * This needs to be done *last* (after the above udbg_printf() even)
 388	 *
 389	 * Right after we return from this function, we turn on the MMU
 390	 * which means the real-mode access trick that btext does will
 391	 * no longer work, it needs to switch to using a real MMU
 392	 * mapping. This call will ensure that it does
 393	 */
 394	btext_map();
 395#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
 396}
 397
 398#ifdef CONFIG_SMP
 399void early_setup_secondary(void)
 400{
 401	/* Mark interrupts disabled in PACA */
 402	irq_soft_mask_set(IRQS_DISABLED);
 403
 404	/* Initialize the hash table or TLB handling */
 405	early_init_mmu_secondary();
 406
 407	/* Perform any KUP setup that is per-cpu */
 408	setup_kup();
 409
 410	/*
 411	 * At this point, we can let interrupts switch to virtual mode
 412	 * (the MMU has been setup), so adjust the MSR in the PACA to
 413	 * have IR and DR set.
 414	 */
 415	cpu_ready_for_interrupts();
 416}
 417
 418#endif /* CONFIG_SMP */
 419
 420void panic_smp_self_stop(void)
 421{
 422	hard_irq_disable();
 423	spin_begin();
 424	while (1)
 425		spin_cpu_relax();
 426}
 427
 428#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
 429static bool use_spinloop(void)
 430{
 431	if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
 432		/*
 433		 * See comments in head_64.S -- not all platforms insert
 434		 * secondaries at __secondary_hold and wait at the spin
 435		 * loop.
 436		 */
 437		if (firmware_has_feature(FW_FEATURE_OPAL))
 438			return false;
 439		return true;
 440	}
 441
 442	/*
 443	 * When book3e boots from kexec, the ePAPR spin table does
 444	 * not get used.
 445	 */
 446	return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
 447}
 448
 449void smp_release_cpus(void)
 450{
 451	unsigned long *ptr;
 452	int i;
 453
 454	if (!use_spinloop())
 455		return;
 456
 457	/* All secondary cpus are spinning on a common spinloop, release them
 458	 * all now so they can start to spin on their individual paca
 459	 * spinloops. For non SMP kernels, the secondary cpus never get out
 460	 * of the common spinloop.
 461	 */
 462
 463	ptr  = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
 464			- PHYSICAL_START);
 465	*ptr = ppc_function_entry(generic_secondary_smp_init);
 466
 467	/* And wait a bit for them to catch up */
 468	for (i = 0; i < 100000; i++) {
 469		mb();
 470		HMT_low();
 471		if (spinning_secondaries == 0)
 472			break;
 473		udelay(1);
 474	}
 475	pr_debug("spinning_secondaries = %d\n", spinning_secondaries);
 476}
 477#endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
 478
 479/*
 480 * Initialize some remaining members of the ppc64_caches and systemcfg
 481 * structures
 482 * (at least until we get rid of them completely). This is mostly some
 483 * cache informations about the CPU that will be used by cache flush
 484 * routines and/or provided to userland
 485 */
 486
 487static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
 488			    u32 bsize, u32 sets)
 489{
 490	info->size = size;
 491	info->sets = sets;
 492	info->line_size = lsize;
 493	info->block_size = bsize;
 494	info->log_block_size = __ilog2(bsize);
 495	if (bsize)
 496		info->blocks_per_page = PAGE_SIZE / bsize;
 497	else
 498		info->blocks_per_page = 0;
 499
 500	if (sets == 0)
 501		info->assoc = 0xffff;
 502	else
 503		info->assoc = size / (sets * lsize);
 504}
 505
 506static bool __init parse_cache_info(struct device_node *np,
 507				    bool icache,
 508				    struct ppc_cache_info *info)
 509{
 510	static const char *ipropnames[] __initdata = {
 511		"i-cache-size",
 512		"i-cache-sets",
 513		"i-cache-block-size",
 514		"i-cache-line-size",
 515	};
 516	static const char *dpropnames[] __initdata = {
 517		"d-cache-size",
 518		"d-cache-sets",
 519		"d-cache-block-size",
 520		"d-cache-line-size",
 521	};
 522	const char **propnames = icache ? ipropnames : dpropnames;
 523	const __be32 *sizep, *lsizep, *bsizep, *setsp;
 524	u32 size, lsize, bsize, sets;
 525	bool success = true;
 526
 527	size = 0;
 528	sets = -1u;
 529	lsize = bsize = cur_cpu_spec->dcache_bsize;
 530	sizep = of_get_property(np, propnames[0], NULL);
 531	if (sizep != NULL)
 532		size = be32_to_cpu(*sizep);
 533	setsp = of_get_property(np, propnames[1], NULL);
 534	if (setsp != NULL)
 535		sets = be32_to_cpu(*setsp);
 536	bsizep = of_get_property(np, propnames[2], NULL);
 537	lsizep = of_get_property(np, propnames[3], NULL);
 538	if (bsizep == NULL)
 539		bsizep = lsizep;
 540	if (lsizep == NULL)
 541		lsizep = bsizep;
 542	if (lsizep != NULL)
 543		lsize = be32_to_cpu(*lsizep);
 544	if (bsizep != NULL)
 545		bsize = be32_to_cpu(*bsizep);
 546	if (sizep == NULL || bsizep == NULL || lsizep == NULL)
 547		success = false;
 548
 549	/*
 550	 * OF is weird .. it represents fully associative caches
 551	 * as "1 way" which doesn't make much sense and doesn't
 552	 * leave room for direct mapped. We'll assume that 0
 553	 * in OF means direct mapped for that reason.
 554	 */
 555	if (sets == 1)
 556		sets = 0;
 557	else if (sets == 0)
 558		sets = 1;
 559
 560	init_cache_info(info, size, lsize, bsize, sets);
 561
 562	return success;
 563}
 564
 565void __init initialize_cache_info(void)
 566{
 567	struct device_node *cpu = NULL, *l2, *l3 = NULL;
 568	u32 pvr;
 569
 570	/*
 571	 * All shipping POWER8 machines have a firmware bug that
 572	 * puts incorrect information in the device-tree. This will
 573	 * be (hopefully) fixed for future chips but for now hard
 574	 * code the values if we are running on one of these
 575	 */
 576	pvr = PVR_VER(mfspr(SPRN_PVR));
 577	if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
 578	    pvr == PVR_POWER8NVL) {
 579						/* size    lsize   blk  sets */
 580		init_cache_info(&ppc64_caches.l1i, 0x8000,   128,  128, 32);
 581		init_cache_info(&ppc64_caches.l1d, 0x10000,  128,  128, 64);
 582		init_cache_info(&ppc64_caches.l2,  0x80000,  128,  0,   512);
 583		init_cache_info(&ppc64_caches.l3,  0x800000, 128,  0,   8192);
 584	} else
 585		cpu = of_find_node_by_type(NULL, "cpu");
 586
 587	/*
 588	 * We're assuming *all* of the CPUs have the same
 589	 * d-cache and i-cache sizes... -Peter
 590	 */
 591	if (cpu) {
 592		if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
 593			pr_warn("Argh, can't find dcache properties !\n");
 594
 595		if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
 596			pr_warn("Argh, can't find icache properties !\n");
 597
 598		/*
 599		 * Try to find the L2 and L3 if any. Assume they are
 600		 * unified and use the D-side properties.
 601		 */
 602		l2 = of_find_next_cache_node(cpu);
 603		of_node_put(cpu);
 604		if (l2) {
 605			parse_cache_info(l2, false, &ppc64_caches.l2);
 606			l3 = of_find_next_cache_node(l2);
 607			of_node_put(l2);
 608		}
 609		if (l3) {
 610			parse_cache_info(l3, false, &ppc64_caches.l3);
 611			of_node_put(l3);
 612		}
 613	}
 614
 615	/* For use by binfmt_elf */
 616	dcache_bsize = ppc64_caches.l1d.block_size;
 617	icache_bsize = ppc64_caches.l1i.block_size;
 618
 619	cur_cpu_spec->dcache_bsize = dcache_bsize;
 620	cur_cpu_spec->icache_bsize = icache_bsize;
 621}
 622
 623/*
 624 * This returns the limit below which memory accesses to the linear
 625 * mapping are guarnateed not to cause an architectural exception (e.g.,
 626 * TLB or SLB miss fault).
 627 *
 628 * This is used to allocate PACAs and various interrupt stacks that
 629 * that are accessed early in interrupt handlers that must not cause
 630 * re-entrant interrupts.
 631 */
 632__init u64 ppc64_bolted_size(void)
 633{
 634#ifdef CONFIG_PPC_BOOK3E
 635	/* Freescale BookE bolts the entire linear mapping */
 636	/* XXX: BookE ppc64_rma_limit setup seems to disagree? */
 637	if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E))
 638		return linear_map_top;
 639	/* Other BookE, we assume the first GB is bolted */
 640	return 1ul << 30;
 641#else
 642	/* BookS radix, does not take faults on linear mapping */
 643	if (early_radix_enabled())
 644		return ULONG_MAX;
 645
 646	/* BookS hash, the first segment is bolted */
 647	if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT))
 648		return 1UL << SID_SHIFT_1T;
 649	return 1UL << SID_SHIFT;
 650#endif
 651}
 652
 653static void *__init alloc_stack(unsigned long limit, int cpu)
 654{
 655	void *ptr;
 656
 657	BUILD_BUG_ON(STACK_INT_FRAME_SIZE % 16);
 658
 659	ptr = memblock_alloc_try_nid(THREAD_SIZE, THREAD_ALIGN,
 660				     MEMBLOCK_LOW_LIMIT, limit,
 661				     early_cpu_to_node(cpu));
 662	if (!ptr)
 663		panic("cannot allocate stacks");
 664
 665	return ptr;
 666}
 667
 668void __init irqstack_early_init(void)
 669{
 670	u64 limit = ppc64_bolted_size();
 671	unsigned int i;
 672
 673	/*
 674	 * Interrupt stacks must be in the first segment since we
 675	 * cannot afford to take SLB misses on them. They are not
 676	 * accessed in realmode.
 677	 */
 678	for_each_possible_cpu(i) {
 679		softirq_ctx[i] = alloc_stack(limit, i);
 680		hardirq_ctx[i] = alloc_stack(limit, i);
 681	}
 682}
 683
 684#ifdef CONFIG_PPC_BOOK3E
 685void __init exc_lvl_early_init(void)
 686{
 687	unsigned int i;
 688
 689	for_each_possible_cpu(i) {
 690		void *sp;
 691
 692		sp = alloc_stack(ULONG_MAX, i);
 693		critirq_ctx[i] = sp;
 694		paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE;
 695
 696		sp = alloc_stack(ULONG_MAX, i);
 697		dbgirq_ctx[i] = sp;
 698		paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE;
 699
 700		sp = alloc_stack(ULONG_MAX, i);
 701		mcheckirq_ctx[i] = sp;
 702		paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE;
 703	}
 704
 705	if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
 706		patch_exception(0x040, exc_debug_debug_book3e);
 707}
 708#endif
 709
 710/*
 711 * Stack space used when we detect a bad kernel stack pointer, and
 712 * early in SMP boots before relocation is enabled. Exclusive emergency
 713 * stack for machine checks.
 714 */
 715void __init emergency_stack_init(void)
 716{
 717	u64 limit, mce_limit;
 718	unsigned int i;
 719
 720	/*
 721	 * Emergency stacks must be under 256MB, we cannot afford to take
 722	 * SLB misses on them. The ABI also requires them to be 128-byte
 723	 * aligned.
 724	 *
 725	 * Since we use these as temporary stacks during secondary CPU
 726	 * bringup, machine check, system reset, and HMI, we need to get
 727	 * at them in real mode. This means they must also be within the RMO
 728	 * region.
 729	 *
 730	 * The IRQ stacks allocated elsewhere in this file are zeroed and
 731	 * initialized in kernel/irq.c. These are initialized here in order
 732	 * to have emergency stacks available as early as possible.
 733	 */
 734	limit = mce_limit = min(ppc64_bolted_size(), ppc64_rma_size);
 735
 736	/*
 737	 * Machine check on pseries calls rtas, but can't use the static
 738	 * rtas_args due to a machine check hitting while the lock is held.
 739	 * rtas args have to be under 4GB, so the machine check stack is
 740	 * limited to 4GB so args can be put on stack.
 741	 */
 742	if (firmware_has_feature(FW_FEATURE_LPAR) && mce_limit > SZ_4G)
 743		mce_limit = SZ_4G;
 744
 745	for_each_possible_cpu(i) {
 746		paca_ptrs[i]->emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
 747
 748#ifdef CONFIG_PPC_BOOK3S_64
 749		/* emergency stack for NMI exception handling. */
 750		paca_ptrs[i]->nmi_emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
 751
 752		/* emergency stack for machine check exception handling. */
 753		paca_ptrs[i]->mc_emergency_sp = alloc_stack(mce_limit, i) + THREAD_SIZE;
 754#endif
 755	}
 756}
 757
 758#ifdef CONFIG_SMP
 759#define PCPU_DYN_SIZE		()
 760
 761static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
 762{
 763	return memblock_alloc_try_nid(size, align, __pa(MAX_DMA_ADDRESS),
 764				      MEMBLOCK_ALLOC_ACCESSIBLE,
 765				      early_cpu_to_node(cpu));
 766
 767}
 768
 769static void __init pcpu_fc_free(void *ptr, size_t size)
 770{
 771	memblock_free(__pa(ptr), size);
 772}
 773
 774static int pcpu_cpu_distance(unsigned int from, unsigned int to)
 775{
 776	if (early_cpu_to_node(from) == early_cpu_to_node(to))
 777		return LOCAL_DISTANCE;
 778	else
 779		return REMOTE_DISTANCE;
 780}
 781
 
 
 
 
 
 782unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
 783EXPORT_SYMBOL(__per_cpu_offset);
 784
 785void __init setup_per_cpu_areas(void)
 786{
 787	const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
 788	size_t atom_size;
 789	unsigned long delta;
 790	unsigned int cpu;
 791	int rc;
 792
 793	/*
 794	 * Linear mapping is one of 4K, 1M and 16M.  For 4K, no need
 795	 * to group units.  For larger mappings, use 1M atom which
 796	 * should be large enough to contain a number of units.
 797	 */
 798	if (mmu_linear_psize == MMU_PAGE_4K)
 
 
 799		atom_size = PAGE_SIZE;
 800	else
 801		atom_size = 1 << 20;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 802
 803	rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
 804				    pcpu_fc_alloc, pcpu_fc_free);
 805	if (rc < 0)
 806		panic("cannot initialize percpu area (err=%d)", rc);
 807
 808	delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
 809	for_each_possible_cpu(cpu) {
 810                __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
 811		paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu];
 812	}
 813}
 814#endif
 815
 816#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
 817unsigned long memory_block_size_bytes(void)
 818{
 819	if (ppc_md.memory_block_size)
 820		return ppc_md.memory_block_size();
 821
 822	return MIN_MEMORY_BLOCK_SIZE;
 823}
 824#endif
 825
 826#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
 827struct ppc_pci_io ppc_pci_io;
 828EXPORT_SYMBOL(ppc_pci_io);
 829#endif
 830
 831#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
 832u64 hw_nmi_get_sample_period(int watchdog_thresh)
 833{
 834	return ppc_proc_freq * watchdog_thresh;
 835}
 836#endif
 837
 838/*
 839 * The perf based hardlockup detector breaks PMU event based branches, so
 840 * disable it by default. Book3S has a soft-nmi hardlockup detector based
 841 * on the decrementer interrupt, so it does not suffer from this problem.
 842 *
 843 * It is likely to get false positives in VM guests, so disable it there
 844 * by default too.
 
 
 845 */
 846static int __init disable_hardlockup_detector(void)
 847{
 848#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
 849	hardlockup_detector_disable();
 850#else
 851	if (firmware_has_feature(FW_FEATURE_LPAR))
 852		hardlockup_detector_disable();
 
 
 853#endif
 854
 855	return 0;
 856}
 857early_initcall(disable_hardlockup_detector);
 858
 859#ifdef CONFIG_PPC_BOOK3S_64
 860static enum l1d_flush_type enabled_flush_types;
 861static void *l1d_flush_fallback_area;
 862static bool no_rfi_flush;
 863bool rfi_flush;
 864
 865static int __init handle_no_rfi_flush(char *p)
 866{
 867	pr_info("rfi-flush: disabled on command line.");
 868	no_rfi_flush = true;
 869	return 0;
 870}
 871early_param("no_rfi_flush", handle_no_rfi_flush);
 872
 873/*
 874 * The RFI flush is not KPTI, but because users will see doco that says to use
 875 * nopti we hijack that option here to also disable the RFI flush.
 876 */
 877static int __init handle_no_pti(char *p)
 878{
 879	pr_info("rfi-flush: disabling due to 'nopti' on command line.\n");
 880	handle_no_rfi_flush(NULL);
 881	return 0;
 882}
 883early_param("nopti", handle_no_pti);
 884
 885static void do_nothing(void *unused)
 886{
 887	/*
 888	 * We don't need to do the flush explicitly, just enter+exit kernel is
 889	 * sufficient, the RFI exit handlers will do the right thing.
 890	 */
 891}
 892
 893void rfi_flush_enable(bool enable)
 894{
 895	if (enable) {
 896		do_rfi_flush_fixups(enabled_flush_types);
 897		on_each_cpu(do_nothing, NULL, 1);
 898	} else
 899		do_rfi_flush_fixups(L1D_FLUSH_NONE);
 900
 901	rfi_flush = enable;
 902}
 903
 904static void __ref init_fallback_flush(void)
 905{
 906	u64 l1d_size, limit;
 907	int cpu;
 908
 909	/* Only allocate the fallback flush area once (at boot time). */
 910	if (l1d_flush_fallback_area)
 911		return;
 912
 913	l1d_size = ppc64_caches.l1d.size;
 914
 915	/*
 916	 * If there is no d-cache-size property in the device tree, l1d_size
 917	 * could be zero. That leads to the loop in the asm wrapping around to
 918	 * 2^64-1, and then walking off the end of the fallback area and
 919	 * eventually causing a page fault which is fatal. Just default to
 920	 * something vaguely sane.
 921	 */
 922	if (!l1d_size)
 923		l1d_size = (64 * 1024);
 924
 925	limit = min(ppc64_bolted_size(), ppc64_rma_size);
 926
 927	/*
 928	 * Align to L1d size, and size it at 2x L1d size, to catch possible
 929	 * hardware prefetch runoff. We don't have a recipe for load patterns to
 930	 * reliably avoid the prefetcher.
 931	 */
 932	l1d_flush_fallback_area = memblock_alloc_try_nid(l1d_size * 2,
 933						l1d_size, MEMBLOCK_LOW_LIMIT,
 934						limit, NUMA_NO_NODE);
 935	if (!l1d_flush_fallback_area)
 936		panic("%s: Failed to allocate %llu bytes align=0x%llx max_addr=%pa\n",
 937		      __func__, l1d_size * 2, l1d_size, &limit);
 938
 939
 940	for_each_possible_cpu(cpu) {
 941		struct paca_struct *paca = paca_ptrs[cpu];
 942		paca->rfi_flush_fallback_area = l1d_flush_fallback_area;
 943		paca->l1d_flush_size = l1d_size;
 944	}
 945}
 946
 947void setup_rfi_flush(enum l1d_flush_type types, bool enable)
 948{
 949	if (types & L1D_FLUSH_FALLBACK) {
 950		pr_info("rfi-flush: fallback displacement flush available\n");
 951		init_fallback_flush();
 952	}
 953
 954	if (types & L1D_FLUSH_ORI)
 955		pr_info("rfi-flush: ori type flush available\n");
 956
 957	if (types & L1D_FLUSH_MTTRIG)
 958		pr_info("rfi-flush: mttrig type flush available\n");
 959
 960	enabled_flush_types = types;
 961
 962	if (!no_rfi_flush && !cpu_mitigations_off())
 963		rfi_flush_enable(enable);
 964}
 965
 966#ifdef CONFIG_DEBUG_FS
 967static int rfi_flush_set(void *data, u64 val)
 968{
 969	bool enable;
 970
 971	if (val == 1)
 972		enable = true;
 973	else if (val == 0)
 974		enable = false;
 975	else
 976		return -EINVAL;
 977
 978	/* Only do anything if we're changing state */
 979	if (enable != rfi_flush)
 980		rfi_flush_enable(enable);
 981
 982	return 0;
 983}
 984
 985static int rfi_flush_get(void *data, u64 *val)
 986{
 987	*val = rfi_flush ? 1 : 0;
 988	return 0;
 989}
 990
 991DEFINE_SIMPLE_ATTRIBUTE(fops_rfi_flush, rfi_flush_get, rfi_flush_set, "%llu\n");
 992
 993static __init int rfi_flush_debugfs_init(void)
 994{
 995	debugfs_create_file("rfi_flush", 0600, powerpc_debugfs_root, NULL, &fops_rfi_flush);
 996	return 0;
 997}
 998device_initcall(rfi_flush_debugfs_init);
 999#endif
1000#endif /* CONFIG_PPC_BOOK3S_64 */