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1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*
3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#ifndef MLX5_ABI_USER_H
35#define MLX5_ABI_USER_H
36
37#include <linux/types.h>
38#include <linux/if_ether.h> /* For ETH_ALEN. */
39#include <rdma/ib_user_ioctl_verbs.h>
40
41enum {
42 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
43 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
44 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
45 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3,
46 MLX5_QP_FLAG_TYPE_DCT = 1 << 4,
47 MLX5_QP_FLAG_TYPE_DCI = 1 << 5,
48 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6,
49 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7,
50 MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8,
51 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9,
52 MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10,
53};
54
55enum {
56 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
57};
58
59enum {
60 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
61};
62
63/* Increment this value if any changes that break userspace ABI
64 * compatibility are made.
65 */
66#define MLX5_IB_UVERBS_ABI_VERSION 1
67
68/* Make sure that all structs defined in this file remain laid out so
69 * that they pack the same way on 32-bit and 64-bit architectures (to
70 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
71 * In particular do not use pointer types -- pass pointers in __u64
72 * instead.
73 */
74
75struct mlx5_ib_alloc_ucontext_req {
76 __u32 total_num_bfregs;
77 __u32 num_low_latency_bfregs;
78};
79
80enum mlx5_lib_caps {
81 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
82 MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 1,
83};
84
85enum mlx5_ib_alloc_uctx_v2_flags {
86 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0,
87};
88struct mlx5_ib_alloc_ucontext_req_v2 {
89 __u32 total_num_bfregs;
90 __u32 num_low_latency_bfregs;
91 __u32 flags;
92 __u32 comp_mask;
93 __u8 max_cqe_version;
94 __u8 reserved0;
95 __u16 reserved1;
96 __u32 reserved2;
97 __aligned_u64 lib_caps;
98};
99
100enum mlx5_ib_alloc_ucontext_resp_mask {
101 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
102 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1,
103 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE = 1UL << 2,
104};
105
106enum mlx5_user_cmds_supp_uhw {
107 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
108 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
109};
110
111/* The eth_min_inline response value is set to off-by-one vs the FW
112 * returned value to allow user-space to deal with older kernels.
113 */
114enum mlx5_user_inline_mode {
115 MLX5_USER_INLINE_MODE_NA,
116 MLX5_USER_INLINE_MODE_NONE,
117 MLX5_USER_INLINE_MODE_L2,
118 MLX5_USER_INLINE_MODE_IP,
119 MLX5_USER_INLINE_MODE_TCP_UDP,
120};
121
122enum {
123 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
124 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
125 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
126 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
127 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
128};
129
130struct mlx5_ib_alloc_ucontext_resp {
131 __u32 qp_tab_size;
132 __u32 bf_reg_size;
133 __u32 tot_bfregs;
134 __u32 cache_line_size;
135 __u16 max_sq_desc_sz;
136 __u16 max_rq_desc_sz;
137 __u32 max_send_wqebb;
138 __u32 max_recv_wr;
139 __u32 max_srq_recv_wr;
140 __u16 num_ports;
141 __u16 flow_action_flags;
142 __u32 comp_mask;
143 __u32 response_length;
144 __u8 cqe_version;
145 __u8 cmds_supp_uhw;
146 __u8 eth_min_inline;
147 __u8 clock_info_versions;
148 __aligned_u64 hca_core_clock_offset;
149 __u32 log_uar_size;
150 __u32 num_uars_per_page;
151 __u32 num_dyn_bfregs;
152 __u32 dump_fill_mkey;
153};
154
155struct mlx5_ib_alloc_pd_resp {
156 __u32 pdn;
157};
158
159struct mlx5_ib_tso_caps {
160 __u32 max_tso; /* Maximum tso payload size in bytes */
161
162 /* Corresponding bit will be set if qp type from
163 * 'enum ib_qp_type' is supported, e.g.
164 * supported_qpts |= 1 << IB_QPT_UD
165 */
166 __u32 supported_qpts;
167};
168
169struct mlx5_ib_rss_caps {
170 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
171 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
172 __u8 reserved[7];
173};
174
175enum mlx5_ib_cqe_comp_res_format {
176 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
177 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
178 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2,
179};
180
181struct mlx5_ib_cqe_comp_caps {
182 __u32 max_num;
183 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
184};
185
186enum mlx5_ib_packet_pacing_cap_flags {
187 MLX5_IB_PP_SUPPORT_BURST = 1 << 0,
188};
189
190struct mlx5_packet_pacing_caps {
191 __u32 qp_rate_limit_min;
192 __u32 qp_rate_limit_max; /* In kpbs */
193
194 /* Corresponding bit will be set if qp type from
195 * 'enum ib_qp_type' is supported, e.g.
196 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
197 */
198 __u32 supported_qpts;
199 __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */
200 __u8 reserved[3];
201};
202
203enum mlx5_ib_mpw_caps {
204 MPW_RESERVED = 1 << 0,
205 MLX5_IB_ALLOW_MPW = 1 << 1,
206 MLX5_IB_SUPPORT_EMPW = 1 << 2,
207};
208
209enum mlx5_ib_sw_parsing_offloads {
210 MLX5_IB_SW_PARSING = 1 << 0,
211 MLX5_IB_SW_PARSING_CSUM = 1 << 1,
212 MLX5_IB_SW_PARSING_LSO = 1 << 2,
213};
214
215struct mlx5_ib_sw_parsing_caps {
216 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */
217
218 /* Corresponding bit will be set if qp type from
219 * 'enum ib_qp_type' is supported, e.g.
220 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
221 */
222 __u32 supported_qpts;
223};
224
225struct mlx5_ib_striding_rq_caps {
226 __u32 min_single_stride_log_num_of_bytes;
227 __u32 max_single_stride_log_num_of_bytes;
228 __u32 min_single_wqe_log_num_of_strides;
229 __u32 max_single_wqe_log_num_of_strides;
230
231 /* Corresponding bit will be set if qp type from
232 * 'enum ib_qp_type' is supported, e.g.
233 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
234 */
235 __u32 supported_qpts;
236 __u32 reserved;
237};
238
239enum mlx5_ib_query_dev_resp_flags {
240 /* Support 128B CQE compression */
241 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
242 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
243 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2,
244 MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3,
245};
246
247enum mlx5_ib_tunnel_offloads {
248 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
249 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
250 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2,
251 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3,
252 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4,
253};
254
255struct mlx5_ib_query_device_resp {
256 __u32 comp_mask;
257 __u32 response_length;
258 struct mlx5_ib_tso_caps tso_caps;
259 struct mlx5_ib_rss_caps rss_caps;
260 struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
261 struct mlx5_packet_pacing_caps packet_pacing_caps;
262 __u32 mlx5_ib_support_multi_pkt_send_wqes;
263 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */
264 struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
265 struct mlx5_ib_striding_rq_caps striding_rq_caps;
266 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
267 __u32 reserved;
268};
269
270enum mlx5_ib_create_cq_flags {
271 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
272 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1,
273};
274
275struct mlx5_ib_create_cq {
276 __aligned_u64 buf_addr;
277 __aligned_u64 db_addr;
278 __u32 cqe_size;
279 __u8 cqe_comp_en;
280 __u8 cqe_comp_res_format;
281 __u16 flags;
282 __u16 uar_page_index;
283 __u16 reserved0;
284 __u32 reserved1;
285};
286
287struct mlx5_ib_create_cq_resp {
288 __u32 cqn;
289 __u32 reserved;
290};
291
292struct mlx5_ib_resize_cq {
293 __aligned_u64 buf_addr;
294 __u16 cqe_size;
295 __u16 reserved0;
296 __u32 reserved1;
297};
298
299struct mlx5_ib_create_srq {
300 __aligned_u64 buf_addr;
301 __aligned_u64 db_addr;
302 __u32 flags;
303 __u32 reserved0; /* explicit padding (optional on i386) */
304 __u32 uidx;
305 __u32 reserved1;
306};
307
308struct mlx5_ib_create_srq_resp {
309 __u32 srqn;
310 __u32 reserved;
311};
312
313struct mlx5_ib_create_qp {
314 __aligned_u64 buf_addr;
315 __aligned_u64 db_addr;
316 __u32 sq_wqe_count;
317 __u32 rq_wqe_count;
318 __u32 rq_wqe_shift;
319 __u32 flags;
320 __u32 uidx;
321 __u32 bfreg_index;
322 union {
323 __aligned_u64 sq_buf_addr;
324 __aligned_u64 access_key;
325 };
326 __u32 ece_options;
327 __u32 reserved;
328};
329
330/* RX Hash function flags */
331enum mlx5_rx_hash_function_flags {
332 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
333};
334
335/*
336 * RX Hash flags, these flags allows to set which incoming packet's field should
337 * participates in RX Hash. Each flag represent certain packet's field,
338 * when the flag is set the field that is represented by the flag will
339 * participate in RX Hash calculation.
340 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
341 * and *TCP and *UDP flags can't be enabled together on the same QP.
342*/
343enum mlx5_rx_hash_fields {
344 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
345 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
346 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
347 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
348 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
349 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
350 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
351 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
352 MLX5_RX_HASH_IPSEC_SPI = 1 << 8,
353 /* Save bits for future fields */
354 MLX5_RX_HASH_INNER = (1UL << 31),
355};
356
357struct mlx5_ib_create_qp_rss {
358 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
359 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
360 __u8 rx_key_len; /* valid only for Toeplitz */
361 __u8 reserved[6];
362 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
363 __u32 comp_mask;
364 __u32 flags;
365};
366
367enum mlx5_ib_create_qp_resp_mask {
368 MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0,
369 MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1,
370 MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2,
371 MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3,
372 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR = 1UL << 4,
373};
374
375struct mlx5_ib_create_qp_resp {
376 __u32 bfreg_index;
377 __u32 ece_options;
378 __u32 comp_mask;
379 __u32 tirn;
380 __u32 tisn;
381 __u32 rqn;
382 __u32 sqn;
383 __u32 reserved1;
384 __u64 tir_icm_addr;
385};
386
387struct mlx5_ib_alloc_mw {
388 __u32 comp_mask;
389 __u8 num_klms;
390 __u8 reserved1;
391 __u16 reserved2;
392};
393
394enum mlx5_ib_create_wq_mask {
395 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
396};
397
398struct mlx5_ib_create_wq {
399 __aligned_u64 buf_addr;
400 __aligned_u64 db_addr;
401 __u32 rq_wqe_count;
402 __u32 rq_wqe_shift;
403 __u32 user_index;
404 __u32 flags;
405 __u32 comp_mask;
406 __u32 single_stride_log_num_of_bytes;
407 __u32 single_wqe_log_num_of_strides;
408 __u32 two_byte_shift_en;
409};
410
411struct mlx5_ib_create_ah_resp {
412 __u32 response_length;
413 __u8 dmac[ETH_ALEN];
414 __u8 reserved[6];
415};
416
417struct mlx5_ib_burst_info {
418 __u32 max_burst_sz;
419 __u16 typical_pkt_sz;
420 __u16 reserved;
421};
422
423struct mlx5_ib_modify_qp {
424 __u32 comp_mask;
425 struct mlx5_ib_burst_info burst_info;
426 __u32 ece_options;
427};
428
429struct mlx5_ib_modify_qp_resp {
430 __u32 response_length;
431 __u32 dctn;
432 __u32 ece_options;
433 __u32 reserved;
434};
435
436struct mlx5_ib_create_wq_resp {
437 __u32 response_length;
438 __u32 reserved;
439};
440
441struct mlx5_ib_create_rwq_ind_tbl_resp {
442 __u32 response_length;
443 __u32 reserved;
444};
445
446struct mlx5_ib_modify_wq {
447 __u32 comp_mask;
448 __u32 reserved;
449};
450
451struct mlx5_ib_clock_info {
452 __u32 sign;
453 __u32 resv;
454 __aligned_u64 nsec;
455 __aligned_u64 cycles;
456 __aligned_u64 frac;
457 __u32 mult;
458 __u32 shift;
459 __aligned_u64 mask;
460 __aligned_u64 overflow_period;
461};
462
463enum mlx5_ib_mmap_cmd {
464 MLX5_IB_MMAP_REGULAR_PAGE = 0,
465 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
466 MLX5_IB_MMAP_WC_PAGE = 2,
467 MLX5_IB_MMAP_NC_PAGE = 3,
468 /* 5 is chosen in order to be compatible with old versions of libmlx5 */
469 MLX5_IB_MMAP_CORE_CLOCK = 5,
470 MLX5_IB_MMAP_ALLOC_WC = 6,
471 MLX5_IB_MMAP_CLOCK_INFO = 7,
472 MLX5_IB_MMAP_DEVICE_MEM = 8,
473};
474
475enum {
476 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
477};
478
479/* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
480enum {
481 MLX5_IB_CLOCK_INFO_V1 = 0,
482};
483
484struct mlx5_ib_flow_counters_desc {
485 __u32 description;
486 __u32 index;
487};
488
489struct mlx5_ib_flow_counters_data {
490 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data);
491 __u32 ncounters;
492 __u32 reserved;
493};
494
495struct mlx5_ib_create_flow {
496 __u32 ncounters_data;
497 __u32 reserved;
498 /*
499 * Following are counters data based on ncounters_data, each
500 * entry in the data[] should match a corresponding counter object
501 * that was pointed by a counters spec upon the flow creation
502 */
503 struct mlx5_ib_flow_counters_data data[];
504};
505
506#endif /* MLX5_ABI_USER_H */
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*
3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#ifndef MLX5_ABI_USER_H
35#define MLX5_ABI_USER_H
36
37#include <linux/types.h>
38#include <linux/if_ether.h> /* For ETH_ALEN. */
39#include <rdma/ib_user_ioctl_verbs.h>
40
41enum {
42 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
43 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
44 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
45 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3,
46 MLX5_QP_FLAG_TYPE_DCT = 1 << 4,
47 MLX5_QP_FLAG_TYPE_DCI = 1 << 5,
48 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6,
49 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7,
50 MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8,
51 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9,
52 MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10,
53 MLX5_QP_FLAG_DCI_STREAM = 1 << 11,
54};
55
56enum {
57 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
58};
59
60enum {
61 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
62};
63
64/* Increment this value if any changes that break userspace ABI
65 * compatibility are made.
66 */
67#define MLX5_IB_UVERBS_ABI_VERSION 1
68
69/* Make sure that all structs defined in this file remain laid out so
70 * that they pack the same way on 32-bit and 64-bit architectures (to
71 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
72 * In particular do not use pointer types -- pass pointers in __u64
73 * instead.
74 */
75
76struct mlx5_ib_alloc_ucontext_req {
77 __u32 total_num_bfregs;
78 __u32 num_low_latency_bfregs;
79};
80
81enum mlx5_lib_caps {
82 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
83 MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 1,
84};
85
86enum mlx5_ib_alloc_uctx_v2_flags {
87 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0,
88};
89struct mlx5_ib_alloc_ucontext_req_v2 {
90 __u32 total_num_bfregs;
91 __u32 num_low_latency_bfregs;
92 __u32 flags;
93 __u32 comp_mask;
94 __u8 max_cqe_version;
95 __u8 reserved0;
96 __u16 reserved1;
97 __u32 reserved2;
98 __aligned_u64 lib_caps;
99};
100
101enum mlx5_ib_alloc_ucontext_resp_mask {
102 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
103 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1,
104 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE = 1UL << 2,
105 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS = 1UL << 3,
106 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS = 1UL << 4,
107 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG = 1UL << 5,
108};
109
110enum mlx5_user_cmds_supp_uhw {
111 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
112 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
113};
114
115/* The eth_min_inline response value is set to off-by-one vs the FW
116 * returned value to allow user-space to deal with older kernels.
117 */
118enum mlx5_user_inline_mode {
119 MLX5_USER_INLINE_MODE_NA,
120 MLX5_USER_INLINE_MODE_NONE,
121 MLX5_USER_INLINE_MODE_L2,
122 MLX5_USER_INLINE_MODE_IP,
123 MLX5_USER_INLINE_MODE_TCP_UDP,
124};
125
126enum {
127 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
128 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
129 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
130 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
131 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
132};
133
134struct mlx5_ib_alloc_ucontext_resp {
135 __u32 qp_tab_size;
136 __u32 bf_reg_size;
137 __u32 tot_bfregs;
138 __u32 cache_line_size;
139 __u16 max_sq_desc_sz;
140 __u16 max_rq_desc_sz;
141 __u32 max_send_wqebb;
142 __u32 max_recv_wr;
143 __u32 max_srq_recv_wr;
144 __u16 num_ports;
145 __u16 flow_action_flags;
146 __u32 comp_mask;
147 __u32 response_length;
148 __u8 cqe_version;
149 __u8 cmds_supp_uhw;
150 __u8 eth_min_inline;
151 __u8 clock_info_versions;
152 __aligned_u64 hca_core_clock_offset;
153 __u32 log_uar_size;
154 __u32 num_uars_per_page;
155 __u32 num_dyn_bfregs;
156 __u32 dump_fill_mkey;
157};
158
159struct mlx5_ib_alloc_pd_resp {
160 __u32 pdn;
161};
162
163struct mlx5_ib_tso_caps {
164 __u32 max_tso; /* Maximum tso payload size in bytes */
165
166 /* Corresponding bit will be set if qp type from
167 * 'enum ib_qp_type' is supported, e.g.
168 * supported_qpts |= 1 << IB_QPT_UD
169 */
170 __u32 supported_qpts;
171};
172
173struct mlx5_ib_rss_caps {
174 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
175 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
176 __u8 reserved[7];
177};
178
179enum mlx5_ib_cqe_comp_res_format {
180 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
181 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
182 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2,
183};
184
185struct mlx5_ib_cqe_comp_caps {
186 __u32 max_num;
187 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
188};
189
190enum mlx5_ib_packet_pacing_cap_flags {
191 MLX5_IB_PP_SUPPORT_BURST = 1 << 0,
192};
193
194struct mlx5_packet_pacing_caps {
195 __u32 qp_rate_limit_min;
196 __u32 qp_rate_limit_max; /* In kpbs */
197
198 /* Corresponding bit will be set if qp type from
199 * 'enum ib_qp_type' is supported, e.g.
200 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
201 */
202 __u32 supported_qpts;
203 __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */
204 __u8 reserved[3];
205};
206
207enum mlx5_ib_mpw_caps {
208 MPW_RESERVED = 1 << 0,
209 MLX5_IB_ALLOW_MPW = 1 << 1,
210 MLX5_IB_SUPPORT_EMPW = 1 << 2,
211};
212
213enum mlx5_ib_sw_parsing_offloads {
214 MLX5_IB_SW_PARSING = 1 << 0,
215 MLX5_IB_SW_PARSING_CSUM = 1 << 1,
216 MLX5_IB_SW_PARSING_LSO = 1 << 2,
217};
218
219struct mlx5_ib_sw_parsing_caps {
220 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */
221
222 /* Corresponding bit will be set if qp type from
223 * 'enum ib_qp_type' is supported, e.g.
224 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
225 */
226 __u32 supported_qpts;
227};
228
229struct mlx5_ib_striding_rq_caps {
230 __u32 min_single_stride_log_num_of_bytes;
231 __u32 max_single_stride_log_num_of_bytes;
232 __u32 min_single_wqe_log_num_of_strides;
233 __u32 max_single_wqe_log_num_of_strides;
234
235 /* Corresponding bit will be set if qp type from
236 * 'enum ib_qp_type' is supported, e.g.
237 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
238 */
239 __u32 supported_qpts;
240 __u32 reserved;
241};
242
243struct mlx5_ib_dci_streams_caps {
244 __u8 max_log_num_concurent;
245 __u8 max_log_num_errored;
246};
247
248enum mlx5_ib_query_dev_resp_flags {
249 /* Support 128B CQE compression */
250 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
251 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
252 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2,
253 MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3,
254};
255
256enum mlx5_ib_tunnel_offloads {
257 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
258 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
259 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2,
260 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3,
261 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4,
262};
263
264struct mlx5_ib_query_device_resp {
265 __u32 comp_mask;
266 __u32 response_length;
267 struct mlx5_ib_tso_caps tso_caps;
268 struct mlx5_ib_rss_caps rss_caps;
269 struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
270 struct mlx5_packet_pacing_caps packet_pacing_caps;
271 __u32 mlx5_ib_support_multi_pkt_send_wqes;
272 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */
273 struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
274 struct mlx5_ib_striding_rq_caps striding_rq_caps;
275 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
276 struct mlx5_ib_dci_streams_caps dci_streams_caps;
277 __u16 reserved;
278};
279
280enum mlx5_ib_create_cq_flags {
281 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
282 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1,
283 MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS = 1 << 2,
284};
285
286struct mlx5_ib_create_cq {
287 __aligned_u64 buf_addr;
288 __aligned_u64 db_addr;
289 __u32 cqe_size;
290 __u8 cqe_comp_en;
291 __u8 cqe_comp_res_format;
292 __u16 flags;
293 __u16 uar_page_index;
294 __u16 reserved0;
295 __u32 reserved1;
296};
297
298struct mlx5_ib_create_cq_resp {
299 __u32 cqn;
300 __u32 reserved;
301};
302
303struct mlx5_ib_resize_cq {
304 __aligned_u64 buf_addr;
305 __u16 cqe_size;
306 __u16 reserved0;
307 __u32 reserved1;
308};
309
310struct mlx5_ib_create_srq {
311 __aligned_u64 buf_addr;
312 __aligned_u64 db_addr;
313 __u32 flags;
314 __u32 reserved0; /* explicit padding (optional on i386) */
315 __u32 uidx;
316 __u32 reserved1;
317};
318
319struct mlx5_ib_create_srq_resp {
320 __u32 srqn;
321 __u32 reserved;
322};
323
324struct mlx5_ib_create_qp_dci_streams {
325 __u8 log_num_concurent;
326 __u8 log_num_errored;
327};
328
329struct mlx5_ib_create_qp {
330 __aligned_u64 buf_addr;
331 __aligned_u64 db_addr;
332 __u32 sq_wqe_count;
333 __u32 rq_wqe_count;
334 __u32 rq_wqe_shift;
335 __u32 flags;
336 __u32 uidx;
337 __u32 bfreg_index;
338 union {
339 __aligned_u64 sq_buf_addr;
340 __aligned_u64 access_key;
341 };
342 __u32 ece_options;
343 struct mlx5_ib_create_qp_dci_streams dci_streams;
344 __u16 reserved;
345};
346
347/* RX Hash function flags */
348enum mlx5_rx_hash_function_flags {
349 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
350};
351
352/*
353 * RX Hash flags, these flags allows to set which incoming packet's field should
354 * participates in RX Hash. Each flag represent certain packet's field,
355 * when the flag is set the field that is represented by the flag will
356 * participate in RX Hash calculation.
357 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
358 * and *TCP and *UDP flags can't be enabled together on the same QP.
359*/
360enum mlx5_rx_hash_fields {
361 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
362 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
363 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
364 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
365 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
366 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
367 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
368 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
369 MLX5_RX_HASH_IPSEC_SPI = 1 << 8,
370 /* Save bits for future fields */
371 MLX5_RX_HASH_INNER = (1UL << 31),
372};
373
374struct mlx5_ib_create_qp_rss {
375 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
376 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
377 __u8 rx_key_len; /* valid only for Toeplitz */
378 __u8 reserved[6];
379 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
380 __u32 comp_mask;
381 __u32 flags;
382};
383
384enum mlx5_ib_create_qp_resp_mask {
385 MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0,
386 MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1,
387 MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2,
388 MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3,
389 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR = 1UL << 4,
390};
391
392struct mlx5_ib_create_qp_resp {
393 __u32 bfreg_index;
394 __u32 ece_options;
395 __u32 comp_mask;
396 __u32 tirn;
397 __u32 tisn;
398 __u32 rqn;
399 __u32 sqn;
400 __u32 reserved1;
401 __u64 tir_icm_addr;
402};
403
404struct mlx5_ib_alloc_mw {
405 __u32 comp_mask;
406 __u8 num_klms;
407 __u8 reserved1;
408 __u16 reserved2;
409};
410
411enum mlx5_ib_create_wq_mask {
412 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
413};
414
415struct mlx5_ib_create_wq {
416 __aligned_u64 buf_addr;
417 __aligned_u64 db_addr;
418 __u32 rq_wqe_count;
419 __u32 rq_wqe_shift;
420 __u32 user_index;
421 __u32 flags;
422 __u32 comp_mask;
423 __u32 single_stride_log_num_of_bytes;
424 __u32 single_wqe_log_num_of_strides;
425 __u32 two_byte_shift_en;
426};
427
428struct mlx5_ib_create_ah_resp {
429 __u32 response_length;
430 __u8 dmac[ETH_ALEN];
431 __u8 reserved[6];
432};
433
434struct mlx5_ib_burst_info {
435 __u32 max_burst_sz;
436 __u16 typical_pkt_sz;
437 __u16 reserved;
438};
439
440struct mlx5_ib_modify_qp {
441 __u32 comp_mask;
442 struct mlx5_ib_burst_info burst_info;
443 __u32 ece_options;
444};
445
446struct mlx5_ib_modify_qp_resp {
447 __u32 response_length;
448 __u32 dctn;
449 __u32 ece_options;
450 __u32 reserved;
451};
452
453struct mlx5_ib_create_wq_resp {
454 __u32 response_length;
455 __u32 reserved;
456};
457
458struct mlx5_ib_create_rwq_ind_tbl_resp {
459 __u32 response_length;
460 __u32 reserved;
461};
462
463struct mlx5_ib_modify_wq {
464 __u32 comp_mask;
465 __u32 reserved;
466};
467
468struct mlx5_ib_clock_info {
469 __u32 sign;
470 __u32 resv;
471 __aligned_u64 nsec;
472 __aligned_u64 cycles;
473 __aligned_u64 frac;
474 __u32 mult;
475 __u32 shift;
476 __aligned_u64 mask;
477 __aligned_u64 overflow_period;
478};
479
480enum mlx5_ib_mmap_cmd {
481 MLX5_IB_MMAP_REGULAR_PAGE = 0,
482 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1,
483 MLX5_IB_MMAP_WC_PAGE = 2,
484 MLX5_IB_MMAP_NC_PAGE = 3,
485 /* 5 is chosen in order to be compatible with old versions of libmlx5 */
486 MLX5_IB_MMAP_CORE_CLOCK = 5,
487 MLX5_IB_MMAP_ALLOC_WC = 6,
488 MLX5_IB_MMAP_CLOCK_INFO = 7,
489 MLX5_IB_MMAP_DEVICE_MEM = 8,
490};
491
492enum {
493 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
494};
495
496/* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
497enum {
498 MLX5_IB_CLOCK_INFO_V1 = 0,
499};
500
501struct mlx5_ib_flow_counters_desc {
502 __u32 description;
503 __u32 index;
504};
505
506struct mlx5_ib_flow_counters_data {
507 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data);
508 __u32 ncounters;
509 __u32 reserved;
510};
511
512struct mlx5_ib_create_flow {
513 __u32 ncounters_data;
514 __u32 reserved;
515 /*
516 * Following are counters data based on ncounters_data, each
517 * entry in the data[] should match a corresponding counter object
518 * that was pointed by a counters spec upon the flow creation
519 */
520 struct mlx5_ib_flow_counters_data data[];
521};
522
523#endif /* MLX5_ABI_USER_H */