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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Intel Running Average Power Limit (RAPL) Driver via MSR interface
4 * Copyright (c) 2019, Intel Corporation.
5 */
6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/list.h>
11#include <linux/types.h>
12#include <linux/device.h>
13#include <linux/slab.h>
14#include <linux/log2.h>
15#include <linux/bitmap.h>
16#include <linux/delay.h>
17#include <linux/sysfs.h>
18#include <linux/cpu.h>
19#include <linux/powercap.h>
20#include <linux/suspend.h>
21#include <linux/intel_rapl.h>
22#include <linux/processor.h>
23#include <linux/platform_device.h>
24
25#include <asm/iosf_mbi.h>
26#include <asm/cpu_device_id.h>
27#include <asm/intel-family.h>
28
29/* Local defines */
30#define MSR_PLATFORM_POWER_LIMIT 0x0000065C
31#define MSR_VR_CURRENT_CONFIG 0x00000601
32
33/* private data for RAPL MSR Interface */
34static struct rapl_if_priv rapl_msr_priv = {
35 .reg_unit = MSR_RAPL_POWER_UNIT,
36 .regs[RAPL_DOMAIN_PACKAGE] = {
37 MSR_PKG_POWER_LIMIT, MSR_PKG_ENERGY_STATUS, MSR_PKG_PERF_STATUS, 0, MSR_PKG_POWER_INFO },
38 .regs[RAPL_DOMAIN_PP0] = {
39 MSR_PP0_POWER_LIMIT, MSR_PP0_ENERGY_STATUS, 0, MSR_PP0_POLICY, 0 },
40 .regs[RAPL_DOMAIN_PP1] = {
41 MSR_PP1_POWER_LIMIT, MSR_PP1_ENERGY_STATUS, 0, MSR_PP1_POLICY, 0 },
42 .regs[RAPL_DOMAIN_DRAM] = {
43 MSR_DRAM_POWER_LIMIT, MSR_DRAM_ENERGY_STATUS, MSR_DRAM_PERF_STATUS, 0, MSR_DRAM_POWER_INFO },
44 .regs[RAPL_DOMAIN_PLATFORM] = {
45 MSR_PLATFORM_POWER_LIMIT, MSR_PLATFORM_ENERGY_STATUS, 0, 0, 0},
46 .limits[RAPL_DOMAIN_PACKAGE] = 2,
47};
48
49/* Handles CPU hotplug on multi-socket systems.
50 * If a CPU goes online as the first CPU of the physical package
51 * we add the RAPL package to the system. Similarly, when the last
52 * CPU of the package is removed, we remove the RAPL package and its
53 * associated domains. Cooling devices are handled accordingly at
54 * per-domain level.
55 */
56static int rapl_cpu_online(unsigned int cpu)
57{
58 struct rapl_package *rp;
59
60 rp = rapl_find_package_domain(cpu, &rapl_msr_priv);
61 if (!rp) {
62 rp = rapl_add_package(cpu, &rapl_msr_priv);
63 if (IS_ERR(rp))
64 return PTR_ERR(rp);
65 }
66 cpumask_set_cpu(cpu, &rp->cpumask);
67 return 0;
68}
69
70static int rapl_cpu_down_prep(unsigned int cpu)
71{
72 struct rapl_package *rp;
73 int lead_cpu;
74
75 rp = rapl_find_package_domain(cpu, &rapl_msr_priv);
76 if (!rp)
77 return 0;
78
79 cpumask_clear_cpu(cpu, &rp->cpumask);
80 lead_cpu = cpumask_first(&rp->cpumask);
81 if (lead_cpu >= nr_cpu_ids)
82 rapl_remove_package(rp);
83 else if (rp->lead_cpu == cpu)
84 rp->lead_cpu = lead_cpu;
85 return 0;
86}
87
88static int rapl_msr_read_raw(int cpu, struct reg_action *ra)
89{
90 u32 msr = (u32)ra->reg;
91
92 if (rdmsrl_safe_on_cpu(cpu, msr, &ra->value)) {
93 pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu);
94 return -EIO;
95 }
96 ra->value &= ra->mask;
97 return 0;
98}
99
100static void rapl_msr_update_func(void *info)
101{
102 struct reg_action *ra = info;
103 u32 msr = (u32)ra->reg;
104 u64 val;
105
106 ra->err = rdmsrl_safe(msr, &val);
107 if (ra->err)
108 return;
109
110 val &= ~ra->mask;
111 val |= ra->value;
112
113 ra->err = wrmsrl_safe(msr, val);
114}
115
116static int rapl_msr_write_raw(int cpu, struct reg_action *ra)
117{
118 int ret;
119
120 ret = smp_call_function_single(cpu, rapl_msr_update_func, ra, 1);
121 if (WARN_ON_ONCE(ret))
122 return ret;
123
124 return ra->err;
125}
126
127/* List of verified CPUs. */
128static const struct x86_cpu_id pl4_support_ids[] = {
129 { X86_VENDOR_INTEL, 6, INTEL_FAM6_TIGERLAKE_L, X86_FEATURE_ANY },
130 {}
131};
132
133static int rapl_msr_probe(struct platform_device *pdev)
134{
135 const struct x86_cpu_id *id = x86_match_cpu(pl4_support_ids);
136 int ret;
137
138 rapl_msr_priv.read_raw = rapl_msr_read_raw;
139 rapl_msr_priv.write_raw = rapl_msr_write_raw;
140
141 if (id) {
142 rapl_msr_priv.limits[RAPL_DOMAIN_PACKAGE] = 3;
143 rapl_msr_priv.regs[RAPL_DOMAIN_PACKAGE][RAPL_DOMAIN_REG_PL4] =
144 MSR_VR_CURRENT_CONFIG;
145 pr_info("PL4 support detected.\n");
146 }
147
148 rapl_msr_priv.control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
149 if (IS_ERR(rapl_msr_priv.control_type)) {
150 pr_debug("failed to register powercap control_type.\n");
151 return PTR_ERR(rapl_msr_priv.control_type);
152 }
153
154 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powercap/rapl:online",
155 rapl_cpu_online, rapl_cpu_down_prep);
156 if (ret < 0)
157 goto out;
158 rapl_msr_priv.pcap_rapl_online = ret;
159
160 /* Don't bail out if PSys is not supported */
161 rapl_add_platform_domain(&rapl_msr_priv);
162
163 return 0;
164
165out:
166 if (ret)
167 powercap_unregister_control_type(rapl_msr_priv.control_type);
168 return ret;
169}
170
171static int rapl_msr_remove(struct platform_device *pdev)
172{
173 cpuhp_remove_state(rapl_msr_priv.pcap_rapl_online);
174 rapl_remove_platform_domain(&rapl_msr_priv);
175 powercap_unregister_control_type(rapl_msr_priv.control_type);
176 return 0;
177}
178
179static const struct platform_device_id rapl_msr_ids[] = {
180 { .name = "intel_rapl_msr", },
181 {}
182};
183MODULE_DEVICE_TABLE(platform, rapl_msr_ids);
184
185static struct platform_driver intel_rapl_msr_driver = {
186 .probe = rapl_msr_probe,
187 .remove = rapl_msr_remove,
188 .id_table = rapl_msr_ids,
189 .driver = {
190 .name = "intel_rapl_msr",
191 },
192};
193
194module_platform_driver(intel_rapl_msr_driver);
195
196MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit) control via MSR interface");
197MODULE_AUTHOR("Zhang Rui <rui.zhang@intel.com>");
198MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Intel Running Average Power Limit (RAPL) Driver via MSR interface
4 * Copyright (c) 2019, Intel Corporation.
5 */
6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/list.h>
11#include <linux/types.h>
12#include <linux/device.h>
13#include <linux/slab.h>
14#include <linux/log2.h>
15#include <linux/bitmap.h>
16#include <linux/delay.h>
17#include <linux/sysfs.h>
18#include <linux/cpu.h>
19#include <linux/powercap.h>
20#include <linux/suspend.h>
21#include <linux/intel_rapl.h>
22#include <linux/processor.h>
23#include <linux/platform_device.h>
24
25#include <asm/iosf_mbi.h>
26#include <asm/cpu_device_id.h>
27#include <asm/intel-family.h>
28
29/* Local defines */
30#define MSR_PLATFORM_POWER_LIMIT 0x0000065C
31#define MSR_VR_CURRENT_CONFIG 0x00000601
32
33/* private data for RAPL MSR Interface */
34static struct rapl_if_priv *rapl_msr_priv;
35
36static struct rapl_if_priv rapl_msr_priv_intel = {
37 .reg_unit = MSR_RAPL_POWER_UNIT,
38 .regs[RAPL_DOMAIN_PACKAGE] = {
39 MSR_PKG_POWER_LIMIT, MSR_PKG_ENERGY_STATUS, MSR_PKG_PERF_STATUS, 0, MSR_PKG_POWER_INFO },
40 .regs[RAPL_DOMAIN_PP0] = {
41 MSR_PP0_POWER_LIMIT, MSR_PP0_ENERGY_STATUS, 0, MSR_PP0_POLICY, 0 },
42 .regs[RAPL_DOMAIN_PP1] = {
43 MSR_PP1_POWER_LIMIT, MSR_PP1_ENERGY_STATUS, 0, MSR_PP1_POLICY, 0 },
44 .regs[RAPL_DOMAIN_DRAM] = {
45 MSR_DRAM_POWER_LIMIT, MSR_DRAM_ENERGY_STATUS, MSR_DRAM_PERF_STATUS, 0, MSR_DRAM_POWER_INFO },
46 .regs[RAPL_DOMAIN_PLATFORM] = {
47 MSR_PLATFORM_POWER_LIMIT, MSR_PLATFORM_ENERGY_STATUS, 0, 0, 0},
48 .limits[RAPL_DOMAIN_PACKAGE] = 2,
49 .limits[RAPL_DOMAIN_PLATFORM] = 2,
50};
51
52static struct rapl_if_priv rapl_msr_priv_amd = {
53 .reg_unit = MSR_AMD_RAPL_POWER_UNIT,
54 .regs[RAPL_DOMAIN_PACKAGE] = {
55 0, MSR_AMD_PKG_ENERGY_STATUS, 0, 0, 0 },
56 .regs[RAPL_DOMAIN_PP0] = {
57 0, MSR_AMD_CORE_ENERGY_STATUS, 0, 0, 0 },
58};
59
60/* Handles CPU hotplug on multi-socket systems.
61 * If a CPU goes online as the first CPU of the physical package
62 * we add the RAPL package to the system. Similarly, when the last
63 * CPU of the package is removed, we remove the RAPL package and its
64 * associated domains. Cooling devices are handled accordingly at
65 * per-domain level.
66 */
67static int rapl_cpu_online(unsigned int cpu)
68{
69 struct rapl_package *rp;
70
71 rp = rapl_find_package_domain(cpu, rapl_msr_priv);
72 if (!rp) {
73 rp = rapl_add_package(cpu, rapl_msr_priv);
74 if (IS_ERR(rp))
75 return PTR_ERR(rp);
76 }
77 cpumask_set_cpu(cpu, &rp->cpumask);
78 return 0;
79}
80
81static int rapl_cpu_down_prep(unsigned int cpu)
82{
83 struct rapl_package *rp;
84 int lead_cpu;
85
86 rp = rapl_find_package_domain(cpu, rapl_msr_priv);
87 if (!rp)
88 return 0;
89
90 cpumask_clear_cpu(cpu, &rp->cpumask);
91 lead_cpu = cpumask_first(&rp->cpumask);
92 if (lead_cpu >= nr_cpu_ids)
93 rapl_remove_package(rp);
94 else if (rp->lead_cpu == cpu)
95 rp->lead_cpu = lead_cpu;
96 return 0;
97}
98
99static int rapl_msr_read_raw(int cpu, struct reg_action *ra)
100{
101 u32 msr = (u32)ra->reg;
102
103 if (rdmsrl_safe_on_cpu(cpu, msr, &ra->value)) {
104 pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu);
105 return -EIO;
106 }
107 ra->value &= ra->mask;
108 return 0;
109}
110
111static void rapl_msr_update_func(void *info)
112{
113 struct reg_action *ra = info;
114 u32 msr = (u32)ra->reg;
115 u64 val;
116
117 ra->err = rdmsrl_safe(msr, &val);
118 if (ra->err)
119 return;
120
121 val &= ~ra->mask;
122 val |= ra->value;
123
124 ra->err = wrmsrl_safe(msr, val);
125}
126
127static int rapl_msr_write_raw(int cpu, struct reg_action *ra)
128{
129 int ret;
130
131 ret = smp_call_function_single(cpu, rapl_msr_update_func, ra, 1);
132 if (WARN_ON_ONCE(ret))
133 return ret;
134
135 return ra->err;
136}
137
138/* List of verified CPUs. */
139static const struct x86_cpu_id pl4_support_ids[] = {
140 { X86_VENDOR_INTEL, 6, INTEL_FAM6_TIGERLAKE_L, X86_FEATURE_ANY },
141 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ALDERLAKE, X86_FEATURE_ANY },
142 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ALDERLAKE_L, X86_FEATURE_ANY },
143 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ALDERLAKE_N, X86_FEATURE_ANY },
144 { X86_VENDOR_INTEL, 6, INTEL_FAM6_RAPTORLAKE, X86_FEATURE_ANY },
145 { X86_VENDOR_INTEL, 6, INTEL_FAM6_RAPTORLAKE_P, X86_FEATURE_ANY },
146 {}
147};
148
149static int rapl_msr_probe(struct platform_device *pdev)
150{
151 const struct x86_cpu_id *id = x86_match_cpu(pl4_support_ids);
152 int ret;
153
154 switch (boot_cpu_data.x86_vendor) {
155 case X86_VENDOR_INTEL:
156 rapl_msr_priv = &rapl_msr_priv_intel;
157 break;
158 case X86_VENDOR_HYGON:
159 case X86_VENDOR_AMD:
160 rapl_msr_priv = &rapl_msr_priv_amd;
161 break;
162 default:
163 pr_err("intel-rapl does not support CPU vendor %d\n", boot_cpu_data.x86_vendor);
164 return -ENODEV;
165 }
166 rapl_msr_priv->read_raw = rapl_msr_read_raw;
167 rapl_msr_priv->write_raw = rapl_msr_write_raw;
168
169 if (id) {
170 rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] = 3;
171 rapl_msr_priv->regs[RAPL_DOMAIN_PACKAGE][RAPL_DOMAIN_REG_PL4] =
172 MSR_VR_CURRENT_CONFIG;
173 pr_info("PL4 support detected.\n");
174 }
175
176 rapl_msr_priv->control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
177 if (IS_ERR(rapl_msr_priv->control_type)) {
178 pr_debug("failed to register powercap control_type.\n");
179 return PTR_ERR(rapl_msr_priv->control_type);
180 }
181
182 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powercap/rapl:online",
183 rapl_cpu_online, rapl_cpu_down_prep);
184 if (ret < 0)
185 goto out;
186 rapl_msr_priv->pcap_rapl_online = ret;
187
188 return 0;
189
190out:
191 if (ret)
192 powercap_unregister_control_type(rapl_msr_priv->control_type);
193 return ret;
194}
195
196static int rapl_msr_remove(struct platform_device *pdev)
197{
198 cpuhp_remove_state(rapl_msr_priv->pcap_rapl_online);
199 powercap_unregister_control_type(rapl_msr_priv->control_type);
200 return 0;
201}
202
203static const struct platform_device_id rapl_msr_ids[] = {
204 { .name = "intel_rapl_msr", },
205 {}
206};
207MODULE_DEVICE_TABLE(platform, rapl_msr_ids);
208
209static struct platform_driver intel_rapl_msr_driver = {
210 .probe = rapl_msr_probe,
211 .remove = rapl_msr_remove,
212 .id_table = rapl_msr_ids,
213 .driver = {
214 .name = "intel_rapl_msr",
215 },
216};
217
218module_platform_driver(intel_rapl_msr_driver);
219
220MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit) control via MSR interface");
221MODULE_AUTHOR("Zhang Rui <rui.zhang@intel.com>");
222MODULE_LICENSE("GPL v2");