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1// SPDX-License-Identifier: GPL-2.0
2/**
3 * Wrapper driver for SERDES used in J721E
4 *
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9#include <dt-bindings/phy/phy.h>
10#include <linux/clk.h>
11#include <linux/clk-provider.h>
12#include <linux/gpio.h>
13#include <linux/gpio/consumer.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/mux/consumer.h>
17#include <linux/of_address.h>
18#include <linux/of_platform.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
22#include <linux/reset-controller.h>
23#include <dt-bindings/phy/phy.h>
24
25#define WIZ_SERDES_CTRL 0x404
26#define WIZ_SERDES_TOP_CTRL 0x408
27#define WIZ_SERDES_RST 0x40c
28#define WIZ_SERDES_TYPEC 0x410
29#define WIZ_LANECTL(n) (0x480 + (0x40 * (n)))
30
31#define WIZ_MAX_LANES 4
32#define WIZ_MUX_NUM_CLOCKS 3
33#define WIZ_DIV_NUM_CLOCKS_16G 2
34#define WIZ_DIV_NUM_CLOCKS_10G 1
35
36#define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30)
37
38enum wiz_lane_standard_mode {
39 LANE_MODE_GEN1,
40 LANE_MODE_GEN2,
41 LANE_MODE_GEN3,
42 LANE_MODE_GEN4,
43};
44
45enum wiz_refclk_mux_sel {
46 PLL0_REFCLK,
47 PLL1_REFCLK,
48 REFCLK_DIG,
49};
50
51enum wiz_refclk_div_sel {
52 CMN_REFCLK_DIG_DIV,
53 CMN_REFCLK1_DIG_DIV,
54};
55
56static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
57static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
58static const struct reg_field pll1_refclk_mux_sel =
59 REG_FIELD(WIZ_SERDES_RST, 29, 29);
60static const struct reg_field pll0_refclk_mux_sel =
61 REG_FIELD(WIZ_SERDES_RST, 28, 28);
62static const struct reg_field refclk_dig_sel_16g =
63 REG_FIELD(WIZ_SERDES_RST, 24, 25);
64static const struct reg_field refclk_dig_sel_10g =
65 REG_FIELD(WIZ_SERDES_RST, 24, 24);
66static const struct reg_field pma_cmn_refclk_int_mode =
67 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
68static const struct reg_field pma_cmn_refclk_mode =
69 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
70static const struct reg_field pma_cmn_refclk_dig_div =
71 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
72static const struct reg_field pma_cmn_refclk1_dig_div =
73 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
74
75static const struct reg_field p_enable[WIZ_MAX_LANES] = {
76 REG_FIELD(WIZ_LANECTL(0), 30, 31),
77 REG_FIELD(WIZ_LANECTL(1), 30, 31),
78 REG_FIELD(WIZ_LANECTL(2), 30, 31),
79 REG_FIELD(WIZ_LANECTL(3), 30, 31),
80};
81
82enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };
83
84static const struct reg_field p_align[WIZ_MAX_LANES] = {
85 REG_FIELD(WIZ_LANECTL(0), 29, 29),
86 REG_FIELD(WIZ_LANECTL(1), 29, 29),
87 REG_FIELD(WIZ_LANECTL(2), 29, 29),
88 REG_FIELD(WIZ_LANECTL(3), 29, 29),
89};
90
91static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
92 REG_FIELD(WIZ_LANECTL(0), 28, 28),
93 REG_FIELD(WIZ_LANECTL(1), 28, 28),
94 REG_FIELD(WIZ_LANECTL(2), 28, 28),
95 REG_FIELD(WIZ_LANECTL(3), 28, 28),
96};
97
98static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
99 REG_FIELD(WIZ_LANECTL(0), 24, 25),
100 REG_FIELD(WIZ_LANECTL(1), 24, 25),
101 REG_FIELD(WIZ_LANECTL(2), 24, 25),
102 REG_FIELD(WIZ_LANECTL(3), 24, 25),
103};
104
105static const struct reg_field typec_ln10_swap =
106 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
107
108struct wiz_clk_mux {
109 struct clk_hw hw;
110 struct regmap_field *field;
111 u32 *table;
112 struct clk_init_data clk_data;
113};
114
115#define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw)
116
117struct wiz_clk_divider {
118 struct clk_hw hw;
119 struct regmap_field *field;
120 const struct clk_div_table *table;
121 struct clk_init_data clk_data;
122};
123
124#define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw)
125
126struct wiz_clk_mux_sel {
127 struct regmap_field *field;
128 u32 table[4];
129 const char *node_name;
130};
131
132struct wiz_clk_div_sel {
133 struct regmap_field *field;
134 const struct clk_div_table *table;
135 const char *node_name;
136};
137
138static struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
139 {
140 /*
141 * Mux value to be configured for each of the input clocks
142 * in the order populated in device tree
143 */
144 .table = { 1, 0 },
145 .node_name = "pll0-refclk",
146 },
147 {
148 .table = { 1, 0 },
149 .node_name = "pll1-refclk",
150 },
151 {
152 .table = { 1, 3, 0, 2 },
153 .node_name = "refclk-dig",
154 },
155};
156
157static struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
158 {
159 /*
160 * Mux value to be configured for each of the input clocks
161 * in the order populated in device tree
162 */
163 .table = { 1, 0 },
164 .node_name = "pll0-refclk",
165 },
166 {
167 .table = { 1, 0 },
168 .node_name = "pll1-refclk",
169 },
170 {
171 .table = { 1, 0 },
172 .node_name = "refclk-dig",
173 },
174};
175
176static const struct clk_div_table clk_div_table[] = {
177 { .val = 0, .div = 1, },
178 { .val = 1, .div = 2, },
179 { .val = 2, .div = 4, },
180 { .val = 3, .div = 8, },
181};
182
183static struct wiz_clk_div_sel clk_div_sel[] = {
184 {
185 .table = clk_div_table,
186 .node_name = "cmn-refclk-dig-div",
187 },
188 {
189 .table = clk_div_table,
190 .node_name = "cmn-refclk1-dig-div",
191 },
192};
193
194enum wiz_type {
195 J721E_WIZ_16G,
196 J721E_WIZ_10G,
197};
198
199#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
200#define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
201
202struct wiz {
203 struct regmap *regmap;
204 enum wiz_type type;
205 struct wiz_clk_mux_sel *clk_mux_sel;
206 struct wiz_clk_div_sel *clk_div_sel;
207 unsigned int clk_div_sel_num;
208 struct regmap_field *por_en;
209 struct regmap_field *phy_reset_n;
210 struct regmap_field *p_enable[WIZ_MAX_LANES];
211 struct regmap_field *p_align[WIZ_MAX_LANES];
212 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
213 struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
214 struct regmap_field *pma_cmn_refclk_int_mode;
215 struct regmap_field *pma_cmn_refclk_mode;
216 struct regmap_field *pma_cmn_refclk_dig_div;
217 struct regmap_field *pma_cmn_refclk1_dig_div;
218 struct regmap_field *typec_ln10_swap;
219
220 struct device *dev;
221 u32 num_lanes;
222 struct platform_device *serdes_pdev;
223 struct reset_controller_dev wiz_phy_reset_dev;
224 struct gpio_desc *gpio_typec_dir;
225 int typec_dir_delay;
226 u32 lane_phy_type[WIZ_MAX_LANES];
227};
228
229static int wiz_reset(struct wiz *wiz)
230{
231 int ret;
232
233 ret = regmap_field_write(wiz->por_en, 0x1);
234 if (ret)
235 return ret;
236
237 mdelay(1);
238
239 ret = regmap_field_write(wiz->por_en, 0x0);
240 if (ret)
241 return ret;
242
243 return 0;
244}
245
246static int wiz_mode_select(struct wiz *wiz)
247{
248 u32 num_lanes = wiz->num_lanes;
249 enum wiz_lane_standard_mode mode;
250 int ret;
251 int i;
252
253 for (i = 0; i < num_lanes; i++) {
254 if (wiz->lane_phy_type[i] == PHY_TYPE_DP)
255 mode = LANE_MODE_GEN1;
256 else
257 mode = LANE_MODE_GEN4;
258
259 ret = regmap_field_write(wiz->p_standard_mode[i], mode);
260 if (ret)
261 return ret;
262 }
263
264 return 0;
265}
266
267static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
268{
269 u32 num_lanes = wiz->num_lanes;
270 int i;
271 int ret;
272
273 for (i = 0; i < num_lanes; i++) {
274 ret = regmap_field_write(wiz->p_align[i], enable);
275 if (ret)
276 return ret;
277
278 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
279 if (ret)
280 return ret;
281 }
282
283 return 0;
284}
285
286static int wiz_init(struct wiz *wiz)
287{
288 struct device *dev = wiz->dev;
289 int ret;
290
291 ret = wiz_reset(wiz);
292 if (ret) {
293 dev_err(dev, "WIZ reset failed\n");
294 return ret;
295 }
296
297 ret = wiz_mode_select(wiz);
298 if (ret) {
299 dev_err(dev, "WIZ mode select failed\n");
300 return ret;
301 }
302
303 ret = wiz_init_raw_interface(wiz, true);
304 if (ret) {
305 dev_err(dev, "WIZ interface initialization failed\n");
306 return ret;
307 }
308
309 return 0;
310}
311
312static int wiz_regfield_init(struct wiz *wiz)
313{
314 struct wiz_clk_mux_sel *clk_mux_sel;
315 struct wiz_clk_div_sel *clk_div_sel;
316 struct regmap *regmap = wiz->regmap;
317 int num_lanes = wiz->num_lanes;
318 struct device *dev = wiz->dev;
319 int i;
320
321 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
322 if (IS_ERR(wiz->por_en)) {
323 dev_err(dev, "POR_EN reg field init failed\n");
324 return PTR_ERR(wiz->por_en);
325 }
326
327 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
328 phy_reset_n);
329 if (IS_ERR(wiz->phy_reset_n)) {
330 dev_err(dev, "PHY_RESET_N reg field init failed\n");
331 return PTR_ERR(wiz->phy_reset_n);
332 }
333
334 wiz->pma_cmn_refclk_int_mode =
335 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode);
336 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
337 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
338 return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
339 }
340
341 wiz->pma_cmn_refclk_mode =
342 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
343 if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
344 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
345 return PTR_ERR(wiz->pma_cmn_refclk_mode);
346 }
347
348 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK_DIG_DIV];
349 clk_div_sel->field = devm_regmap_field_alloc(dev, regmap,
350 pma_cmn_refclk_dig_div);
351 if (IS_ERR(clk_div_sel->field)) {
352 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
353 return PTR_ERR(clk_div_sel->field);
354 }
355
356 if (wiz->type == J721E_WIZ_16G) {
357 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK1_DIG_DIV];
358 clk_div_sel->field =
359 devm_regmap_field_alloc(dev, regmap,
360 pma_cmn_refclk1_dig_div);
361 if (IS_ERR(clk_div_sel->field)) {
362 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
363 return PTR_ERR(clk_div_sel->field);
364 }
365 }
366
367 clk_mux_sel = &wiz->clk_mux_sel[PLL0_REFCLK];
368 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap,
369 pll0_refclk_mux_sel);
370 if (IS_ERR(clk_mux_sel->field)) {
371 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
372 return PTR_ERR(clk_mux_sel->field);
373 }
374
375 clk_mux_sel = &wiz->clk_mux_sel[PLL1_REFCLK];
376 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap,
377 pll1_refclk_mux_sel);
378 if (IS_ERR(clk_mux_sel->field)) {
379 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
380 return PTR_ERR(clk_mux_sel->field);
381 }
382
383 clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG];
384 if (wiz->type == J721E_WIZ_10G)
385 clk_mux_sel->field =
386 devm_regmap_field_alloc(dev, regmap,
387 refclk_dig_sel_10g);
388 else
389 clk_mux_sel->field =
390 devm_regmap_field_alloc(dev, regmap,
391 refclk_dig_sel_16g);
392
393 if (IS_ERR(clk_mux_sel->field)) {
394 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
395 return PTR_ERR(clk_mux_sel->field);
396 }
397
398 for (i = 0; i < num_lanes; i++) {
399 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
400 p_enable[i]);
401 if (IS_ERR(wiz->p_enable[i])) {
402 dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
403 return PTR_ERR(wiz->p_enable[i]);
404 }
405
406 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
407 p_align[i]);
408 if (IS_ERR(wiz->p_align[i])) {
409 dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
410 return PTR_ERR(wiz->p_align[i]);
411 }
412
413 wiz->p_raw_auto_start[i] =
414 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]);
415 if (IS_ERR(wiz->p_raw_auto_start[i])) {
416 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
417 i);
418 return PTR_ERR(wiz->p_raw_auto_start[i]);
419 }
420
421 wiz->p_standard_mode[i] =
422 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]);
423 if (IS_ERR(wiz->p_standard_mode[i])) {
424 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
425 i);
426 return PTR_ERR(wiz->p_standard_mode[i]);
427 }
428 }
429
430 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
431 typec_ln10_swap);
432 if (IS_ERR(wiz->typec_ln10_swap)) {
433 dev_err(dev, "LN10_SWAP reg field init failed\n");
434 return PTR_ERR(wiz->typec_ln10_swap);
435 }
436
437 return 0;
438}
439
440static u8 wiz_clk_mux_get_parent(struct clk_hw *hw)
441{
442 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
443 struct regmap_field *field = mux->field;
444 unsigned int val;
445
446 regmap_field_read(field, &val);
447 return clk_mux_val_to_index(hw, mux->table, 0, val);
448}
449
450static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index)
451{
452 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
453 struct regmap_field *field = mux->field;
454 int val;
455
456 val = mux->table[index];
457 return regmap_field_write(field, val);
458}
459
460static const struct clk_ops wiz_clk_mux_ops = {
461 .set_parent = wiz_clk_mux_set_parent,
462 .get_parent = wiz_clk_mux_get_parent,
463};
464
465static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node,
466 struct regmap_field *field, u32 *table)
467{
468 struct device *dev = wiz->dev;
469 struct clk_init_data *init;
470 const char **parent_names;
471 unsigned int num_parents;
472 struct wiz_clk_mux *mux;
473 char clk_name[100];
474 struct clk *clk;
475 int ret;
476
477 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
478 if (!mux)
479 return -ENOMEM;
480
481 num_parents = of_clk_get_parent_count(node);
482 if (num_parents < 2) {
483 dev_err(dev, "SERDES clock must have parents\n");
484 return -EINVAL;
485 }
486
487 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
488 GFP_KERNEL);
489 if (!parent_names)
490 return -ENOMEM;
491
492 of_clk_parent_fill(node, parent_names, num_parents);
493
494 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
495 node->name);
496
497 init = &mux->clk_data;
498
499 init->ops = &wiz_clk_mux_ops;
500 init->flags = CLK_SET_RATE_NO_REPARENT;
501 init->parent_names = parent_names;
502 init->num_parents = num_parents;
503 init->name = clk_name;
504
505 mux->field = field;
506 mux->table = table;
507 mux->hw.init = init;
508
509 clk = devm_clk_register(dev, &mux->hw);
510 if (IS_ERR(clk))
511 return PTR_ERR(clk);
512
513 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
514 if (ret)
515 dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
516
517 return ret;
518}
519
520static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw,
521 unsigned long parent_rate)
522{
523 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
524 struct regmap_field *field = div->field;
525 int val;
526
527 regmap_field_read(field, &val);
528
529 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2);
530}
531
532static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
533 unsigned long *prate)
534{
535 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
536
537 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0);
538}
539
540static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
541 unsigned long parent_rate)
542{
543 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
544 struct regmap_field *field = div->field;
545 int val;
546
547 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0);
548 if (val < 0)
549 return val;
550
551 return regmap_field_write(field, val);
552}
553
554static const struct clk_ops wiz_clk_div_ops = {
555 .recalc_rate = wiz_clk_div_recalc_rate,
556 .round_rate = wiz_clk_div_round_rate,
557 .set_rate = wiz_clk_div_set_rate,
558};
559
560static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,
561 struct regmap_field *field,
562 const struct clk_div_table *table)
563{
564 struct device *dev = wiz->dev;
565 struct wiz_clk_divider *div;
566 struct clk_init_data *init;
567 const char **parent_names;
568 char clk_name[100];
569 struct clk *clk;
570 int ret;
571
572 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
573 if (!div)
574 return -ENOMEM;
575
576 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
577 node->name);
578
579 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
580 if (!parent_names)
581 return -ENOMEM;
582
583 of_clk_parent_fill(node, parent_names, 1);
584
585 init = &div->clk_data;
586
587 init->ops = &wiz_clk_div_ops;
588 init->flags = 0;
589 init->parent_names = parent_names;
590 init->num_parents = 1;
591 init->name = clk_name;
592
593 div->field = field;
594 div->table = table;
595 div->hw.init = init;
596
597 clk = devm_clk_register(dev, &div->hw);
598 if (IS_ERR(clk))
599 return PTR_ERR(clk);
600
601 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
602 if (ret)
603 dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
604
605 return ret;
606}
607
608static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
609{
610 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
611 struct device_node *clk_node;
612 int i;
613
614 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
615 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name);
616 of_clk_del_provider(clk_node);
617 of_node_put(clk_node);
618 }
619}
620
621static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
622{
623 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
624 struct device *dev = wiz->dev;
625 struct device_node *clk_node;
626 const char *node_name;
627 unsigned long rate;
628 struct clk *clk;
629 int ret;
630 int i;
631
632 clk = devm_clk_get(dev, "core_ref_clk");
633 if (IS_ERR(clk)) {
634 dev_err(dev, "core_ref_clk clock not found\n");
635 ret = PTR_ERR(clk);
636 return ret;
637 }
638
639 rate = clk_get_rate(clk);
640 if (rate >= 100000000)
641 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
642 else
643 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
644
645 clk = devm_clk_get(dev, "ext_ref_clk");
646 if (IS_ERR(clk)) {
647 dev_err(dev, "ext_ref_clk clock not found\n");
648 ret = PTR_ERR(clk);
649 return ret;
650 }
651
652 rate = clk_get_rate(clk);
653 if (rate >= 100000000)
654 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
655 else
656 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
657
658 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
659 node_name = clk_mux_sel[i].node_name;
660 clk_node = of_get_child_by_name(node, node_name);
661 if (!clk_node) {
662 dev_err(dev, "Unable to get %s node\n", node_name);
663 ret = -EINVAL;
664 goto err;
665 }
666
667 ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field,
668 clk_mux_sel[i].table);
669 if (ret) {
670 dev_err(dev, "Failed to register %s clock\n",
671 node_name);
672 of_node_put(clk_node);
673 goto err;
674 }
675
676 of_node_put(clk_node);
677 }
678
679 for (i = 0; i < wiz->clk_div_sel_num; i++) {
680 node_name = clk_div_sel[i].node_name;
681 clk_node = of_get_child_by_name(node, node_name);
682 if (!clk_node) {
683 dev_err(dev, "Unable to get %s node\n", node_name);
684 ret = -EINVAL;
685 goto err;
686 }
687
688 ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field,
689 clk_div_sel[i].table);
690 if (ret) {
691 dev_err(dev, "Failed to register %s clock\n",
692 node_name);
693 of_node_put(clk_node);
694 goto err;
695 }
696
697 of_node_put(clk_node);
698 }
699
700 return 0;
701err:
702 wiz_clock_cleanup(wiz, node);
703
704 return ret;
705}
706
707static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
708 unsigned long id)
709{
710 struct device *dev = rcdev->dev;
711 struct wiz *wiz = dev_get_drvdata(dev);
712 int ret = 0;
713
714 if (id == 0) {
715 ret = regmap_field_write(wiz->phy_reset_n, false);
716 return ret;
717 }
718
719 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
720 return ret;
721}
722
723static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
724 unsigned long id)
725{
726 struct device *dev = rcdev->dev;
727 struct wiz *wiz = dev_get_drvdata(dev);
728 int ret;
729
730 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
731 if (id == 0 && wiz->gpio_typec_dir) {
732 if (wiz->typec_dir_delay)
733 msleep_interruptible(wiz->typec_dir_delay);
734
735 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
736 regmap_field_write(wiz->typec_ln10_swap, 1);
737 else
738 regmap_field_write(wiz->typec_ln10_swap, 0);
739 }
740
741 if (id == 0) {
742 ret = regmap_field_write(wiz->phy_reset_n, true);
743 return ret;
744 }
745
746 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
747 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
748 else
749 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
750
751 return ret;
752}
753
754static const struct reset_control_ops wiz_phy_reset_ops = {
755 .assert = wiz_phy_reset_assert,
756 .deassert = wiz_phy_reset_deassert,
757};
758
759static const struct regmap_config wiz_regmap_config = {
760 .reg_bits = 32,
761 .val_bits = 32,
762 .reg_stride = 4,
763 .fast_io = true,
764};
765
766static const struct of_device_id wiz_id_table[] = {
767 {
768 .compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G
769 },
770 {
771 .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
772 },
773 {}
774};
775MODULE_DEVICE_TABLE(of, wiz_id_table);
776
777static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
778{
779 struct device_node *serdes, *subnode;
780
781 serdes = of_get_child_by_name(dev->of_node, "serdes");
782 if (!serdes) {
783 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__);
784 return -EINVAL;
785 }
786
787 for_each_child_of_node(serdes, subnode) {
788 u32 reg, num_lanes = 1, phy_type = PHY_NONE;
789 int ret, i;
790
791 ret = of_property_read_u32(subnode, "reg", ®);
792 if (ret) {
793 dev_err(dev,
794 "%s: Reading \"reg\" from \"%s\" failed: %d\n",
795 __func__, subnode->name, ret);
796 return ret;
797 }
798 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes);
799 of_property_read_u32(subnode, "cdns,phy-type", &phy_type);
800
801 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
802 reg, reg + num_lanes - 1, phy_type);
803
804 for (i = reg; i < reg + num_lanes; i++)
805 wiz->lane_phy_type[i] = phy_type;
806 }
807
808 return 0;
809}
810
811static int wiz_probe(struct platform_device *pdev)
812{
813 struct reset_controller_dev *phy_reset_dev;
814 struct device *dev = &pdev->dev;
815 struct device_node *node = dev->of_node;
816 struct platform_device *serdes_pdev;
817 struct device_node *child_node;
818 struct regmap *regmap;
819 struct resource res;
820 void __iomem *base;
821 struct wiz *wiz;
822 u32 num_lanes;
823 int ret;
824
825 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);
826 if (!wiz)
827 return -ENOMEM;
828
829 wiz->type = (enum wiz_type)of_device_get_match_data(dev);
830
831 child_node = of_get_child_by_name(node, "serdes");
832 if (!child_node) {
833 dev_err(dev, "Failed to get SERDES child DT node\n");
834 return -ENODEV;
835 }
836
837 ret = of_address_to_resource(child_node, 0, &res);
838 if (ret) {
839 dev_err(dev, "Failed to get memory resource\n");
840 goto err_addr_to_resource;
841 }
842
843 base = devm_ioremap(dev, res.start, resource_size(&res));
844 if (!base) {
845 ret = -ENOMEM;
846 goto err_addr_to_resource;
847 }
848
849 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config);
850 if (IS_ERR(regmap)) {
851 dev_err(dev, "Failed to initialize regmap\n");
852 ret = PTR_ERR(regmap);
853 goto err_addr_to_resource;
854 }
855
856 ret = of_property_read_u32(node, "num-lanes", &num_lanes);
857 if (ret) {
858 dev_err(dev, "Failed to read num-lanes property\n");
859 goto err_addr_to_resource;
860 }
861
862 if (num_lanes > WIZ_MAX_LANES) {
863 dev_err(dev, "Cannot support %d lanes\n", num_lanes);
864 ret = -ENODEV;
865 goto err_addr_to_resource;
866 }
867
868 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
869 GPIOD_IN);
870 if (IS_ERR(wiz->gpio_typec_dir)) {
871 ret = PTR_ERR(wiz->gpio_typec_dir);
872 if (ret != -EPROBE_DEFER)
873 dev_err(dev, "Failed to request typec-dir gpio: %d\n",
874 ret);
875 goto err_addr_to_resource;
876 }
877
878 if (wiz->gpio_typec_dir) {
879 ret = of_property_read_u32(node, "typec-dir-debounce-ms",
880 &wiz->typec_dir_delay);
881 if (ret && ret != -EINVAL) {
882 dev_err(dev, "Invalid typec-dir-debounce property\n");
883 goto err_addr_to_resource;
884 }
885
886 /* use min. debounce from Type-C spec if not provided in DT */
887 if (ret == -EINVAL)
888 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;
889
890 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||
891 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {
892 dev_err(dev, "Invalid typec-dir-debounce property\n");
893 goto err_addr_to_resource;
894 }
895 }
896
897 ret = wiz_get_lane_phy_types(dev, wiz);
898 if (ret)
899 return ret;
900
901 wiz->dev = dev;
902 wiz->regmap = regmap;
903 wiz->num_lanes = num_lanes;
904 if (wiz->type == J721E_WIZ_10G)
905 wiz->clk_mux_sel = clk_mux_sel_10g;
906 else
907 wiz->clk_mux_sel = clk_mux_sel_16g;
908
909 wiz->clk_div_sel = clk_div_sel;
910
911 if (wiz->type == J721E_WIZ_10G)
912 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
913 else
914 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
915
916 platform_set_drvdata(pdev, wiz);
917
918 ret = wiz_regfield_init(wiz);
919 if (ret) {
920 dev_err(dev, "Failed to initialize regfields\n");
921 goto err_addr_to_resource;
922 }
923
924 phy_reset_dev = &wiz->wiz_phy_reset_dev;
925 phy_reset_dev->dev = dev;
926 phy_reset_dev->ops = &wiz_phy_reset_ops,
927 phy_reset_dev->owner = THIS_MODULE,
928 phy_reset_dev->of_node = node;
929 /* Reset for each of the lane and one for the entire SERDES */
930 phy_reset_dev->nr_resets = num_lanes + 1;
931
932 ret = devm_reset_controller_register(dev, phy_reset_dev);
933 if (ret < 0) {
934 dev_warn(dev, "Failed to register reset controller\n");
935 goto err_addr_to_resource;
936 }
937
938 pm_runtime_enable(dev);
939 ret = pm_runtime_get_sync(dev);
940 if (ret < 0) {
941 dev_err(dev, "pm_runtime_get_sync failed\n");
942 goto err_get_sync;
943 }
944
945 ret = wiz_clock_init(wiz, node);
946 if (ret < 0) {
947 dev_warn(dev, "Failed to initialize clocks\n");
948 goto err_get_sync;
949 }
950
951 serdes_pdev = of_platform_device_create(child_node, NULL, dev);
952 if (!serdes_pdev) {
953 dev_WARN(dev, "Unable to create SERDES platform device\n");
954 ret = -ENOMEM;
955 goto err_pdev_create;
956 }
957 wiz->serdes_pdev = serdes_pdev;
958
959 ret = wiz_init(wiz);
960 if (ret) {
961 dev_err(dev, "WIZ initialization failed\n");
962 goto err_wiz_init;
963 }
964
965 of_node_put(child_node);
966 return 0;
967
968err_wiz_init:
969 of_platform_device_destroy(&serdes_pdev->dev, NULL);
970
971err_pdev_create:
972 wiz_clock_cleanup(wiz, node);
973
974err_get_sync:
975 pm_runtime_put(dev);
976 pm_runtime_disable(dev);
977
978err_addr_to_resource:
979 of_node_put(child_node);
980
981 return ret;
982}
983
984static int wiz_remove(struct platform_device *pdev)
985{
986 struct device *dev = &pdev->dev;
987 struct device_node *node = dev->of_node;
988 struct platform_device *serdes_pdev;
989 struct wiz *wiz;
990
991 wiz = dev_get_drvdata(dev);
992 serdes_pdev = wiz->serdes_pdev;
993
994 of_platform_device_destroy(&serdes_pdev->dev, NULL);
995 wiz_clock_cleanup(wiz, node);
996 pm_runtime_put(dev);
997 pm_runtime_disable(dev);
998
999 return 0;
1000}
1001
1002static struct platform_driver wiz_driver = {
1003 .probe = wiz_probe,
1004 .remove = wiz_remove,
1005 .driver = {
1006 .name = "wiz",
1007 .of_match_table = wiz_id_table,
1008 },
1009};
1010module_platform_driver(wiz_driver);
1011
1012MODULE_AUTHOR("Texas Instruments Inc.");
1013MODULE_DESCRIPTION("TI J721E WIZ driver");
1014MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Wrapper driver for SERDES used in J721E
4 *
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/phy/phy-ti.h>
11#include <linux/slab.h>
12#include <linux/clk.h>
13#include <linux/clk-provider.h>
14#include <linux/gpio.h>
15#include <linux/gpio/consumer.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/mfd/syscon.h>
19#include <linux/mux/consumer.h>
20#include <linux/of_address.h>
21#include <linux/of_platform.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24#include <linux/regmap.h>
25#include <linux/reset-controller.h>
26
27#define REF_CLK_19_2MHZ 19200000
28#define REF_CLK_25MHZ 25000000
29#define REF_CLK_100MHZ 100000000
30#define REF_CLK_156_25MHZ 156250000
31
32/* SCM offsets */
33#define SERDES_SUP_CTRL 0x4400
34
35/* SERDES offsets */
36#define WIZ_SERDES_CTRL 0x404
37#define WIZ_SERDES_TOP_CTRL 0x408
38#define WIZ_SERDES_RST 0x40c
39#define WIZ_SERDES_TYPEC 0x410
40#define WIZ_LANECTL(n) (0x480 + (0x40 * (n)))
41#define WIZ_LANEDIV(n) (0x484 + (0x40 * (n)))
42
43#define WIZ_MAX_INPUT_CLOCKS 4
44/* To include mux clocks, divider clocks and gate clocks */
45#define WIZ_MAX_OUTPUT_CLOCKS 32
46
47#define WIZ_MAX_LANES 4
48#define WIZ_MUX_NUM_CLOCKS 3
49#define WIZ_DIV_NUM_CLOCKS_16G 2
50#define WIZ_DIV_NUM_CLOCKS_10G 1
51
52#define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30)
53
54enum wiz_lane_standard_mode {
55 LANE_MODE_GEN1,
56 LANE_MODE_GEN2,
57 LANE_MODE_GEN3,
58 LANE_MODE_GEN4,
59};
60
61enum wiz_refclk_mux_sel {
62 PLL0_REFCLK,
63 PLL1_REFCLK,
64 REFCLK_DIG,
65};
66
67enum wiz_refclk_div_sel {
68 CMN_REFCLK_DIG_DIV,
69 CMN_REFCLK1_DIG_DIV,
70};
71
72enum wiz_clock_input {
73 WIZ_CORE_REFCLK,
74 WIZ_EXT_REFCLK,
75 WIZ_CORE_REFCLK1,
76 WIZ_EXT_REFCLK1,
77};
78
79static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
80static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
81static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30);
82static const struct reg_field pll1_refclk_mux_sel =
83 REG_FIELD(WIZ_SERDES_RST, 29, 29);
84static const struct reg_field pll1_refclk_mux_sel_2 =
85 REG_FIELD(WIZ_SERDES_RST, 22, 23);
86static const struct reg_field pll0_refclk_mux_sel =
87 REG_FIELD(WIZ_SERDES_RST, 28, 28);
88static const struct reg_field pll0_refclk_mux_sel_2 =
89 REG_FIELD(WIZ_SERDES_RST, 28, 29);
90static const struct reg_field refclk_dig_sel_16g =
91 REG_FIELD(WIZ_SERDES_RST, 24, 25);
92static const struct reg_field refclk_dig_sel_10g =
93 REG_FIELD(WIZ_SERDES_RST, 24, 24);
94static const struct reg_field pma_cmn_refclk_int_mode =
95 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
96static const struct reg_field pma_cmn_refclk1_int_mode =
97 REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21);
98static const struct reg_field pma_cmn_refclk_mode =
99 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
100static const struct reg_field pma_cmn_refclk_dig_div =
101 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
102static const struct reg_field pma_cmn_refclk1_dig_div =
103 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
104
105static const struct reg_field sup_pll0_refclk_mux_sel =
106 REG_FIELD(SERDES_SUP_CTRL, 0, 1);
107static const struct reg_field sup_pll1_refclk_mux_sel =
108 REG_FIELD(SERDES_SUP_CTRL, 2, 3);
109static const struct reg_field sup_pma_cmn_refclk1_int_mode =
110 REG_FIELD(SERDES_SUP_CTRL, 4, 5);
111static const struct reg_field sup_refclk_dig_sel_10g =
112 REG_FIELD(SERDES_SUP_CTRL, 6, 7);
113static const struct reg_field sup_legacy_clk_override =
114 REG_FIELD(SERDES_SUP_CTRL, 8, 8);
115
116static const char * const output_clk_names[] = {
117 [TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
118 [TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
119 [TI_WIZ_REFCLK_DIG] = "refclk-dig",
120 [TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk",
121};
122
123static const struct reg_field p_enable[WIZ_MAX_LANES] = {
124 REG_FIELD(WIZ_LANECTL(0), 30, 31),
125 REG_FIELD(WIZ_LANECTL(1), 30, 31),
126 REG_FIELD(WIZ_LANECTL(2), 30, 31),
127 REG_FIELD(WIZ_LANECTL(3), 30, 31),
128};
129
130enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };
131
132static const struct reg_field p_align[WIZ_MAX_LANES] = {
133 REG_FIELD(WIZ_LANECTL(0), 29, 29),
134 REG_FIELD(WIZ_LANECTL(1), 29, 29),
135 REG_FIELD(WIZ_LANECTL(2), 29, 29),
136 REG_FIELD(WIZ_LANECTL(3), 29, 29),
137};
138
139static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
140 REG_FIELD(WIZ_LANECTL(0), 28, 28),
141 REG_FIELD(WIZ_LANECTL(1), 28, 28),
142 REG_FIELD(WIZ_LANECTL(2), 28, 28),
143 REG_FIELD(WIZ_LANECTL(3), 28, 28),
144};
145
146static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
147 REG_FIELD(WIZ_LANECTL(0), 24, 25),
148 REG_FIELD(WIZ_LANECTL(1), 24, 25),
149 REG_FIELD(WIZ_LANECTL(2), 24, 25),
150 REG_FIELD(WIZ_LANECTL(3), 24, 25),
151};
152
153static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
154 REG_FIELD(WIZ_LANECTL(0), 22, 23),
155 REG_FIELD(WIZ_LANECTL(1), 22, 23),
156 REG_FIELD(WIZ_LANECTL(2), 22, 23),
157 REG_FIELD(WIZ_LANECTL(3), 22, 23),
158};
159
160static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = {
161 REG_FIELD(WIZ_LANECTL(0), 20, 21),
162 REG_FIELD(WIZ_LANECTL(1), 20, 21),
163 REG_FIELD(WIZ_LANECTL(2), 20, 21),
164 REG_FIELD(WIZ_LANECTL(3), 20, 21),
165};
166
167static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = {
168 REG_FIELD(WIZ_LANECTL(0), 6, 7),
169 REG_FIELD(WIZ_LANECTL(1), 6, 7),
170 REG_FIELD(WIZ_LANECTL(2), 6, 7),
171 REG_FIELD(WIZ_LANECTL(3), 6, 7),
172};
173
174static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = {
175 REG_FIELD(WIZ_LANECTL(0), 18, 19),
176 REG_FIELD(WIZ_LANECTL(1), 18, 19),
177 REG_FIELD(WIZ_LANECTL(2), 18, 19),
178 REG_FIELD(WIZ_LANECTL(3), 18, 19),
179};
180static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {
181 REG_FIELD(WIZ_LANEDIV(0), 16, 22),
182 REG_FIELD(WIZ_LANEDIV(1), 16, 22),
183 REG_FIELD(WIZ_LANEDIV(2), 16, 22),
184 REG_FIELD(WIZ_LANEDIV(3), 16, 22),
185};
186
187static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
188 REG_FIELD(WIZ_LANEDIV(0), 0, 8),
189 REG_FIELD(WIZ_LANEDIV(1), 0, 8),
190 REG_FIELD(WIZ_LANEDIV(2), 0, 8),
191 REG_FIELD(WIZ_LANEDIV(3), 0, 8),
192};
193
194static const struct reg_field typec_ln10_swap =
195 REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
196
197struct wiz_clk_mux {
198 struct clk_hw hw;
199 struct regmap_field *field;
200 const u32 *table;
201 struct clk_init_data clk_data;
202};
203
204#define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw)
205
206struct wiz_clk_divider {
207 struct clk_hw hw;
208 struct regmap_field *field;
209 const struct clk_div_table *table;
210 struct clk_init_data clk_data;
211};
212
213#define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw)
214
215struct wiz_clk_mux_sel {
216 u32 table[WIZ_MAX_INPUT_CLOCKS];
217 const char *node_name;
218 u32 num_parents;
219 u32 parents[WIZ_MAX_INPUT_CLOCKS];
220};
221
222struct wiz_clk_div_sel {
223 const struct clk_div_table *table;
224 const char *node_name;
225};
226
227struct wiz_phy_en_refclk {
228 struct clk_hw hw;
229 struct regmap_field *phy_en_refclk;
230 struct clk_init_data clk_data;
231};
232
233#define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw)
234
235static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
236 {
237 /*
238 * Mux value to be configured for each of the input clocks
239 * in the order populated in device tree
240 */
241 .table = { 1, 0 },
242 .node_name = "pll0-refclk",
243 },
244 {
245 .table = { 1, 0 },
246 .node_name = "pll1-refclk",
247 },
248 {
249 .table = { 1, 3, 0, 2 },
250 .node_name = "refclk-dig",
251 },
252};
253
254static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
255 {
256 /*
257 * Mux value to be configured for each of the input clocks
258 * in the order populated in device tree
259 */
260 .num_parents = 2,
261 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
262 .table = { 1, 0 },
263 .node_name = "pll0-refclk",
264 },
265 {
266 .num_parents = 2,
267 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
268 .table = { 1, 0 },
269 .node_name = "pll1-refclk",
270 },
271 {
272 .num_parents = 2,
273 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
274 .table = { 1, 0 },
275 .node_name = "refclk-dig",
276 },
277};
278
279static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = {
280 {
281 .num_parents = 3,
282 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
283 .table = { 2, 3, 0 },
284 .node_name = "pll0-refclk",
285 },
286 {
287 .num_parents = 3,
288 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
289 .table = { 2, 3, 0 },
290 .node_name = "pll1-refclk",
291 },
292 {
293 .num_parents = 3,
294 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
295 .table = { 2, 3, 0 },
296 .node_name = "refclk-dig",
297 },
298};
299
300static const struct clk_div_table clk_div_table[] = {
301 { .val = 0, .div = 1, },
302 { .val = 1, .div = 2, },
303 { .val = 2, .div = 4, },
304 { .val = 3, .div = 8, },
305 { /* sentinel */ },
306};
307
308static const struct wiz_clk_div_sel clk_div_sel[] = {
309 {
310 .table = clk_div_table,
311 .node_name = "cmn-refclk-dig-div",
312 },
313 {
314 .table = clk_div_table,
315 .node_name = "cmn-refclk1-dig-div",
316 },
317};
318
319enum wiz_type {
320 J721E_WIZ_16G,
321 J721E_WIZ_10G, /* Also for J7200 SR1.0 */
322 AM64_WIZ_10G,
323 J7200_WIZ_10G, /* J7200 SR2.0 */
324 J784S4_WIZ_10G,
325 J721S2_WIZ_10G,
326};
327
328struct wiz_data {
329 enum wiz_type type;
330 const struct reg_field *pll0_refclk_mux_sel;
331 const struct reg_field *pll1_refclk_mux_sel;
332 const struct reg_field *refclk_dig_sel;
333 const struct reg_field *pma_cmn_refclk1_dig_div;
334 const struct reg_field *pma_cmn_refclk1_int_mode;
335 const struct wiz_clk_mux_sel *clk_mux_sel;
336 unsigned int clk_div_sel_num;
337};
338
339#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
340#define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
341
342struct wiz {
343 struct regmap *regmap;
344 struct regmap *scm_regmap;
345 enum wiz_type type;
346 const struct wiz_clk_mux_sel *clk_mux_sel;
347 const struct wiz_clk_div_sel *clk_div_sel;
348 unsigned int clk_div_sel_num;
349 struct regmap_field *por_en;
350 struct regmap_field *phy_reset_n;
351 struct regmap_field *phy_en_refclk;
352 struct regmap_field *p_enable[WIZ_MAX_LANES];
353 struct regmap_field *p_align[WIZ_MAX_LANES];
354 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
355 struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
356 struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES];
357 struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES];
358 struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
359 struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES];
360 struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES];
361 struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES];
362 struct regmap_field *pma_cmn_refclk_int_mode;
363 struct regmap_field *pma_cmn_refclk1_int_mode;
364 struct regmap_field *pma_cmn_refclk_mode;
365 struct regmap_field *pma_cmn_refclk_dig_div;
366 struct regmap_field *pma_cmn_refclk1_dig_div;
367 struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
368 struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
369 struct regmap_field *typec_ln10_swap;
370 struct regmap_field *sup_legacy_clk_override;
371
372 struct device *dev;
373 u32 num_lanes;
374 struct platform_device *serdes_pdev;
375 struct reset_controller_dev wiz_phy_reset_dev;
376 struct gpio_desc *gpio_typec_dir;
377 int typec_dir_delay;
378 u32 lane_phy_type[WIZ_MAX_LANES];
379 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
380 struct clk *output_clks[WIZ_MAX_OUTPUT_CLOCKS];
381 struct clk_onecell_data clk_data;
382 const struct wiz_data *data;
383};
384
385static int wiz_reset(struct wiz *wiz)
386{
387 int ret;
388
389 ret = regmap_field_write(wiz->por_en, 0x1);
390 if (ret)
391 return ret;
392
393 mdelay(1);
394
395 ret = regmap_field_write(wiz->por_en, 0x0);
396 if (ret)
397 return ret;
398
399 return 0;
400}
401
402static int wiz_p_mac_div_sel(struct wiz *wiz)
403{
404 u32 num_lanes = wiz->num_lanes;
405 int ret;
406 int i;
407
408 for (i = 0; i < num_lanes; i++) {
409 if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII ||
410 wiz->lane_phy_type[i] == PHY_TYPE_QSGMII ||
411 wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
412 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
413 if (ret)
414 return ret;
415
416 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);
417 if (ret)
418 return ret;
419 }
420 }
421
422 return 0;
423}
424
425static int wiz_mode_select(struct wiz *wiz)
426{
427 u32 num_lanes = wiz->num_lanes;
428 enum wiz_lane_standard_mode mode;
429 int ret;
430 int i;
431
432 for (i = 0; i < num_lanes; i++) {
433 if (wiz->lane_phy_type[i] == PHY_TYPE_DP)
434 mode = LANE_MODE_GEN1;
435 else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII)
436 mode = LANE_MODE_GEN2;
437 else
438 continue;
439
440 if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
441 ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3);
442 ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3);
443 ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3);
444 mode = LANE_MODE_GEN1;
445 }
446
447 ret = regmap_field_write(wiz->p_standard_mode[i], mode);
448 if (ret)
449 return ret;
450 }
451
452 return 0;
453}
454
455static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
456{
457 u32 num_lanes = wiz->num_lanes;
458 int i;
459 int ret;
460
461 for (i = 0; i < num_lanes; i++) {
462 ret = regmap_field_write(wiz->p_align[i], enable);
463 if (ret)
464 return ret;
465
466 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
467 if (ret)
468 return ret;
469 }
470
471 return 0;
472}
473
474static int wiz_init(struct wiz *wiz)
475{
476 struct device *dev = wiz->dev;
477 int ret;
478
479 ret = wiz_reset(wiz);
480 if (ret) {
481 dev_err(dev, "WIZ reset failed\n");
482 return ret;
483 }
484
485 ret = wiz_mode_select(wiz);
486 if (ret) {
487 dev_err(dev, "WIZ mode select failed\n");
488 return ret;
489 }
490
491 ret = wiz_p_mac_div_sel(wiz);
492 if (ret) {
493 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n");
494 return ret;
495 }
496
497 ret = wiz_init_raw_interface(wiz, true);
498 if (ret) {
499 dev_err(dev, "WIZ interface initialization failed\n");
500 return ret;
501 }
502
503 return 0;
504}
505
506static int wiz_regfield_init(struct wiz *wiz)
507{
508 struct regmap *regmap = wiz->regmap;
509 struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */
510 int num_lanes = wiz->num_lanes;
511 struct device *dev = wiz->dev;
512 const struct wiz_data *data = wiz->data;
513 int i;
514
515 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
516 if (IS_ERR(wiz->por_en)) {
517 dev_err(dev, "POR_EN reg field init failed\n");
518 return PTR_ERR(wiz->por_en);
519 }
520
521 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
522 phy_reset_n);
523 if (IS_ERR(wiz->phy_reset_n)) {
524 dev_err(dev, "PHY_RESET_N reg field init failed\n");
525 return PTR_ERR(wiz->phy_reset_n);
526 }
527
528 wiz->pma_cmn_refclk_int_mode =
529 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode);
530 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
531 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
532 return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
533 }
534
535 wiz->pma_cmn_refclk_mode =
536 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
537 if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
538 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
539 return PTR_ERR(wiz->pma_cmn_refclk_mode);
540 }
541
542 wiz->div_sel_field[CMN_REFCLK_DIG_DIV] =
543 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div);
544 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) {
545 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
546 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]);
547 }
548
549 if (data->pma_cmn_refclk1_dig_div) {
550 wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] =
551 devm_regmap_field_alloc(dev, regmap,
552 *data->pma_cmn_refclk1_dig_div);
553 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) {
554 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
555 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]);
556 }
557 }
558
559 if (wiz->scm_regmap) {
560 scm_regmap = wiz->scm_regmap;
561 wiz->sup_legacy_clk_override =
562 devm_regmap_field_alloc(dev, scm_regmap, sup_legacy_clk_override);
563 if (IS_ERR(wiz->sup_legacy_clk_override)) {
564 dev_err(dev, "SUP_LEGACY_CLK_OVERRIDE reg field init failed\n");
565 return PTR_ERR(wiz->sup_legacy_clk_override);
566 }
567 }
568
569 wiz->mux_sel_field[PLL0_REFCLK] =
570 devm_regmap_field_alloc(dev, scm_regmap, *data->pll0_refclk_mux_sel);
571 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
572 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
573 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
574 }
575
576 wiz->mux_sel_field[PLL1_REFCLK] =
577 devm_regmap_field_alloc(dev, scm_regmap, *data->pll1_refclk_mux_sel);
578 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
579 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
580 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
581 }
582
583 wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap,
584 *data->refclk_dig_sel);
585 if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
586 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
587 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
588 }
589
590 if (data->pma_cmn_refclk1_int_mode) {
591 wiz->pma_cmn_refclk1_int_mode =
592 devm_regmap_field_alloc(dev, scm_regmap, *data->pma_cmn_refclk1_int_mode);
593 if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) {
594 dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n");
595 return PTR_ERR(wiz->pma_cmn_refclk1_int_mode);
596 }
597 }
598
599 for (i = 0; i < num_lanes; i++) {
600 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
601 p_enable[i]);
602 if (IS_ERR(wiz->p_enable[i])) {
603 dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
604 return PTR_ERR(wiz->p_enable[i]);
605 }
606
607 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
608 p_align[i]);
609 if (IS_ERR(wiz->p_align[i])) {
610 dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
611 return PTR_ERR(wiz->p_align[i]);
612 }
613
614 wiz->p_raw_auto_start[i] =
615 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]);
616 if (IS_ERR(wiz->p_raw_auto_start[i])) {
617 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
618 i);
619 return PTR_ERR(wiz->p_raw_auto_start[i]);
620 }
621
622 wiz->p_standard_mode[i] =
623 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]);
624 if (IS_ERR(wiz->p_standard_mode[i])) {
625 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
626 i);
627 return PTR_ERR(wiz->p_standard_mode[i]);
628 }
629
630 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
631 if (IS_ERR(wiz->p0_fullrt_div[i])) {
632 dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i);
633 return PTR_ERR(wiz->p0_fullrt_div[i]);
634 }
635
636 wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]);
637 if (IS_ERR(wiz->p0_mac_src_sel[i])) {
638 dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i);
639 return PTR_ERR(wiz->p0_mac_src_sel[i]);
640 }
641
642 wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]);
643 if (IS_ERR(wiz->p0_rxfclk_sel[i])) {
644 dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i);
645 return PTR_ERR(wiz->p0_rxfclk_sel[i]);
646 }
647
648 wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]);
649 if (IS_ERR(wiz->p0_refclk_sel[i])) {
650 dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i);
651 return PTR_ERR(wiz->p0_refclk_sel[i]);
652 }
653
654 wiz->p_mac_div_sel0[i] =
655 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]);
656 if (IS_ERR(wiz->p_mac_div_sel0[i])) {
657 dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n",
658 i);
659 return PTR_ERR(wiz->p_mac_div_sel0[i]);
660 }
661
662 wiz->p_mac_div_sel1[i] =
663 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]);
664 if (IS_ERR(wiz->p_mac_div_sel1[i])) {
665 dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n",
666 i);
667 return PTR_ERR(wiz->p_mac_div_sel1[i]);
668 }
669 }
670
671 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
672 typec_ln10_swap);
673 if (IS_ERR(wiz->typec_ln10_swap)) {
674 dev_err(dev, "LN10_SWAP reg field init failed\n");
675 return PTR_ERR(wiz->typec_ln10_swap);
676 }
677
678 wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
679 if (IS_ERR(wiz->phy_en_refclk)) {
680 dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
681 return PTR_ERR(wiz->phy_en_refclk);
682 }
683
684 return 0;
685}
686
687static int wiz_phy_en_refclk_enable(struct clk_hw *hw)
688{
689 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
690 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
691
692 regmap_field_write(phy_en_refclk, 1);
693
694 return 0;
695}
696
697static void wiz_phy_en_refclk_disable(struct clk_hw *hw)
698{
699 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
700 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
701
702 regmap_field_write(phy_en_refclk, 0);
703}
704
705static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw)
706{
707 struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
708 struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
709 int val;
710
711 regmap_field_read(phy_en_refclk, &val);
712
713 return !!val;
714}
715
716static const struct clk_ops wiz_phy_en_refclk_ops = {
717 .enable = wiz_phy_en_refclk_enable,
718 .disable = wiz_phy_en_refclk_disable,
719 .is_enabled = wiz_phy_en_refclk_is_enabled,
720};
721
722static int wiz_phy_en_refclk_register(struct wiz *wiz)
723{
724 struct wiz_phy_en_refclk *wiz_phy_en_refclk;
725 struct device *dev = wiz->dev;
726 struct clk_init_data *init;
727 struct clk *clk;
728 char *clk_name;
729 unsigned int sz;
730
731 wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL);
732 if (!wiz_phy_en_refclk)
733 return -ENOMEM;
734
735 init = &wiz_phy_en_refclk->clk_data;
736
737 init->ops = &wiz_phy_en_refclk_ops;
738 init->flags = 0;
739
740 sz = strlen(dev_name(dev)) + strlen(output_clk_names[TI_WIZ_PHY_EN_REFCLK]) + 2;
741
742 clk_name = kzalloc(sz, GFP_KERNEL);
743 if (!clk_name)
744 return -ENOMEM;
745
746 snprintf(clk_name, sz, "%s_%s", dev_name(dev), output_clk_names[TI_WIZ_PHY_EN_REFCLK]);
747 init->name = clk_name;
748
749 wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk;
750 wiz_phy_en_refclk->hw.init = init;
751
752 clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw);
753
754 kfree(clk_name);
755
756 if (IS_ERR(clk))
757 return PTR_ERR(clk);
758
759 wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk;
760
761 return 0;
762}
763
764static u8 wiz_clk_mux_get_parent(struct clk_hw *hw)
765{
766 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
767 struct regmap_field *field = mux->field;
768 unsigned int val;
769
770 regmap_field_read(field, &val);
771 return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val);
772}
773
774static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index)
775{
776 struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
777 struct regmap_field *field = mux->field;
778 int val;
779
780 val = mux->table[index];
781 return regmap_field_write(field, val);
782}
783
784static const struct clk_ops wiz_clk_mux_ops = {
785 .set_parent = wiz_clk_mux_set_parent,
786 .get_parent = wiz_clk_mux_get_parent,
787};
788
789static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field,
790 const struct wiz_clk_mux_sel *mux_sel, int clk_index)
791{
792 struct device *dev = wiz->dev;
793 struct clk_init_data *init;
794 const char **parent_names;
795 unsigned int num_parents;
796 struct wiz_clk_mux *mux;
797 char clk_name[100];
798 struct clk *clk;
799 int ret = 0, i;
800
801 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
802 if (!mux)
803 return -ENOMEM;
804
805 num_parents = mux_sel->num_parents;
806
807 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
808 if (!parent_names)
809 return -ENOMEM;
810
811 for (i = 0; i < num_parents; i++) {
812 clk = wiz->input_clks[mux_sel->parents[i]];
813 if (IS_ERR_OR_NULL(clk)) {
814 dev_err(dev, "Failed to get parent clk for %s\n",
815 output_clk_names[clk_index]);
816 ret = -EINVAL;
817 goto err;
818 }
819 parent_names[i] = __clk_get_name(clk);
820 }
821
822 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]);
823
824 init = &mux->clk_data;
825
826 init->ops = &wiz_clk_mux_ops;
827 init->flags = CLK_SET_RATE_NO_REPARENT;
828 init->parent_names = parent_names;
829 init->num_parents = num_parents;
830 init->name = clk_name;
831
832 mux->field = field;
833 mux->table = mux_sel->table;
834 mux->hw.init = init;
835
836 clk = devm_clk_register(dev, &mux->hw);
837 if (IS_ERR(clk)) {
838 ret = PTR_ERR(clk);
839 goto err;
840 }
841
842 wiz->output_clks[clk_index] = clk;
843
844err:
845 kfree(parent_names);
846
847 return ret;
848}
849
850static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node,
851 struct regmap_field *field, const u32 *table)
852{
853 struct device *dev = wiz->dev;
854 struct clk_init_data *init;
855 const char **parent_names;
856 unsigned int num_parents;
857 struct wiz_clk_mux *mux;
858 char clk_name[100];
859 struct clk *clk;
860 int ret;
861
862 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
863 if (!mux)
864 return -ENOMEM;
865
866 num_parents = of_clk_get_parent_count(node);
867 if (num_parents < 2) {
868 dev_err(dev, "SERDES clock must have parents\n");
869 return -EINVAL;
870 }
871
872 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
873 GFP_KERNEL);
874 if (!parent_names)
875 return -ENOMEM;
876
877 of_clk_parent_fill(node, parent_names, num_parents);
878
879 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
880 node->name);
881
882 init = &mux->clk_data;
883
884 init->ops = &wiz_clk_mux_ops;
885 init->flags = CLK_SET_RATE_NO_REPARENT;
886 init->parent_names = parent_names;
887 init->num_parents = num_parents;
888 init->name = clk_name;
889
890 mux->field = field;
891 mux->table = table;
892 mux->hw.init = init;
893
894 clk = devm_clk_register(dev, &mux->hw);
895 if (IS_ERR(clk))
896 return PTR_ERR(clk);
897
898 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
899 if (ret)
900 dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
901
902 return ret;
903}
904
905static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw,
906 unsigned long parent_rate)
907{
908 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
909 struct regmap_field *field = div->field;
910 int val;
911
912 regmap_field_read(field, &val);
913
914 return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2);
915}
916
917static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
918 unsigned long *prate)
919{
920 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
921
922 return divider_round_rate(hw, rate, prate, div->table, 2, 0x0);
923}
924
925static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
926 unsigned long parent_rate)
927{
928 struct wiz_clk_divider *div = to_wiz_clk_div(hw);
929 struct regmap_field *field = div->field;
930 int val;
931
932 val = divider_get_val(rate, parent_rate, div->table, 2, 0x0);
933 if (val < 0)
934 return val;
935
936 return regmap_field_write(field, val);
937}
938
939static const struct clk_ops wiz_clk_div_ops = {
940 .recalc_rate = wiz_clk_div_recalc_rate,
941 .round_rate = wiz_clk_div_round_rate,
942 .set_rate = wiz_clk_div_set_rate,
943};
944
945static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,
946 struct regmap_field *field,
947 const struct clk_div_table *table)
948{
949 struct device *dev = wiz->dev;
950 struct wiz_clk_divider *div;
951 struct clk_init_data *init;
952 const char **parent_names;
953 char clk_name[100];
954 struct clk *clk;
955 int ret;
956
957 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
958 if (!div)
959 return -ENOMEM;
960
961 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
962 node->name);
963
964 parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
965 if (!parent_names)
966 return -ENOMEM;
967
968 of_clk_parent_fill(node, parent_names, 1);
969
970 init = &div->clk_data;
971
972 init->ops = &wiz_clk_div_ops;
973 init->flags = 0;
974 init->parent_names = parent_names;
975 init->num_parents = 1;
976 init->name = clk_name;
977
978 div->field = field;
979 div->table = table;
980 div->hw.init = init;
981
982 clk = devm_clk_register(dev, &div->hw);
983 if (IS_ERR(clk))
984 return PTR_ERR(clk);
985
986 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
987 if (ret)
988 dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
989
990 return ret;
991}
992
993static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
994{
995 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
996 struct device *dev = wiz->dev;
997 struct device_node *clk_node;
998 int i;
999
1000 switch (wiz->type) {
1001 case AM64_WIZ_10G:
1002 case J7200_WIZ_10G:
1003 case J784S4_WIZ_10G:
1004 case J721S2_WIZ_10G:
1005 of_clk_del_provider(dev->of_node);
1006 return;
1007 default:
1008 break;
1009 }
1010
1011 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
1012 clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name);
1013 of_clk_del_provider(clk_node);
1014 of_node_put(clk_node);
1015 }
1016
1017 for (i = 0; i < wiz->clk_div_sel_num; i++) {
1018 clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name);
1019 of_clk_del_provider(clk_node);
1020 of_node_put(clk_node);
1021 }
1022
1023 of_clk_del_provider(wiz->dev->of_node);
1024}
1025
1026static int wiz_clock_register(struct wiz *wiz)
1027{
1028 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
1029 struct device *dev = wiz->dev;
1030 struct device_node *node = dev->of_node;
1031 int clk_index;
1032 int ret;
1033 int i;
1034
1035 clk_index = TI_WIZ_PLL0_REFCLK;
1036 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) {
1037 ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index);
1038 if (ret) {
1039 dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]);
1040 return ret;
1041 }
1042 }
1043
1044 ret = wiz_phy_en_refclk_register(wiz);
1045 if (ret) {
1046 dev_err(dev, "Failed to add phy-en-refclk\n");
1047 return ret;
1048 }
1049
1050 wiz->clk_data.clks = wiz->output_clks;
1051 wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS;
1052 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data);
1053 if (ret)
1054 dev_err(dev, "Failed to add clock provider: %s\n", node->name);
1055
1056 return ret;
1057}
1058
1059static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
1060{
1061 const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
1062 struct device *dev = wiz->dev;
1063 struct device_node *clk_node;
1064 const char *node_name;
1065 unsigned long rate;
1066 struct clk *clk;
1067 int ret;
1068 int i;
1069
1070 clk = devm_clk_get(dev, "core_ref_clk");
1071 if (IS_ERR(clk)) {
1072 dev_err(dev, "core_ref_clk clock not found\n");
1073 ret = PTR_ERR(clk);
1074 return ret;
1075 }
1076 wiz->input_clks[WIZ_CORE_REFCLK] = clk;
1077
1078 rate = clk_get_rate(clk);
1079 if (rate >= 100000000)
1080 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
1081 else
1082 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
1083
1084 switch (wiz->type) {
1085 case AM64_WIZ_10G:
1086 case J7200_WIZ_10G:
1087 switch (rate) {
1088 case REF_CLK_100MHZ:
1089 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2);
1090 break;
1091 case REF_CLK_156_25MHZ:
1092 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3);
1093 break;
1094 default:
1095 regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0);
1096 break;
1097 }
1098 break;
1099 default:
1100 break;
1101 }
1102
1103 if (wiz->data->pma_cmn_refclk1_int_mode) {
1104 clk = devm_clk_get(dev, "core_ref1_clk");
1105 if (IS_ERR(clk)) {
1106 dev_err(dev, "core_ref1_clk clock not found\n");
1107 ret = PTR_ERR(clk);
1108 return ret;
1109 }
1110 wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
1111
1112 rate = clk_get_rate(clk);
1113 if (rate >= 100000000)
1114 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);
1115 else
1116 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);
1117 }
1118
1119 clk = devm_clk_get(dev, "ext_ref_clk");
1120 if (IS_ERR(clk)) {
1121 dev_err(dev, "ext_ref_clk clock not found\n");
1122 ret = PTR_ERR(clk);
1123 return ret;
1124 }
1125 wiz->input_clks[WIZ_EXT_REFCLK] = clk;
1126
1127 rate = clk_get_rate(clk);
1128 if (rate >= 100000000)
1129 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
1130 else
1131 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
1132
1133 switch (wiz->type) {
1134 case AM64_WIZ_10G:
1135 case J7200_WIZ_10G:
1136 case J784S4_WIZ_10G:
1137 case J721S2_WIZ_10G:
1138 ret = wiz_clock_register(wiz);
1139 if (ret)
1140 dev_err(dev, "Failed to register wiz clocks\n");
1141 return ret;
1142 default:
1143 break;
1144 }
1145
1146 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
1147 node_name = clk_mux_sel[i].node_name;
1148 clk_node = of_get_child_by_name(node, node_name);
1149 if (!clk_node) {
1150 dev_err(dev, "Unable to get %s node\n", node_name);
1151 ret = -EINVAL;
1152 goto err;
1153 }
1154
1155 ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i],
1156 clk_mux_sel[i].table);
1157 if (ret) {
1158 dev_err(dev, "Failed to register %s clock\n",
1159 node_name);
1160 of_node_put(clk_node);
1161 goto err;
1162 }
1163
1164 of_node_put(clk_node);
1165 }
1166
1167 for (i = 0; i < wiz->clk_div_sel_num; i++) {
1168 node_name = clk_div_sel[i].node_name;
1169 clk_node = of_get_child_by_name(node, node_name);
1170 if (!clk_node) {
1171 dev_err(dev, "Unable to get %s node\n", node_name);
1172 ret = -EINVAL;
1173 goto err;
1174 }
1175
1176 ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i],
1177 clk_div_sel[i].table);
1178 if (ret) {
1179 dev_err(dev, "Failed to register %s clock\n",
1180 node_name);
1181 of_node_put(clk_node);
1182 goto err;
1183 }
1184
1185 of_node_put(clk_node);
1186 }
1187
1188 return 0;
1189err:
1190 wiz_clock_cleanup(wiz, node);
1191
1192 return ret;
1193}
1194
1195static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
1196 unsigned long id)
1197{
1198 struct device *dev = rcdev->dev;
1199 struct wiz *wiz = dev_get_drvdata(dev);
1200 int ret = 0;
1201
1202 if (id == 0) {
1203 ret = regmap_field_write(wiz->phy_reset_n, false);
1204 return ret;
1205 }
1206
1207 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
1208 return ret;
1209}
1210
1211static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
1212{
1213 switch (wiz->type) {
1214 case AM64_WIZ_10G:
1215 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
1216 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
1217 break;
1218 case J721E_WIZ_10G:
1219 case J7200_WIZ_10G:
1220 case J721S2_WIZ_10G:
1221 if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
1222 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
1223 break;
1224 default:
1225 return 0;
1226 }
1227 return 0;
1228}
1229
1230static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
1231 unsigned long id)
1232{
1233 struct device *dev = rcdev->dev;
1234 struct wiz *wiz = dev_get_drvdata(dev);
1235 int ret;
1236
1237 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
1238 if (id == 0 && wiz->gpio_typec_dir) {
1239 if (wiz->typec_dir_delay)
1240 msleep_interruptible(wiz->typec_dir_delay);
1241
1242 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
1243 regmap_field_write(wiz->typec_ln10_swap, 1);
1244 else
1245 regmap_field_write(wiz->typec_ln10_swap, 0);
1246 }
1247
1248 if (id == 0) {
1249 ret = regmap_field_write(wiz->phy_reset_n, true);
1250 return ret;
1251 }
1252
1253 ret = wiz_phy_fullrt_div(wiz, id - 1);
1254 if (ret)
1255 return ret;
1256
1257 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
1258 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
1259 else
1260 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
1261
1262 return ret;
1263}
1264
1265static const struct reset_control_ops wiz_phy_reset_ops = {
1266 .assert = wiz_phy_reset_assert,
1267 .deassert = wiz_phy_reset_deassert,
1268};
1269
1270static const struct regmap_config wiz_regmap_config = {
1271 .reg_bits = 32,
1272 .val_bits = 32,
1273 .reg_stride = 4,
1274 .fast_io = true,
1275};
1276
1277static struct wiz_data j721e_16g_data = {
1278 .type = J721E_WIZ_16G,
1279 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
1280 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
1281 .refclk_dig_sel = &refclk_dig_sel_16g,
1282 .pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div,
1283 .clk_mux_sel = clk_mux_sel_16g,
1284 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G,
1285};
1286
1287static struct wiz_data j721e_10g_data = {
1288 .type = J721E_WIZ_10G,
1289 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
1290 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
1291 .refclk_dig_sel = &refclk_dig_sel_10g,
1292 .clk_mux_sel = clk_mux_sel_10g,
1293 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1294};
1295
1296static struct wiz_data am64_10g_data = {
1297 .type = AM64_WIZ_10G,
1298 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
1299 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
1300 .refclk_dig_sel = &refclk_dig_sel_10g,
1301 .clk_mux_sel = clk_mux_sel_10g,
1302 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1303};
1304
1305static struct wiz_data j7200_pg2_10g_data = {
1306 .type = J7200_WIZ_10G,
1307 .pll0_refclk_mux_sel = &sup_pll0_refclk_mux_sel,
1308 .pll1_refclk_mux_sel = &sup_pll1_refclk_mux_sel,
1309 .refclk_dig_sel = &sup_refclk_dig_sel_10g,
1310 .pma_cmn_refclk1_int_mode = &sup_pma_cmn_refclk1_int_mode,
1311 .clk_mux_sel = clk_mux_sel_10g_2_refclk,
1312 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1313};
1314
1315static struct wiz_data j784s4_10g_data = {
1316 .type = J784S4_WIZ_10G,
1317 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel_2,
1318 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel_2,
1319 .refclk_dig_sel = &refclk_dig_sel_16g,
1320 .pma_cmn_refclk1_int_mode = &pma_cmn_refclk1_int_mode,
1321 .clk_mux_sel = clk_mux_sel_10g_2_refclk,
1322 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1323};
1324
1325static struct wiz_data j721s2_10g_data = {
1326 .type = J721S2_WIZ_10G,
1327 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
1328 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
1329 .refclk_dig_sel = &refclk_dig_sel_10g,
1330 .clk_mux_sel = clk_mux_sel_10g,
1331 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1332};
1333
1334static const struct of_device_id wiz_id_table[] = {
1335 {
1336 .compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data,
1337 },
1338 {
1339 .compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data,
1340 },
1341 {
1342 .compatible = "ti,am64-wiz-10g", .data = &am64_10g_data,
1343 },
1344 {
1345 .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data,
1346 },
1347 {
1348 .compatible = "ti,j784s4-wiz-10g", .data = &j784s4_10g_data,
1349 },
1350 {
1351 .compatible = "ti,j721s2-wiz-10g", .data = &j721s2_10g_data,
1352 },
1353 {}
1354};
1355MODULE_DEVICE_TABLE(of, wiz_id_table);
1356
1357static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
1358{
1359 struct device_node *serdes, *subnode;
1360
1361 serdes = of_get_child_by_name(dev->of_node, "serdes");
1362 if (!serdes) {
1363 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__);
1364 return -EINVAL;
1365 }
1366
1367 for_each_child_of_node(serdes, subnode) {
1368 u32 reg, num_lanes = 1, phy_type = PHY_NONE;
1369 int ret, i;
1370
1371 if (!(of_node_name_eq(subnode, "phy") ||
1372 of_node_name_eq(subnode, "link")))
1373 continue;
1374
1375 ret = of_property_read_u32(subnode, "reg", ®);
1376 if (ret) {
1377 of_node_put(subnode);
1378 dev_err(dev,
1379 "%s: Reading \"reg\" from \"%s\" failed: %d\n",
1380 __func__, subnode->name, ret);
1381 return ret;
1382 }
1383 of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes);
1384 of_property_read_u32(subnode, "cdns,phy-type", &phy_type);
1385
1386 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
1387 reg, reg + num_lanes - 1, phy_type);
1388
1389 for (i = reg; i < reg + num_lanes; i++)
1390 wiz->lane_phy_type[i] = phy_type;
1391 }
1392
1393 return 0;
1394}
1395
1396static int wiz_probe(struct platform_device *pdev)
1397{
1398 struct reset_controller_dev *phy_reset_dev;
1399 struct device *dev = &pdev->dev;
1400 struct device_node *node = dev->of_node;
1401 struct platform_device *serdes_pdev;
1402 bool already_configured = false;
1403 struct device_node *child_node;
1404 struct regmap *regmap;
1405 struct resource res;
1406 void __iomem *base;
1407 struct wiz *wiz;
1408 int ret, val, i;
1409 u32 num_lanes;
1410 const struct wiz_data *data;
1411
1412 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);
1413 if (!wiz)
1414 return -ENOMEM;
1415
1416 data = of_device_get_match_data(dev);
1417 if (!data) {
1418 dev_err(dev, "NULL device data\n");
1419 return -EINVAL;
1420 }
1421
1422 wiz->data = data;
1423 wiz->type = data->type;
1424
1425 child_node = of_get_child_by_name(node, "serdes");
1426 if (!child_node) {
1427 dev_err(dev, "Failed to get SERDES child DT node\n");
1428 return -ENODEV;
1429 }
1430
1431 ret = of_address_to_resource(child_node, 0, &res);
1432 if (ret) {
1433 dev_err(dev, "Failed to get memory resource\n");
1434 goto err_addr_to_resource;
1435 }
1436
1437 base = devm_ioremap(dev, res.start, resource_size(&res));
1438 if (!base) {
1439 ret = -ENOMEM;
1440 goto err_addr_to_resource;
1441 }
1442
1443 regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config);
1444 if (IS_ERR(regmap)) {
1445 dev_err(dev, "Failed to initialize regmap\n");
1446 ret = PTR_ERR(regmap);
1447 goto err_addr_to_resource;
1448 }
1449
1450 wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm");
1451 if (IS_ERR(wiz->scm_regmap)) {
1452 if (wiz->type == J7200_WIZ_10G) {
1453 dev_err(dev, "Couldn't get ti,scm regmap\n");
1454 ret = -ENODEV;
1455 goto err_addr_to_resource;
1456 }
1457
1458 wiz->scm_regmap = NULL;
1459 }
1460
1461 ret = of_property_read_u32(node, "num-lanes", &num_lanes);
1462 if (ret) {
1463 dev_err(dev, "Failed to read num-lanes property\n");
1464 goto err_addr_to_resource;
1465 }
1466
1467 if (num_lanes > WIZ_MAX_LANES) {
1468 dev_err(dev, "Cannot support %d lanes\n", num_lanes);
1469 ret = -ENODEV;
1470 goto err_addr_to_resource;
1471 }
1472
1473 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
1474 GPIOD_IN);
1475 if (IS_ERR(wiz->gpio_typec_dir)) {
1476 ret = PTR_ERR(wiz->gpio_typec_dir);
1477 if (ret != -EPROBE_DEFER)
1478 dev_err(dev, "Failed to request typec-dir gpio: %d\n",
1479 ret);
1480 goto err_addr_to_resource;
1481 }
1482
1483 if (wiz->gpio_typec_dir) {
1484 ret = of_property_read_u32(node, "typec-dir-debounce-ms",
1485 &wiz->typec_dir_delay);
1486 if (ret && ret != -EINVAL) {
1487 dev_err(dev, "Invalid typec-dir-debounce property\n");
1488 goto err_addr_to_resource;
1489 }
1490
1491 /* use min. debounce from Type-C spec if not provided in DT */
1492 if (ret == -EINVAL)
1493 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;
1494
1495 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||
1496 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {
1497 ret = -EINVAL;
1498 dev_err(dev, "Invalid typec-dir-debounce property\n");
1499 goto err_addr_to_resource;
1500 }
1501 }
1502
1503 ret = wiz_get_lane_phy_types(dev, wiz);
1504 if (ret)
1505 goto err_addr_to_resource;
1506
1507 wiz->dev = dev;
1508 wiz->regmap = regmap;
1509 wiz->num_lanes = num_lanes;
1510 wiz->clk_mux_sel = data->clk_mux_sel;
1511 wiz->clk_div_sel = clk_div_sel;
1512 wiz->clk_div_sel_num = data->clk_div_sel_num;
1513
1514 platform_set_drvdata(pdev, wiz);
1515
1516 ret = wiz_regfield_init(wiz);
1517 if (ret) {
1518 dev_err(dev, "Failed to initialize regfields\n");
1519 goto err_addr_to_resource;
1520 }
1521
1522 /* Enable supplemental Control override if available */
1523 if (wiz->scm_regmap)
1524 regmap_field_write(wiz->sup_legacy_clk_override, 1);
1525
1526 phy_reset_dev = &wiz->wiz_phy_reset_dev;
1527 phy_reset_dev->dev = dev;
1528 phy_reset_dev->ops = &wiz_phy_reset_ops,
1529 phy_reset_dev->owner = THIS_MODULE,
1530 phy_reset_dev->of_node = node;
1531 /* Reset for each of the lane and one for the entire SERDES */
1532 phy_reset_dev->nr_resets = num_lanes + 1;
1533
1534 ret = devm_reset_controller_register(dev, phy_reset_dev);
1535 if (ret < 0) {
1536 dev_warn(dev, "Failed to register reset controller\n");
1537 goto err_addr_to_resource;
1538 }
1539
1540 pm_runtime_enable(dev);
1541 ret = pm_runtime_get_sync(dev);
1542 if (ret < 0) {
1543 dev_err(dev, "pm_runtime_get_sync failed\n");
1544 goto err_get_sync;
1545 }
1546
1547 ret = wiz_clock_init(wiz, node);
1548 if (ret < 0) {
1549 dev_warn(dev, "Failed to initialize clocks\n");
1550 goto err_get_sync;
1551 }
1552
1553 for (i = 0; i < wiz->num_lanes; i++) {
1554 regmap_field_read(wiz->p_enable[i], &val);
1555 if (val & (P_ENABLE | P_ENABLE_FORCE)) {
1556 already_configured = true;
1557 break;
1558 }
1559 }
1560
1561 if (!already_configured) {
1562 ret = wiz_init(wiz);
1563 if (ret) {
1564 dev_err(dev, "WIZ initialization failed\n");
1565 goto err_wiz_init;
1566 }
1567 }
1568
1569 serdes_pdev = of_platform_device_create(child_node, NULL, dev);
1570 if (!serdes_pdev) {
1571 dev_WARN(dev, "Unable to create SERDES platform device\n");
1572 ret = -ENOMEM;
1573 goto err_wiz_init;
1574 }
1575 wiz->serdes_pdev = serdes_pdev;
1576
1577 of_node_put(child_node);
1578 return 0;
1579
1580err_wiz_init:
1581 wiz_clock_cleanup(wiz, node);
1582
1583err_get_sync:
1584 pm_runtime_put(dev);
1585 pm_runtime_disable(dev);
1586
1587err_addr_to_resource:
1588 of_node_put(child_node);
1589
1590 return ret;
1591}
1592
1593static int wiz_remove(struct platform_device *pdev)
1594{
1595 struct device *dev = &pdev->dev;
1596 struct device_node *node = dev->of_node;
1597 struct platform_device *serdes_pdev;
1598 struct wiz *wiz;
1599
1600 wiz = dev_get_drvdata(dev);
1601 serdes_pdev = wiz->serdes_pdev;
1602
1603 of_platform_device_destroy(&serdes_pdev->dev, NULL);
1604 wiz_clock_cleanup(wiz, node);
1605 pm_runtime_put(dev);
1606 pm_runtime_disable(dev);
1607
1608 return 0;
1609}
1610
1611static struct platform_driver wiz_driver = {
1612 .probe = wiz_probe,
1613 .remove = wiz_remove,
1614 .driver = {
1615 .name = "wiz",
1616 .of_match_table = wiz_id_table,
1617 },
1618};
1619module_platform_driver(wiz_driver);
1620
1621MODULE_AUTHOR("Texas Instruments Inc.");
1622MODULE_DESCRIPTION("TI J721E WIZ driver");
1623MODULE_LICENSE("GPL v2");