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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Core, IRQ and I2C device driver for DA9061 and DA9062 PMICs
4 * Copyright (C) 2015-2017 Dialog Semiconductor
5 */
6
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/device.h>
11#include <linux/interrupt.h>
12#include <linux/regmap.h>
13#include <linux/irq.h>
14#include <linux/mfd/core.h>
15#include <linux/i2c.h>
16#include <linux/mfd/da9062/core.h>
17#include <linux/mfd/da9062/registers.h>
18#include <linux/regulator/of_regulator.h>
19
20#define DA9062_REG_EVENT_A_OFFSET 0
21#define DA9062_REG_EVENT_B_OFFSET 1
22#define DA9062_REG_EVENT_C_OFFSET 2
23
24#define DA9062_IRQ_LOW 0
25#define DA9062_IRQ_HIGH 1
26
27static struct regmap_irq da9061_irqs[] = {
28 /* EVENT A */
29 [DA9061_IRQ_ONKEY] = {
30 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
31 .mask = DA9062AA_M_NONKEY_MASK,
32 },
33 [DA9061_IRQ_WDG_WARN] = {
34 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
35 .mask = DA9062AA_M_WDG_WARN_MASK,
36 },
37 [DA9061_IRQ_SEQ_RDY] = {
38 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
39 .mask = DA9062AA_M_SEQ_RDY_MASK,
40 },
41 /* EVENT B */
42 [DA9061_IRQ_TEMP] = {
43 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
44 .mask = DA9062AA_M_TEMP_MASK,
45 },
46 [DA9061_IRQ_LDO_LIM] = {
47 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
48 .mask = DA9062AA_M_LDO_LIM_MASK,
49 },
50 [DA9061_IRQ_DVC_RDY] = {
51 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
52 .mask = DA9062AA_M_DVC_RDY_MASK,
53 },
54 [DA9061_IRQ_VDD_WARN] = {
55 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
56 .mask = DA9062AA_M_VDD_WARN_MASK,
57 },
58 /* EVENT C */
59 [DA9061_IRQ_GPI0] = {
60 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
61 .mask = DA9062AA_M_GPI0_MASK,
62 },
63 [DA9061_IRQ_GPI1] = {
64 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
65 .mask = DA9062AA_M_GPI1_MASK,
66 },
67 [DA9061_IRQ_GPI2] = {
68 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
69 .mask = DA9062AA_M_GPI2_MASK,
70 },
71 [DA9061_IRQ_GPI3] = {
72 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
73 .mask = DA9062AA_M_GPI3_MASK,
74 },
75 [DA9061_IRQ_GPI4] = {
76 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
77 .mask = DA9062AA_M_GPI4_MASK,
78 },
79};
80
81static struct regmap_irq_chip da9061_irq_chip = {
82 .name = "da9061-irq",
83 .irqs = da9061_irqs,
84 .num_irqs = DA9061_NUM_IRQ,
85 .num_regs = 3,
86 .status_base = DA9062AA_EVENT_A,
87 .mask_base = DA9062AA_IRQ_MASK_A,
88 .ack_base = DA9062AA_EVENT_A,
89};
90
91static struct regmap_irq da9062_irqs[] = {
92 /* EVENT A */
93 [DA9062_IRQ_ONKEY] = {
94 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
95 .mask = DA9062AA_M_NONKEY_MASK,
96 },
97 [DA9062_IRQ_ALARM] = {
98 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
99 .mask = DA9062AA_M_ALARM_MASK,
100 },
101 [DA9062_IRQ_TICK] = {
102 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
103 .mask = DA9062AA_M_TICK_MASK,
104 },
105 [DA9062_IRQ_WDG_WARN] = {
106 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
107 .mask = DA9062AA_M_WDG_WARN_MASK,
108 },
109 [DA9062_IRQ_SEQ_RDY] = {
110 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
111 .mask = DA9062AA_M_SEQ_RDY_MASK,
112 },
113 /* EVENT B */
114 [DA9062_IRQ_TEMP] = {
115 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
116 .mask = DA9062AA_M_TEMP_MASK,
117 },
118 [DA9062_IRQ_LDO_LIM] = {
119 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
120 .mask = DA9062AA_M_LDO_LIM_MASK,
121 },
122 [DA9062_IRQ_DVC_RDY] = {
123 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
124 .mask = DA9062AA_M_DVC_RDY_MASK,
125 },
126 [DA9062_IRQ_VDD_WARN] = {
127 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
128 .mask = DA9062AA_M_VDD_WARN_MASK,
129 },
130 /* EVENT C */
131 [DA9062_IRQ_GPI0] = {
132 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
133 .mask = DA9062AA_M_GPI0_MASK,
134 },
135 [DA9062_IRQ_GPI1] = {
136 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
137 .mask = DA9062AA_M_GPI1_MASK,
138 },
139 [DA9062_IRQ_GPI2] = {
140 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
141 .mask = DA9062AA_M_GPI2_MASK,
142 },
143 [DA9062_IRQ_GPI3] = {
144 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
145 .mask = DA9062AA_M_GPI3_MASK,
146 },
147 [DA9062_IRQ_GPI4] = {
148 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
149 .mask = DA9062AA_M_GPI4_MASK,
150 },
151};
152
153static struct regmap_irq_chip da9062_irq_chip = {
154 .name = "da9062-irq",
155 .irqs = da9062_irqs,
156 .num_irqs = DA9062_NUM_IRQ,
157 .num_regs = 3,
158 .status_base = DA9062AA_EVENT_A,
159 .mask_base = DA9062AA_IRQ_MASK_A,
160 .ack_base = DA9062AA_EVENT_A,
161};
162
163static struct resource da9061_core_resources[] = {
164 DEFINE_RES_IRQ_NAMED(DA9061_IRQ_VDD_WARN, "VDD_WARN"),
165};
166
167static struct resource da9061_regulators_resources[] = {
168 DEFINE_RES_IRQ_NAMED(DA9061_IRQ_LDO_LIM, "LDO_LIM"),
169};
170
171static struct resource da9061_thermal_resources[] = {
172 DEFINE_RES_IRQ_NAMED(DA9061_IRQ_TEMP, "THERMAL"),
173};
174
175static struct resource da9061_wdt_resources[] = {
176 DEFINE_RES_IRQ_NAMED(DA9061_IRQ_WDG_WARN, "WD_WARN"),
177};
178
179static struct resource da9061_onkey_resources[] = {
180 DEFINE_RES_IRQ_NAMED(DA9061_IRQ_ONKEY, "ONKEY"),
181};
182
183static const struct mfd_cell da9061_devs[] = {
184 {
185 .name = "da9061-core",
186 .num_resources = ARRAY_SIZE(da9061_core_resources),
187 .resources = da9061_core_resources,
188 },
189 {
190 .name = "da9062-regulators",
191 .num_resources = ARRAY_SIZE(da9061_regulators_resources),
192 .resources = da9061_regulators_resources,
193 },
194 {
195 .name = "da9061-watchdog",
196 .num_resources = ARRAY_SIZE(da9061_wdt_resources),
197 .resources = da9061_wdt_resources,
198 .of_compatible = "dlg,da9061-watchdog",
199 },
200 {
201 .name = "da9061-thermal",
202 .num_resources = ARRAY_SIZE(da9061_thermal_resources),
203 .resources = da9061_thermal_resources,
204 .of_compatible = "dlg,da9061-thermal",
205 },
206 {
207 .name = "da9061-onkey",
208 .num_resources = ARRAY_SIZE(da9061_onkey_resources),
209 .resources = da9061_onkey_resources,
210 .of_compatible = "dlg,da9061-onkey",
211 },
212};
213
214static struct resource da9062_core_resources[] = {
215 DEFINE_RES_NAMED(DA9062_IRQ_VDD_WARN, 1, "VDD_WARN", IORESOURCE_IRQ),
216};
217
218static struct resource da9062_regulators_resources[] = {
219 DEFINE_RES_NAMED(DA9062_IRQ_LDO_LIM, 1, "LDO_LIM", IORESOURCE_IRQ),
220};
221
222static struct resource da9062_thermal_resources[] = {
223 DEFINE_RES_NAMED(DA9062_IRQ_TEMP, 1, "THERMAL", IORESOURCE_IRQ),
224};
225
226static struct resource da9062_wdt_resources[] = {
227 DEFINE_RES_NAMED(DA9062_IRQ_WDG_WARN, 1, "WD_WARN", IORESOURCE_IRQ),
228};
229
230static struct resource da9062_rtc_resources[] = {
231 DEFINE_RES_NAMED(DA9062_IRQ_ALARM, 1, "ALARM", IORESOURCE_IRQ),
232 DEFINE_RES_NAMED(DA9062_IRQ_TICK, 1, "TICK", IORESOURCE_IRQ),
233};
234
235static struct resource da9062_onkey_resources[] = {
236 DEFINE_RES_NAMED(DA9062_IRQ_ONKEY, 1, "ONKEY", IORESOURCE_IRQ),
237};
238
239static struct resource da9062_gpio_resources[] = {
240 DEFINE_RES_NAMED(DA9062_IRQ_GPI0, 1, "GPI0", IORESOURCE_IRQ),
241 DEFINE_RES_NAMED(DA9062_IRQ_GPI1, 1, "GPI1", IORESOURCE_IRQ),
242 DEFINE_RES_NAMED(DA9062_IRQ_GPI2, 1, "GPI2", IORESOURCE_IRQ),
243 DEFINE_RES_NAMED(DA9062_IRQ_GPI3, 1, "GPI3", IORESOURCE_IRQ),
244 DEFINE_RES_NAMED(DA9062_IRQ_GPI4, 1, "GPI4", IORESOURCE_IRQ),
245};
246
247static const struct mfd_cell da9062_devs[] = {
248 {
249 .name = "da9062-core",
250 .num_resources = ARRAY_SIZE(da9062_core_resources),
251 .resources = da9062_core_resources,
252 },
253 {
254 .name = "da9062-regulators",
255 .num_resources = ARRAY_SIZE(da9062_regulators_resources),
256 .resources = da9062_regulators_resources,
257 },
258 {
259 .name = "da9062-watchdog",
260 .num_resources = ARRAY_SIZE(da9062_wdt_resources),
261 .resources = da9062_wdt_resources,
262 .of_compatible = "dlg,da9062-watchdog",
263 },
264 {
265 .name = "da9062-thermal",
266 .num_resources = ARRAY_SIZE(da9062_thermal_resources),
267 .resources = da9062_thermal_resources,
268 .of_compatible = "dlg,da9062-thermal",
269 },
270 {
271 .name = "da9062-rtc",
272 .num_resources = ARRAY_SIZE(da9062_rtc_resources),
273 .resources = da9062_rtc_resources,
274 .of_compatible = "dlg,da9062-rtc",
275 },
276 {
277 .name = "da9062-onkey",
278 .num_resources = ARRAY_SIZE(da9062_onkey_resources),
279 .resources = da9062_onkey_resources,
280 .of_compatible = "dlg,da9062-onkey",
281 },
282 {
283 .name = "da9062-gpio",
284 .num_resources = ARRAY_SIZE(da9062_gpio_resources),
285 .resources = da9062_gpio_resources,
286 .of_compatible = "dlg,da9062-gpio",
287 },
288};
289
290static int da9062_clear_fault_log(struct da9062 *chip)
291{
292 int ret;
293 int fault_log;
294
295 ret = regmap_read(chip->regmap, DA9062AA_FAULT_LOG, &fault_log);
296 if (ret < 0)
297 return ret;
298
299 if (fault_log) {
300 if (fault_log & DA9062AA_TWD_ERROR_MASK)
301 dev_dbg(chip->dev, "Fault log entry detected: TWD_ERROR\n");
302 if (fault_log & DA9062AA_POR_MASK)
303 dev_dbg(chip->dev, "Fault log entry detected: POR\n");
304 if (fault_log & DA9062AA_VDD_FAULT_MASK)
305 dev_dbg(chip->dev, "Fault log entry detected: VDD_FAULT\n");
306 if (fault_log & DA9062AA_VDD_START_MASK)
307 dev_dbg(chip->dev, "Fault log entry detected: VDD_START\n");
308 if (fault_log & DA9062AA_TEMP_CRIT_MASK)
309 dev_dbg(chip->dev, "Fault log entry detected: TEMP_CRIT\n");
310 if (fault_log & DA9062AA_KEY_RESET_MASK)
311 dev_dbg(chip->dev, "Fault log entry detected: KEY_RESET\n");
312 if (fault_log & DA9062AA_NSHUTDOWN_MASK)
313 dev_dbg(chip->dev, "Fault log entry detected: NSHUTDOWN\n");
314 if (fault_log & DA9062AA_WAIT_SHUT_MASK)
315 dev_dbg(chip->dev, "Fault log entry detected: WAIT_SHUT\n");
316
317 ret = regmap_write(chip->regmap, DA9062AA_FAULT_LOG,
318 fault_log);
319 }
320
321 return ret;
322}
323
324static int da9062_get_device_type(struct da9062 *chip)
325{
326 int device_id, variant_id, variant_mrc, variant_vrc;
327 char *type;
328 int ret;
329
330 ret = regmap_read(chip->regmap, DA9062AA_DEVICE_ID, &device_id);
331 if (ret < 0) {
332 dev_err(chip->dev, "Cannot read chip ID.\n");
333 return -EIO;
334 }
335 if (device_id != DA9062_PMIC_DEVICE_ID) {
336 dev_err(chip->dev, "Invalid device ID: 0x%02x\n", device_id);
337 return -ENODEV;
338 }
339
340 ret = regmap_read(chip->regmap, DA9062AA_VARIANT_ID, &variant_id);
341 if (ret < 0) {
342 dev_err(chip->dev, "Cannot read chip variant id.\n");
343 return -EIO;
344 }
345
346 variant_vrc = (variant_id & DA9062AA_VRC_MASK) >> DA9062AA_VRC_SHIFT;
347
348 switch (variant_vrc) {
349 case DA9062_PMIC_VARIANT_VRC_DA9061:
350 type = "DA9061";
351 break;
352 case DA9062_PMIC_VARIANT_VRC_DA9062:
353 type = "DA9062";
354 break;
355 default:
356 type = "Unknown";
357 break;
358 }
359
360 dev_info(chip->dev,
361 "Device detected (device-ID: 0x%02X, var-ID: 0x%02X, %s)\n",
362 device_id, variant_id, type);
363
364 variant_mrc = (variant_id & DA9062AA_MRC_MASK) >> DA9062AA_MRC_SHIFT;
365
366 if (variant_mrc < DA9062_PMIC_VARIANT_MRC_AA) {
367 dev_err(chip->dev,
368 "Cannot support variant MRC: 0x%02X\n", variant_mrc);
369 return -ENODEV;
370 }
371
372 return ret;
373}
374
375static u32 da9062_configure_irq_type(struct da9062 *chip, int irq, u32 *trigger)
376{
377 u32 irq_type = 0;
378 struct irq_data *irq_data = irq_get_irq_data(irq);
379
380 if (!irq_data) {
381 dev_err(chip->dev, "Invalid IRQ: %d\n", irq);
382 return -EINVAL;
383 }
384 *trigger = irqd_get_trigger_type(irq_data);
385
386 switch (*trigger) {
387 case IRQ_TYPE_LEVEL_HIGH:
388 irq_type = DA9062_IRQ_HIGH;
389 break;
390 case IRQ_TYPE_LEVEL_LOW:
391 irq_type = DA9062_IRQ_LOW;
392 break;
393 default:
394 dev_warn(chip->dev, "Unsupported IRQ type: %d\n", *trigger);
395 return -EINVAL;
396 }
397 return regmap_update_bits(chip->regmap, DA9062AA_CONFIG_A,
398 DA9062AA_IRQ_TYPE_MASK,
399 irq_type << DA9062AA_IRQ_TYPE_SHIFT);
400}
401
402static const struct regmap_range da9061_aa_readable_ranges[] = {
403 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
404 regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
405 regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
406 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
407 regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_GPIO_OUT3_4),
408 regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
409 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
410 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
411 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
412 regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
413 regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
414 regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
415 regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_WAIT),
416 regmap_reg_range(DA9062AA_RESET, DA9062AA_BUCK_ILIM_C),
417 regmap_reg_range(DA9062AA_BUCK1_CFG, DA9062AA_BUCK3_CFG),
418 regmap_reg_range(DA9062AA_VBUCK1_A, DA9062AA_VBUCK4_A),
419 regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
420 regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
421 regmap_reg_range(DA9062AA_CONFIG_A, DA9062AA_CONFIG_A),
422 regmap_reg_range(DA9062AA_VBUCK1_B, DA9062AA_VBUCK4_B),
423 regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
424 regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
425 regmap_reg_range(DA9062AA_INTERFACE, DA9062AA_CONFIG_E),
426 regmap_reg_range(DA9062AA_CONFIG_G, DA9062AA_CONFIG_K),
427 regmap_reg_range(DA9062AA_CONFIG_M, DA9062AA_CONFIG_M),
428 regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
429 regmap_reg_range(DA9062AA_DEVICE_ID, DA9062AA_CONFIG_ID),
430};
431
432static const struct regmap_range da9061_aa_writeable_ranges[] = {
433 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_PAGE_CON),
434 regmap_reg_range(DA9062AA_FAULT_LOG, DA9062AA_EVENT_C),
435 regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
436 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
437 regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_GPIO_OUT3_4),
438 regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
439 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
440 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
441 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
442 regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
443 regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
444 regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
445 regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_WAIT),
446 regmap_reg_range(DA9062AA_RESET, DA9062AA_BUCK_ILIM_C),
447 regmap_reg_range(DA9062AA_BUCK1_CFG, DA9062AA_BUCK3_CFG),
448 regmap_reg_range(DA9062AA_VBUCK1_A, DA9062AA_VBUCK4_A),
449 regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
450 regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
451 regmap_reg_range(DA9062AA_CONFIG_A, DA9062AA_CONFIG_A),
452 regmap_reg_range(DA9062AA_VBUCK1_B, DA9062AA_VBUCK4_B),
453 regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
454 regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
455 regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
456};
457
458static const struct regmap_range da9061_aa_volatile_ranges[] = {
459 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
460 regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
461 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_CONTROL_B),
462 regmap_reg_range(DA9062AA_CONTROL_E, DA9062AA_CONTROL_F),
463 regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
464 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
465 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
466 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
467 regmap_reg_range(DA9062AA_SEQ, DA9062AA_SEQ),
468};
469
470static const struct regmap_access_table da9061_aa_readable_table = {
471 .yes_ranges = da9061_aa_readable_ranges,
472 .n_yes_ranges = ARRAY_SIZE(da9061_aa_readable_ranges),
473};
474
475static const struct regmap_access_table da9061_aa_writeable_table = {
476 .yes_ranges = da9061_aa_writeable_ranges,
477 .n_yes_ranges = ARRAY_SIZE(da9061_aa_writeable_ranges),
478};
479
480static const struct regmap_access_table da9061_aa_volatile_table = {
481 .yes_ranges = da9061_aa_volatile_ranges,
482 .n_yes_ranges = ARRAY_SIZE(da9061_aa_volatile_ranges),
483};
484
485static const struct regmap_range_cfg da9061_range_cfg[] = {
486 {
487 .range_min = DA9062AA_PAGE_CON,
488 .range_max = DA9062AA_CONFIG_ID,
489 .selector_reg = DA9062AA_PAGE_CON,
490 .selector_mask = 1 << DA9062_I2C_PAGE_SEL_SHIFT,
491 .selector_shift = DA9062_I2C_PAGE_SEL_SHIFT,
492 .window_start = 0,
493 .window_len = 256,
494 }
495};
496
497static struct regmap_config da9061_regmap_config = {
498 .reg_bits = 8,
499 .val_bits = 8,
500 .ranges = da9061_range_cfg,
501 .num_ranges = ARRAY_SIZE(da9061_range_cfg),
502 .max_register = DA9062AA_CONFIG_ID,
503 .cache_type = REGCACHE_RBTREE,
504 .rd_table = &da9061_aa_readable_table,
505 .wr_table = &da9061_aa_writeable_table,
506 .volatile_table = &da9061_aa_volatile_table,
507};
508
509static const struct regmap_range da9062_aa_readable_ranges[] = {
510 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
511 regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
512 regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
513 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
514 regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_BUCK4_CONT),
515 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
516 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
517 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
518 regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_SECOND_D),
519 regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
520 regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
521 regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
522 regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_BUCK3_CFG),
523 regmap_reg_range(DA9062AA_VBUCK2_A, DA9062AA_VBUCK4_A),
524 regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
525 regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
526 regmap_reg_range(DA9062AA_VBUCK2_B, DA9062AA_VBUCK4_B),
527 regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
528 regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
529 regmap_reg_range(DA9062AA_BBAT_CONT, DA9062AA_BBAT_CONT),
530 regmap_reg_range(DA9062AA_INTERFACE, DA9062AA_CONFIG_E),
531 regmap_reg_range(DA9062AA_CONFIG_G, DA9062AA_CONFIG_K),
532 regmap_reg_range(DA9062AA_CONFIG_M, DA9062AA_CONFIG_M),
533 regmap_reg_range(DA9062AA_TRIM_CLDR, DA9062AA_GP_ID_19),
534 regmap_reg_range(DA9062AA_DEVICE_ID, DA9062AA_CONFIG_ID),
535};
536
537static const struct regmap_range da9062_aa_writeable_ranges[] = {
538 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_PAGE_CON),
539 regmap_reg_range(DA9062AA_FAULT_LOG, DA9062AA_EVENT_C),
540 regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
541 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
542 regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_BUCK4_CONT),
543 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
544 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
545 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
546 regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_ALARM_Y),
547 regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
548 regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
549 regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
550 regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_BUCK3_CFG),
551 regmap_reg_range(DA9062AA_VBUCK2_A, DA9062AA_VBUCK4_A),
552 regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
553 regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
554 regmap_reg_range(DA9062AA_VBUCK2_B, DA9062AA_VBUCK4_B),
555 regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
556 regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
557 regmap_reg_range(DA9062AA_BBAT_CONT, DA9062AA_BBAT_CONT),
558 regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
559};
560
561static const struct regmap_range da9062_aa_volatile_ranges[] = {
562 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
563 regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
564 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_CONTROL_B),
565 regmap_reg_range(DA9062AA_CONTROL_E, DA9062AA_CONTROL_F),
566 regmap_reg_range(DA9062AA_BUCK2_CONT, DA9062AA_BUCK4_CONT),
567 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
568 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
569 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
570 regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_SECOND_D),
571 regmap_reg_range(DA9062AA_SEQ, DA9062AA_SEQ),
572 regmap_reg_range(DA9062AA_EN_32K, DA9062AA_EN_32K),
573};
574
575static const struct regmap_access_table da9062_aa_readable_table = {
576 .yes_ranges = da9062_aa_readable_ranges,
577 .n_yes_ranges = ARRAY_SIZE(da9062_aa_readable_ranges),
578};
579
580static const struct regmap_access_table da9062_aa_writeable_table = {
581 .yes_ranges = da9062_aa_writeable_ranges,
582 .n_yes_ranges = ARRAY_SIZE(da9062_aa_writeable_ranges),
583};
584
585static const struct regmap_access_table da9062_aa_volatile_table = {
586 .yes_ranges = da9062_aa_volatile_ranges,
587 .n_yes_ranges = ARRAY_SIZE(da9062_aa_volatile_ranges),
588};
589
590static const struct regmap_range_cfg da9062_range_cfg[] = {
591 {
592 .range_min = DA9062AA_PAGE_CON,
593 .range_max = DA9062AA_CONFIG_ID,
594 .selector_reg = DA9062AA_PAGE_CON,
595 .selector_mask = 1 << DA9062_I2C_PAGE_SEL_SHIFT,
596 .selector_shift = DA9062_I2C_PAGE_SEL_SHIFT,
597 .window_start = 0,
598 .window_len = 256,
599 }
600};
601
602static struct regmap_config da9062_regmap_config = {
603 .reg_bits = 8,
604 .val_bits = 8,
605 .ranges = da9062_range_cfg,
606 .num_ranges = ARRAY_SIZE(da9062_range_cfg),
607 .max_register = DA9062AA_CONFIG_ID,
608 .cache_type = REGCACHE_RBTREE,
609 .rd_table = &da9062_aa_readable_table,
610 .wr_table = &da9062_aa_writeable_table,
611 .volatile_table = &da9062_aa_volatile_table,
612};
613
614static const struct of_device_id da9062_dt_ids[] = {
615 { .compatible = "dlg,da9061", .data = (void *)COMPAT_TYPE_DA9061, },
616 { .compatible = "dlg,da9062", .data = (void *)COMPAT_TYPE_DA9062, },
617 { }
618};
619MODULE_DEVICE_TABLE(of, da9062_dt_ids);
620
621static int da9062_i2c_probe(struct i2c_client *i2c,
622 const struct i2c_device_id *id)
623{
624 struct da9062 *chip;
625 const struct of_device_id *match;
626 unsigned int irq_base;
627 const struct mfd_cell *cell;
628 const struct regmap_irq_chip *irq_chip;
629 const struct regmap_config *config;
630 int cell_num;
631 u32 trigger_type = 0;
632 int ret;
633
634 chip = devm_kzalloc(&i2c->dev, sizeof(*chip), GFP_KERNEL);
635 if (!chip)
636 return -ENOMEM;
637
638 if (i2c->dev.of_node) {
639 match = of_match_node(da9062_dt_ids, i2c->dev.of_node);
640 if (!match)
641 return -EINVAL;
642
643 chip->chip_type = (uintptr_t)match->data;
644 } else {
645 chip->chip_type = id->driver_data;
646 }
647
648 i2c_set_clientdata(i2c, chip);
649 chip->dev = &i2c->dev;
650
651 if (!i2c->irq) {
652 dev_err(chip->dev, "No IRQ configured\n");
653 return -EINVAL;
654 }
655
656 switch (chip->chip_type) {
657 case COMPAT_TYPE_DA9061:
658 cell = da9061_devs;
659 cell_num = ARRAY_SIZE(da9061_devs);
660 irq_chip = &da9061_irq_chip;
661 config = &da9061_regmap_config;
662 break;
663 case COMPAT_TYPE_DA9062:
664 cell = da9062_devs;
665 cell_num = ARRAY_SIZE(da9062_devs);
666 irq_chip = &da9062_irq_chip;
667 config = &da9062_regmap_config;
668 break;
669 default:
670 dev_err(chip->dev, "Unrecognised chip type\n");
671 return -ENODEV;
672 }
673
674 chip->regmap = devm_regmap_init_i2c(i2c, config);
675 if (IS_ERR(chip->regmap)) {
676 ret = PTR_ERR(chip->regmap);
677 dev_err(chip->dev, "Failed to allocate register map: %d\n",
678 ret);
679 return ret;
680 }
681
682 ret = da9062_clear_fault_log(chip);
683 if (ret < 0)
684 dev_warn(chip->dev, "Cannot clear fault log\n");
685
686 ret = da9062_get_device_type(chip);
687 if (ret)
688 return ret;
689
690 ret = da9062_configure_irq_type(chip, i2c->irq, &trigger_type);
691 if (ret < 0) {
692 dev_err(chip->dev, "Failed to configure IRQ type\n");
693 return ret;
694 }
695
696 ret = regmap_add_irq_chip(chip->regmap, i2c->irq,
697 trigger_type | IRQF_SHARED | IRQF_ONESHOT,
698 -1, irq_chip, &chip->regmap_irq);
699 if (ret) {
700 dev_err(chip->dev, "Failed to request IRQ %d: %d\n",
701 i2c->irq, ret);
702 return ret;
703 }
704
705 irq_base = regmap_irq_chip_get_base(chip->regmap_irq);
706
707 ret = mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE, cell,
708 cell_num, NULL, irq_base,
709 NULL);
710 if (ret) {
711 dev_err(chip->dev, "Cannot register child devices\n");
712 regmap_del_irq_chip(i2c->irq, chip->regmap_irq);
713 return ret;
714 }
715
716 return ret;
717}
718
719static int da9062_i2c_remove(struct i2c_client *i2c)
720{
721 struct da9062 *chip = i2c_get_clientdata(i2c);
722
723 mfd_remove_devices(chip->dev);
724 regmap_del_irq_chip(i2c->irq, chip->regmap_irq);
725
726 return 0;
727}
728
729static const struct i2c_device_id da9062_i2c_id[] = {
730 { "da9061", COMPAT_TYPE_DA9061 },
731 { "da9062", COMPAT_TYPE_DA9062 },
732 { },
733};
734MODULE_DEVICE_TABLE(i2c, da9062_i2c_id);
735
736static struct i2c_driver da9062_i2c_driver = {
737 .driver = {
738 .name = "da9062",
739 .of_match_table = of_match_ptr(da9062_dt_ids),
740 },
741 .probe = da9062_i2c_probe,
742 .remove = da9062_i2c_remove,
743 .id_table = da9062_i2c_id,
744};
745
746module_i2c_driver(da9062_i2c_driver);
747
748MODULE_DESCRIPTION("Core device driver for Dialog DA9061 and DA9062");
749MODULE_AUTHOR("Steve Twiss <stwiss.opensource@diasemi.com>");
750MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Core, IRQ and I2C device driver for DA9061 and DA9062 PMICs
4 * Copyright (C) 2015-2017 Dialog Semiconductor
5 */
6
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/device.h>
11#include <linux/interrupt.h>
12#include <linux/of_device.h>
13#include <linux/regmap.h>
14#include <linux/irq.h>
15#include <linux/mfd/core.h>
16#include <linux/i2c.h>
17#include <linux/mfd/da9062/core.h>
18#include <linux/mfd/da9062/registers.h>
19#include <linux/regulator/of_regulator.h>
20
21#define DA9062_REG_EVENT_A_OFFSET 0
22#define DA9062_REG_EVENT_B_OFFSET 1
23#define DA9062_REG_EVENT_C_OFFSET 2
24
25#define DA9062_IRQ_LOW 0
26#define DA9062_IRQ_HIGH 1
27
28static struct regmap_irq da9061_irqs[] = {
29 /* EVENT A */
30 [DA9061_IRQ_ONKEY] = {
31 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
32 .mask = DA9062AA_M_NONKEY_MASK,
33 },
34 [DA9061_IRQ_WDG_WARN] = {
35 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
36 .mask = DA9062AA_M_WDG_WARN_MASK,
37 },
38 [DA9061_IRQ_SEQ_RDY] = {
39 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
40 .mask = DA9062AA_M_SEQ_RDY_MASK,
41 },
42 /* EVENT B */
43 [DA9061_IRQ_TEMP] = {
44 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
45 .mask = DA9062AA_M_TEMP_MASK,
46 },
47 [DA9061_IRQ_LDO_LIM] = {
48 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
49 .mask = DA9062AA_M_LDO_LIM_MASK,
50 },
51 [DA9061_IRQ_DVC_RDY] = {
52 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
53 .mask = DA9062AA_M_DVC_RDY_MASK,
54 },
55 [DA9061_IRQ_VDD_WARN] = {
56 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
57 .mask = DA9062AA_M_VDD_WARN_MASK,
58 },
59 /* EVENT C */
60 [DA9061_IRQ_GPI0] = {
61 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
62 .mask = DA9062AA_M_GPI0_MASK,
63 },
64 [DA9061_IRQ_GPI1] = {
65 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
66 .mask = DA9062AA_M_GPI1_MASK,
67 },
68 [DA9061_IRQ_GPI2] = {
69 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
70 .mask = DA9062AA_M_GPI2_MASK,
71 },
72 [DA9061_IRQ_GPI3] = {
73 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
74 .mask = DA9062AA_M_GPI3_MASK,
75 },
76 [DA9061_IRQ_GPI4] = {
77 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
78 .mask = DA9062AA_M_GPI4_MASK,
79 },
80};
81
82static struct regmap_irq_chip da9061_irq_chip = {
83 .name = "da9061-irq",
84 .irqs = da9061_irqs,
85 .num_irqs = DA9061_NUM_IRQ,
86 .num_regs = 3,
87 .status_base = DA9062AA_EVENT_A,
88 .mask_base = DA9062AA_IRQ_MASK_A,
89 .ack_base = DA9062AA_EVENT_A,
90};
91
92static struct regmap_irq da9062_irqs[] = {
93 /* EVENT A */
94 [DA9062_IRQ_ONKEY] = {
95 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
96 .mask = DA9062AA_M_NONKEY_MASK,
97 },
98 [DA9062_IRQ_ALARM] = {
99 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
100 .mask = DA9062AA_M_ALARM_MASK,
101 },
102 [DA9062_IRQ_TICK] = {
103 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
104 .mask = DA9062AA_M_TICK_MASK,
105 },
106 [DA9062_IRQ_WDG_WARN] = {
107 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
108 .mask = DA9062AA_M_WDG_WARN_MASK,
109 },
110 [DA9062_IRQ_SEQ_RDY] = {
111 .reg_offset = DA9062_REG_EVENT_A_OFFSET,
112 .mask = DA9062AA_M_SEQ_RDY_MASK,
113 },
114 /* EVENT B */
115 [DA9062_IRQ_TEMP] = {
116 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
117 .mask = DA9062AA_M_TEMP_MASK,
118 },
119 [DA9062_IRQ_LDO_LIM] = {
120 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
121 .mask = DA9062AA_M_LDO_LIM_MASK,
122 },
123 [DA9062_IRQ_DVC_RDY] = {
124 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
125 .mask = DA9062AA_M_DVC_RDY_MASK,
126 },
127 [DA9062_IRQ_VDD_WARN] = {
128 .reg_offset = DA9062_REG_EVENT_B_OFFSET,
129 .mask = DA9062AA_M_VDD_WARN_MASK,
130 },
131 /* EVENT C */
132 [DA9062_IRQ_GPI0] = {
133 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
134 .mask = DA9062AA_M_GPI0_MASK,
135 },
136 [DA9062_IRQ_GPI1] = {
137 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
138 .mask = DA9062AA_M_GPI1_MASK,
139 },
140 [DA9062_IRQ_GPI2] = {
141 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
142 .mask = DA9062AA_M_GPI2_MASK,
143 },
144 [DA9062_IRQ_GPI3] = {
145 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
146 .mask = DA9062AA_M_GPI3_MASK,
147 },
148 [DA9062_IRQ_GPI4] = {
149 .reg_offset = DA9062_REG_EVENT_C_OFFSET,
150 .mask = DA9062AA_M_GPI4_MASK,
151 },
152};
153
154static struct regmap_irq_chip da9062_irq_chip = {
155 .name = "da9062-irq",
156 .irqs = da9062_irqs,
157 .num_irqs = DA9062_NUM_IRQ,
158 .num_regs = 3,
159 .status_base = DA9062AA_EVENT_A,
160 .mask_base = DA9062AA_IRQ_MASK_A,
161 .ack_base = DA9062AA_EVENT_A,
162};
163
164static const struct resource da9061_core_resources[] = {
165 DEFINE_RES_IRQ_NAMED(DA9061_IRQ_VDD_WARN, "VDD_WARN"),
166};
167
168static const struct resource da9061_regulators_resources[] = {
169 DEFINE_RES_IRQ_NAMED(DA9061_IRQ_LDO_LIM, "LDO_LIM"),
170};
171
172static const struct resource da9061_thermal_resources[] = {
173 DEFINE_RES_IRQ_NAMED(DA9061_IRQ_TEMP, "THERMAL"),
174};
175
176static const struct resource da9061_wdt_resources[] = {
177 DEFINE_RES_IRQ_NAMED(DA9061_IRQ_WDG_WARN, "WD_WARN"),
178};
179
180static const struct resource da9061_onkey_resources[] = {
181 DEFINE_RES_IRQ_NAMED(DA9061_IRQ_ONKEY, "ONKEY"),
182};
183
184static const struct mfd_cell da9061_devs[] = {
185 {
186 .name = "da9061-core",
187 .num_resources = ARRAY_SIZE(da9061_core_resources),
188 .resources = da9061_core_resources,
189 },
190 {
191 .name = "da9062-regulators",
192 .num_resources = ARRAY_SIZE(da9061_regulators_resources),
193 .resources = da9061_regulators_resources,
194 },
195 {
196 .name = "da9061-watchdog",
197 .num_resources = ARRAY_SIZE(da9061_wdt_resources),
198 .resources = da9061_wdt_resources,
199 .of_compatible = "dlg,da9061-watchdog",
200 },
201 {
202 .name = "da9061-thermal",
203 .num_resources = ARRAY_SIZE(da9061_thermal_resources),
204 .resources = da9061_thermal_resources,
205 .of_compatible = "dlg,da9061-thermal",
206 },
207 {
208 .name = "da9061-onkey",
209 .num_resources = ARRAY_SIZE(da9061_onkey_resources),
210 .resources = da9061_onkey_resources,
211 .of_compatible = "dlg,da9061-onkey",
212 },
213};
214
215static const struct resource da9062_core_resources[] = {
216 DEFINE_RES_NAMED(DA9062_IRQ_VDD_WARN, 1, "VDD_WARN", IORESOURCE_IRQ),
217};
218
219static const struct resource da9062_regulators_resources[] = {
220 DEFINE_RES_NAMED(DA9062_IRQ_LDO_LIM, 1, "LDO_LIM", IORESOURCE_IRQ),
221};
222
223static const struct resource da9062_thermal_resources[] = {
224 DEFINE_RES_NAMED(DA9062_IRQ_TEMP, 1, "THERMAL", IORESOURCE_IRQ),
225};
226
227static const struct resource da9062_wdt_resources[] = {
228 DEFINE_RES_NAMED(DA9062_IRQ_WDG_WARN, 1, "WD_WARN", IORESOURCE_IRQ),
229};
230
231static const struct resource da9062_rtc_resources[] = {
232 DEFINE_RES_NAMED(DA9062_IRQ_ALARM, 1, "ALARM", IORESOURCE_IRQ),
233 DEFINE_RES_NAMED(DA9062_IRQ_TICK, 1, "TICK", IORESOURCE_IRQ),
234};
235
236static const struct resource da9062_onkey_resources[] = {
237 DEFINE_RES_NAMED(DA9062_IRQ_ONKEY, 1, "ONKEY", IORESOURCE_IRQ),
238};
239
240static const struct resource da9062_gpio_resources[] = {
241 DEFINE_RES_NAMED(DA9062_IRQ_GPI0, 1, "GPI0", IORESOURCE_IRQ),
242 DEFINE_RES_NAMED(DA9062_IRQ_GPI1, 1, "GPI1", IORESOURCE_IRQ),
243 DEFINE_RES_NAMED(DA9062_IRQ_GPI2, 1, "GPI2", IORESOURCE_IRQ),
244 DEFINE_RES_NAMED(DA9062_IRQ_GPI3, 1, "GPI3", IORESOURCE_IRQ),
245 DEFINE_RES_NAMED(DA9062_IRQ_GPI4, 1, "GPI4", IORESOURCE_IRQ),
246};
247
248static const struct mfd_cell da9062_devs[] = {
249 {
250 .name = "da9062-core",
251 .num_resources = ARRAY_SIZE(da9062_core_resources),
252 .resources = da9062_core_resources,
253 },
254 {
255 .name = "da9062-regulators",
256 .num_resources = ARRAY_SIZE(da9062_regulators_resources),
257 .resources = da9062_regulators_resources,
258 },
259 {
260 .name = "da9062-watchdog",
261 .num_resources = ARRAY_SIZE(da9062_wdt_resources),
262 .resources = da9062_wdt_resources,
263 .of_compatible = "dlg,da9062-watchdog",
264 },
265 {
266 .name = "da9062-thermal",
267 .num_resources = ARRAY_SIZE(da9062_thermal_resources),
268 .resources = da9062_thermal_resources,
269 .of_compatible = "dlg,da9062-thermal",
270 },
271 {
272 .name = "da9062-rtc",
273 .num_resources = ARRAY_SIZE(da9062_rtc_resources),
274 .resources = da9062_rtc_resources,
275 .of_compatible = "dlg,da9062-rtc",
276 },
277 {
278 .name = "da9062-onkey",
279 .num_resources = ARRAY_SIZE(da9062_onkey_resources),
280 .resources = da9062_onkey_resources,
281 .of_compatible = "dlg,da9062-onkey",
282 },
283 {
284 .name = "da9062-gpio",
285 .num_resources = ARRAY_SIZE(da9062_gpio_resources),
286 .resources = da9062_gpio_resources,
287 .of_compatible = "dlg,da9062-gpio",
288 },
289};
290
291static int da9062_clear_fault_log(struct da9062 *chip)
292{
293 int ret;
294 int fault_log;
295
296 ret = regmap_read(chip->regmap, DA9062AA_FAULT_LOG, &fault_log);
297 if (ret < 0)
298 return ret;
299
300 if (fault_log) {
301 if (fault_log & DA9062AA_TWD_ERROR_MASK)
302 dev_dbg(chip->dev, "Fault log entry detected: TWD_ERROR\n");
303 if (fault_log & DA9062AA_POR_MASK)
304 dev_dbg(chip->dev, "Fault log entry detected: POR\n");
305 if (fault_log & DA9062AA_VDD_FAULT_MASK)
306 dev_dbg(chip->dev, "Fault log entry detected: VDD_FAULT\n");
307 if (fault_log & DA9062AA_VDD_START_MASK)
308 dev_dbg(chip->dev, "Fault log entry detected: VDD_START\n");
309 if (fault_log & DA9062AA_TEMP_CRIT_MASK)
310 dev_dbg(chip->dev, "Fault log entry detected: TEMP_CRIT\n");
311 if (fault_log & DA9062AA_KEY_RESET_MASK)
312 dev_dbg(chip->dev, "Fault log entry detected: KEY_RESET\n");
313 if (fault_log & DA9062AA_NSHUTDOWN_MASK)
314 dev_dbg(chip->dev, "Fault log entry detected: NSHUTDOWN\n");
315 if (fault_log & DA9062AA_WAIT_SHUT_MASK)
316 dev_dbg(chip->dev, "Fault log entry detected: WAIT_SHUT\n");
317
318 ret = regmap_write(chip->regmap, DA9062AA_FAULT_LOG,
319 fault_log);
320 }
321
322 return ret;
323}
324
325static int da9062_get_device_type(struct da9062 *chip)
326{
327 int device_id, variant_id, variant_mrc, variant_vrc;
328 char *type;
329 int ret;
330
331 ret = regmap_read(chip->regmap, DA9062AA_DEVICE_ID, &device_id);
332 if (ret < 0) {
333 dev_err(chip->dev, "Cannot read chip ID.\n");
334 return -EIO;
335 }
336 if (device_id != DA9062_PMIC_DEVICE_ID) {
337 dev_err(chip->dev, "Invalid device ID: 0x%02x\n", device_id);
338 return -ENODEV;
339 }
340
341 ret = regmap_read(chip->regmap, DA9062AA_VARIANT_ID, &variant_id);
342 if (ret < 0) {
343 dev_err(chip->dev, "Cannot read chip variant id.\n");
344 return -EIO;
345 }
346
347 variant_vrc = (variant_id & DA9062AA_VRC_MASK) >> DA9062AA_VRC_SHIFT;
348
349 switch (variant_vrc) {
350 case DA9062_PMIC_VARIANT_VRC_DA9061:
351 type = "DA9061";
352 break;
353 case DA9062_PMIC_VARIANT_VRC_DA9062:
354 type = "DA9062";
355 break;
356 default:
357 type = "Unknown";
358 break;
359 }
360
361 dev_info(chip->dev,
362 "Device detected (device-ID: 0x%02X, var-ID: 0x%02X, %s)\n",
363 device_id, variant_id, type);
364
365 variant_mrc = (variant_id & DA9062AA_MRC_MASK) >> DA9062AA_MRC_SHIFT;
366
367 if (variant_mrc < DA9062_PMIC_VARIANT_MRC_AA) {
368 dev_err(chip->dev,
369 "Cannot support variant MRC: 0x%02X\n", variant_mrc);
370 return -ENODEV;
371 }
372
373 return ret;
374}
375
376static u32 da9062_configure_irq_type(struct da9062 *chip, int irq, u32 *trigger)
377{
378 u32 irq_type = 0;
379 struct irq_data *irq_data = irq_get_irq_data(irq);
380
381 if (!irq_data) {
382 dev_err(chip->dev, "Invalid IRQ: %d\n", irq);
383 return -EINVAL;
384 }
385 *trigger = irqd_get_trigger_type(irq_data);
386
387 switch (*trigger) {
388 case IRQ_TYPE_LEVEL_HIGH:
389 irq_type = DA9062_IRQ_HIGH;
390 break;
391 case IRQ_TYPE_LEVEL_LOW:
392 irq_type = DA9062_IRQ_LOW;
393 break;
394 default:
395 dev_warn(chip->dev, "Unsupported IRQ type: %d\n", *trigger);
396 return -EINVAL;
397 }
398 return regmap_update_bits(chip->regmap, DA9062AA_CONFIG_A,
399 DA9062AA_IRQ_TYPE_MASK,
400 irq_type << DA9062AA_IRQ_TYPE_SHIFT);
401}
402
403static const struct regmap_range da9061_aa_readable_ranges[] = {
404 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
405 regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
406 regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
407 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
408 regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_GPIO_OUT3_4),
409 regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
410 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
411 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
412 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
413 regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
414 regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
415 regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
416 regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_WAIT),
417 regmap_reg_range(DA9062AA_RESET, DA9062AA_BUCK_ILIM_C),
418 regmap_reg_range(DA9062AA_BUCK1_CFG, DA9062AA_BUCK3_CFG),
419 regmap_reg_range(DA9062AA_VBUCK1_A, DA9062AA_VBUCK4_A),
420 regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
421 regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
422 regmap_reg_range(DA9062AA_CONFIG_A, DA9062AA_CONFIG_A),
423 regmap_reg_range(DA9062AA_VBUCK1_B, DA9062AA_VBUCK4_B),
424 regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
425 regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
426 regmap_reg_range(DA9062AA_INTERFACE, DA9062AA_CONFIG_E),
427 regmap_reg_range(DA9062AA_CONFIG_G, DA9062AA_CONFIG_K),
428 regmap_reg_range(DA9062AA_CONFIG_M, DA9062AA_CONFIG_M),
429 regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
430 regmap_reg_range(DA9062AA_DEVICE_ID, DA9062AA_CONFIG_ID),
431};
432
433static const struct regmap_range da9061_aa_writeable_ranges[] = {
434 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_PAGE_CON),
435 regmap_reg_range(DA9062AA_FAULT_LOG, DA9062AA_EVENT_C),
436 regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
437 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
438 regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_GPIO_OUT3_4),
439 regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
440 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
441 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
442 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
443 regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
444 regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
445 regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
446 regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_WAIT),
447 regmap_reg_range(DA9062AA_RESET, DA9062AA_BUCK_ILIM_C),
448 regmap_reg_range(DA9062AA_BUCK1_CFG, DA9062AA_BUCK3_CFG),
449 regmap_reg_range(DA9062AA_VBUCK1_A, DA9062AA_VBUCK4_A),
450 regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
451 regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
452 regmap_reg_range(DA9062AA_CONFIG_A, DA9062AA_CONFIG_A),
453 regmap_reg_range(DA9062AA_VBUCK1_B, DA9062AA_VBUCK4_B),
454 regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
455 regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
456 regmap_reg_range(DA9062AA_CONFIG_J, DA9062AA_CONFIG_J),
457 regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
458};
459
460static const struct regmap_range da9061_aa_volatile_ranges[] = {
461 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
462 regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
463 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_CONTROL_B),
464 regmap_reg_range(DA9062AA_CONTROL_E, DA9062AA_CONTROL_F),
465 regmap_reg_range(DA9062AA_BUCK1_CONT, DA9062AA_BUCK4_CONT),
466 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
467 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
468 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
469 regmap_reg_range(DA9062AA_SEQ, DA9062AA_SEQ),
470};
471
472static const struct regmap_access_table da9061_aa_readable_table = {
473 .yes_ranges = da9061_aa_readable_ranges,
474 .n_yes_ranges = ARRAY_SIZE(da9061_aa_readable_ranges),
475};
476
477static const struct regmap_access_table da9061_aa_writeable_table = {
478 .yes_ranges = da9061_aa_writeable_ranges,
479 .n_yes_ranges = ARRAY_SIZE(da9061_aa_writeable_ranges),
480};
481
482static const struct regmap_access_table da9061_aa_volatile_table = {
483 .yes_ranges = da9061_aa_volatile_ranges,
484 .n_yes_ranges = ARRAY_SIZE(da9061_aa_volatile_ranges),
485};
486
487static const struct regmap_range_cfg da9061_range_cfg[] = {
488 {
489 .range_min = DA9062AA_PAGE_CON,
490 .range_max = DA9062AA_CONFIG_ID,
491 .selector_reg = DA9062AA_PAGE_CON,
492 .selector_mask = 1 << DA9062_I2C_PAGE_SEL_SHIFT,
493 .selector_shift = DA9062_I2C_PAGE_SEL_SHIFT,
494 .window_start = 0,
495 .window_len = 256,
496 }
497};
498
499static struct regmap_config da9061_regmap_config = {
500 .reg_bits = 8,
501 .val_bits = 8,
502 .ranges = da9061_range_cfg,
503 .num_ranges = ARRAY_SIZE(da9061_range_cfg),
504 .max_register = DA9062AA_CONFIG_ID,
505 .cache_type = REGCACHE_RBTREE,
506 .rd_table = &da9061_aa_readable_table,
507 .wr_table = &da9061_aa_writeable_table,
508 .volatile_table = &da9061_aa_volatile_table,
509};
510
511static const struct regmap_range da9062_aa_readable_ranges[] = {
512 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
513 regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
514 regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
515 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
516 regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_BUCK4_CONT),
517 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
518 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
519 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
520 regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_SECOND_D),
521 regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
522 regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
523 regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
524 regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_BUCK3_CFG),
525 regmap_reg_range(DA9062AA_VBUCK2_A, DA9062AA_VBUCK4_A),
526 regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
527 regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
528 regmap_reg_range(DA9062AA_VBUCK2_B, DA9062AA_VBUCK4_B),
529 regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
530 regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
531 regmap_reg_range(DA9062AA_BBAT_CONT, DA9062AA_BBAT_CONT),
532 regmap_reg_range(DA9062AA_INTERFACE, DA9062AA_CONFIG_E),
533 regmap_reg_range(DA9062AA_CONFIG_G, DA9062AA_CONFIG_K),
534 regmap_reg_range(DA9062AA_CONFIG_M, DA9062AA_CONFIG_M),
535 regmap_reg_range(DA9062AA_TRIM_CLDR, DA9062AA_GP_ID_19),
536 regmap_reg_range(DA9062AA_DEVICE_ID, DA9062AA_CONFIG_ID),
537};
538
539static const struct regmap_range da9062_aa_writeable_ranges[] = {
540 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_PAGE_CON),
541 regmap_reg_range(DA9062AA_FAULT_LOG, DA9062AA_EVENT_C),
542 regmap_reg_range(DA9062AA_IRQ_MASK_A, DA9062AA_IRQ_MASK_C),
543 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_GPIO_4),
544 regmap_reg_range(DA9062AA_GPIO_WKUP_MODE, DA9062AA_BUCK4_CONT),
545 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
546 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
547 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
548 regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_ALARM_Y),
549 regmap_reg_range(DA9062AA_SEQ, DA9062AA_ID_4_3),
550 regmap_reg_range(DA9062AA_ID_12_11, DA9062AA_ID_16_15),
551 regmap_reg_range(DA9062AA_ID_22_21, DA9062AA_ID_32_31),
552 regmap_reg_range(DA9062AA_SEQ_A, DA9062AA_BUCK3_CFG),
553 regmap_reg_range(DA9062AA_VBUCK2_A, DA9062AA_VBUCK4_A),
554 regmap_reg_range(DA9062AA_VBUCK3_A, DA9062AA_VBUCK3_A),
555 regmap_reg_range(DA9062AA_VLDO1_A, DA9062AA_VLDO4_A),
556 regmap_reg_range(DA9062AA_VBUCK2_B, DA9062AA_VBUCK4_B),
557 regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B),
558 regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B),
559 regmap_reg_range(DA9062AA_BBAT_CONT, DA9062AA_BBAT_CONT),
560 regmap_reg_range(DA9062AA_CONFIG_J, DA9062AA_CONFIG_J),
561 regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19),
562};
563
564static const struct regmap_range da9062_aa_volatile_ranges[] = {
565 regmap_reg_range(DA9062AA_PAGE_CON, DA9062AA_STATUS_B),
566 regmap_reg_range(DA9062AA_STATUS_D, DA9062AA_EVENT_C),
567 regmap_reg_range(DA9062AA_CONTROL_A, DA9062AA_CONTROL_B),
568 regmap_reg_range(DA9062AA_CONTROL_E, DA9062AA_CONTROL_F),
569 regmap_reg_range(DA9062AA_BUCK2_CONT, DA9062AA_BUCK4_CONT),
570 regmap_reg_range(DA9062AA_BUCK3_CONT, DA9062AA_BUCK3_CONT),
571 regmap_reg_range(DA9062AA_LDO1_CONT, DA9062AA_LDO4_CONT),
572 regmap_reg_range(DA9062AA_DVC_1, DA9062AA_DVC_1),
573 regmap_reg_range(DA9062AA_COUNT_S, DA9062AA_SECOND_D),
574 regmap_reg_range(DA9062AA_SEQ, DA9062AA_SEQ),
575 regmap_reg_range(DA9062AA_EN_32K, DA9062AA_EN_32K),
576};
577
578static const struct regmap_access_table da9062_aa_readable_table = {
579 .yes_ranges = da9062_aa_readable_ranges,
580 .n_yes_ranges = ARRAY_SIZE(da9062_aa_readable_ranges),
581};
582
583static const struct regmap_access_table da9062_aa_writeable_table = {
584 .yes_ranges = da9062_aa_writeable_ranges,
585 .n_yes_ranges = ARRAY_SIZE(da9062_aa_writeable_ranges),
586};
587
588static const struct regmap_access_table da9062_aa_volatile_table = {
589 .yes_ranges = da9062_aa_volatile_ranges,
590 .n_yes_ranges = ARRAY_SIZE(da9062_aa_volatile_ranges),
591};
592
593static const struct regmap_range_cfg da9062_range_cfg[] = {
594 {
595 .range_min = DA9062AA_PAGE_CON,
596 .range_max = DA9062AA_CONFIG_ID,
597 .selector_reg = DA9062AA_PAGE_CON,
598 .selector_mask = 1 << DA9062_I2C_PAGE_SEL_SHIFT,
599 .selector_shift = DA9062_I2C_PAGE_SEL_SHIFT,
600 .window_start = 0,
601 .window_len = 256,
602 }
603};
604
605static struct regmap_config da9062_regmap_config = {
606 .reg_bits = 8,
607 .val_bits = 8,
608 .ranges = da9062_range_cfg,
609 .num_ranges = ARRAY_SIZE(da9062_range_cfg),
610 .max_register = DA9062AA_CONFIG_ID,
611 .cache_type = REGCACHE_RBTREE,
612 .rd_table = &da9062_aa_readable_table,
613 .wr_table = &da9062_aa_writeable_table,
614 .volatile_table = &da9062_aa_volatile_table,
615};
616
617static const struct of_device_id da9062_dt_ids[] = {
618 { .compatible = "dlg,da9061", .data = (void *)COMPAT_TYPE_DA9061, },
619 { .compatible = "dlg,da9062", .data = (void *)COMPAT_TYPE_DA9062, },
620 { }
621};
622MODULE_DEVICE_TABLE(of, da9062_dt_ids);
623
624static int da9062_i2c_probe(struct i2c_client *i2c)
625{
626 const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
627 struct da9062 *chip;
628 unsigned int irq_base;
629 const struct mfd_cell *cell;
630 const struct regmap_irq_chip *irq_chip;
631 const struct regmap_config *config;
632 int cell_num;
633 u32 trigger_type = 0;
634 int ret;
635
636 chip = devm_kzalloc(&i2c->dev, sizeof(*chip), GFP_KERNEL);
637 if (!chip)
638 return -ENOMEM;
639
640 if (i2c->dev.of_node)
641 chip->chip_type = (uintptr_t)of_device_get_match_data(&i2c->dev);
642 else
643 chip->chip_type = id->driver_data;
644
645 i2c_set_clientdata(i2c, chip);
646 chip->dev = &i2c->dev;
647
648 if (!i2c->irq) {
649 dev_err(chip->dev, "No IRQ configured\n");
650 return -EINVAL;
651 }
652
653 switch (chip->chip_type) {
654 case COMPAT_TYPE_DA9061:
655 cell = da9061_devs;
656 cell_num = ARRAY_SIZE(da9061_devs);
657 irq_chip = &da9061_irq_chip;
658 config = &da9061_regmap_config;
659 break;
660 case COMPAT_TYPE_DA9062:
661 cell = da9062_devs;
662 cell_num = ARRAY_SIZE(da9062_devs);
663 irq_chip = &da9062_irq_chip;
664 config = &da9062_regmap_config;
665 break;
666 default:
667 dev_err(chip->dev, "Unrecognised chip type\n");
668 return -ENODEV;
669 }
670
671 chip->regmap = devm_regmap_init_i2c(i2c, config);
672 if (IS_ERR(chip->regmap)) {
673 ret = PTR_ERR(chip->regmap);
674 dev_err(chip->dev, "Failed to allocate register map: %d\n",
675 ret);
676 return ret;
677 }
678
679 /* If SMBus is not available and only I2C is possible, enter I2C mode */
680 if (i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) {
681 dev_info(chip->dev, "Entering I2C mode!\n");
682 ret = regmap_clear_bits(chip->regmap, DA9062AA_CONFIG_J,
683 DA9062AA_TWOWIRE_TO_MASK);
684 if (ret < 0) {
685 dev_err(chip->dev, "Failed to set Two-Wire Bus Mode.\n");
686 return ret;
687 }
688 }
689
690 ret = da9062_clear_fault_log(chip);
691 if (ret < 0)
692 dev_warn(chip->dev, "Cannot clear fault log\n");
693
694 ret = da9062_get_device_type(chip);
695 if (ret)
696 return ret;
697
698 ret = da9062_configure_irq_type(chip, i2c->irq, &trigger_type);
699 if (ret < 0) {
700 dev_err(chip->dev, "Failed to configure IRQ type\n");
701 return ret;
702 }
703
704 ret = regmap_add_irq_chip(chip->regmap, i2c->irq,
705 trigger_type | IRQF_SHARED | IRQF_ONESHOT,
706 -1, irq_chip, &chip->regmap_irq);
707 if (ret) {
708 dev_err(chip->dev, "Failed to request IRQ %d: %d\n",
709 i2c->irq, ret);
710 return ret;
711 }
712
713 irq_base = regmap_irq_chip_get_base(chip->regmap_irq);
714
715 ret = mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE, cell,
716 cell_num, NULL, irq_base,
717 NULL);
718 if (ret) {
719 dev_err(chip->dev, "Cannot register child devices\n");
720 regmap_del_irq_chip(i2c->irq, chip->regmap_irq);
721 return ret;
722 }
723
724 return ret;
725}
726
727static void da9062_i2c_remove(struct i2c_client *i2c)
728{
729 struct da9062 *chip = i2c_get_clientdata(i2c);
730
731 mfd_remove_devices(chip->dev);
732 regmap_del_irq_chip(i2c->irq, chip->regmap_irq);
733}
734
735static const struct i2c_device_id da9062_i2c_id[] = {
736 { "da9061", COMPAT_TYPE_DA9061 },
737 { "da9062", COMPAT_TYPE_DA9062 },
738 { },
739};
740MODULE_DEVICE_TABLE(i2c, da9062_i2c_id);
741
742static struct i2c_driver da9062_i2c_driver = {
743 .driver = {
744 .name = "da9062",
745 .of_match_table = da9062_dt_ids,
746 },
747 .probe_new = da9062_i2c_probe,
748 .remove = da9062_i2c_remove,
749 .id_table = da9062_i2c_id,
750};
751
752module_i2c_driver(da9062_i2c_driver);
753
754MODULE_DESCRIPTION("Core device driver for Dialog DA9061 and DA9062");
755MODULE_AUTHOR("Steve Twiss <stwiss.opensource@diasemi.com>");
756MODULE_LICENSE("GPL");