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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Unisoc IOMMU driver
4 *
5 * Copyright (C) 2020 Unisoc, Inc.
6 * Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/device.h>
11#include <linux/dma-mapping.h>
12#include <linux/errno.h>
13#include <linux/iommu.h>
14#include <linux/mfd/syscon.h>
15#include <linux/module.h>
16#include <linux/of_platform.h>
17#include <linux/regmap.h>
18#include <linux/slab.h>
19
20#define SPRD_IOMMU_PAGE_SHIFT 12
21#define SPRD_IOMMU_PAGE_SIZE SZ_4K
22
23#define SPRD_EX_CFG 0x0
24#define SPRD_IOMMU_VAOR_BYPASS BIT(4)
25#define SPRD_IOMMU_GATE_EN BIT(1)
26#define SPRD_IOMMU_EN BIT(0)
27#define SPRD_EX_UPDATE 0x4
28#define SPRD_EX_FIRST_VPN 0x8
29#define SPRD_EX_VPN_RANGE 0xc
30#define SPRD_EX_FIRST_PPN 0x10
31#define SPRD_EX_DEFAULT_PPN 0x14
32
33#define SPRD_IOMMU_VERSION 0x0
34#define SPRD_VERSION_MASK GENMASK(15, 8)
35#define SPRD_VERSION_SHIFT 0x8
36#define SPRD_VAU_CFG 0x4
37#define SPRD_VAU_UPDATE 0x8
38#define SPRD_VAU_AUTH_CFG 0xc
39#define SPRD_VAU_FIRST_PPN 0x10
40#define SPRD_VAU_DEFAULT_PPN_RD 0x14
41#define SPRD_VAU_DEFAULT_PPN_WR 0x18
42#define SPRD_VAU_FIRST_VPN 0x1c
43#define SPRD_VAU_VPN_RANGE 0x20
44
45enum sprd_iommu_version {
46 SPRD_IOMMU_EX,
47 SPRD_IOMMU_VAU,
48};
49
50/*
51 * struct sprd_iommu_device - high-level sprd IOMMU device representation,
52 * including hardware information and configuration, also driver data, etc
53 *
54 * @ver: sprd IOMMU IP version
55 * @prot_page_va: protect page base virtual address
56 * @prot_page_pa: protect page base physical address, data would be
57 * written to here while translation fault
58 * @base: mapped base address for accessing registers
59 * @dev: pointer to basic device structure
60 * @iommu: IOMMU core representation
61 * @group: IOMMU group
62 * @eb: gate clock which controls IOMMU access
63 */
64struct sprd_iommu_device {
65 enum sprd_iommu_version ver;
66 u32 *prot_page_va;
67 dma_addr_t prot_page_pa;
68 void __iomem *base;
69 struct device *dev;
70 struct iommu_device iommu;
71 struct iommu_group *group;
72 struct clk *eb;
73};
74
75struct sprd_iommu_domain {
76 spinlock_t pgtlock; /* lock for page table */
77 struct iommu_domain domain;
78 u32 *pgt_va; /* page table virtual address base */
79 dma_addr_t pgt_pa; /* page table physical address base */
80 struct sprd_iommu_device *sdev;
81};
82
83static const struct iommu_ops sprd_iommu_ops;
84
85static struct sprd_iommu_domain *to_sprd_domain(struct iommu_domain *dom)
86{
87 return container_of(dom, struct sprd_iommu_domain, domain);
88}
89
90static inline void
91sprd_iommu_write(struct sprd_iommu_device *sdev, unsigned int reg, u32 val)
92{
93 writel_relaxed(val, sdev->base + reg);
94}
95
96static inline u32
97sprd_iommu_read(struct sprd_iommu_device *sdev, unsigned int reg)
98{
99 return readl_relaxed(sdev->base + reg);
100}
101
102static inline void
103sprd_iommu_update_bits(struct sprd_iommu_device *sdev, unsigned int reg,
104 u32 mask, u32 shift, u32 val)
105{
106 u32 t = sprd_iommu_read(sdev, reg);
107
108 t = (t & (~(mask << shift))) | ((val & mask) << shift);
109 sprd_iommu_write(sdev, reg, t);
110}
111
112static inline int
113sprd_iommu_get_version(struct sprd_iommu_device *sdev)
114{
115 int ver = (sprd_iommu_read(sdev, SPRD_IOMMU_VERSION) &
116 SPRD_VERSION_MASK) >> SPRD_VERSION_SHIFT;
117
118 switch (ver) {
119 case SPRD_IOMMU_EX:
120 case SPRD_IOMMU_VAU:
121 return ver;
122 default:
123 return -EINVAL;
124 }
125}
126
127static size_t
128sprd_iommu_pgt_size(struct iommu_domain *domain)
129{
130 return ((domain->geometry.aperture_end -
131 domain->geometry.aperture_start + 1) >>
132 SPRD_IOMMU_PAGE_SHIFT) * sizeof(u32);
133}
134
135static struct iommu_domain *sprd_iommu_domain_alloc(unsigned int domain_type)
136{
137 struct sprd_iommu_domain *dom;
138
139 if (domain_type != IOMMU_DOMAIN_DMA && domain_type != IOMMU_DOMAIN_UNMANAGED)
140 return NULL;
141
142 dom = kzalloc(sizeof(*dom), GFP_KERNEL);
143 if (!dom)
144 return NULL;
145
146 spin_lock_init(&dom->pgtlock);
147
148 dom->domain.geometry.aperture_start = 0;
149 dom->domain.geometry.aperture_end = SZ_256M - 1;
150
151 return &dom->domain;
152}
153
154static void sprd_iommu_domain_free(struct iommu_domain *domain)
155{
156 struct sprd_iommu_domain *dom = to_sprd_domain(domain);
157
158 kfree(dom);
159}
160
161static void sprd_iommu_first_vpn(struct sprd_iommu_domain *dom)
162{
163 struct sprd_iommu_device *sdev = dom->sdev;
164 u32 val;
165 unsigned int reg;
166
167 if (sdev->ver == SPRD_IOMMU_EX)
168 reg = SPRD_EX_FIRST_VPN;
169 else
170 reg = SPRD_VAU_FIRST_VPN;
171
172 val = dom->domain.geometry.aperture_start >> SPRD_IOMMU_PAGE_SHIFT;
173 sprd_iommu_write(sdev, reg, val);
174}
175
176static void sprd_iommu_vpn_range(struct sprd_iommu_domain *dom)
177{
178 struct sprd_iommu_device *sdev = dom->sdev;
179 u32 val;
180 unsigned int reg;
181
182 if (sdev->ver == SPRD_IOMMU_EX)
183 reg = SPRD_EX_VPN_RANGE;
184 else
185 reg = SPRD_VAU_VPN_RANGE;
186
187 val = (dom->domain.geometry.aperture_end -
188 dom->domain.geometry.aperture_start) >> SPRD_IOMMU_PAGE_SHIFT;
189 sprd_iommu_write(sdev, reg, val);
190}
191
192static void sprd_iommu_first_ppn(struct sprd_iommu_domain *dom)
193{
194 u32 val = dom->pgt_pa >> SPRD_IOMMU_PAGE_SHIFT;
195 struct sprd_iommu_device *sdev = dom->sdev;
196 unsigned int reg;
197
198 if (sdev->ver == SPRD_IOMMU_EX)
199 reg = SPRD_EX_FIRST_PPN;
200 else
201 reg = SPRD_VAU_FIRST_PPN;
202
203 sprd_iommu_write(sdev, reg, val);
204}
205
206static void sprd_iommu_default_ppn(struct sprd_iommu_device *sdev)
207{
208 u32 val = sdev->prot_page_pa >> SPRD_IOMMU_PAGE_SHIFT;
209
210 if (sdev->ver == SPRD_IOMMU_EX) {
211 sprd_iommu_write(sdev, SPRD_EX_DEFAULT_PPN, val);
212 } else if (sdev->ver == SPRD_IOMMU_VAU) {
213 sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_RD, val);
214 sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_WR, val);
215 }
216}
217
218static void sprd_iommu_hw_en(struct sprd_iommu_device *sdev, bool en)
219{
220 unsigned int reg_cfg;
221 u32 mask, val;
222
223 if (sdev->ver == SPRD_IOMMU_EX)
224 reg_cfg = SPRD_EX_CFG;
225 else
226 reg_cfg = SPRD_VAU_CFG;
227
228 mask = SPRD_IOMMU_EN | SPRD_IOMMU_GATE_EN;
229 val = en ? mask : 0;
230 sprd_iommu_update_bits(sdev, reg_cfg, mask, 0, val);
231}
232
233static int sprd_iommu_attach_device(struct iommu_domain *domain,
234 struct device *dev)
235{
236 struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev);
237 struct sprd_iommu_domain *dom = to_sprd_domain(domain);
238 size_t pgt_size = sprd_iommu_pgt_size(domain);
239
240 if (dom->sdev)
241 return -EINVAL;
242
243 dom->pgt_va = dma_alloc_coherent(sdev->dev, pgt_size, &dom->pgt_pa, GFP_KERNEL);
244 if (!dom->pgt_va)
245 return -ENOMEM;
246
247 dom->sdev = sdev;
248
249 sprd_iommu_first_ppn(dom);
250 sprd_iommu_first_vpn(dom);
251 sprd_iommu_vpn_range(dom);
252 sprd_iommu_default_ppn(sdev);
253 sprd_iommu_hw_en(sdev, true);
254
255 return 0;
256}
257
258static void sprd_iommu_detach_device(struct iommu_domain *domain,
259 struct device *dev)
260{
261 struct sprd_iommu_domain *dom = to_sprd_domain(domain);
262 struct sprd_iommu_device *sdev = dom->sdev;
263 size_t pgt_size = sprd_iommu_pgt_size(domain);
264
265 if (!sdev)
266 return;
267
268 dma_free_coherent(sdev->dev, pgt_size, dom->pgt_va, dom->pgt_pa);
269 sprd_iommu_hw_en(sdev, false);
270 dom->sdev = NULL;
271}
272
273static int sprd_iommu_map(struct iommu_domain *domain, unsigned long iova,
274 phys_addr_t paddr, size_t pgsize, size_t pgcount,
275 int prot, gfp_t gfp, size_t *mapped)
276{
277 struct sprd_iommu_domain *dom = to_sprd_domain(domain);
278 size_t size = pgcount * SPRD_IOMMU_PAGE_SIZE;
279 unsigned long flags;
280 unsigned int i;
281 u32 *pgt_base_iova;
282 u32 pabase = (u32)paddr;
283 unsigned long start = domain->geometry.aperture_start;
284 unsigned long end = domain->geometry.aperture_end;
285
286 if (!dom->sdev) {
287 pr_err("No sprd_iommu_device attached to the domain\n");
288 return -EINVAL;
289 }
290
291 if (iova < start || (iova + size) > (end + 1)) {
292 dev_err(dom->sdev->dev, "(iova(0x%lx) + size(%zx)) are not in the range!\n",
293 iova, size);
294 return -EINVAL;
295 }
296
297 pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT);
298
299 spin_lock_irqsave(&dom->pgtlock, flags);
300 for (i = 0; i < pgcount; i++) {
301 pgt_base_iova[i] = pabase >> SPRD_IOMMU_PAGE_SHIFT;
302 pabase += SPRD_IOMMU_PAGE_SIZE;
303 }
304 spin_unlock_irqrestore(&dom->pgtlock, flags);
305
306 *mapped = size;
307 return 0;
308}
309
310static size_t sprd_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
311 size_t pgsize, size_t pgcount,
312 struct iommu_iotlb_gather *iotlb_gather)
313{
314 struct sprd_iommu_domain *dom = to_sprd_domain(domain);
315 unsigned long flags;
316 u32 *pgt_base_iova;
317 size_t size = pgcount * SPRD_IOMMU_PAGE_SIZE;
318 unsigned long start = domain->geometry.aperture_start;
319 unsigned long end = domain->geometry.aperture_end;
320
321 if (iova < start || (iova + size) > (end + 1))
322 return 0;
323
324 pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT);
325
326 spin_lock_irqsave(&dom->pgtlock, flags);
327 memset(pgt_base_iova, 0, pgcount * sizeof(u32));
328 spin_unlock_irqrestore(&dom->pgtlock, flags);
329
330 return size;
331}
332
333static void sprd_iommu_sync_map(struct iommu_domain *domain,
334 unsigned long iova, size_t size)
335{
336 struct sprd_iommu_domain *dom = to_sprd_domain(domain);
337 unsigned int reg;
338
339 if (dom->sdev->ver == SPRD_IOMMU_EX)
340 reg = SPRD_EX_UPDATE;
341 else
342 reg = SPRD_VAU_UPDATE;
343
344 /* clear IOMMU TLB buffer after page table updated */
345 sprd_iommu_write(dom->sdev, reg, 0xffffffff);
346}
347
348static void sprd_iommu_sync(struct iommu_domain *domain,
349 struct iommu_iotlb_gather *iotlb_gather)
350{
351 sprd_iommu_sync_map(domain, 0, 0);
352}
353
354static phys_addr_t sprd_iommu_iova_to_phys(struct iommu_domain *domain,
355 dma_addr_t iova)
356{
357 struct sprd_iommu_domain *dom = to_sprd_domain(domain);
358 unsigned long flags;
359 phys_addr_t pa;
360 unsigned long start = domain->geometry.aperture_start;
361 unsigned long end = domain->geometry.aperture_end;
362
363 if (WARN_ON(iova < start || iova > end))
364 return 0;
365
366 spin_lock_irqsave(&dom->pgtlock, flags);
367 pa = *(dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT));
368 pa = (pa << SPRD_IOMMU_PAGE_SHIFT) + ((iova - start) & (SPRD_IOMMU_PAGE_SIZE - 1));
369 spin_unlock_irqrestore(&dom->pgtlock, flags);
370
371 return pa;
372}
373
374static struct iommu_device *sprd_iommu_probe_device(struct device *dev)
375{
376 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
377 struct sprd_iommu_device *sdev;
378
379 if (!fwspec || fwspec->ops != &sprd_iommu_ops)
380 return ERR_PTR(-ENODEV);
381
382 sdev = dev_iommu_priv_get(dev);
383
384 return &sdev->iommu;
385}
386
387static struct iommu_group *sprd_iommu_device_group(struct device *dev)
388{
389 struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev);
390
391 return iommu_group_ref_get(sdev->group);
392}
393
394static int sprd_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
395{
396 struct platform_device *pdev;
397
398 if (!dev_iommu_priv_get(dev)) {
399 pdev = of_find_device_by_node(args->np);
400 dev_iommu_priv_set(dev, platform_get_drvdata(pdev));
401 platform_device_put(pdev);
402 }
403
404 return 0;
405}
406
407
408static const struct iommu_ops sprd_iommu_ops = {
409 .domain_alloc = sprd_iommu_domain_alloc,
410 .probe_device = sprd_iommu_probe_device,
411 .device_group = sprd_iommu_device_group,
412 .of_xlate = sprd_iommu_of_xlate,
413 .pgsize_bitmap = SPRD_IOMMU_PAGE_SIZE,
414 .owner = THIS_MODULE,
415 .default_domain_ops = &(const struct iommu_domain_ops) {
416 .attach_dev = sprd_iommu_attach_device,
417 .detach_dev = sprd_iommu_detach_device,
418 .map_pages = sprd_iommu_map,
419 .unmap_pages = sprd_iommu_unmap,
420 .iotlb_sync_map = sprd_iommu_sync_map,
421 .iotlb_sync = sprd_iommu_sync,
422 .iova_to_phys = sprd_iommu_iova_to_phys,
423 .free = sprd_iommu_domain_free,
424 }
425};
426
427static const struct of_device_id sprd_iommu_of_match[] = {
428 { .compatible = "sprd,iommu-v1" },
429 { },
430};
431MODULE_DEVICE_TABLE(of, sprd_iommu_of_match);
432
433/*
434 * Clock is not required, access to some of IOMMUs is controlled by gate
435 * clk, enabled clocks for that kind of IOMMUs before accessing.
436 * Return 0 for success or no clocks found.
437 */
438static int sprd_iommu_clk_enable(struct sprd_iommu_device *sdev)
439{
440 struct clk *eb;
441
442 eb = devm_clk_get_optional(sdev->dev, NULL);
443 if (!eb)
444 return 0;
445
446 if (IS_ERR(eb))
447 return PTR_ERR(eb);
448
449 sdev->eb = eb;
450 return clk_prepare_enable(eb);
451}
452
453static void sprd_iommu_clk_disable(struct sprd_iommu_device *sdev)
454{
455 if (sdev->eb)
456 clk_disable_unprepare(sdev->eb);
457}
458
459static int sprd_iommu_probe(struct platform_device *pdev)
460{
461 struct sprd_iommu_device *sdev;
462 struct device *dev = &pdev->dev;
463 void __iomem *base;
464 int ret;
465
466 sdev = devm_kzalloc(dev, sizeof(*sdev), GFP_KERNEL);
467 if (!sdev)
468 return -ENOMEM;
469
470 base = devm_platform_ioremap_resource(pdev, 0);
471 if (IS_ERR(base)) {
472 dev_err(dev, "Failed to get ioremap resource.\n");
473 return PTR_ERR(base);
474 }
475 sdev->base = base;
476
477 sdev->prot_page_va = dma_alloc_coherent(dev, SPRD_IOMMU_PAGE_SIZE,
478 &sdev->prot_page_pa, GFP_KERNEL);
479 if (!sdev->prot_page_va)
480 return -ENOMEM;
481
482 platform_set_drvdata(pdev, sdev);
483 sdev->dev = dev;
484
485 /* All the client devices are in the same iommu-group */
486 sdev->group = iommu_group_alloc();
487 if (IS_ERR(sdev->group)) {
488 ret = PTR_ERR(sdev->group);
489 goto free_page;
490 }
491
492 ret = iommu_device_sysfs_add(&sdev->iommu, dev, NULL, dev_name(dev));
493 if (ret)
494 goto put_group;
495
496 ret = iommu_device_register(&sdev->iommu, &sprd_iommu_ops, dev);
497 if (ret)
498 goto remove_sysfs;
499
500 ret = sprd_iommu_clk_enable(sdev);
501 if (ret)
502 goto unregister_iommu;
503
504 ret = sprd_iommu_get_version(sdev);
505 if (ret < 0) {
506 dev_err(dev, "IOMMU version(%d) is invalid.\n", ret);
507 goto disable_clk;
508 }
509 sdev->ver = ret;
510
511 return 0;
512
513disable_clk:
514 sprd_iommu_clk_disable(sdev);
515unregister_iommu:
516 iommu_device_unregister(&sdev->iommu);
517remove_sysfs:
518 iommu_device_sysfs_remove(&sdev->iommu);
519put_group:
520 iommu_group_put(sdev->group);
521free_page:
522 dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa);
523 return ret;
524}
525
526static int sprd_iommu_remove(struct platform_device *pdev)
527{
528 struct sprd_iommu_device *sdev = platform_get_drvdata(pdev);
529
530 dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa);
531
532 iommu_group_put(sdev->group);
533 sdev->group = NULL;
534
535 platform_set_drvdata(pdev, NULL);
536 iommu_device_sysfs_remove(&sdev->iommu);
537 iommu_device_unregister(&sdev->iommu);
538
539 return 0;
540}
541
542static struct platform_driver sprd_iommu_driver = {
543 .driver = {
544 .name = "sprd-iommu",
545 .of_match_table = sprd_iommu_of_match,
546 .suppress_bind_attrs = true,
547 },
548 .probe = sprd_iommu_probe,
549 .remove = sprd_iommu_remove,
550};
551module_platform_driver(sprd_iommu_driver);
552
553MODULE_DESCRIPTION("IOMMU driver for Unisoc SoCs");
554MODULE_ALIAS("platform:sprd-iommu");
555MODULE_LICENSE("GPL");