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1/*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26#ifndef VIRTIO_DRV_H
27#define VIRTIO_DRV_H
28
29#include <linux/virtio.h>
30#include <linux/virtio_ids.h>
31#include <linux/virtio_config.h>
32#include <linux/virtio_gpu.h>
33
34#include <drm/drm_atomic.h>
35#include <drm/drm_drv.h>
36#include <drm/drm_encoder.h>
37#include <drm/drm_fb_helper.h>
38#include <drm/drm_gem.h>
39#include <drm/drm_gem_shmem_helper.h>
40#include <drm/drm_ioctl.h>
41#include <drm/drm_probe_helper.h>
42#include <drm/virtgpu_drm.h>
43
44#define DRIVER_NAME "virtio_gpu"
45#define DRIVER_DESC "virtio GPU"
46#define DRIVER_DATE "0"
47
48#define DRIVER_MAJOR 0
49#define DRIVER_MINOR 1
50#define DRIVER_PATCHLEVEL 0
51
52struct virtio_gpu_object_params {
53 uint32_t format;
54 uint32_t width;
55 uint32_t height;
56 unsigned long size;
57 bool dumb;
58 /* 3d */
59 bool virgl;
60 uint32_t target;
61 uint32_t bind;
62 uint32_t depth;
63 uint32_t array_size;
64 uint32_t last_level;
65 uint32_t nr_samples;
66 uint32_t flags;
67};
68
69struct virtio_gpu_object {
70 struct drm_gem_shmem_object base;
71 uint32_t hw_res_handle;
72 bool dumb;
73 bool created;
74};
75#define gem_to_virtio_gpu_obj(gobj) \
76 container_of((gobj), struct virtio_gpu_object, base.base)
77
78struct virtio_gpu_object_shmem {
79 struct virtio_gpu_object base;
80 struct sg_table *pages;
81 uint32_t mapped;
82};
83
84#define to_virtio_gpu_shmem(virtio_gpu_object) \
85 container_of((virtio_gpu_object), struct virtio_gpu_object_shmem, base)
86
87struct virtio_gpu_object_array {
88 struct ww_acquire_ctx ticket;
89 struct list_head next;
90 u32 nents, total;
91 struct drm_gem_object *objs[];
92};
93
94struct virtio_gpu_vbuffer;
95struct virtio_gpu_device;
96
97typedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *vgdev,
98 struct virtio_gpu_vbuffer *vbuf);
99
100struct virtio_gpu_fence_driver {
101 atomic64_t last_seq;
102 uint64_t sync_seq;
103 uint64_t context;
104 struct list_head fences;
105 spinlock_t lock;
106};
107
108struct virtio_gpu_fence {
109 struct dma_fence f;
110 struct virtio_gpu_fence_driver *drv;
111 struct list_head node;
112};
113
114struct virtio_gpu_vbuffer {
115 char *buf;
116 int size;
117
118 void *data_buf;
119 uint32_t data_size;
120
121 char *resp_buf;
122 int resp_size;
123 virtio_gpu_resp_cb resp_cb;
124 void *resp_cb_data;
125
126 struct virtio_gpu_object_array *objs;
127 struct list_head list;
128};
129
130struct virtio_gpu_output {
131 int index;
132 struct drm_crtc crtc;
133 struct drm_connector conn;
134 struct drm_encoder enc;
135 struct virtio_gpu_display_one info;
136 struct virtio_gpu_update_cursor cursor;
137 struct edid *edid;
138 int cur_x;
139 int cur_y;
140 bool needs_modeset;
141};
142#define drm_crtc_to_virtio_gpu_output(x) \
143 container_of(x, struct virtio_gpu_output, crtc)
144
145struct virtio_gpu_framebuffer {
146 struct drm_framebuffer base;
147 struct virtio_gpu_fence *fence;
148};
149#define to_virtio_gpu_framebuffer(x) \
150 container_of(x, struct virtio_gpu_framebuffer, base)
151
152struct virtio_gpu_queue {
153 struct virtqueue *vq;
154 spinlock_t qlock;
155 wait_queue_head_t ack_queue;
156 struct work_struct dequeue_work;
157};
158
159struct virtio_gpu_drv_capset {
160 uint32_t id;
161 uint32_t max_version;
162 uint32_t max_size;
163};
164
165struct virtio_gpu_drv_cap_cache {
166 struct list_head head;
167 void *caps_cache;
168 uint32_t id;
169 uint32_t version;
170 uint32_t size;
171 atomic_t is_valid;
172};
173
174struct virtio_gpu_device {
175 struct device *dev;
176 struct drm_device *ddev;
177
178 struct virtio_device *vdev;
179
180 struct virtio_gpu_output outputs[VIRTIO_GPU_MAX_SCANOUTS];
181 uint32_t num_scanouts;
182
183 struct virtio_gpu_queue ctrlq;
184 struct virtio_gpu_queue cursorq;
185 struct kmem_cache *vbufs;
186
187 atomic_t pending_commands;
188
189 struct ida resource_ida;
190
191 wait_queue_head_t resp_wq;
192 /* current display info */
193 spinlock_t display_info_lock;
194 bool display_info_pending;
195
196 struct virtio_gpu_fence_driver fence_drv;
197
198 struct ida ctx_id_ida;
199
200 bool has_virgl_3d;
201 bool has_edid;
202 bool has_indirect;
203
204 struct work_struct config_changed_work;
205
206 struct work_struct obj_free_work;
207 spinlock_t obj_free_lock;
208 struct list_head obj_free_list;
209
210 struct virtio_gpu_drv_capset *capsets;
211 uint32_t num_capsets;
212 struct list_head cap_cache;
213};
214
215struct virtio_gpu_fpriv {
216 uint32_t ctx_id;
217 bool context_created;
218 struct mutex context_lock;
219};
220
221/* virtgpu_ioctl.c */
222#define DRM_VIRTIO_NUM_IOCTLS 10
223extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS];
224void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file);
225
226/* virtgpu_kms.c */
227int virtio_gpu_init(struct drm_device *dev);
228void virtio_gpu_deinit(struct drm_device *dev);
229void virtio_gpu_release(struct drm_device *dev);
230int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file);
231void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file);
232
233/* virtgpu_gem.c */
234int virtio_gpu_gem_object_open(struct drm_gem_object *obj,
235 struct drm_file *file);
236void virtio_gpu_gem_object_close(struct drm_gem_object *obj,
237 struct drm_file *file);
238int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
239 struct drm_device *dev,
240 struct drm_mode_create_dumb *args);
241int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv,
242 struct drm_device *dev,
243 uint32_t handle, uint64_t *offset_p);
244
245struct virtio_gpu_object_array *virtio_gpu_array_alloc(u32 nents);
246struct virtio_gpu_object_array*
247virtio_gpu_array_from_handles(struct drm_file *drm_file, u32 *handles, u32 nents);
248void virtio_gpu_array_add_obj(struct virtio_gpu_object_array *objs,
249 struct drm_gem_object *obj);
250int virtio_gpu_array_lock_resv(struct virtio_gpu_object_array *objs);
251void virtio_gpu_array_unlock_resv(struct virtio_gpu_object_array *objs);
252void virtio_gpu_array_add_fence(struct virtio_gpu_object_array *objs,
253 struct dma_fence *fence);
254void virtio_gpu_array_put_free(struct virtio_gpu_object_array *objs);
255void virtio_gpu_array_put_free_delayed(struct virtio_gpu_device *vgdev,
256 struct virtio_gpu_object_array *objs);
257void virtio_gpu_array_put_free_work(struct work_struct *work);
258
259/* virtgpu_vq.c */
260int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev);
261void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev);
262void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
263 struct virtio_gpu_object *bo,
264 struct virtio_gpu_object_params *params,
265 struct virtio_gpu_object_array *objs,
266 struct virtio_gpu_fence *fence);
267void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
268 struct virtio_gpu_object *bo);
269void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
270 uint64_t offset,
271 uint32_t width, uint32_t height,
272 uint32_t x, uint32_t y,
273 struct virtio_gpu_object_array *objs,
274 struct virtio_gpu_fence *fence);
275void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
276 uint32_t resource_id,
277 uint32_t x, uint32_t y,
278 uint32_t width, uint32_t height);
279void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
280 uint32_t scanout_id, uint32_t resource_id,
281 uint32_t width, uint32_t height,
282 uint32_t x, uint32_t y);
283void virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
284 struct virtio_gpu_object *obj,
285 struct virtio_gpu_mem_entry *ents,
286 unsigned int nents);
287int virtio_gpu_attach_status_page(struct virtio_gpu_device *vgdev);
288int virtio_gpu_detach_status_page(struct virtio_gpu_device *vgdev);
289void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
290 struct virtio_gpu_output *output);
291int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev);
292int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx);
293int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
294 int idx, int version,
295 struct virtio_gpu_drv_cap_cache **cache_p);
296int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev);
297void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
298 uint32_t nlen, const char *name);
299void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
300 uint32_t id);
301void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
302 uint32_t ctx_id,
303 struct virtio_gpu_object_array *objs);
304void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
305 uint32_t ctx_id,
306 struct virtio_gpu_object_array *objs);
307void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
308 void *data, uint32_t data_size,
309 uint32_t ctx_id,
310 struct virtio_gpu_object_array *objs,
311 struct virtio_gpu_fence *fence);
312void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
313 uint32_t ctx_id,
314 uint64_t offset, uint32_t level,
315 struct drm_virtgpu_3d_box *box,
316 struct virtio_gpu_object_array *objs,
317 struct virtio_gpu_fence *fence);
318void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
319 uint32_t ctx_id,
320 uint64_t offset, uint32_t level,
321 struct drm_virtgpu_3d_box *box,
322 struct virtio_gpu_object_array *objs,
323 struct virtio_gpu_fence *fence);
324void
325virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
326 struct virtio_gpu_object *bo,
327 struct virtio_gpu_object_params *params,
328 struct virtio_gpu_object_array *objs,
329 struct virtio_gpu_fence *fence);
330void virtio_gpu_ctrl_ack(struct virtqueue *vq);
331void virtio_gpu_cursor_ack(struct virtqueue *vq);
332void virtio_gpu_fence_ack(struct virtqueue *vq);
333void virtio_gpu_dequeue_ctrl_func(struct work_struct *work);
334void virtio_gpu_dequeue_cursor_func(struct work_struct *work);
335void virtio_gpu_dequeue_fence_func(struct work_struct *work);
336
337void virtio_gpu_notify(struct virtio_gpu_device *vgdev);
338
339/* virtgpu_display.c */
340void virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev);
341void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev);
342
343/* virtgpu_plane.c */
344uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc);
345struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
346 enum drm_plane_type type,
347 int index);
348
349/* virtgpu_fence.c */
350struct virtio_gpu_fence *virtio_gpu_fence_alloc(
351 struct virtio_gpu_device *vgdev);
352void virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev,
353 struct virtio_gpu_ctrl_hdr *cmd_hdr,
354 struct virtio_gpu_fence *fence);
355void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev,
356 u64 last_seq);
357
358/* virtgpu_object.c */
359void virtio_gpu_cleanup_object(struct virtio_gpu_object *bo);
360struct drm_gem_object *virtio_gpu_create_object(struct drm_device *dev,
361 size_t size);
362int virtio_gpu_object_create(struct virtio_gpu_device *vgdev,
363 struct virtio_gpu_object_params *params,
364 struct virtio_gpu_object **bo_ptr,
365 struct virtio_gpu_fence *fence);
366
367bool virtio_gpu_is_shmem(struct virtio_gpu_object *bo);
368
369/* virtgpu_prime.c */
370struct drm_gem_object *virtgpu_gem_prime_import_sg_table(
371 struct drm_device *dev, struct dma_buf_attachment *attach,
372 struct sg_table *sgt);
373
374/* virtgpu_debugfs.c */
375void virtio_gpu_debugfs_init(struct drm_minor *minor);
376
377#endif
1/*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26#ifndef VIRTIO_DRV_H
27#define VIRTIO_DRV_H
28
29#include <linux/dma-direction.h>
30#include <linux/virtio.h>
31#include <linux/virtio_ids.h>
32#include <linux/virtio_config.h>
33#include <linux/virtio_gpu.h>
34
35#include <drm/drm_atomic.h>
36#include <drm/drm_drv.h>
37#include <drm/drm_encoder.h>
38#include <drm/drm_fourcc.h>
39#include <drm/drm_framebuffer.h>
40#include <drm/drm_gem.h>
41#include <drm/drm_gem_shmem_helper.h>
42#include <drm/drm_ioctl.h>
43#include <drm/drm_probe_helper.h>
44#include <drm/virtgpu_drm.h>
45
46#define DRIVER_NAME "virtio_gpu"
47#define DRIVER_DESC "virtio GPU"
48#define DRIVER_DATE "0"
49
50#define DRIVER_MAJOR 0
51#define DRIVER_MINOR 1
52#define DRIVER_PATCHLEVEL 0
53
54#define STATE_INITIALIZING 0
55#define STATE_OK 1
56#define STATE_ERR 2
57
58#define MAX_CAPSET_ID 63
59#define MAX_RINGS 64
60
61struct virtio_gpu_object_params {
62 unsigned long size;
63 bool dumb;
64 /* 3d */
65 bool virgl;
66 bool blob;
67
68 /* classic resources only */
69 uint32_t format;
70 uint32_t width;
71 uint32_t height;
72 uint32_t target;
73 uint32_t bind;
74 uint32_t depth;
75 uint32_t array_size;
76 uint32_t last_level;
77 uint32_t nr_samples;
78 uint32_t flags;
79
80 /* blob resources only */
81 uint32_t ctx_id;
82 uint32_t blob_mem;
83 uint32_t blob_flags;
84 uint64_t blob_id;
85};
86
87struct virtio_gpu_object {
88 struct drm_gem_shmem_object base;
89 uint32_t hw_res_handle;
90 bool dumb;
91 bool created;
92 bool host3d_blob, guest_blob;
93 uint32_t blob_mem, blob_flags;
94
95 int uuid_state;
96 uuid_t uuid;
97};
98#define gem_to_virtio_gpu_obj(gobj) \
99 container_of((gobj), struct virtio_gpu_object, base.base)
100
101struct virtio_gpu_object_shmem {
102 struct virtio_gpu_object base;
103};
104
105struct virtio_gpu_object_vram {
106 struct virtio_gpu_object base;
107 uint32_t map_state;
108 uint32_t map_info;
109 struct drm_mm_node vram_node;
110};
111
112#define to_virtio_gpu_shmem(virtio_gpu_object) \
113 container_of((virtio_gpu_object), struct virtio_gpu_object_shmem, base)
114
115#define to_virtio_gpu_vram(virtio_gpu_object) \
116 container_of((virtio_gpu_object), struct virtio_gpu_object_vram, base)
117
118struct virtio_gpu_object_array {
119 struct ww_acquire_ctx ticket;
120 struct list_head next;
121 u32 nents, total;
122 struct drm_gem_object *objs[];
123};
124
125struct virtio_gpu_vbuffer;
126struct virtio_gpu_device;
127
128typedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *vgdev,
129 struct virtio_gpu_vbuffer *vbuf);
130
131struct virtio_gpu_fence_driver {
132 atomic64_t last_fence_id;
133 uint64_t current_fence_id;
134 uint64_t context;
135 struct list_head fences;
136 spinlock_t lock;
137};
138
139struct virtio_gpu_fence_event {
140 struct drm_pending_event base;
141 struct drm_event event;
142};
143
144struct virtio_gpu_fence {
145 struct dma_fence f;
146 uint32_t ring_idx;
147 uint64_t fence_id;
148 bool emit_fence_info;
149 struct virtio_gpu_fence_event *e;
150 struct virtio_gpu_fence_driver *drv;
151 struct list_head node;
152};
153
154struct virtio_gpu_vbuffer {
155 char *buf;
156 int size;
157
158 void *data_buf;
159 uint32_t data_size;
160
161 char *resp_buf;
162 int resp_size;
163 virtio_gpu_resp_cb resp_cb;
164 void *resp_cb_data;
165
166 struct virtio_gpu_object_array *objs;
167 struct list_head list;
168};
169
170struct virtio_gpu_output {
171 int index;
172 struct drm_crtc crtc;
173 struct drm_connector conn;
174 struct drm_encoder enc;
175 struct virtio_gpu_display_one info;
176 struct virtio_gpu_update_cursor cursor;
177 struct edid *edid;
178 int cur_x;
179 int cur_y;
180 bool needs_modeset;
181};
182#define drm_crtc_to_virtio_gpu_output(x) \
183 container_of(x, struct virtio_gpu_output, crtc)
184
185struct virtio_gpu_framebuffer {
186 struct drm_framebuffer base;
187 struct virtio_gpu_fence *fence;
188};
189#define to_virtio_gpu_framebuffer(x) \
190 container_of(x, struct virtio_gpu_framebuffer, base)
191
192struct virtio_gpu_queue {
193 struct virtqueue *vq;
194 spinlock_t qlock;
195 wait_queue_head_t ack_queue;
196 struct work_struct dequeue_work;
197};
198
199struct virtio_gpu_drv_capset {
200 uint32_t id;
201 uint32_t max_version;
202 uint32_t max_size;
203};
204
205struct virtio_gpu_drv_cap_cache {
206 struct list_head head;
207 void *caps_cache;
208 uint32_t id;
209 uint32_t version;
210 uint32_t size;
211 atomic_t is_valid;
212};
213
214struct virtio_gpu_device {
215 struct drm_device *ddev;
216
217 struct virtio_device *vdev;
218
219 struct virtio_gpu_output outputs[VIRTIO_GPU_MAX_SCANOUTS];
220 uint32_t num_scanouts;
221
222 struct virtio_gpu_queue ctrlq;
223 struct virtio_gpu_queue cursorq;
224 struct kmem_cache *vbufs;
225
226 atomic_t pending_commands;
227
228 struct ida resource_ida;
229
230 wait_queue_head_t resp_wq;
231 /* current display info */
232 spinlock_t display_info_lock;
233 bool display_info_pending;
234
235 struct virtio_gpu_fence_driver fence_drv;
236
237 struct ida ctx_id_ida;
238
239 bool has_virgl_3d;
240 bool has_edid;
241 bool has_indirect;
242 bool has_resource_assign_uuid;
243 bool has_resource_blob;
244 bool has_host_visible;
245 bool has_context_init;
246 struct virtio_shm_region host_visible_region;
247 struct drm_mm host_visible_mm;
248
249 struct work_struct config_changed_work;
250
251 struct work_struct obj_free_work;
252 spinlock_t obj_free_lock;
253 struct list_head obj_free_list;
254
255 struct virtio_gpu_drv_capset *capsets;
256 uint32_t num_capsets;
257 uint64_t capset_id_mask;
258 struct list_head cap_cache;
259
260 /* protects uuid state when exporting */
261 spinlock_t resource_export_lock;
262 /* protects map state and host_visible_mm */
263 spinlock_t host_visible_lock;
264};
265
266struct virtio_gpu_fpriv {
267 uint32_t ctx_id;
268 uint32_t context_init;
269 bool context_created;
270 uint32_t num_rings;
271 uint64_t base_fence_ctx;
272 uint64_t ring_idx_mask;
273 struct mutex context_lock;
274};
275
276/* virtgpu_ioctl.c */
277#define DRM_VIRTIO_NUM_IOCTLS 12
278extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS];
279void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file);
280
281/* virtgpu_kms.c */
282int virtio_gpu_init(struct virtio_device *vdev, struct drm_device *dev);
283void virtio_gpu_deinit(struct drm_device *dev);
284void virtio_gpu_release(struct drm_device *dev);
285int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file);
286void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file);
287
288/* virtgpu_gem.c */
289int virtio_gpu_gem_object_open(struct drm_gem_object *obj,
290 struct drm_file *file);
291void virtio_gpu_gem_object_close(struct drm_gem_object *obj,
292 struct drm_file *file);
293int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
294 struct drm_device *dev,
295 struct drm_mode_create_dumb *args);
296int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv,
297 struct drm_device *dev,
298 uint32_t handle, uint64_t *offset_p);
299
300struct virtio_gpu_object_array *virtio_gpu_array_alloc(u32 nents);
301struct virtio_gpu_object_array*
302virtio_gpu_array_from_handles(struct drm_file *drm_file, u32 *handles, u32 nents);
303void virtio_gpu_array_add_obj(struct virtio_gpu_object_array *objs,
304 struct drm_gem_object *obj);
305int virtio_gpu_array_lock_resv(struct virtio_gpu_object_array *objs);
306void virtio_gpu_array_unlock_resv(struct virtio_gpu_object_array *objs);
307void virtio_gpu_array_add_fence(struct virtio_gpu_object_array *objs,
308 struct dma_fence *fence);
309void virtio_gpu_array_put_free(struct virtio_gpu_object_array *objs);
310void virtio_gpu_array_put_free_delayed(struct virtio_gpu_device *vgdev,
311 struct virtio_gpu_object_array *objs);
312void virtio_gpu_array_put_free_work(struct work_struct *work);
313
314/* virtgpu_vq.c */
315int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev);
316void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev);
317void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
318 struct virtio_gpu_object *bo,
319 struct virtio_gpu_object_params *params,
320 struct virtio_gpu_object_array *objs,
321 struct virtio_gpu_fence *fence);
322void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
323 struct virtio_gpu_object *bo);
324void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
325 uint64_t offset,
326 uint32_t width, uint32_t height,
327 uint32_t x, uint32_t y,
328 struct virtio_gpu_object_array *objs,
329 struct virtio_gpu_fence *fence);
330void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
331 uint32_t resource_id,
332 uint32_t x, uint32_t y,
333 uint32_t width, uint32_t height,
334 struct virtio_gpu_object_array *objs,
335 struct virtio_gpu_fence *fence);
336void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
337 uint32_t scanout_id, uint32_t resource_id,
338 uint32_t width, uint32_t height,
339 uint32_t x, uint32_t y);
340void virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
341 struct virtio_gpu_object *obj,
342 struct virtio_gpu_mem_entry *ents,
343 unsigned int nents);
344int virtio_gpu_attach_status_page(struct virtio_gpu_device *vgdev);
345int virtio_gpu_detach_status_page(struct virtio_gpu_device *vgdev);
346void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
347 struct virtio_gpu_output *output);
348int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev);
349int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx);
350int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
351 int idx, int version,
352 struct virtio_gpu_drv_cap_cache **cache_p);
353int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev);
354void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
355 uint32_t context_init, uint32_t nlen,
356 const char *name);
357void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
358 uint32_t id);
359void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
360 uint32_t ctx_id,
361 struct virtio_gpu_object_array *objs);
362void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
363 uint32_t ctx_id,
364 struct virtio_gpu_object_array *objs);
365void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
366 void *data, uint32_t data_size,
367 uint32_t ctx_id,
368 struct virtio_gpu_object_array *objs,
369 struct virtio_gpu_fence *fence);
370void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
371 uint32_t ctx_id,
372 uint64_t offset, uint32_t level,
373 uint32_t stride,
374 uint32_t layer_stride,
375 struct drm_virtgpu_3d_box *box,
376 struct virtio_gpu_object_array *objs,
377 struct virtio_gpu_fence *fence);
378void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
379 uint32_t ctx_id,
380 uint64_t offset, uint32_t level,
381 uint32_t stride,
382 uint32_t layer_stride,
383 struct drm_virtgpu_3d_box *box,
384 struct virtio_gpu_object_array *objs,
385 struct virtio_gpu_fence *fence);
386void
387virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
388 struct virtio_gpu_object *bo,
389 struct virtio_gpu_object_params *params,
390 struct virtio_gpu_object_array *objs,
391 struct virtio_gpu_fence *fence);
392void virtio_gpu_ctrl_ack(struct virtqueue *vq);
393void virtio_gpu_cursor_ack(struct virtqueue *vq);
394void virtio_gpu_fence_ack(struct virtqueue *vq);
395void virtio_gpu_dequeue_ctrl_func(struct work_struct *work);
396void virtio_gpu_dequeue_cursor_func(struct work_struct *work);
397void virtio_gpu_dequeue_fence_func(struct work_struct *work);
398
399void virtio_gpu_notify(struct virtio_gpu_device *vgdev);
400
401int
402virtio_gpu_cmd_resource_assign_uuid(struct virtio_gpu_device *vgdev,
403 struct virtio_gpu_object_array *objs);
404
405int virtio_gpu_cmd_map(struct virtio_gpu_device *vgdev,
406 struct virtio_gpu_object_array *objs, uint64_t offset);
407
408void virtio_gpu_cmd_unmap(struct virtio_gpu_device *vgdev,
409 struct virtio_gpu_object *bo);
410
411void
412virtio_gpu_cmd_resource_create_blob(struct virtio_gpu_device *vgdev,
413 struct virtio_gpu_object *bo,
414 struct virtio_gpu_object_params *params,
415 struct virtio_gpu_mem_entry *ents,
416 uint32_t nents);
417void
418virtio_gpu_cmd_set_scanout_blob(struct virtio_gpu_device *vgdev,
419 uint32_t scanout_id,
420 struct virtio_gpu_object *bo,
421 struct drm_framebuffer *fb,
422 uint32_t width, uint32_t height,
423 uint32_t x, uint32_t y);
424
425/* virtgpu_display.c */
426int virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev);
427void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev);
428
429/* virtgpu_plane.c */
430uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc);
431struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
432 enum drm_plane_type type,
433 int index);
434
435/* virtgpu_fence.c */
436struct virtio_gpu_fence *virtio_gpu_fence_alloc(struct virtio_gpu_device *vgdev,
437 uint64_t base_fence_ctx,
438 uint32_t ring_idx);
439void virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev,
440 struct virtio_gpu_ctrl_hdr *cmd_hdr,
441 struct virtio_gpu_fence *fence);
442void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev,
443 u64 fence_id);
444
445/* virtgpu_object.c */
446void virtio_gpu_cleanup_object(struct virtio_gpu_object *bo);
447struct drm_gem_object *virtio_gpu_create_object(struct drm_device *dev,
448 size_t size);
449int virtio_gpu_object_create(struct virtio_gpu_device *vgdev,
450 struct virtio_gpu_object_params *params,
451 struct virtio_gpu_object **bo_ptr,
452 struct virtio_gpu_fence *fence);
453
454bool virtio_gpu_is_shmem(struct virtio_gpu_object *bo);
455
456int virtio_gpu_resource_id_get(struct virtio_gpu_device *vgdev,
457 uint32_t *resid);
458/* virtgpu_prime.c */
459int virtio_gpu_resource_assign_uuid(struct virtio_gpu_device *vgdev,
460 struct virtio_gpu_object *bo);
461struct dma_buf *virtgpu_gem_prime_export(struct drm_gem_object *obj,
462 int flags);
463struct drm_gem_object *virtgpu_gem_prime_import(struct drm_device *dev,
464 struct dma_buf *buf);
465int virtgpu_gem_prime_get_uuid(struct drm_gem_object *obj,
466 uuid_t *uuid);
467struct drm_gem_object *virtgpu_gem_prime_import_sg_table(
468 struct drm_device *dev, struct dma_buf_attachment *attach,
469 struct sg_table *sgt);
470
471/* virtgpu_debugfs.c */
472void virtio_gpu_debugfs_init(struct drm_minor *minor);
473
474/* virtgpu_vram.c */
475bool virtio_gpu_is_vram(struct virtio_gpu_object *bo);
476int virtio_gpu_vram_create(struct virtio_gpu_device *vgdev,
477 struct virtio_gpu_object_params *params,
478 struct virtio_gpu_object **bo_ptr);
479struct sg_table *virtio_gpu_vram_map_dma_buf(struct virtio_gpu_object *bo,
480 struct device *dev,
481 enum dma_data_direction dir);
482void virtio_gpu_vram_unmap_dma_buf(struct device *dev,
483 struct sg_table *sgt,
484 enum dma_data_direction dir);
485
486#endif