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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2003-2015 Broadcom Corporation
4 * All Rights Reserved
5 */
6
7#include <linux/gpio/driver.h>
8#include <linux/platform_device.h>
9#include <linux/of_device.h>
10#include <linux/module.h>
11#include <linux/irq.h>
12#include <linux/interrupt.h>
13#include <linux/irqchip/chained_irq.h>
14#include <linux/acpi.h>
15
16/*
17 * XLP GPIO has multiple 32 bit registers for each feature where each register
18 * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
19 * require 3 32-bit registers for each feature.
20 * Here we only define offset of the first register for each feature. Offset of
21 * the registers for pins greater than 32 can be calculated as following(Use
22 * GPIO_INT_STAT as example):
23 *
24 * offset = (gpio / XLP_GPIO_REGSZ) * 4;
25 * reg_addr = addr + offset;
26 *
27 * where addr is base address of the that feature register and gpio is the pin.
28 */
29#define GPIO_OUTPUT_EN 0x00
30#define GPIO_PADDRV 0x08
31#define GPIO_INT_EN00 0x18
32#define GPIO_INT_EN10 0x20
33#define GPIO_INT_EN20 0x28
34#define GPIO_INT_EN30 0x30
35#define GPIO_INT_POL 0x38
36#define GPIO_INT_TYPE 0x40
37#define GPIO_INT_STAT 0x48
38
39#define GPIO_9XX_BYTESWAP 0X00
40#define GPIO_9XX_CTRL 0X04
41#define GPIO_9XX_OUTPUT_EN 0x14
42#define GPIO_9XX_PADDRV 0x24
43/*
44 * Only for 4 interrupt enable reg are defined for now,
45 * total reg available are 12.
46 */
47#define GPIO_9XX_INT_EN00 0x44
48#define GPIO_9XX_INT_EN10 0x54
49#define GPIO_9XX_INT_EN20 0x64
50#define GPIO_9XX_INT_EN30 0x74
51#define GPIO_9XX_INT_POL 0x104
52#define GPIO_9XX_INT_TYPE 0x114
53#define GPIO_9XX_INT_STAT 0x124
54
55#define GPIO_3XX_INT_EN00 0x18
56#define GPIO_3XX_INT_EN10 0x20
57#define GPIO_3XX_INT_EN20 0x28
58#define GPIO_3XX_INT_EN30 0x30
59#define GPIO_3XX_INT_POL 0x78
60#define GPIO_3XX_INT_TYPE 0x80
61#define GPIO_3XX_INT_STAT 0x88
62
63/* Interrupt type register mask */
64#define XLP_GPIO_IRQ_TYPE_LVL 0x0
65#define XLP_GPIO_IRQ_TYPE_EDGE 0x1
66
67/* Interrupt polarity register mask */
68#define XLP_GPIO_IRQ_POL_HIGH 0x0
69#define XLP_GPIO_IRQ_POL_LOW 0x1
70
71#define XLP_GPIO_REGSZ 32
72#define XLP_GPIO_IRQ_BASE 768
73#define XLP_MAX_NR_GPIO 96
74
75/* XLP variants supported by this driver */
76enum {
77 XLP_GPIO_VARIANT_XLP832 = 1,
78 XLP_GPIO_VARIANT_XLP316,
79 XLP_GPIO_VARIANT_XLP208,
80 XLP_GPIO_VARIANT_XLP980,
81 XLP_GPIO_VARIANT_XLP532,
82 GPIO_VARIANT_VULCAN
83};
84
85struct xlp_gpio_priv {
86 struct gpio_chip chip;
87 DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
88 void __iomem *gpio_intr_en; /* pointer to first intr enable reg */
89 void __iomem *gpio_intr_stat; /* pointer to first intr status reg */
90 void __iomem *gpio_intr_type; /* pointer to first intr type reg */
91 void __iomem *gpio_intr_pol; /* pointer to first intr polarity reg */
92 void __iomem *gpio_out_en; /* pointer to first output enable reg */
93 void __iomem *gpio_paddrv; /* pointer to first pad drive reg */
94 spinlock_t lock;
95};
96
97static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
98{
99 u32 pos, regset;
100
101 pos = gpio % XLP_GPIO_REGSZ;
102 regset = (gpio / XLP_GPIO_REGSZ) * 4;
103 return !!(readl(addr + regset) & BIT(pos));
104}
105
106static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
107{
108 u32 value, pos, regset;
109
110 pos = gpio % XLP_GPIO_REGSZ;
111 regset = (gpio / XLP_GPIO_REGSZ) * 4;
112 value = readl(addr + regset);
113
114 if (state)
115 value |= BIT(pos);
116 else
117 value &= ~BIT(pos);
118
119 writel(value, addr + regset);
120}
121
122static void xlp_gpio_irq_disable(struct irq_data *d)
123{
124 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
125 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
126 unsigned long flags;
127
128 spin_lock_irqsave(&priv->lock, flags);
129 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
130 __clear_bit(d->hwirq, priv->gpio_enabled_mask);
131 spin_unlock_irqrestore(&priv->lock, flags);
132}
133
134static void xlp_gpio_irq_mask_ack(struct irq_data *d)
135{
136 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
137 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
138 unsigned long flags;
139
140 spin_lock_irqsave(&priv->lock, flags);
141 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
142 xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
143 __clear_bit(d->hwirq, priv->gpio_enabled_mask);
144 spin_unlock_irqrestore(&priv->lock, flags);
145}
146
147static void xlp_gpio_irq_unmask(struct irq_data *d)
148{
149 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
150 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
151 unsigned long flags;
152
153 spin_lock_irqsave(&priv->lock, flags);
154 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
155 __set_bit(d->hwirq, priv->gpio_enabled_mask);
156 spin_unlock_irqrestore(&priv->lock, flags);
157}
158
159static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
160{
161 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
162 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
163 int pol, irq_type;
164
165 switch (type) {
166 case IRQ_TYPE_EDGE_RISING:
167 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
168 pol = XLP_GPIO_IRQ_POL_HIGH;
169 break;
170 case IRQ_TYPE_EDGE_FALLING:
171 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
172 pol = XLP_GPIO_IRQ_POL_LOW;
173 break;
174 case IRQ_TYPE_LEVEL_HIGH:
175 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
176 pol = XLP_GPIO_IRQ_POL_HIGH;
177 break;
178 case IRQ_TYPE_LEVEL_LOW:
179 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
180 pol = XLP_GPIO_IRQ_POL_LOW;
181 break;
182 default:
183 return -EINVAL;
184 }
185
186 xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
187 xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
188
189 return 0;
190}
191
192static struct irq_chip xlp_gpio_irq_chip = {
193 .name = "XLP-GPIO",
194 .irq_mask_ack = xlp_gpio_irq_mask_ack,
195 .irq_disable = xlp_gpio_irq_disable,
196 .irq_set_type = xlp_gpio_set_irq_type,
197 .irq_unmask = xlp_gpio_irq_unmask,
198 .flags = IRQCHIP_ONESHOT_SAFE,
199};
200
201static void xlp_gpio_generic_handler(struct irq_desc *desc)
202{
203 struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
204 struct irq_chip *irqchip = irq_desc_get_chip(desc);
205 int gpio, regoff;
206 u32 gpio_stat;
207
208 regoff = -1;
209 gpio_stat = 0;
210
211 chained_irq_enter(irqchip, desc);
212 for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
213 if (regoff != gpio / XLP_GPIO_REGSZ) {
214 regoff = gpio / XLP_GPIO_REGSZ;
215 gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
216 }
217
218 if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
219 generic_handle_irq(irq_find_mapping(
220 priv->chip.irq.domain, gpio));
221 }
222 chained_irq_exit(irqchip, desc);
223}
224
225static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
226{
227 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
228
229 BUG_ON(gpio >= gc->ngpio);
230 xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
231
232 return 0;
233}
234
235static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
236{
237 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
238
239 BUG_ON(gpio >= gc->ngpio);
240 xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
241
242 return 0;
243}
244
245static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
246{
247 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
248
249 BUG_ON(gpio >= gc->ngpio);
250 return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
251}
252
253static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
254{
255 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
256
257 BUG_ON(gpio >= gc->ngpio);
258 xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
259}
260
261static const struct of_device_id xlp_gpio_of_ids[] = {
262 {
263 .compatible = "netlogic,xlp832-gpio",
264 .data = (void *)XLP_GPIO_VARIANT_XLP832,
265 },
266 {
267 .compatible = "netlogic,xlp316-gpio",
268 .data = (void *)XLP_GPIO_VARIANT_XLP316,
269 },
270 {
271 .compatible = "netlogic,xlp208-gpio",
272 .data = (void *)XLP_GPIO_VARIANT_XLP208,
273 },
274 {
275 .compatible = "netlogic,xlp980-gpio",
276 .data = (void *)XLP_GPIO_VARIANT_XLP980,
277 },
278 {
279 .compatible = "netlogic,xlp532-gpio",
280 .data = (void *)XLP_GPIO_VARIANT_XLP532,
281 },
282 {
283 .compatible = "brcm,vulcan-gpio",
284 .data = (void *)GPIO_VARIANT_VULCAN,
285 },
286 { /* sentinel */ },
287};
288MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids);
289
290static int xlp_gpio_probe(struct platform_device *pdev)
291{
292 struct gpio_chip *gc;
293 struct gpio_irq_chip *girq;
294 struct xlp_gpio_priv *priv;
295 void __iomem *gpio_base;
296 int irq_base, irq, err;
297 int ngpio;
298 u32 soc_type;
299
300 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
301 if (!priv)
302 return -ENOMEM;
303
304 gpio_base = devm_platform_ioremap_resource(pdev, 0);
305 if (IS_ERR(gpio_base))
306 return PTR_ERR(gpio_base);
307
308 irq = platform_get_irq(pdev, 0);
309 if (irq < 0)
310 return irq;
311
312 if (pdev->dev.of_node) {
313 soc_type = (uintptr_t)of_device_get_match_data(&pdev->dev);
314 } else {
315 const struct acpi_device_id *acpi_id;
316
317 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
318 &pdev->dev);
319 if (!acpi_id || !acpi_id->driver_data) {
320 dev_err(&pdev->dev, "Unable to match ACPI ID\n");
321 return -ENODEV;
322 }
323 soc_type = (uintptr_t) acpi_id->driver_data;
324 }
325
326 switch (soc_type) {
327 case XLP_GPIO_VARIANT_XLP832:
328 priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
329 priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
330 priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT;
331 priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE;
332 priv->gpio_intr_pol = gpio_base + GPIO_INT_POL;
333 priv->gpio_intr_en = gpio_base + GPIO_INT_EN00;
334 ngpio = 41;
335 break;
336 case XLP_GPIO_VARIANT_XLP208:
337 case XLP_GPIO_VARIANT_XLP316:
338 priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
339 priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
340 priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT;
341 priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE;
342 priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL;
343 priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00;
344
345 ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57;
346 break;
347 case XLP_GPIO_VARIANT_XLP980:
348 case XLP_GPIO_VARIANT_XLP532:
349 case GPIO_VARIANT_VULCAN:
350 priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
351 priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
352 priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
353 priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
354 priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
355 priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
356
357 if (soc_type == XLP_GPIO_VARIANT_XLP980)
358 ngpio = 66;
359 else if (soc_type == XLP_GPIO_VARIANT_XLP532)
360 ngpio = 67;
361 else
362 ngpio = 70;
363 break;
364 default:
365 dev_err(&pdev->dev, "Unknown Processor type!\n");
366 return -ENODEV;
367 }
368
369 bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
370
371 gc = &priv->chip;
372
373 gc->owner = THIS_MODULE;
374 gc->label = dev_name(&pdev->dev);
375 gc->base = 0;
376 gc->parent = &pdev->dev;
377 gc->ngpio = ngpio;
378 gc->of_node = pdev->dev.of_node;
379 gc->direction_output = xlp_gpio_dir_output;
380 gc->direction_input = xlp_gpio_dir_input;
381 gc->set = xlp_gpio_set;
382 gc->get = xlp_gpio_get;
383
384 spin_lock_init(&priv->lock);
385
386 /* XLP(MIPS) has fixed range for GPIO IRQs, Vulcan(ARM64) does not */
387 if (soc_type != GPIO_VARIANT_VULCAN) {
388 irq_base = devm_irq_alloc_descs(&pdev->dev, -1,
389 XLP_GPIO_IRQ_BASE,
390 gc->ngpio, 0);
391 if (irq_base < 0) {
392 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
393 return irq_base;
394 }
395 } else {
396 irq_base = 0;
397 }
398
399 girq = &gc->irq;
400 girq->chip = &xlp_gpio_irq_chip;
401 girq->parent_handler = xlp_gpio_generic_handler;
402 girq->num_parents = 1;
403 girq->parents = devm_kcalloc(&pdev->dev, 1,
404 sizeof(*girq->parents),
405 GFP_KERNEL);
406 if (!girq->parents)
407 return -ENOMEM;
408 girq->parents[0] = irq;
409 girq->first = irq_base;
410 girq->default_type = IRQ_TYPE_NONE;
411 girq->handler = handle_level_irq;
412
413 err = gpiochip_add_data(gc, priv);
414 if (err < 0)
415 return err;
416
417 dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);
418
419 return 0;
420}
421
422#ifdef CONFIG_ACPI
423static const struct acpi_device_id xlp_gpio_acpi_match[] = {
424 { "BRCM9006", GPIO_VARIANT_VULCAN },
425 { "CAV9006", GPIO_VARIANT_VULCAN },
426 {},
427};
428MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match);
429#endif
430
431static struct platform_driver xlp_gpio_driver = {
432 .driver = {
433 .name = "xlp-gpio",
434 .of_match_table = xlp_gpio_of_ids,
435 .acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match),
436 },
437 .probe = xlp_gpio_probe,
438};
439module_platform_driver(xlp_gpio_driver);
440
441MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
442MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
443MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
444MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2003-2015 Broadcom Corporation
4 * All Rights Reserved
5 */
6
7#include <linux/gpio/driver.h>
8#include <linux/platform_device.h>
9#include <linux/module.h>
10#include <linux/irq.h>
11#include <linux/interrupt.h>
12#include <linux/irqchip/chained_irq.h>
13#include <linux/acpi.h>
14
15/*
16 * XLP GPIO has multiple 32 bit registers for each feature where each register
17 * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
18 * require 3 32-bit registers for each feature.
19 * Here we only define offset of the first register for each feature. Offset of
20 * the registers for pins greater than 32 can be calculated as following(Use
21 * GPIO_INT_STAT as example):
22 *
23 * offset = (gpio / XLP_GPIO_REGSZ) * 4;
24 * reg_addr = addr + offset;
25 *
26 * where addr is base address of the that feature register and gpio is the pin.
27 */
28#define GPIO_9XX_BYTESWAP 0X00
29#define GPIO_9XX_CTRL 0X04
30#define GPIO_9XX_OUTPUT_EN 0x14
31#define GPIO_9XX_PADDRV 0x24
32/*
33 * Only for 4 interrupt enable reg are defined for now,
34 * total reg available are 12.
35 */
36#define GPIO_9XX_INT_EN00 0x44
37#define GPIO_9XX_INT_EN10 0x54
38#define GPIO_9XX_INT_EN20 0x64
39#define GPIO_9XX_INT_EN30 0x74
40#define GPIO_9XX_INT_POL 0x104
41#define GPIO_9XX_INT_TYPE 0x114
42#define GPIO_9XX_INT_STAT 0x124
43
44/* Interrupt type register mask */
45#define XLP_GPIO_IRQ_TYPE_LVL 0x0
46#define XLP_GPIO_IRQ_TYPE_EDGE 0x1
47
48/* Interrupt polarity register mask */
49#define XLP_GPIO_IRQ_POL_HIGH 0x0
50#define XLP_GPIO_IRQ_POL_LOW 0x1
51
52#define XLP_GPIO_REGSZ 32
53#define XLP_GPIO_IRQ_BASE 768
54#define XLP_MAX_NR_GPIO 96
55
56struct xlp_gpio_priv {
57 struct gpio_chip chip;
58 DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
59 void __iomem *gpio_intr_en; /* pointer to first intr enable reg */
60 void __iomem *gpio_intr_stat; /* pointer to first intr status reg */
61 void __iomem *gpio_intr_type; /* pointer to first intr type reg */
62 void __iomem *gpio_intr_pol; /* pointer to first intr polarity reg */
63 void __iomem *gpio_out_en; /* pointer to first output enable reg */
64 void __iomem *gpio_paddrv; /* pointer to first pad drive reg */
65 spinlock_t lock;
66};
67
68static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
69{
70 u32 pos, regset;
71
72 pos = gpio % XLP_GPIO_REGSZ;
73 regset = (gpio / XLP_GPIO_REGSZ) * 4;
74 return !!(readl(addr + regset) & BIT(pos));
75}
76
77static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
78{
79 u32 value, pos, regset;
80
81 pos = gpio % XLP_GPIO_REGSZ;
82 regset = (gpio / XLP_GPIO_REGSZ) * 4;
83 value = readl(addr + regset);
84
85 if (state)
86 value |= BIT(pos);
87 else
88 value &= ~BIT(pos);
89
90 writel(value, addr + regset);
91}
92
93static void xlp_gpio_irq_disable(struct irq_data *d)
94{
95 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
96 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
97 unsigned long flags;
98
99 spin_lock_irqsave(&priv->lock, flags);
100 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
101 __clear_bit(d->hwirq, priv->gpio_enabled_mask);
102 spin_unlock_irqrestore(&priv->lock, flags);
103}
104
105static void xlp_gpio_irq_mask_ack(struct irq_data *d)
106{
107 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
108 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
109 unsigned long flags;
110
111 spin_lock_irqsave(&priv->lock, flags);
112 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
113 xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
114 __clear_bit(d->hwirq, priv->gpio_enabled_mask);
115 spin_unlock_irqrestore(&priv->lock, flags);
116}
117
118static void xlp_gpio_irq_unmask(struct irq_data *d)
119{
120 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
121 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
122 unsigned long flags;
123
124 spin_lock_irqsave(&priv->lock, flags);
125 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
126 __set_bit(d->hwirq, priv->gpio_enabled_mask);
127 spin_unlock_irqrestore(&priv->lock, flags);
128}
129
130static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
131{
132 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
133 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
134 int pol, irq_type;
135
136 switch (type) {
137 case IRQ_TYPE_EDGE_RISING:
138 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
139 pol = XLP_GPIO_IRQ_POL_HIGH;
140 break;
141 case IRQ_TYPE_EDGE_FALLING:
142 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
143 pol = XLP_GPIO_IRQ_POL_LOW;
144 break;
145 case IRQ_TYPE_LEVEL_HIGH:
146 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
147 pol = XLP_GPIO_IRQ_POL_HIGH;
148 break;
149 case IRQ_TYPE_LEVEL_LOW:
150 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
151 pol = XLP_GPIO_IRQ_POL_LOW;
152 break;
153 default:
154 return -EINVAL;
155 }
156
157 xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
158 xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
159
160 return 0;
161}
162
163static struct irq_chip xlp_gpio_irq_chip = {
164 .name = "XLP-GPIO",
165 .irq_mask_ack = xlp_gpio_irq_mask_ack,
166 .irq_disable = xlp_gpio_irq_disable,
167 .irq_set_type = xlp_gpio_set_irq_type,
168 .irq_unmask = xlp_gpio_irq_unmask,
169 .flags = IRQCHIP_ONESHOT_SAFE,
170};
171
172static void xlp_gpio_generic_handler(struct irq_desc *desc)
173{
174 struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
175 struct irq_chip *irqchip = irq_desc_get_chip(desc);
176 int gpio, regoff;
177 u32 gpio_stat;
178
179 regoff = -1;
180 gpio_stat = 0;
181
182 chained_irq_enter(irqchip, desc);
183 for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
184 if (regoff != gpio / XLP_GPIO_REGSZ) {
185 regoff = gpio / XLP_GPIO_REGSZ;
186 gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
187 }
188
189 if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
190 generic_handle_domain_irq(priv->chip.irq.domain, gpio);
191 }
192 chained_irq_exit(irqchip, desc);
193}
194
195static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
196{
197 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
198
199 BUG_ON(gpio >= gc->ngpio);
200 xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
201
202 return 0;
203}
204
205static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
206{
207 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
208
209 BUG_ON(gpio >= gc->ngpio);
210 xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
211
212 return 0;
213}
214
215static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
216{
217 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
218
219 BUG_ON(gpio >= gc->ngpio);
220 return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
221}
222
223static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
224{
225 struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
226
227 BUG_ON(gpio >= gc->ngpio);
228 xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
229}
230
231static int xlp_gpio_probe(struct platform_device *pdev)
232{
233 struct gpio_chip *gc;
234 struct gpio_irq_chip *girq;
235 struct xlp_gpio_priv *priv;
236 void __iomem *gpio_base;
237 int irq, err;
238
239 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
240 if (!priv)
241 return -ENOMEM;
242
243 gpio_base = devm_platform_ioremap_resource(pdev, 0);
244 if (IS_ERR(gpio_base))
245 return PTR_ERR(gpio_base);
246
247 irq = platform_get_irq(pdev, 0);
248 if (irq < 0)
249 return irq;
250
251 priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
252 priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
253 priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
254 priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
255 priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
256 priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
257
258 bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
259
260 gc = &priv->chip;
261
262 gc->owner = THIS_MODULE;
263 gc->label = dev_name(&pdev->dev);
264 gc->base = 0;
265 gc->parent = &pdev->dev;
266 gc->ngpio = 70;
267 gc->direction_output = xlp_gpio_dir_output;
268 gc->direction_input = xlp_gpio_dir_input;
269 gc->set = xlp_gpio_set;
270 gc->get = xlp_gpio_get;
271
272 spin_lock_init(&priv->lock);
273
274 girq = &gc->irq;
275 girq->chip = &xlp_gpio_irq_chip;
276 girq->parent_handler = xlp_gpio_generic_handler;
277 girq->num_parents = 1;
278 girq->parents = devm_kcalloc(&pdev->dev, 1,
279 sizeof(*girq->parents),
280 GFP_KERNEL);
281 if (!girq->parents)
282 return -ENOMEM;
283 girq->parents[0] = irq;
284 girq->first = 0;
285 girq->default_type = IRQ_TYPE_NONE;
286 girq->handler = handle_level_irq;
287
288 err = gpiochip_add_data(gc, priv);
289 if (err < 0)
290 return err;
291
292 dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);
293
294 return 0;
295}
296
297#ifdef CONFIG_ACPI
298static const struct acpi_device_id xlp_gpio_acpi_match[] = {
299 { "BRCM9006" },
300 { "CAV9006" },
301 {},
302};
303MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match);
304#endif
305
306static struct platform_driver xlp_gpio_driver = {
307 .driver = {
308 .name = "xlp-gpio",
309 .acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match),
310 },
311 .probe = xlp_gpio_probe,
312};
313module_platform_driver(xlp_gpio_driver);
314
315MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
316MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
317MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
318MODULE_LICENSE("GPL v2");