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1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright(c) 2021 Intel Corporation. All rights reserved. */
3#include <linux/platform_device.h>
4#include <linux/module.h>
5#include <linux/device.h>
6#include <linux/kernel.h>
7#include <linux/acpi.h>
8#include <linux/pci.h>
9#include <asm/div64.h>
10#include "cxlpci.h"
11#include "cxl.h"
12
13#define CXL_RCRB_SIZE SZ_8K
14
15struct cxl_cxims_data {
16 int nr_maps;
17 u64 xormaps[];
18};
19
20/*
21 * Find a targets entry (n) in the host bridge interleave list.
22 * CXL Specfication 3.0 Table 9-22
23 */
24static int cxl_xor_calc_n(u64 hpa, struct cxl_cxims_data *cximsd, int iw,
25 int ig)
26{
27 int i = 0, n = 0;
28 u8 eiw;
29
30 /* IW: 2,4,6,8,12,16 begin building 'n' using xormaps */
31 if (iw != 3) {
32 for (i = 0; i < cximsd->nr_maps; i++)
33 n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i;
34 }
35 /* IW: 3,6,12 add a modulo calculation to 'n' */
36 if (!is_power_of_2(iw)) {
37 if (ways_to_eiw(iw, &eiw))
38 return -1;
39 hpa &= GENMASK_ULL(51, eiw + ig);
40 n |= do_div(hpa, 3) << i;
41 }
42 return n;
43}
44
45static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos)
46{
47 struct cxl_cxims_data *cximsd = cxlrd->platform_data;
48 struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
49 struct cxl_decoder *cxld = &cxlsd->cxld;
50 int ig = cxld->interleave_granularity;
51 int iw = cxld->interleave_ways;
52 int n = 0;
53 u64 hpa;
54
55 if (dev_WARN_ONCE(&cxld->dev,
56 cxld->interleave_ways != cxlsd->nr_targets,
57 "misconfigured root decoder\n"))
58 return NULL;
59
60 hpa = cxlrd->res->start + pos * ig;
61
62 /* Entry (n) is 0 for no interleave (iw == 1) */
63 if (iw != 1)
64 n = cxl_xor_calc_n(hpa, cximsd, iw, ig);
65
66 if (n < 0)
67 return NULL;
68
69 return cxlrd->cxlsd.target[n];
70}
71
72struct cxl_cxims_context {
73 struct device *dev;
74 struct cxl_root_decoder *cxlrd;
75};
76
77static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg,
78 const unsigned long end)
79{
80 struct acpi_cedt_cxims *cxims = (struct acpi_cedt_cxims *)header;
81 struct cxl_cxims_context *ctx = arg;
82 struct cxl_root_decoder *cxlrd = ctx->cxlrd;
83 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
84 struct device *dev = ctx->dev;
85 struct cxl_cxims_data *cximsd;
86 unsigned int hbig, nr_maps;
87 int rc;
88
89 rc = eig_to_granularity(cxims->hbig, &hbig);
90 if (rc)
91 return rc;
92
93 /* Does this CXIMS entry apply to the given CXL Window? */
94 if (hbig != cxld->interleave_granularity)
95 return 0;
96
97 /* IW 1,3 do not use xormaps and skip this parsing entirely */
98 if (is_power_of_2(cxld->interleave_ways))
99 /* 2, 4, 8, 16 way */
100 nr_maps = ilog2(cxld->interleave_ways);
101 else
102 /* 6, 12 way */
103 nr_maps = ilog2(cxld->interleave_ways / 3);
104
105 if (cxims->nr_xormaps < nr_maps) {
106 dev_dbg(dev, "CXIMS nr_xormaps[%d] expected[%d]\n",
107 cxims->nr_xormaps, nr_maps);
108 return -ENXIO;
109 }
110
111 cximsd = devm_kzalloc(dev, struct_size(cximsd, xormaps, nr_maps),
112 GFP_KERNEL);
113 if (!cximsd)
114 return -ENOMEM;
115 memcpy(cximsd->xormaps, cxims->xormap_list,
116 nr_maps * sizeof(*cximsd->xormaps));
117 cximsd->nr_maps = nr_maps;
118 cxlrd->platform_data = cximsd;
119
120 return 0;
121}
122
123static unsigned long cfmws_to_decoder_flags(int restrictions)
124{
125 unsigned long flags = CXL_DECODER_F_ENABLE;
126
127 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2)
128 flags |= CXL_DECODER_F_TYPE2;
129 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3)
130 flags |= CXL_DECODER_F_TYPE3;
131 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
132 flags |= CXL_DECODER_F_RAM;
133 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
134 flags |= CXL_DECODER_F_PMEM;
135 if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED)
136 flags |= CXL_DECODER_F_LOCK;
137
138 return flags;
139}
140
141static int cxl_acpi_cfmws_verify(struct device *dev,
142 struct acpi_cedt_cfmws *cfmws)
143{
144 int rc, expected_len;
145 unsigned int ways;
146
147 if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO &&
148 cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
149 dev_err(dev, "CFMWS Unknown Interleave Arithmetic: %d\n",
150 cfmws->interleave_arithmetic);
151 return -EINVAL;
152 }
153
154 if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {
155 dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");
156 return -EINVAL;
157 }
158
159 if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {
160 dev_err(dev, "CFMWS Window Size not 256MB aligned\n");
161 return -EINVAL;
162 }
163
164 rc = eiw_to_ways(cfmws->interleave_ways, &ways);
165 if (rc) {
166 dev_err(dev, "CFMWS Interleave Ways (%d) invalid\n",
167 cfmws->interleave_ways);
168 return -EINVAL;
169 }
170
171 expected_len = struct_size(cfmws, interleave_targets, ways);
172
173 if (cfmws->header.length < expected_len) {
174 dev_err(dev, "CFMWS length %d less than expected %d\n",
175 cfmws->header.length, expected_len);
176 return -EINVAL;
177 }
178
179 if (cfmws->header.length > expected_len)
180 dev_dbg(dev, "CFMWS length %d greater than expected %d\n",
181 cfmws->header.length, expected_len);
182
183 return 0;
184}
185
186/*
187 * Note, @dev must be the first member, see 'struct cxl_chbs_context'
188 * and mock_acpi_table_parse_cedt()
189 */
190struct cxl_cfmws_context {
191 struct device *dev;
192 struct cxl_port *root_port;
193 struct resource *cxl_res;
194 int id;
195};
196
197static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
198 const unsigned long end)
199{
200 int target_map[CXL_DECODER_MAX_INTERLEAVE];
201 struct cxl_cfmws_context *ctx = arg;
202 struct cxl_port *root_port = ctx->root_port;
203 struct resource *cxl_res = ctx->cxl_res;
204 struct cxl_cxims_context cxims_ctx;
205 struct cxl_root_decoder *cxlrd;
206 struct device *dev = ctx->dev;
207 struct acpi_cedt_cfmws *cfmws;
208 cxl_calc_hb_fn cxl_calc_hb;
209 struct cxl_decoder *cxld;
210 unsigned int ways, i, ig;
211 struct resource *res;
212 int rc;
213
214 cfmws = (struct acpi_cedt_cfmws *) header;
215
216 rc = cxl_acpi_cfmws_verify(dev, cfmws);
217 if (rc) {
218 dev_err(dev, "CFMWS range %#llx-%#llx not registered\n",
219 cfmws->base_hpa,
220 cfmws->base_hpa + cfmws->window_size - 1);
221 return 0;
222 }
223
224 rc = eiw_to_ways(cfmws->interleave_ways, &ways);
225 if (rc)
226 return rc;
227 rc = eig_to_granularity(cfmws->granularity, &ig);
228 if (rc)
229 return rc;
230 for (i = 0; i < ways; i++)
231 target_map[i] = cfmws->interleave_targets[i];
232
233 res = kzalloc(sizeof(*res), GFP_KERNEL);
234 if (!res)
235 return -ENOMEM;
236
237 res->name = kasprintf(GFP_KERNEL, "CXL Window %d", ctx->id++);
238 if (!res->name)
239 goto err_name;
240
241 res->start = cfmws->base_hpa;
242 res->end = cfmws->base_hpa + cfmws->window_size - 1;
243 res->flags = IORESOURCE_MEM;
244
245 /* add to the local resource tracking to establish a sort order */
246 rc = insert_resource(cxl_res, res);
247 if (rc)
248 goto err_insert;
249
250 if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_MODULO)
251 cxl_calc_hb = cxl_hb_modulo;
252 else
253 cxl_calc_hb = cxl_hb_xor;
254
255 cxlrd = cxl_root_decoder_alloc(root_port, ways, cxl_calc_hb);
256 if (IS_ERR(cxlrd))
257 return 0;
258
259 cxld = &cxlrd->cxlsd.cxld;
260 cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
261 cxld->target_type = CXL_DECODER_EXPANDER;
262 cxld->hpa_range = (struct range) {
263 .start = res->start,
264 .end = res->end,
265 };
266 cxld->interleave_ways = ways;
267 /*
268 * Minimize the x1 granularity to advertise support for any
269 * valid region granularity
270 */
271 if (ways == 1)
272 ig = CXL_DECODER_MIN_GRANULARITY;
273 cxld->interleave_granularity = ig;
274
275 if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
276 if (ways != 1 && ways != 3) {
277 cxims_ctx = (struct cxl_cxims_context) {
278 .dev = dev,
279 .cxlrd = cxlrd,
280 };
281 rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS,
282 cxl_parse_cxims, &cxims_ctx);
283 if (rc < 0)
284 goto err_xormap;
285 if (!cxlrd->platform_data) {
286 dev_err(dev, "No CXIMS for HBIG %u\n", ig);
287 rc = -EINVAL;
288 goto err_xormap;
289 }
290 }
291 }
292 rc = cxl_decoder_add(cxld, target_map);
293err_xormap:
294 if (rc)
295 put_device(&cxld->dev);
296 else
297 rc = cxl_decoder_autoremove(dev, cxld);
298 if (rc) {
299 dev_err(dev, "Failed to add decode range [%#llx - %#llx]\n",
300 cxld->hpa_range.start, cxld->hpa_range.end);
301 return 0;
302 }
303 dev_dbg(dev, "add: %s node: %d range [%#llx - %#llx]\n",
304 dev_name(&cxld->dev),
305 phys_to_target_node(cxld->hpa_range.start),
306 cxld->hpa_range.start, cxld->hpa_range.end);
307
308 return 0;
309
310err_insert:
311 kfree(res->name);
312err_name:
313 kfree(res);
314 return -ENOMEM;
315}
316
317__mock struct acpi_device *to_cxl_host_bridge(struct device *host,
318 struct device *dev)
319{
320 struct acpi_device *adev = to_acpi_device(dev);
321
322 if (!acpi_pci_find_root(adev->handle))
323 return NULL;
324
325 if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)
326 return adev;
327 return NULL;
328}
329
330/*
331 * A host bridge is a dport to a CFMWS decode and it is a uport to the
332 * dport (PCIe Root Ports) in the host bridge.
333 */
334static int add_host_bridge_uport(struct device *match, void *arg)
335{
336 struct cxl_port *root_port = arg;
337 struct device *host = root_port->dev.parent;
338 struct acpi_device *hb = to_cxl_host_bridge(host, match);
339 struct acpi_pci_root *pci_root;
340 struct cxl_dport *dport;
341 struct cxl_port *port;
342 struct device *bridge;
343 int rc;
344
345 if (!hb)
346 return 0;
347
348 pci_root = acpi_pci_find_root(hb->handle);
349 bridge = pci_root->bus->bridge;
350 dport = cxl_find_dport_by_dev(root_port, bridge);
351 if (!dport) {
352 dev_dbg(host, "host bridge expected and not found\n");
353 return 0;
354 }
355
356 if (dport->rch) {
357 dev_info(bridge, "host supports CXL (restricted)\n");
358 return 0;
359 }
360
361 rc = devm_cxl_register_pci_bus(host, bridge, pci_root->bus);
362 if (rc)
363 return rc;
364
365 port = devm_cxl_add_port(host, bridge, dport->component_reg_phys,
366 dport);
367 if (IS_ERR(port))
368 return PTR_ERR(port);
369
370 dev_info(bridge, "host supports CXL\n");
371
372 return 0;
373}
374
375struct cxl_chbs_context {
376 struct device *dev;
377 unsigned long long uid;
378 resource_size_t rcrb;
379 resource_size_t chbcr;
380 u32 cxl_version;
381};
382
383static int cxl_get_chbcr(union acpi_subtable_headers *header, void *arg,
384 const unsigned long end)
385{
386 struct cxl_chbs_context *ctx = arg;
387 struct acpi_cedt_chbs *chbs;
388
389 if (ctx->chbcr)
390 return 0;
391
392 chbs = (struct acpi_cedt_chbs *) header;
393
394 if (ctx->uid != chbs->uid)
395 return 0;
396
397 ctx->cxl_version = chbs->cxl_version;
398 ctx->rcrb = CXL_RESOURCE_NONE;
399 ctx->chbcr = CXL_RESOURCE_NONE;
400
401 if (!chbs->base)
402 return 0;
403
404 if (chbs->cxl_version != ACPI_CEDT_CHBS_VERSION_CXL11) {
405 ctx->chbcr = chbs->base;
406 return 0;
407 }
408
409 if (chbs->length != CXL_RCRB_SIZE)
410 return 0;
411
412 ctx->rcrb = chbs->base;
413 ctx->chbcr = cxl_rcrb_to_component(ctx->dev, chbs->base,
414 CXL_RCRB_DOWNSTREAM);
415
416 return 0;
417}
418
419static int add_host_bridge_dport(struct device *match, void *arg)
420{
421 acpi_status rc;
422 struct device *bridge;
423 unsigned long long uid;
424 struct cxl_dport *dport;
425 struct cxl_chbs_context ctx;
426 struct acpi_pci_root *pci_root;
427 struct cxl_port *root_port = arg;
428 struct device *host = root_port->dev.parent;
429 struct acpi_device *hb = to_cxl_host_bridge(host, match);
430
431 if (!hb)
432 return 0;
433
434 rc = acpi_evaluate_integer(hb->handle, METHOD_NAME__UID, NULL, &uid);
435 if (rc != AE_OK) {
436 dev_err(match, "unable to retrieve _UID\n");
437 return -ENODEV;
438 }
439
440 dev_dbg(match, "UID found: %lld\n", uid);
441
442 ctx = (struct cxl_chbs_context) {
443 .dev = match,
444 .uid = uid,
445 };
446 acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbcr, &ctx);
447
448 if (!ctx.chbcr) {
449 dev_warn(match, "No CHBS found for Host Bridge (UID %lld)\n",
450 uid);
451 return 0;
452 }
453
454 if (ctx.rcrb != CXL_RESOURCE_NONE)
455 dev_dbg(match, "RCRB found for UID %lld: %pa\n", uid, &ctx.rcrb);
456
457 if (ctx.chbcr == CXL_RESOURCE_NONE) {
458 dev_warn(match, "CHBCR invalid for Host Bridge (UID %lld)\n",
459 uid);
460 return 0;
461 }
462
463 dev_dbg(match, "CHBCR found: %pa\n", &ctx.chbcr);
464
465 pci_root = acpi_pci_find_root(hb->handle);
466 bridge = pci_root->bus->bridge;
467 if (ctx.cxl_version == ACPI_CEDT_CHBS_VERSION_CXL11)
468 dport = devm_cxl_add_rch_dport(root_port, bridge, uid,
469 ctx.chbcr, ctx.rcrb);
470 else
471 dport = devm_cxl_add_dport(root_port, bridge, uid,
472 ctx.chbcr);
473 if (IS_ERR(dport))
474 return PTR_ERR(dport);
475
476 return 0;
477}
478
479static int add_root_nvdimm_bridge(struct device *match, void *data)
480{
481 struct cxl_decoder *cxld;
482 struct cxl_port *root_port = data;
483 struct cxl_nvdimm_bridge *cxl_nvb;
484 struct device *host = root_port->dev.parent;
485
486 if (!is_root_decoder(match))
487 return 0;
488
489 cxld = to_cxl_decoder(match);
490 if (!(cxld->flags & CXL_DECODER_F_PMEM))
491 return 0;
492
493 cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);
494 if (IS_ERR(cxl_nvb)) {
495 dev_dbg(host, "failed to register pmem\n");
496 return PTR_ERR(cxl_nvb);
497 }
498 dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),
499 dev_name(&cxl_nvb->dev));
500 return 1;
501}
502
503static struct lock_class_key cxl_root_key;
504
505static void cxl_acpi_lock_reset_class(void *dev)
506{
507 device_lock_reset_class(dev);
508}
509
510static void del_cxl_resource(struct resource *res)
511{
512 kfree(res->name);
513 kfree(res);
514}
515
516static void cxl_set_public_resource(struct resource *priv, struct resource *pub)
517{
518 priv->desc = (unsigned long) pub;
519}
520
521static struct resource *cxl_get_public_resource(struct resource *priv)
522{
523 return (struct resource *) priv->desc;
524}
525
526static void remove_cxl_resources(void *data)
527{
528 struct resource *res, *next, *cxl = data;
529
530 for (res = cxl->child; res; res = next) {
531 struct resource *victim = cxl_get_public_resource(res);
532
533 next = res->sibling;
534 remove_resource(res);
535
536 if (victim) {
537 remove_resource(victim);
538 kfree(victim);
539 }
540
541 del_cxl_resource(res);
542 }
543}
544
545/**
546 * add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource
547 * @cxl_res: A standalone resource tree where each CXL window is a sibling
548 *
549 * Walk each CXL window in @cxl_res and add it to iomem_resource potentially
550 * expanding its boundaries to ensure that any conflicting resources become
551 * children. If a window is expanded it may then conflict with a another window
552 * entry and require the window to be truncated or trimmed. Consider this
553 * situation:
554 *
555 * |-- "CXL Window 0" --||----- "CXL Window 1" -----|
556 * |--------------- "System RAM" -------------|
557 *
558 * ...where platform firmware has established as System RAM resource across 2
559 * windows, but has left some portion of window 1 for dynamic CXL region
560 * provisioning. In this case "Window 0" will span the entirety of the "System
561 * RAM" span, and "CXL Window 1" is truncated to the remaining tail past the end
562 * of that "System RAM" resource.
563 */
564static int add_cxl_resources(struct resource *cxl_res)
565{
566 struct resource *res, *new, *next;
567
568 for (res = cxl_res->child; res; res = next) {
569 new = kzalloc(sizeof(*new), GFP_KERNEL);
570 if (!new)
571 return -ENOMEM;
572 new->name = res->name;
573 new->start = res->start;
574 new->end = res->end;
575 new->flags = IORESOURCE_MEM;
576 new->desc = IORES_DESC_CXL;
577
578 /*
579 * Record the public resource in the private cxl_res tree for
580 * later removal.
581 */
582 cxl_set_public_resource(res, new);
583
584 insert_resource_expand_to_fit(&iomem_resource, new);
585
586 next = res->sibling;
587 while (next && resource_overlaps(new, next)) {
588 if (resource_contains(new, next)) {
589 struct resource *_next = next->sibling;
590
591 remove_resource(next);
592 del_cxl_resource(next);
593 next = _next;
594 } else
595 next->start = new->end + 1;
596 }
597 }
598 return 0;
599}
600
601static int pair_cxl_resource(struct device *dev, void *data)
602{
603 struct resource *cxl_res = data;
604 struct resource *p;
605
606 if (!is_root_decoder(dev))
607 return 0;
608
609 for (p = cxl_res->child; p; p = p->sibling) {
610 struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev);
611 struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
612 struct resource res = {
613 .start = cxld->hpa_range.start,
614 .end = cxld->hpa_range.end,
615 .flags = IORESOURCE_MEM,
616 };
617
618 if (resource_contains(p, &res)) {
619 cxlrd->res = cxl_get_public_resource(p);
620 break;
621 }
622 }
623
624 return 0;
625}
626
627static int cxl_acpi_probe(struct platform_device *pdev)
628{
629 int rc;
630 struct resource *cxl_res;
631 struct cxl_port *root_port;
632 struct device *host = &pdev->dev;
633 struct acpi_device *adev = ACPI_COMPANION(host);
634 struct cxl_cfmws_context ctx;
635
636 device_lock_set_class(&pdev->dev, &cxl_root_key);
637 rc = devm_add_action_or_reset(&pdev->dev, cxl_acpi_lock_reset_class,
638 &pdev->dev);
639 if (rc)
640 return rc;
641
642 cxl_res = devm_kzalloc(host, sizeof(*cxl_res), GFP_KERNEL);
643 if (!cxl_res)
644 return -ENOMEM;
645 cxl_res->name = "CXL mem";
646 cxl_res->start = 0;
647 cxl_res->end = -1;
648 cxl_res->flags = IORESOURCE_MEM;
649
650 root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);
651 if (IS_ERR(root_port))
652 return PTR_ERR(root_port);
653
654 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
655 add_host_bridge_dport);
656 if (rc < 0)
657 return rc;
658
659 rc = devm_add_action_or_reset(host, remove_cxl_resources, cxl_res);
660 if (rc)
661 return rc;
662
663 ctx = (struct cxl_cfmws_context) {
664 .dev = host,
665 .root_port = root_port,
666 .cxl_res = cxl_res,
667 };
668 rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
669 if (rc < 0)
670 return -ENXIO;
671
672 rc = add_cxl_resources(cxl_res);
673 if (rc)
674 return rc;
675
676 /*
677 * Populate the root decoders with their related iomem resource,
678 * if present
679 */
680 device_for_each_child(&root_port->dev, cxl_res, pair_cxl_resource);
681
682 /*
683 * Root level scanned with host-bridge as dports, now scan host-bridges
684 * for their role as CXL uports to their CXL-capable PCIe Root Ports.
685 */
686 rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
687 add_host_bridge_uport);
688 if (rc < 0)
689 return rc;
690
691 if (IS_ENABLED(CONFIG_CXL_PMEM))
692 rc = device_for_each_child(&root_port->dev, root_port,
693 add_root_nvdimm_bridge);
694 if (rc < 0)
695 return rc;
696
697 /* In case PCI is scanned before ACPI re-trigger memdev attach */
698 cxl_bus_rescan();
699 return 0;
700}
701
702static const struct acpi_device_id cxl_acpi_ids[] = {
703 { "ACPI0017" },
704 { },
705};
706MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);
707
708static const struct platform_device_id cxl_test_ids[] = {
709 { "cxl_acpi" },
710 { },
711};
712MODULE_DEVICE_TABLE(platform, cxl_test_ids);
713
714static struct platform_driver cxl_acpi_driver = {
715 .probe = cxl_acpi_probe,
716 .driver = {
717 .name = KBUILD_MODNAME,
718 .acpi_match_table = cxl_acpi_ids,
719 },
720 .id_table = cxl_test_ids,
721};
722
723static int __init cxl_acpi_init(void)
724{
725 return platform_driver_register(&cxl_acpi_driver);
726}
727
728static void __exit cxl_acpi_exit(void)
729{
730 platform_driver_unregister(&cxl_acpi_driver);
731 cxl_bus_drain();
732}
733
734module_init(cxl_acpi_init);
735module_exit(cxl_acpi_exit);
736MODULE_LICENSE("GPL v2");
737MODULE_IMPORT_NS(CXL);
738MODULE_IMPORT_NS(ACPI);