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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
3// Copyright (c) 2018, Linaro Limited
4
5#include <linux/irq.h>
6#include <linux/kernel.h>
7#include <linux/init.h>
8#include <linux/slab.h>
9#include <linux/interrupt.h>
10#include <linux/platform_device.h>
11#include <linux/dma-mapping.h>
12#include <linux/dmaengine.h>
13#include <linux/slimbus.h>
14#include <linux/delay.h>
15#include <linux/pm_runtime.h>
16#include <linux/of.h>
17#include <linux/io.h>
18#include <linux/soc/qcom/qmi.h>
19#include <net/sock.h>
20#include "slimbus.h"
21
22/* NGD (Non-ported Generic Device) registers */
23#define NGD_CFG 0x0
24#define NGD_CFG_ENABLE BIT(0)
25#define NGD_CFG_RX_MSGQ_EN BIT(1)
26#define NGD_CFG_TX_MSGQ_EN BIT(2)
27#define NGD_STATUS 0x4
28#define NGD_LADDR BIT(1)
29#define NGD_RX_MSGQ_CFG 0x8
30#define NGD_INT_EN 0x10
31#define NGD_INT_RECFG_DONE BIT(24)
32#define NGD_INT_TX_NACKED_2 BIT(25)
33#define NGD_INT_MSG_BUF_CONTE BIT(26)
34#define NGD_INT_MSG_TX_INVAL BIT(27)
35#define NGD_INT_IE_VE_CHG BIT(28)
36#define NGD_INT_DEV_ERR BIT(29)
37#define NGD_INT_RX_MSG_RCVD BIT(30)
38#define NGD_INT_TX_MSG_SENT BIT(31)
39#define NGD_INT_STAT 0x14
40#define NGD_INT_CLR 0x18
41#define DEF_NGD_INT_MASK (NGD_INT_TX_NACKED_2 | NGD_INT_MSG_BUF_CONTE | \
42 NGD_INT_MSG_TX_INVAL | NGD_INT_IE_VE_CHG | \
43 NGD_INT_DEV_ERR | NGD_INT_TX_MSG_SENT | \
44 NGD_INT_RX_MSG_RCVD)
45
46/* Slimbus QMI service */
47#define SLIMBUS_QMI_SVC_ID 0x0301
48#define SLIMBUS_QMI_SVC_V1 1
49#define SLIMBUS_QMI_INS_ID 0
50#define SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01 0x0020
51#define SLIMBUS_QMI_SELECT_INSTANCE_RESP_V01 0x0020
52#define SLIMBUS_QMI_POWER_REQ_V01 0x0021
53#define SLIMBUS_QMI_POWER_RESP_V01 0x0021
54#define SLIMBUS_QMI_CHECK_FRAMER_STATUS_REQ 0x0022
55#define SLIMBUS_QMI_CHECK_FRAMER_STATUS_RESP 0x0022
56#define SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN 14
57#define SLIMBUS_QMI_POWER_RESP_MAX_MSG_LEN 7
58#define SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN 14
59#define SLIMBUS_QMI_SELECT_INSTANCE_RESP_MAX_MSG_LEN 7
60#define SLIMBUS_QMI_CHECK_FRAMER_STAT_RESP_MAX_MSG_LEN 7
61/* QMI response timeout of 500ms */
62#define SLIMBUS_QMI_RESP_TOUT 1000
63
64/* User defined commands */
65#define SLIM_USR_MC_GENERIC_ACK 0x25
66#define SLIM_USR_MC_MASTER_CAPABILITY 0x0
67#define SLIM_USR_MC_REPORT_SATELLITE 0x1
68#define SLIM_USR_MC_ADDR_QUERY 0xD
69#define SLIM_USR_MC_ADDR_REPLY 0xE
70#define SLIM_USR_MC_DEFINE_CHAN 0x20
71#define SLIM_USR_MC_DEF_ACT_CHAN 0x21
72#define SLIM_USR_MC_CHAN_CTRL 0x23
73#define SLIM_USR_MC_RECONFIG_NOW 0x24
74#define SLIM_USR_MC_REQ_BW 0x28
75#define SLIM_USR_MC_CONNECT_SRC 0x2C
76#define SLIM_USR_MC_CONNECT_SINK 0x2D
77#define SLIM_USR_MC_DISCONNECT_PORT 0x2E
78#define SLIM_USR_MC_REPEAT_CHANGE_VALUE 0x0
79
80#define QCOM_SLIM_NGD_AUTOSUSPEND MSEC_PER_SEC
81#define SLIM_RX_MSGQ_TIMEOUT_VAL 0x10000
82
83#define SLIM_LA_MGR 0xFF
84#define SLIM_ROOT_FREQ 24576000
85#define LADDR_RETRY 5
86
87/* Per spec.max 40 bytes per received message */
88#define SLIM_MSGQ_BUF_LEN 40
89#define QCOM_SLIM_NGD_DESC_NUM 32
90
91#define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \
92 ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16))
93
94#define INIT_MX_RETRIES 10
95#define DEF_RETRY_MS 10
96#define SAT_MAGIC_LSB 0xD9
97#define SAT_MAGIC_MSB 0xC5
98#define SAT_MSG_VER 0x1
99#define SAT_MSG_PROT 0x1
100#define to_ngd(d) container_of(d, struct qcom_slim_ngd, dev)
101
102struct ngd_reg_offset_data {
103 u32 offset, size;
104};
105
106static const struct ngd_reg_offset_data ngd_v1_5_offset_info = {
107 .offset = 0x1000,
108 .size = 0x1000,
109};
110
111enum qcom_slim_ngd_state {
112 QCOM_SLIM_NGD_CTRL_AWAKE,
113 QCOM_SLIM_NGD_CTRL_IDLE,
114 QCOM_SLIM_NGD_CTRL_ASLEEP,
115 QCOM_SLIM_NGD_CTRL_DOWN,
116};
117
118struct qcom_slim_ngd_qmi {
119 struct qmi_handle qmi;
120 struct sockaddr_qrtr svc_info;
121 struct qmi_handle svc_event_hdl;
122 struct qmi_response_type_v01 resp;
123 struct qmi_handle *handle;
124 struct completion qmi_comp;
125};
126
127struct qcom_slim_ngd_ctrl;
128struct qcom_slim_ngd;
129
130struct qcom_slim_ngd_dma_desc {
131 struct dma_async_tx_descriptor *desc;
132 struct qcom_slim_ngd_ctrl *ctrl;
133 struct completion *comp;
134 dma_cookie_t cookie;
135 dma_addr_t phys;
136 void *base;
137};
138
139struct qcom_slim_ngd {
140 struct platform_device *pdev;
141 void __iomem *base;
142 int id;
143};
144
145struct qcom_slim_ngd_ctrl {
146 struct slim_framer framer;
147 struct slim_controller ctrl;
148 struct qcom_slim_ngd_qmi qmi;
149 struct qcom_slim_ngd *ngd;
150 struct device *dev;
151 void __iomem *base;
152 struct dma_chan *dma_rx_channel;
153 struct dma_chan *dma_tx_channel;
154 struct qcom_slim_ngd_dma_desc rx_desc[QCOM_SLIM_NGD_DESC_NUM];
155 struct qcom_slim_ngd_dma_desc txdesc[QCOM_SLIM_NGD_DESC_NUM];
156 struct completion reconf;
157 struct work_struct m_work;
158 struct workqueue_struct *mwq;
159 spinlock_t tx_buf_lock;
160 enum qcom_slim_ngd_state state;
161 dma_addr_t rx_phys_base;
162 dma_addr_t tx_phys_base;
163 void *rx_base;
164 void *tx_base;
165 int tx_tail;
166 int tx_head;
167 u32 ver;
168};
169
170enum slimbus_mode_enum_type_v01 {
171 /* To force a 32 bit signed enum. Do not change or use*/
172 SLIMBUS_MODE_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
173 SLIMBUS_MODE_SATELLITE_V01 = 1,
174 SLIMBUS_MODE_MASTER_V01 = 2,
175 SLIMBUS_MODE_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
176};
177
178enum slimbus_pm_enum_type_v01 {
179 /* To force a 32 bit signed enum. Do not change or use*/
180 SLIMBUS_PM_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
181 SLIMBUS_PM_INACTIVE_V01 = 1,
182 SLIMBUS_PM_ACTIVE_V01 = 2,
183 SLIMBUS_PM_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
184};
185
186enum slimbus_resp_enum_type_v01 {
187 SLIMBUS_RESP_ENUM_TYPE_MIN_VAL_V01 = INT_MIN,
188 SLIMBUS_RESP_SYNCHRONOUS_V01 = 1,
189 SLIMBUS_RESP_ENUM_TYPE_MAX_VAL_V01 = INT_MAX,
190};
191
192struct slimbus_select_inst_req_msg_v01 {
193 uint32_t instance;
194 uint8_t mode_valid;
195 enum slimbus_mode_enum_type_v01 mode;
196};
197
198struct slimbus_select_inst_resp_msg_v01 {
199 struct qmi_response_type_v01 resp;
200};
201
202struct slimbus_power_req_msg_v01 {
203 enum slimbus_pm_enum_type_v01 pm_req;
204 uint8_t resp_type_valid;
205 enum slimbus_resp_enum_type_v01 resp_type;
206};
207
208struct slimbus_power_resp_msg_v01 {
209 struct qmi_response_type_v01 resp;
210};
211
212static struct qmi_elem_info slimbus_select_inst_req_msg_v01_ei[] = {
213 {
214 .data_type = QMI_UNSIGNED_4_BYTE,
215 .elem_len = 1,
216 .elem_size = sizeof(uint32_t),
217 .array_type = NO_ARRAY,
218 .tlv_type = 0x01,
219 .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
220 instance),
221 .ei_array = NULL,
222 },
223 {
224 .data_type = QMI_OPT_FLAG,
225 .elem_len = 1,
226 .elem_size = sizeof(uint8_t),
227 .array_type = NO_ARRAY,
228 .tlv_type = 0x10,
229 .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
230 mode_valid),
231 .ei_array = NULL,
232 },
233 {
234 .data_type = QMI_UNSIGNED_4_BYTE,
235 .elem_len = 1,
236 .elem_size = sizeof(enum slimbus_mode_enum_type_v01),
237 .array_type = NO_ARRAY,
238 .tlv_type = 0x10,
239 .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
240 mode),
241 .ei_array = NULL,
242 },
243 {
244 .data_type = QMI_EOTI,
245 .elem_len = 0,
246 .elem_size = 0,
247 .array_type = NO_ARRAY,
248 .tlv_type = 0x00,
249 .offset = 0,
250 .ei_array = NULL,
251 },
252};
253
254static struct qmi_elem_info slimbus_select_inst_resp_msg_v01_ei[] = {
255 {
256 .data_type = QMI_STRUCT,
257 .elem_len = 1,
258 .elem_size = sizeof(struct qmi_response_type_v01),
259 .array_type = NO_ARRAY,
260 .tlv_type = 0x02,
261 .offset = offsetof(struct slimbus_select_inst_resp_msg_v01,
262 resp),
263 .ei_array = qmi_response_type_v01_ei,
264 },
265 {
266 .data_type = QMI_EOTI,
267 .elem_len = 0,
268 .elem_size = 0,
269 .array_type = NO_ARRAY,
270 .tlv_type = 0x00,
271 .offset = 0,
272 .ei_array = NULL,
273 },
274};
275
276static struct qmi_elem_info slimbus_power_req_msg_v01_ei[] = {
277 {
278 .data_type = QMI_UNSIGNED_4_BYTE,
279 .elem_len = 1,
280 .elem_size = sizeof(enum slimbus_pm_enum_type_v01),
281 .array_type = NO_ARRAY,
282 .tlv_type = 0x01,
283 .offset = offsetof(struct slimbus_power_req_msg_v01,
284 pm_req),
285 .ei_array = NULL,
286 },
287 {
288 .data_type = QMI_OPT_FLAG,
289 .elem_len = 1,
290 .elem_size = sizeof(uint8_t),
291 .array_type = NO_ARRAY,
292 .tlv_type = 0x10,
293 .offset = offsetof(struct slimbus_power_req_msg_v01,
294 resp_type_valid),
295 },
296 {
297 .data_type = QMI_SIGNED_4_BYTE_ENUM,
298 .elem_len = 1,
299 .elem_size = sizeof(enum slimbus_resp_enum_type_v01),
300 .array_type = NO_ARRAY,
301 .tlv_type = 0x10,
302 .offset = offsetof(struct slimbus_power_req_msg_v01,
303 resp_type),
304 },
305 {
306 .data_type = QMI_EOTI,
307 .elem_len = 0,
308 .elem_size = 0,
309 .array_type = NO_ARRAY,
310 .tlv_type = 0x00,
311 .offset = 0,
312 .ei_array = NULL,
313 },
314};
315
316static struct qmi_elem_info slimbus_power_resp_msg_v01_ei[] = {
317 {
318 .data_type = QMI_STRUCT,
319 .elem_len = 1,
320 .elem_size = sizeof(struct qmi_response_type_v01),
321 .array_type = NO_ARRAY,
322 .tlv_type = 0x02,
323 .offset = offsetof(struct slimbus_power_resp_msg_v01, resp),
324 .ei_array = qmi_response_type_v01_ei,
325 },
326 {
327 .data_type = QMI_EOTI,
328 .elem_len = 0,
329 .elem_size = 0,
330 .array_type = NO_ARRAY,
331 .tlv_type = 0x00,
332 .offset = 0,
333 .ei_array = NULL,
334 },
335};
336
337static int qcom_slim_qmi_send_select_inst_req(struct qcom_slim_ngd_ctrl *ctrl,
338 struct slimbus_select_inst_req_msg_v01 *req)
339{
340 struct slimbus_select_inst_resp_msg_v01 resp = { { 0, 0 } };
341 struct qmi_txn txn;
342 int rc;
343
344 rc = qmi_txn_init(ctrl->qmi.handle, &txn,
345 slimbus_select_inst_resp_msg_v01_ei, &resp);
346 if (rc < 0) {
347 dev_err(ctrl->dev, "QMI TXN init fail: %d\n", rc);
348 return rc;
349 }
350
351 rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn,
352 SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01,
353 SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN,
354 slimbus_select_inst_req_msg_v01_ei, req);
355 if (rc < 0) {
356 dev_err(ctrl->dev, "QMI send req fail %d\n", rc);
357 qmi_txn_cancel(&txn);
358 return rc;
359 }
360
361 rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT);
362 if (rc < 0) {
363 dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc);
364 return rc;
365 }
366 /* Check the response */
367 if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
368 dev_err(ctrl->dev, "QMI request failed 0x%x\n",
369 resp.resp.result);
370 return -EREMOTEIO;
371 }
372
373 return 0;
374}
375
376static void qcom_slim_qmi_power_resp_cb(struct qmi_handle *handle,
377 struct sockaddr_qrtr *sq,
378 struct qmi_txn *txn, const void *data)
379{
380 struct slimbus_power_resp_msg_v01 *resp;
381
382 resp = (struct slimbus_power_resp_msg_v01 *)data;
383 if (resp->resp.result != QMI_RESULT_SUCCESS_V01)
384 pr_err("QMI power request failed 0x%x\n",
385 resp->resp.result);
386
387 complete(&txn->completion);
388}
389
390static int qcom_slim_qmi_send_power_request(struct qcom_slim_ngd_ctrl *ctrl,
391 struct slimbus_power_req_msg_v01 *req)
392{
393 struct slimbus_power_resp_msg_v01 resp = { { 0, 0 } };
394 struct qmi_txn txn;
395 int rc;
396
397 rc = qmi_txn_init(ctrl->qmi.handle, &txn,
398 slimbus_power_resp_msg_v01_ei, &resp);
399
400 rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn,
401 SLIMBUS_QMI_POWER_REQ_V01,
402 SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN,
403 slimbus_power_req_msg_v01_ei, req);
404 if (rc < 0) {
405 dev_err(ctrl->dev, "QMI send req fail %d\n", rc);
406 qmi_txn_cancel(&txn);
407 return rc;
408 }
409
410 rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT);
411 if (rc < 0) {
412 dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc);
413 return rc;
414 }
415
416 /* Check the response */
417 if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
418 dev_err(ctrl->dev, "QMI request failed 0x%x\n",
419 resp.resp.result);
420 return -EREMOTEIO;
421 }
422
423 return 0;
424}
425
426static struct qmi_msg_handler qcom_slim_qmi_msg_handlers[] = {
427 {
428 .type = QMI_RESPONSE,
429 .msg_id = SLIMBUS_QMI_POWER_RESP_V01,
430 .ei = slimbus_power_resp_msg_v01_ei,
431 .decoded_size = sizeof(struct slimbus_power_resp_msg_v01),
432 .fn = qcom_slim_qmi_power_resp_cb,
433 },
434 {}
435};
436
437static int qcom_slim_qmi_init(struct qcom_slim_ngd_ctrl *ctrl,
438 bool apps_is_master)
439{
440 struct slimbus_select_inst_req_msg_v01 req;
441 struct qmi_handle *handle;
442 int rc;
443
444 handle = devm_kzalloc(ctrl->dev, sizeof(*handle), GFP_KERNEL);
445 if (!handle)
446 return -ENOMEM;
447
448 rc = qmi_handle_init(handle, SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN,
449 NULL, qcom_slim_qmi_msg_handlers);
450 if (rc < 0) {
451 dev_err(ctrl->dev, "QMI client init failed: %d\n", rc);
452 goto qmi_handle_init_failed;
453 }
454
455 rc = kernel_connect(handle->sock,
456 (struct sockaddr *)&ctrl->qmi.svc_info,
457 sizeof(ctrl->qmi.svc_info), 0);
458 if (rc < 0) {
459 dev_err(ctrl->dev, "Remote Service connect failed: %d\n", rc);
460 goto qmi_connect_to_service_failed;
461 }
462
463 /* Instance is 0 based */
464 req.instance = (ctrl->ngd->id >> 1);
465 req.mode_valid = 1;
466
467 /* Mode indicates the role of the ADSP */
468 if (apps_is_master)
469 req.mode = SLIMBUS_MODE_SATELLITE_V01;
470 else
471 req.mode = SLIMBUS_MODE_MASTER_V01;
472
473 ctrl->qmi.handle = handle;
474
475 rc = qcom_slim_qmi_send_select_inst_req(ctrl, &req);
476 if (rc) {
477 dev_err(ctrl->dev, "failed to select h/w instance\n");
478 goto qmi_select_instance_failed;
479 }
480
481 return 0;
482
483qmi_select_instance_failed:
484 ctrl->qmi.handle = NULL;
485qmi_connect_to_service_failed:
486 qmi_handle_release(handle);
487qmi_handle_init_failed:
488 devm_kfree(ctrl->dev, handle);
489 return rc;
490}
491
492static void qcom_slim_qmi_exit(struct qcom_slim_ngd_ctrl *ctrl)
493{
494 if (!ctrl->qmi.handle)
495 return;
496
497 qmi_handle_release(ctrl->qmi.handle);
498 devm_kfree(ctrl->dev, ctrl->qmi.handle);
499 ctrl->qmi.handle = NULL;
500}
501
502static int qcom_slim_qmi_power_request(struct qcom_slim_ngd_ctrl *ctrl,
503 bool active)
504{
505 struct slimbus_power_req_msg_v01 req;
506
507 if (active)
508 req.pm_req = SLIMBUS_PM_ACTIVE_V01;
509 else
510 req.pm_req = SLIMBUS_PM_INACTIVE_V01;
511
512 req.resp_type_valid = 0;
513
514 return qcom_slim_qmi_send_power_request(ctrl, &req);
515}
516
517static u32 *qcom_slim_ngd_tx_msg_get(struct qcom_slim_ngd_ctrl *ctrl, int len,
518 struct completion *comp)
519{
520 struct qcom_slim_ngd_dma_desc *desc;
521 unsigned long flags;
522
523 spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
524
525 if ((ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM == ctrl->tx_head) {
526 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
527 return NULL;
528 }
529 desc = &ctrl->txdesc[ctrl->tx_tail];
530 desc->base = ctrl->tx_base + ctrl->tx_tail * SLIM_MSGQ_BUF_LEN;
531 desc->comp = comp;
532 ctrl->tx_tail = (ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM;
533
534 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
535
536 return desc->base;
537}
538
539static void qcom_slim_ngd_tx_msg_dma_cb(void *args)
540{
541 struct qcom_slim_ngd_dma_desc *desc = args;
542 struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl;
543 unsigned long flags;
544
545 spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
546
547 if (desc->comp) {
548 complete(desc->comp);
549 desc->comp = NULL;
550 }
551
552 ctrl->tx_head = (ctrl->tx_head + 1) % QCOM_SLIM_NGD_DESC_NUM;
553 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
554}
555
556static int qcom_slim_ngd_tx_msg_post(struct qcom_slim_ngd_ctrl *ctrl,
557 void *buf, int len)
558{
559 struct qcom_slim_ngd_dma_desc *desc;
560 unsigned long flags;
561 int index, offset;
562
563 spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
564 offset = buf - ctrl->tx_base;
565 index = offset/SLIM_MSGQ_BUF_LEN;
566
567 desc = &ctrl->txdesc[index];
568 desc->phys = ctrl->tx_phys_base + offset;
569 desc->base = ctrl->tx_base + offset;
570 desc->ctrl = ctrl;
571 len = (len + 3) & 0xfc;
572
573 desc->desc = dmaengine_prep_slave_single(ctrl->dma_tx_channel,
574 desc->phys, len,
575 DMA_MEM_TO_DEV,
576 DMA_PREP_INTERRUPT);
577 if (!desc->desc) {
578 dev_err(ctrl->dev, "unable to prepare channel\n");
579 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
580 return -EINVAL;
581 }
582
583 desc->desc->callback = qcom_slim_ngd_tx_msg_dma_cb;
584 desc->desc->callback_param = desc;
585 desc->desc->cookie = dmaengine_submit(desc->desc);
586 dma_async_issue_pending(ctrl->dma_tx_channel);
587 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
588
589 return 0;
590}
591
592static void qcom_slim_ngd_rx(struct qcom_slim_ngd_ctrl *ctrl, u8 *buf)
593{
594 u8 mc, mt, len;
595
596 mt = SLIM_HEADER_GET_MT(buf[0]);
597 len = SLIM_HEADER_GET_RL(buf[0]);
598 mc = SLIM_HEADER_GET_MC(buf[1]);
599
600 if (mc == SLIM_USR_MC_MASTER_CAPABILITY &&
601 mt == SLIM_MSG_MT_SRC_REFERRED_USER)
602 queue_work(ctrl->mwq, &ctrl->m_work);
603
604 if (mc == SLIM_MSG_MC_REPLY_INFORMATION ||
605 mc == SLIM_MSG_MC_REPLY_VALUE || (mc == SLIM_USR_MC_ADDR_REPLY &&
606 mt == SLIM_MSG_MT_SRC_REFERRED_USER) ||
607 (mc == SLIM_USR_MC_GENERIC_ACK &&
608 mt == SLIM_MSG_MT_SRC_REFERRED_USER)) {
609 slim_msg_response(&ctrl->ctrl, &buf[4], buf[3], len - 4);
610 pm_runtime_mark_last_busy(ctrl->dev);
611 }
612}
613
614static void qcom_slim_ngd_rx_msgq_cb(void *args)
615{
616 struct qcom_slim_ngd_dma_desc *desc = args;
617 struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl;
618
619 qcom_slim_ngd_rx(ctrl, (u8 *)desc->base);
620 /* Add descriptor back to the queue */
621 desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel,
622 desc->phys, SLIM_MSGQ_BUF_LEN,
623 DMA_DEV_TO_MEM,
624 DMA_PREP_INTERRUPT);
625 if (!desc->desc) {
626 dev_err(ctrl->dev, "Unable to prepare rx channel\n");
627 return;
628 }
629
630 desc->desc->callback = qcom_slim_ngd_rx_msgq_cb;
631 desc->desc->callback_param = desc;
632 desc->desc->cookie = dmaengine_submit(desc->desc);
633 dma_async_issue_pending(ctrl->dma_rx_channel);
634}
635
636static int qcom_slim_ngd_post_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
637{
638 struct qcom_slim_ngd_dma_desc *desc;
639 int i;
640
641 for (i = 0; i < QCOM_SLIM_NGD_DESC_NUM; i++) {
642 desc = &ctrl->rx_desc[i];
643 desc->phys = ctrl->rx_phys_base + i * SLIM_MSGQ_BUF_LEN;
644 desc->ctrl = ctrl;
645 desc->base = ctrl->rx_base + i * SLIM_MSGQ_BUF_LEN;
646 desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel,
647 desc->phys, SLIM_MSGQ_BUF_LEN,
648 DMA_DEV_TO_MEM,
649 DMA_PREP_INTERRUPT);
650 if (!desc->desc) {
651 dev_err(ctrl->dev, "Unable to prepare rx channel\n");
652 return -EINVAL;
653 }
654
655 desc->desc->callback = qcom_slim_ngd_rx_msgq_cb;
656 desc->desc->callback_param = desc;
657 desc->desc->cookie = dmaengine_submit(desc->desc);
658 }
659 dma_async_issue_pending(ctrl->dma_rx_channel);
660
661 return 0;
662}
663
664static int qcom_slim_ngd_init_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
665{
666 struct device *dev = ctrl->dev;
667 int ret, size;
668
669 ctrl->dma_rx_channel = dma_request_chan(dev, "rx");
670 if (IS_ERR(ctrl->dma_rx_channel)) {
671 dev_err(dev, "Failed to request RX dma channel");
672 ret = PTR_ERR(ctrl->dma_rx_channel);
673 ctrl->dma_rx_channel = NULL;
674 return ret;
675 }
676
677 size = QCOM_SLIM_NGD_DESC_NUM * SLIM_MSGQ_BUF_LEN;
678 ctrl->rx_base = dma_alloc_coherent(dev, size, &ctrl->rx_phys_base,
679 GFP_KERNEL);
680 if (!ctrl->rx_base) {
681 dev_err(dev, "dma_alloc_coherent failed\n");
682 ret = -ENOMEM;
683 goto rel_rx;
684 }
685
686 ret = qcom_slim_ngd_post_rx_msgq(ctrl);
687 if (ret) {
688 dev_err(dev, "post_rx_msgq() failed 0x%x\n", ret);
689 goto rx_post_err;
690 }
691
692 return 0;
693
694rx_post_err:
695 dma_free_coherent(dev, size, ctrl->rx_base, ctrl->rx_phys_base);
696rel_rx:
697 dma_release_channel(ctrl->dma_rx_channel);
698 return ret;
699}
700
701static int qcom_slim_ngd_init_tx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
702{
703 struct device *dev = ctrl->dev;
704 unsigned long flags;
705 int ret = 0;
706 int size;
707
708 ctrl->dma_tx_channel = dma_request_chan(dev, "tx");
709 if (IS_ERR(ctrl->dma_tx_channel)) {
710 dev_err(dev, "Failed to request TX dma channel");
711 ret = PTR_ERR(ctrl->dma_tx_channel);
712 ctrl->dma_tx_channel = NULL;
713 return ret;
714 }
715
716 size = ((QCOM_SLIM_NGD_DESC_NUM + 1) * SLIM_MSGQ_BUF_LEN);
717 ctrl->tx_base = dma_alloc_coherent(dev, size, &ctrl->tx_phys_base,
718 GFP_KERNEL);
719 if (!ctrl->tx_base) {
720 dev_err(dev, "dma_alloc_coherent failed\n");
721 ret = -EINVAL;
722 goto rel_tx;
723 }
724
725 spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
726 ctrl->tx_tail = 0;
727 ctrl->tx_head = 0;
728 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
729
730 return 0;
731rel_tx:
732 dma_release_channel(ctrl->dma_tx_channel);
733 return ret;
734}
735
736static int qcom_slim_ngd_init_dma(struct qcom_slim_ngd_ctrl *ctrl)
737{
738 int ret = 0;
739
740 ret = qcom_slim_ngd_init_rx_msgq(ctrl);
741 if (ret) {
742 dev_err(ctrl->dev, "rx dma init failed\n");
743 return ret;
744 }
745
746 ret = qcom_slim_ngd_init_tx_msgq(ctrl);
747 if (ret)
748 dev_err(ctrl->dev, "tx dma init failed\n");
749
750 return ret;
751}
752
753static irqreturn_t qcom_slim_ngd_interrupt(int irq, void *d)
754{
755 struct qcom_slim_ngd_ctrl *ctrl = d;
756 void __iomem *base = ctrl->ngd->base;
757 u32 stat = readl(base + NGD_INT_STAT);
758
759 if ((stat & NGD_INT_MSG_BUF_CONTE) ||
760 (stat & NGD_INT_MSG_TX_INVAL) || (stat & NGD_INT_DEV_ERR) ||
761 (stat & NGD_INT_TX_NACKED_2)) {
762 dev_err(ctrl->dev, "Error Interrupt received 0x%x\n", stat);
763 }
764
765 writel(stat, base + NGD_INT_CLR);
766
767 return IRQ_HANDLED;
768}
769
770static int qcom_slim_ngd_xfer_msg(struct slim_controller *sctrl,
771 struct slim_msg_txn *txn)
772{
773 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
774 DECLARE_COMPLETION_ONSTACK(tx_sent);
775 DECLARE_COMPLETION_ONSTACK(done);
776 int ret, timeout, i;
777 u8 wbuf[SLIM_MSGQ_BUF_LEN];
778 u8 rbuf[SLIM_MSGQ_BUF_LEN];
779 u32 *pbuf;
780 u8 *puc;
781 u8 la = txn->la;
782 bool usr_msg = false;
783
784 if (txn->mt == SLIM_MSG_MT_CORE &&
785 (txn->mc >= SLIM_MSG_MC_BEGIN_RECONFIGURATION &&
786 txn->mc <= SLIM_MSG_MC_RECONFIGURE_NOW))
787 return 0;
788
789 if (txn->dt == SLIM_MSG_DEST_ENUMADDR)
790 return -EPROTONOSUPPORT;
791
792 if (txn->msg->num_bytes > SLIM_MSGQ_BUF_LEN ||
793 txn->rl > SLIM_MSGQ_BUF_LEN) {
794 dev_err(ctrl->dev, "msg exceeds HW limit\n");
795 return -EINVAL;
796 }
797
798 pbuf = qcom_slim_ngd_tx_msg_get(ctrl, txn->rl, &tx_sent);
799 if (!pbuf) {
800 dev_err(ctrl->dev, "Message buffer unavailable\n");
801 return -ENOMEM;
802 }
803
804 if (txn->mt == SLIM_MSG_MT_CORE &&
805 (txn->mc == SLIM_MSG_MC_CONNECT_SOURCE ||
806 txn->mc == SLIM_MSG_MC_CONNECT_SINK ||
807 txn->mc == SLIM_MSG_MC_DISCONNECT_PORT)) {
808 txn->mt = SLIM_MSG_MT_DEST_REFERRED_USER;
809 switch (txn->mc) {
810 case SLIM_MSG_MC_CONNECT_SOURCE:
811 txn->mc = SLIM_USR_MC_CONNECT_SRC;
812 break;
813 case SLIM_MSG_MC_CONNECT_SINK:
814 txn->mc = SLIM_USR_MC_CONNECT_SINK;
815 break;
816 case SLIM_MSG_MC_DISCONNECT_PORT:
817 txn->mc = SLIM_USR_MC_DISCONNECT_PORT;
818 break;
819 default:
820 return -EINVAL;
821 }
822
823 usr_msg = true;
824 i = 0;
825 wbuf[i++] = txn->la;
826 la = SLIM_LA_MGR;
827 wbuf[i++] = txn->msg->wbuf[0];
828 if (txn->mc != SLIM_USR_MC_DISCONNECT_PORT)
829 wbuf[i++] = txn->msg->wbuf[1];
830
831 txn->comp = &done;
832 ret = slim_alloc_txn_tid(sctrl, txn);
833 if (ret) {
834 dev_err(ctrl->dev, "Unable to allocate TID\n");
835 return ret;
836 }
837
838 wbuf[i++] = txn->tid;
839
840 txn->msg->num_bytes = i;
841 txn->msg->wbuf = wbuf;
842 txn->msg->rbuf = rbuf;
843 txn->rl = txn->msg->num_bytes + 4;
844 }
845
846 /* HW expects length field to be excluded */
847 txn->rl--;
848 puc = (u8 *)pbuf;
849 *pbuf = 0;
850 if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) {
851 *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 0,
852 la);
853 puc += 3;
854 } else {
855 *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 1,
856 la);
857 puc += 2;
858 }
859
860 if (slim_tid_txn(txn->mt, txn->mc))
861 *(puc++) = txn->tid;
862
863 if (slim_ec_txn(txn->mt, txn->mc)) {
864 *(puc++) = (txn->ec & 0xFF);
865 *(puc++) = (txn->ec >> 8) & 0xFF;
866 }
867
868 if (txn->msg && txn->msg->wbuf)
869 memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes);
870
871 ret = qcom_slim_ngd_tx_msg_post(ctrl, pbuf, txn->rl);
872 if (ret)
873 return ret;
874
875 timeout = wait_for_completion_timeout(&tx_sent, HZ);
876 if (!timeout) {
877 dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
878 txn->mt);
879 return -ETIMEDOUT;
880 }
881
882 if (usr_msg) {
883 timeout = wait_for_completion_timeout(&done, HZ);
884 if (!timeout) {
885 dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x",
886 txn->mc, txn->mt);
887 return -ETIMEDOUT;
888 }
889 }
890
891 return 0;
892}
893
894static int qcom_slim_ngd_xfer_msg_sync(struct slim_controller *ctrl,
895 struct slim_msg_txn *txn)
896{
897 DECLARE_COMPLETION_ONSTACK(done);
898 int ret, timeout;
899
900 pm_runtime_get_sync(ctrl->dev);
901
902 txn->comp = &done;
903
904 ret = qcom_slim_ngd_xfer_msg(ctrl, txn);
905 if (ret)
906 return ret;
907
908 timeout = wait_for_completion_timeout(&done, HZ);
909 if (!timeout) {
910 dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
911 txn->mt);
912 return -ETIMEDOUT;
913 }
914 return 0;
915}
916
917static int qcom_slim_ngd_enable_stream(struct slim_stream_runtime *rt)
918{
919 struct slim_device *sdev = rt->dev;
920 struct slim_controller *ctrl = sdev->ctrl;
921 struct slim_val_inf msg = {0};
922 u8 wbuf[SLIM_MSGQ_BUF_LEN];
923 u8 rbuf[SLIM_MSGQ_BUF_LEN];
924 struct slim_msg_txn txn = {0,};
925 int i, ret;
926
927 txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER;
928 txn.dt = SLIM_MSG_DEST_LOGICALADDR;
929 txn.la = SLIM_LA_MGR;
930 txn.ec = 0;
931 txn.msg = &msg;
932 txn.msg->num_bytes = 0;
933 txn.msg->wbuf = wbuf;
934 txn.msg->rbuf = rbuf;
935
936 for (i = 0; i < rt->num_ports; i++) {
937 struct slim_port *port = &rt->ports[i];
938
939 if (txn.msg->num_bytes == 0) {
940 int seg_interval = SLIM_SLOTS_PER_SUPERFRAME/rt->ratem;
941 int exp;
942
943 wbuf[txn.msg->num_bytes++] = sdev->laddr;
944 wbuf[txn.msg->num_bytes] = rt->bps >> 2 |
945 (port->ch.aux_fmt << 6);
946
947 /* Data channel segment interval not multiple of 3 */
948 exp = seg_interval % 3;
949 if (exp)
950 wbuf[txn.msg->num_bytes] |= BIT(5);
951
952 txn.msg->num_bytes++;
953 wbuf[txn.msg->num_bytes++] = exp << 4 | rt->prot;
954
955 if (rt->prot == SLIM_PROTO_ISO)
956 wbuf[txn.msg->num_bytes++] =
957 port->ch.prrate |
958 SLIM_CHANNEL_CONTENT_FL;
959 else
960 wbuf[txn.msg->num_bytes++] = port->ch.prrate;
961
962 ret = slim_alloc_txn_tid(ctrl, &txn);
963 if (ret) {
964 dev_err(&sdev->dev, "Fail to allocate TID\n");
965 return -ENXIO;
966 }
967 wbuf[txn.msg->num_bytes++] = txn.tid;
968 }
969 wbuf[txn.msg->num_bytes++] = port->ch.id;
970 }
971
972 txn.mc = SLIM_USR_MC_DEF_ACT_CHAN;
973 txn.rl = txn.msg->num_bytes + 4;
974 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
975 if (ret) {
976 slim_free_txn_tid(ctrl, &txn);
977 dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc,
978 txn.mt);
979 return ret;
980 }
981
982 txn.mc = SLIM_USR_MC_RECONFIG_NOW;
983 txn.msg->num_bytes = 2;
984 wbuf[1] = sdev->laddr;
985 txn.rl = txn.msg->num_bytes + 4;
986
987 ret = slim_alloc_txn_tid(ctrl, &txn);
988 if (ret) {
989 dev_err(ctrl->dev, "Fail to allocate TID\n");
990 return ret;
991 }
992
993 wbuf[0] = txn.tid;
994 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
995 if (ret) {
996 slim_free_txn_tid(ctrl, &txn);
997 dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc,
998 txn.mt);
999 }
1000
1001 return ret;
1002}
1003
1004static int qcom_slim_ngd_get_laddr(struct slim_controller *ctrl,
1005 struct slim_eaddr *ea, u8 *laddr)
1006{
1007 struct slim_val_inf msg = {0};
1008 u8 failed_ea[6] = {0, 0, 0, 0, 0, 0};
1009 struct slim_msg_txn txn;
1010 u8 wbuf[10] = {0};
1011 u8 rbuf[10] = {0};
1012 int ret;
1013
1014 txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER;
1015 txn.dt = SLIM_MSG_DEST_LOGICALADDR;
1016 txn.la = SLIM_LA_MGR;
1017 txn.ec = 0;
1018
1019 txn.mc = SLIM_USR_MC_ADDR_QUERY;
1020 txn.rl = 11;
1021 txn.msg = &msg;
1022 txn.msg->num_bytes = 7;
1023 txn.msg->wbuf = wbuf;
1024 txn.msg->rbuf = rbuf;
1025
1026 ret = slim_alloc_txn_tid(ctrl, &txn);
1027 if (ret < 0)
1028 return ret;
1029
1030 wbuf[0] = (u8)txn.tid;
1031 memcpy(&wbuf[1], ea, sizeof(*ea));
1032
1033 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
1034 if (ret) {
1035 slim_free_txn_tid(ctrl, &txn);
1036 return ret;
1037 }
1038
1039 if (!memcmp(rbuf, failed_ea, 6))
1040 return -ENXIO;
1041
1042 *laddr = rbuf[6];
1043
1044 return ret;
1045}
1046
1047static int qcom_slim_ngd_exit_dma(struct qcom_slim_ngd_ctrl *ctrl)
1048{
1049 if (ctrl->dma_rx_channel) {
1050 dmaengine_terminate_sync(ctrl->dma_rx_channel);
1051 dma_release_channel(ctrl->dma_rx_channel);
1052 }
1053
1054 if (ctrl->dma_tx_channel) {
1055 dmaengine_terminate_sync(ctrl->dma_tx_channel);
1056 dma_release_channel(ctrl->dma_tx_channel);
1057 }
1058
1059 ctrl->dma_tx_channel = ctrl->dma_rx_channel = NULL;
1060
1061 return 0;
1062}
1063
1064static void qcom_slim_ngd_setup(struct qcom_slim_ngd_ctrl *ctrl)
1065{
1066 u32 cfg = readl_relaxed(ctrl->ngd->base);
1067
1068 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN)
1069 qcom_slim_ngd_init_dma(ctrl);
1070
1071 /* By default enable message queues */
1072 cfg |= NGD_CFG_RX_MSGQ_EN;
1073 cfg |= NGD_CFG_TX_MSGQ_EN;
1074
1075 /* Enable NGD if it's not already enabled*/
1076 if (!(cfg & NGD_CFG_ENABLE))
1077 cfg |= NGD_CFG_ENABLE;
1078
1079 writel_relaxed(cfg, ctrl->ngd->base);
1080}
1081
1082static int qcom_slim_ngd_power_up(struct qcom_slim_ngd_ctrl *ctrl)
1083{
1084 enum qcom_slim_ngd_state cur_state = ctrl->state;
1085 struct qcom_slim_ngd *ngd = ctrl->ngd;
1086 u32 laddr, rx_msgq;
1087 int timeout, ret = 0;
1088
1089 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) {
1090 timeout = wait_for_completion_timeout(&ctrl->qmi.qmi_comp, HZ);
1091 if (!timeout)
1092 return -EREMOTEIO;
1093 }
1094
1095 if (ctrl->state == QCOM_SLIM_NGD_CTRL_ASLEEP ||
1096 ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) {
1097 ret = qcom_slim_qmi_power_request(ctrl, true);
1098 if (ret) {
1099 dev_err(ctrl->dev, "SLIM QMI power request failed:%d\n",
1100 ret);
1101 return ret;
1102 }
1103 }
1104
1105 ctrl->ver = readl_relaxed(ctrl->base);
1106 /* Version info in 16 MSbits */
1107 ctrl->ver >>= 16;
1108
1109 laddr = readl_relaxed(ngd->base + NGD_STATUS);
1110 if (laddr & NGD_LADDR) {
1111 /*
1112 * external MDM restart case where ADSP itself was active framer
1113 * For example, modem restarted when playback was active
1114 */
1115 if (cur_state == QCOM_SLIM_NGD_CTRL_AWAKE) {
1116 dev_info(ctrl->dev, "Subsys restart: ADSP active framer\n");
1117 return 0;
1118 }
1119 return 0;
1120 }
1121
1122 writel_relaxed(DEF_NGD_INT_MASK, ngd->base + NGD_INT_EN);
1123 rx_msgq = readl_relaxed(ngd->base + NGD_RX_MSGQ_CFG);
1124
1125 writel_relaxed(rx_msgq|SLIM_RX_MSGQ_TIMEOUT_VAL,
1126 ngd->base + NGD_RX_MSGQ_CFG);
1127 qcom_slim_ngd_setup(ctrl);
1128
1129 timeout = wait_for_completion_timeout(&ctrl->reconf, HZ);
1130 if (!timeout) {
1131 dev_err(ctrl->dev, "capability exchange timed-out\n");
1132 return -ETIMEDOUT;
1133 }
1134
1135 return 0;
1136}
1137
1138static void qcom_slim_ngd_notify_slaves(struct qcom_slim_ngd_ctrl *ctrl)
1139{
1140 struct slim_device *sbdev;
1141 struct device_node *node;
1142
1143 for_each_child_of_node(ctrl->ngd->pdev->dev.of_node, node) {
1144 sbdev = of_slim_get_device(&ctrl->ctrl, node);
1145 if (!sbdev)
1146 continue;
1147
1148 if (slim_get_logical_addr(sbdev))
1149 dev_err(ctrl->dev, "Failed to get logical address\n");
1150 }
1151}
1152
1153static void qcom_slim_ngd_master_worker(struct work_struct *work)
1154{
1155 struct qcom_slim_ngd_ctrl *ctrl;
1156 struct slim_msg_txn txn;
1157 struct slim_val_inf msg = {0};
1158 int retries = 0;
1159 u8 wbuf[8];
1160 int ret = 0;
1161
1162 ctrl = container_of(work, struct qcom_slim_ngd_ctrl, m_work);
1163 txn.dt = SLIM_MSG_DEST_LOGICALADDR;
1164 txn.ec = 0;
1165 txn.mc = SLIM_USR_MC_REPORT_SATELLITE;
1166 txn.mt = SLIM_MSG_MT_SRC_REFERRED_USER;
1167 txn.la = SLIM_LA_MGR;
1168 wbuf[0] = SAT_MAGIC_LSB;
1169 wbuf[1] = SAT_MAGIC_MSB;
1170 wbuf[2] = SAT_MSG_VER;
1171 wbuf[3] = SAT_MSG_PROT;
1172 txn.msg = &msg;
1173 txn.msg->wbuf = wbuf;
1174 txn.msg->num_bytes = 4;
1175 txn.rl = 8;
1176
1177 dev_info(ctrl->dev, "SLIM SAT: Rcvd master capability\n");
1178
1179capability_retry:
1180 ret = qcom_slim_ngd_xfer_msg(&ctrl->ctrl, &txn);
1181 if (!ret) {
1182 if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP)
1183 complete(&ctrl->reconf);
1184 else
1185 dev_err(ctrl->dev, "unexpected state:%d\n",
1186 ctrl->state);
1187
1188 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN)
1189 qcom_slim_ngd_notify_slaves(ctrl);
1190
1191 } else if (ret == -EIO) {
1192 dev_err(ctrl->dev, "capability message NACKed, retrying\n");
1193 if (retries < INIT_MX_RETRIES) {
1194 msleep(DEF_RETRY_MS);
1195 retries++;
1196 goto capability_retry;
1197 }
1198 } else {
1199 dev_err(ctrl->dev, "SLIM: capability TX failed:%d\n", ret);
1200 }
1201}
1202
1203static int qcom_slim_ngd_runtime_resume(struct device *dev)
1204{
1205 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
1206 int ret = 0;
1207
1208 if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP)
1209 ret = qcom_slim_ngd_power_up(ctrl);
1210 if (ret) {
1211 /* Did SSR cause this power up failure */
1212 if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN)
1213 ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP;
1214 else
1215 dev_err(ctrl->dev, "HW wakeup attempt during SSR\n");
1216 } else {
1217 ctrl->state = QCOM_SLIM_NGD_CTRL_AWAKE;
1218 }
1219
1220 return 0;
1221}
1222
1223static int qcom_slim_ngd_enable(struct qcom_slim_ngd_ctrl *ctrl, bool enable)
1224{
1225 if (enable) {
1226 int ret = qcom_slim_qmi_init(ctrl, false);
1227
1228 if (ret) {
1229 dev_err(ctrl->dev, "qmi init fail, ret:%d, state:%d\n",
1230 ret, ctrl->state);
1231 return ret;
1232 }
1233 /* controller state should be in sync with framework state */
1234 complete(&ctrl->qmi.qmi_comp);
1235 if (!pm_runtime_enabled(ctrl->dev) ||
1236 !pm_runtime_suspended(ctrl->dev))
1237 qcom_slim_ngd_runtime_resume(ctrl->dev);
1238 else
1239 pm_runtime_resume(ctrl->dev);
1240 pm_runtime_mark_last_busy(ctrl->dev);
1241 pm_runtime_put(ctrl->dev);
1242
1243 ret = slim_register_controller(&ctrl->ctrl);
1244 if (ret) {
1245 dev_err(ctrl->dev, "error adding slim controller\n");
1246 return ret;
1247 }
1248
1249 dev_info(ctrl->dev, "SLIM controller Registered\n");
1250 } else {
1251 qcom_slim_qmi_exit(ctrl);
1252 slim_unregister_controller(&ctrl->ctrl);
1253 }
1254
1255 return 0;
1256}
1257
1258static int qcom_slim_ngd_qmi_new_server(struct qmi_handle *hdl,
1259 struct qmi_service *service)
1260{
1261 struct qcom_slim_ngd_qmi *qmi =
1262 container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl);
1263 struct qcom_slim_ngd_ctrl *ctrl =
1264 container_of(qmi, struct qcom_slim_ngd_ctrl, qmi);
1265
1266 qmi->svc_info.sq_family = AF_QIPCRTR;
1267 qmi->svc_info.sq_node = service->node;
1268 qmi->svc_info.sq_port = service->port;
1269
1270 qcom_slim_ngd_enable(ctrl, true);
1271
1272 return 0;
1273}
1274
1275static void qcom_slim_ngd_qmi_del_server(struct qmi_handle *hdl,
1276 struct qmi_service *service)
1277{
1278 struct qcom_slim_ngd_qmi *qmi =
1279 container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl);
1280
1281 qmi->svc_info.sq_node = 0;
1282 qmi->svc_info.sq_port = 0;
1283}
1284
1285static struct qmi_ops qcom_slim_ngd_qmi_svc_event_ops = {
1286 .new_server = qcom_slim_ngd_qmi_new_server,
1287 .del_server = qcom_slim_ngd_qmi_del_server,
1288};
1289
1290static int qcom_slim_ngd_qmi_svc_event_init(struct qcom_slim_ngd_ctrl *ctrl)
1291{
1292 struct qcom_slim_ngd_qmi *qmi = &ctrl->qmi;
1293 int ret;
1294
1295 ret = qmi_handle_init(&qmi->svc_event_hdl, 0,
1296 &qcom_slim_ngd_qmi_svc_event_ops, NULL);
1297 if (ret < 0) {
1298 dev_err(ctrl->dev, "qmi_handle_init failed: %d\n", ret);
1299 return ret;
1300 }
1301
1302 ret = qmi_add_lookup(&qmi->svc_event_hdl, SLIMBUS_QMI_SVC_ID,
1303 SLIMBUS_QMI_SVC_V1, SLIMBUS_QMI_INS_ID);
1304 if (ret < 0) {
1305 dev_err(ctrl->dev, "qmi_add_lookup failed: %d\n", ret);
1306 qmi_handle_release(&qmi->svc_event_hdl);
1307 }
1308 return ret;
1309}
1310
1311static void qcom_slim_ngd_qmi_svc_event_deinit(struct qcom_slim_ngd_qmi *qmi)
1312{
1313 qmi_handle_release(&qmi->svc_event_hdl);
1314}
1315
1316static struct platform_driver qcom_slim_ngd_driver;
1317#define QCOM_SLIM_NGD_DRV_NAME "qcom,slim-ngd"
1318
1319static const struct of_device_id qcom_slim_ngd_dt_match[] = {
1320 {
1321 .compatible = "qcom,slim-ngd-v1.5.0",
1322 .data = &ngd_v1_5_offset_info,
1323 },{
1324 .compatible = "qcom,slim-ngd-v2.1.0",
1325 .data = &ngd_v1_5_offset_info,
1326 },
1327 {}
1328};
1329
1330MODULE_DEVICE_TABLE(of, qcom_slim_ngd_dt_match);
1331
1332static int of_qcom_slim_ngd_register(struct device *parent,
1333 struct qcom_slim_ngd_ctrl *ctrl)
1334{
1335 const struct ngd_reg_offset_data *data;
1336 struct qcom_slim_ngd *ngd;
1337 const struct of_device_id *match;
1338 struct device_node *node;
1339 u32 id;
1340
1341 match = of_match_node(qcom_slim_ngd_dt_match, parent->of_node);
1342 data = match->data;
1343 for_each_available_child_of_node(parent->of_node, node) {
1344 if (of_property_read_u32(node, "reg", &id))
1345 continue;
1346
1347 ngd = kzalloc(sizeof(*ngd), GFP_KERNEL);
1348 if (!ngd) {
1349 of_node_put(node);
1350 return -ENOMEM;
1351 }
1352
1353 ngd->pdev = platform_device_alloc(QCOM_SLIM_NGD_DRV_NAME, id);
1354 if (!ngd->pdev) {
1355 kfree(ngd);
1356 of_node_put(node);
1357 return -ENOMEM;
1358 }
1359 ngd->id = id;
1360 ngd->pdev->dev.parent = parent;
1361 ngd->pdev->driver_override = QCOM_SLIM_NGD_DRV_NAME;
1362 ngd->pdev->dev.of_node = node;
1363 ctrl->ngd = ngd;
1364
1365 platform_device_add(ngd->pdev);
1366 ngd->base = ctrl->base + ngd->id * data->offset +
1367 (ngd->id - 1) * data->size;
1368
1369 return 0;
1370 }
1371
1372 return -ENODEV;
1373}
1374
1375static int qcom_slim_ngd_probe(struct platform_device *pdev)
1376{
1377 struct device *dev = &pdev->dev;
1378 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev->parent);
1379 int ret;
1380
1381 ctrl->ctrl.dev = dev;
1382
1383 platform_set_drvdata(pdev, ctrl);
1384 pm_runtime_use_autosuspend(dev);
1385 pm_runtime_set_autosuspend_delay(dev, QCOM_SLIM_NGD_AUTOSUSPEND);
1386 pm_runtime_set_suspended(dev);
1387 pm_runtime_enable(dev);
1388 pm_runtime_get_noresume(dev);
1389 ret = qcom_slim_ngd_qmi_svc_event_init(ctrl);
1390 if (ret) {
1391 dev_err(&pdev->dev, "QMI service registration failed:%d", ret);
1392 return ret;
1393 }
1394
1395 INIT_WORK(&ctrl->m_work, qcom_slim_ngd_master_worker);
1396 ctrl->mwq = create_singlethread_workqueue("ngd_master");
1397 if (!ctrl->mwq) {
1398 dev_err(&pdev->dev, "Failed to start master worker\n");
1399 ret = -ENOMEM;
1400 goto wq_err;
1401 }
1402
1403 return 0;
1404wq_err:
1405 qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi);
1406 if (ctrl->mwq)
1407 destroy_workqueue(ctrl->mwq);
1408
1409 return ret;
1410}
1411
1412static int qcom_slim_ngd_ctrl_probe(struct platform_device *pdev)
1413{
1414 struct device *dev = &pdev->dev;
1415 struct qcom_slim_ngd_ctrl *ctrl;
1416 struct resource *res;
1417 int ret;
1418
1419 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1420 if (!ctrl)
1421 return -ENOMEM;
1422
1423 dev_set_drvdata(dev, ctrl);
1424
1425 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1426 ctrl->base = devm_ioremap_resource(dev, res);
1427 if (IS_ERR(ctrl->base))
1428 return PTR_ERR(ctrl->base);
1429
1430 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1431 if (!res) {
1432 dev_err(&pdev->dev, "no slimbus IRQ resource\n");
1433 return -ENODEV;
1434 }
1435
1436 ret = devm_request_irq(dev, res->start, qcom_slim_ngd_interrupt,
1437 IRQF_TRIGGER_HIGH, "slim-ngd", ctrl);
1438 if (ret) {
1439 dev_err(&pdev->dev, "request IRQ failed\n");
1440 return ret;
1441 }
1442
1443 ctrl->dev = dev;
1444 ctrl->framer.rootfreq = SLIM_ROOT_FREQ >> 3;
1445 ctrl->framer.superfreq =
1446 ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8;
1447
1448 ctrl->ctrl.a_framer = &ctrl->framer;
1449 ctrl->ctrl.clkgear = SLIM_MAX_CLK_GEAR;
1450 ctrl->ctrl.get_laddr = qcom_slim_ngd_get_laddr;
1451 ctrl->ctrl.enable_stream = qcom_slim_ngd_enable_stream;
1452 ctrl->ctrl.xfer_msg = qcom_slim_ngd_xfer_msg;
1453 ctrl->ctrl.wakeup = NULL;
1454 ctrl->state = QCOM_SLIM_NGD_CTRL_DOWN;
1455
1456 spin_lock_init(&ctrl->tx_buf_lock);
1457 init_completion(&ctrl->reconf);
1458 init_completion(&ctrl->qmi.qmi_comp);
1459
1460 platform_driver_register(&qcom_slim_ngd_driver);
1461 return of_qcom_slim_ngd_register(dev, ctrl);
1462}
1463
1464static int qcom_slim_ngd_ctrl_remove(struct platform_device *pdev)
1465{
1466 platform_driver_unregister(&qcom_slim_ngd_driver);
1467
1468 return 0;
1469}
1470
1471static int qcom_slim_ngd_remove(struct platform_device *pdev)
1472{
1473 struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev);
1474
1475 pm_runtime_disable(&pdev->dev);
1476 qcom_slim_ngd_enable(ctrl, false);
1477 qcom_slim_ngd_exit_dma(ctrl);
1478 qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi);
1479 if (ctrl->mwq)
1480 destroy_workqueue(ctrl->mwq);
1481
1482 kfree(ctrl->ngd);
1483 ctrl->ngd = NULL;
1484 return 0;
1485}
1486
1487static int __maybe_unused qcom_slim_ngd_runtime_idle(struct device *dev)
1488{
1489 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
1490
1491 if (ctrl->state == QCOM_SLIM_NGD_CTRL_AWAKE)
1492 ctrl->state = QCOM_SLIM_NGD_CTRL_IDLE;
1493 pm_request_autosuspend(dev);
1494 return -EAGAIN;
1495}
1496
1497static int __maybe_unused qcom_slim_ngd_runtime_suspend(struct device *dev)
1498{
1499 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
1500 int ret = 0;
1501
1502 ret = qcom_slim_qmi_power_request(ctrl, false);
1503 if (ret && ret != -EBUSY)
1504 dev_info(ctrl->dev, "slim resource not idle:%d\n", ret);
1505 if (!ret || ret == -ETIMEDOUT)
1506 ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP;
1507
1508 return ret;
1509}
1510
1511static const struct dev_pm_ops qcom_slim_ngd_dev_pm_ops = {
1512 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1513 pm_runtime_force_resume)
1514 SET_RUNTIME_PM_OPS(
1515 qcom_slim_ngd_runtime_suspend,
1516 qcom_slim_ngd_runtime_resume,
1517 qcom_slim_ngd_runtime_idle
1518 )
1519};
1520
1521static struct platform_driver qcom_slim_ngd_ctrl_driver = {
1522 .probe = qcom_slim_ngd_ctrl_probe,
1523 .remove = qcom_slim_ngd_ctrl_remove,
1524 .driver = {
1525 .name = "qcom,slim-ngd-ctrl",
1526 .of_match_table = qcom_slim_ngd_dt_match,
1527 },
1528};
1529
1530static struct platform_driver qcom_slim_ngd_driver = {
1531 .probe = qcom_slim_ngd_probe,
1532 .remove = qcom_slim_ngd_remove,
1533 .driver = {
1534 .name = QCOM_SLIM_NGD_DRV_NAME,
1535 .pm = &qcom_slim_ngd_dev_pm_ops,
1536 },
1537};
1538
1539module_platform_driver(qcom_slim_ngd_ctrl_driver);
1540MODULE_LICENSE("GPL v2");
1541MODULE_DESCRIPTION("Qualcomm SLIMBus NGD controller");
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
3// Copyright (c) 2018, Linaro Limited
4
5#include <linux/irq.h>
6#include <linux/kernel.h>
7#include <linux/init.h>
8#include <linux/slab.h>
9#include <linux/interrupt.h>
10#include <linux/platform_device.h>
11#include <linux/dma-mapping.h>
12#include <linux/dmaengine.h>
13#include <linux/slimbus.h>
14#include <linux/delay.h>
15#include <linux/pm_runtime.h>
16#include <linux/mutex.h>
17#include <linux/notifier.h>
18#include <linux/remoteproc/qcom_rproc.h>
19#include <linux/of.h>
20#include <linux/io.h>
21#include <linux/soc/qcom/qmi.h>
22#include <linux/soc/qcom/pdr.h>
23#include <net/sock.h>
24#include "slimbus.h"
25
26/* NGD (Non-ported Generic Device) registers */
27#define NGD_CFG 0x0
28#define NGD_CFG_ENABLE BIT(0)
29#define NGD_CFG_RX_MSGQ_EN BIT(1)
30#define NGD_CFG_TX_MSGQ_EN BIT(2)
31#define NGD_STATUS 0x4
32#define NGD_LADDR BIT(1)
33#define NGD_RX_MSGQ_CFG 0x8
34#define NGD_INT_EN 0x10
35#define NGD_INT_RECFG_DONE BIT(24)
36#define NGD_INT_TX_NACKED_2 BIT(25)
37#define NGD_INT_MSG_BUF_CONTE BIT(26)
38#define NGD_INT_MSG_TX_INVAL BIT(27)
39#define NGD_INT_IE_VE_CHG BIT(28)
40#define NGD_INT_DEV_ERR BIT(29)
41#define NGD_INT_RX_MSG_RCVD BIT(30)
42#define NGD_INT_TX_MSG_SENT BIT(31)
43#define NGD_INT_STAT 0x14
44#define NGD_INT_CLR 0x18
45#define DEF_NGD_INT_MASK (NGD_INT_TX_NACKED_2 | NGD_INT_MSG_BUF_CONTE | \
46 NGD_INT_MSG_TX_INVAL | NGD_INT_IE_VE_CHG | \
47 NGD_INT_DEV_ERR | NGD_INT_TX_MSG_SENT | \
48 NGD_INT_RX_MSG_RCVD)
49
50/* Slimbus QMI service */
51#define SLIMBUS_QMI_SVC_ID 0x0301
52#define SLIMBUS_QMI_SVC_V1 1
53#define SLIMBUS_QMI_INS_ID 0
54#define SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01 0x0020
55#define SLIMBUS_QMI_SELECT_INSTANCE_RESP_V01 0x0020
56#define SLIMBUS_QMI_POWER_REQ_V01 0x0021
57#define SLIMBUS_QMI_POWER_RESP_V01 0x0021
58#define SLIMBUS_QMI_CHECK_FRAMER_STATUS_REQ 0x0022
59#define SLIMBUS_QMI_CHECK_FRAMER_STATUS_RESP 0x0022
60#define SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN 14
61#define SLIMBUS_QMI_POWER_RESP_MAX_MSG_LEN 7
62#define SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN 14
63#define SLIMBUS_QMI_SELECT_INSTANCE_RESP_MAX_MSG_LEN 7
64#define SLIMBUS_QMI_CHECK_FRAMER_STAT_RESP_MAX_MSG_LEN 7
65/* QMI response timeout of 500ms */
66#define SLIMBUS_QMI_RESP_TOUT 1000
67
68/* User defined commands */
69#define SLIM_USR_MC_GENERIC_ACK 0x25
70#define SLIM_USR_MC_MASTER_CAPABILITY 0x0
71#define SLIM_USR_MC_REPORT_SATELLITE 0x1
72#define SLIM_USR_MC_ADDR_QUERY 0xD
73#define SLIM_USR_MC_ADDR_REPLY 0xE
74#define SLIM_USR_MC_DEFINE_CHAN 0x20
75#define SLIM_USR_MC_DEF_ACT_CHAN 0x21
76#define SLIM_USR_MC_CHAN_CTRL 0x23
77#define SLIM_USR_MC_RECONFIG_NOW 0x24
78#define SLIM_USR_MC_REQ_BW 0x28
79#define SLIM_USR_MC_CONNECT_SRC 0x2C
80#define SLIM_USR_MC_CONNECT_SINK 0x2D
81#define SLIM_USR_MC_DISCONNECT_PORT 0x2E
82#define SLIM_USR_MC_REPEAT_CHANGE_VALUE 0x0
83
84#define SLIM_RX_MSGQ_TIMEOUT_VAL 0x10000
85
86#define SLIM_LA_MGR 0xFF
87#define SLIM_ROOT_FREQ 24576000
88#define LADDR_RETRY 5
89
90/* Per spec.max 40 bytes per received message */
91#define SLIM_MSGQ_BUF_LEN 40
92#define QCOM_SLIM_NGD_DESC_NUM 32
93
94#define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \
95 ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16))
96
97#define INIT_MX_RETRIES 10
98#define DEF_RETRY_MS 10
99#define SAT_MAGIC_LSB 0xD9
100#define SAT_MAGIC_MSB 0xC5
101#define SAT_MSG_VER 0x1
102#define SAT_MSG_PROT 0x1
103#define to_ngd(d) container_of(d, struct qcom_slim_ngd, dev)
104
105struct ngd_reg_offset_data {
106 u32 offset, size;
107};
108
109static const struct ngd_reg_offset_data ngd_v1_5_offset_info = {
110 .offset = 0x1000,
111 .size = 0x1000,
112};
113
114enum qcom_slim_ngd_state {
115 QCOM_SLIM_NGD_CTRL_AWAKE,
116 QCOM_SLIM_NGD_CTRL_IDLE,
117 QCOM_SLIM_NGD_CTRL_ASLEEP,
118 QCOM_SLIM_NGD_CTRL_DOWN,
119};
120
121struct qcom_slim_ngd_qmi {
122 struct qmi_handle qmi;
123 struct sockaddr_qrtr svc_info;
124 struct qmi_handle svc_event_hdl;
125 struct qmi_response_type_v01 resp;
126 struct qmi_handle *handle;
127 struct completion qmi_comp;
128};
129
130struct qcom_slim_ngd_ctrl;
131struct qcom_slim_ngd;
132
133struct qcom_slim_ngd_dma_desc {
134 struct dma_async_tx_descriptor *desc;
135 struct qcom_slim_ngd_ctrl *ctrl;
136 struct completion *comp;
137 dma_cookie_t cookie;
138 dma_addr_t phys;
139 void *base;
140};
141
142struct qcom_slim_ngd {
143 struct platform_device *pdev;
144 void __iomem *base;
145 int id;
146};
147
148struct qcom_slim_ngd_ctrl {
149 struct slim_framer framer;
150 struct slim_controller ctrl;
151 struct qcom_slim_ngd_qmi qmi;
152 struct qcom_slim_ngd *ngd;
153 struct device *dev;
154 void __iomem *base;
155 struct dma_chan *dma_rx_channel;
156 struct dma_chan *dma_tx_channel;
157 struct qcom_slim_ngd_dma_desc rx_desc[QCOM_SLIM_NGD_DESC_NUM];
158 struct qcom_slim_ngd_dma_desc txdesc[QCOM_SLIM_NGD_DESC_NUM];
159 struct completion reconf;
160 struct work_struct m_work;
161 struct work_struct ngd_up_work;
162 struct workqueue_struct *mwq;
163 struct completion qmi_up;
164 spinlock_t tx_buf_lock;
165 struct mutex tx_lock;
166 struct mutex ssr_lock;
167 struct notifier_block nb;
168 void *notifier;
169 struct pdr_handle *pdr;
170 enum qcom_slim_ngd_state state;
171 dma_addr_t rx_phys_base;
172 dma_addr_t tx_phys_base;
173 void *rx_base;
174 void *tx_base;
175 int tx_tail;
176 int tx_head;
177 u32 ver;
178};
179
180enum slimbus_mode_enum_type_v01 {
181 /* To force a 32 bit signed enum. Do not change or use*/
182 SLIMBUS_MODE_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
183 SLIMBUS_MODE_SATELLITE_V01 = 1,
184 SLIMBUS_MODE_MASTER_V01 = 2,
185 SLIMBUS_MODE_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
186};
187
188enum slimbus_pm_enum_type_v01 {
189 /* To force a 32 bit signed enum. Do not change or use*/
190 SLIMBUS_PM_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
191 SLIMBUS_PM_INACTIVE_V01 = 1,
192 SLIMBUS_PM_ACTIVE_V01 = 2,
193 SLIMBUS_PM_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
194};
195
196enum slimbus_resp_enum_type_v01 {
197 SLIMBUS_RESP_ENUM_TYPE_MIN_VAL_V01 = INT_MIN,
198 SLIMBUS_RESP_SYNCHRONOUS_V01 = 1,
199 SLIMBUS_RESP_ENUM_TYPE_MAX_VAL_V01 = INT_MAX,
200};
201
202struct slimbus_select_inst_req_msg_v01 {
203 uint32_t instance;
204 uint8_t mode_valid;
205 enum slimbus_mode_enum_type_v01 mode;
206};
207
208struct slimbus_select_inst_resp_msg_v01 {
209 struct qmi_response_type_v01 resp;
210};
211
212struct slimbus_power_req_msg_v01 {
213 enum slimbus_pm_enum_type_v01 pm_req;
214 uint8_t resp_type_valid;
215 enum slimbus_resp_enum_type_v01 resp_type;
216};
217
218struct slimbus_power_resp_msg_v01 {
219 struct qmi_response_type_v01 resp;
220};
221
222static const struct qmi_elem_info slimbus_select_inst_req_msg_v01_ei[] = {
223 {
224 .data_type = QMI_UNSIGNED_4_BYTE,
225 .elem_len = 1,
226 .elem_size = sizeof(uint32_t),
227 .array_type = NO_ARRAY,
228 .tlv_type = 0x01,
229 .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
230 instance),
231 .ei_array = NULL,
232 },
233 {
234 .data_type = QMI_OPT_FLAG,
235 .elem_len = 1,
236 .elem_size = sizeof(uint8_t),
237 .array_type = NO_ARRAY,
238 .tlv_type = 0x10,
239 .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
240 mode_valid),
241 .ei_array = NULL,
242 },
243 {
244 .data_type = QMI_UNSIGNED_4_BYTE,
245 .elem_len = 1,
246 .elem_size = sizeof(enum slimbus_mode_enum_type_v01),
247 .array_type = NO_ARRAY,
248 .tlv_type = 0x10,
249 .offset = offsetof(struct slimbus_select_inst_req_msg_v01,
250 mode),
251 .ei_array = NULL,
252 },
253 {
254 .data_type = QMI_EOTI,
255 .elem_len = 0,
256 .elem_size = 0,
257 .array_type = NO_ARRAY,
258 .tlv_type = 0x00,
259 .offset = 0,
260 .ei_array = NULL,
261 },
262};
263
264static const struct qmi_elem_info slimbus_select_inst_resp_msg_v01_ei[] = {
265 {
266 .data_type = QMI_STRUCT,
267 .elem_len = 1,
268 .elem_size = sizeof(struct qmi_response_type_v01),
269 .array_type = NO_ARRAY,
270 .tlv_type = 0x02,
271 .offset = offsetof(struct slimbus_select_inst_resp_msg_v01,
272 resp),
273 .ei_array = qmi_response_type_v01_ei,
274 },
275 {
276 .data_type = QMI_EOTI,
277 .elem_len = 0,
278 .elem_size = 0,
279 .array_type = NO_ARRAY,
280 .tlv_type = 0x00,
281 .offset = 0,
282 .ei_array = NULL,
283 },
284};
285
286static const struct qmi_elem_info slimbus_power_req_msg_v01_ei[] = {
287 {
288 .data_type = QMI_UNSIGNED_4_BYTE,
289 .elem_len = 1,
290 .elem_size = sizeof(enum slimbus_pm_enum_type_v01),
291 .array_type = NO_ARRAY,
292 .tlv_type = 0x01,
293 .offset = offsetof(struct slimbus_power_req_msg_v01,
294 pm_req),
295 .ei_array = NULL,
296 },
297 {
298 .data_type = QMI_OPT_FLAG,
299 .elem_len = 1,
300 .elem_size = sizeof(uint8_t),
301 .array_type = NO_ARRAY,
302 .tlv_type = 0x10,
303 .offset = offsetof(struct slimbus_power_req_msg_v01,
304 resp_type_valid),
305 },
306 {
307 .data_type = QMI_SIGNED_4_BYTE_ENUM,
308 .elem_len = 1,
309 .elem_size = sizeof(enum slimbus_resp_enum_type_v01),
310 .array_type = NO_ARRAY,
311 .tlv_type = 0x10,
312 .offset = offsetof(struct slimbus_power_req_msg_v01,
313 resp_type),
314 },
315 {
316 .data_type = QMI_EOTI,
317 .elem_len = 0,
318 .elem_size = 0,
319 .array_type = NO_ARRAY,
320 .tlv_type = 0x00,
321 .offset = 0,
322 .ei_array = NULL,
323 },
324};
325
326static const struct qmi_elem_info slimbus_power_resp_msg_v01_ei[] = {
327 {
328 .data_type = QMI_STRUCT,
329 .elem_len = 1,
330 .elem_size = sizeof(struct qmi_response_type_v01),
331 .array_type = NO_ARRAY,
332 .tlv_type = 0x02,
333 .offset = offsetof(struct slimbus_power_resp_msg_v01, resp),
334 .ei_array = qmi_response_type_v01_ei,
335 },
336 {
337 .data_type = QMI_EOTI,
338 .elem_len = 0,
339 .elem_size = 0,
340 .array_type = NO_ARRAY,
341 .tlv_type = 0x00,
342 .offset = 0,
343 .ei_array = NULL,
344 },
345};
346
347static int qcom_slim_qmi_send_select_inst_req(struct qcom_slim_ngd_ctrl *ctrl,
348 struct slimbus_select_inst_req_msg_v01 *req)
349{
350 struct slimbus_select_inst_resp_msg_v01 resp = { { 0, 0 } };
351 struct qmi_txn txn;
352 int rc;
353
354 rc = qmi_txn_init(ctrl->qmi.handle, &txn,
355 slimbus_select_inst_resp_msg_v01_ei, &resp);
356 if (rc < 0) {
357 dev_err(ctrl->dev, "QMI TXN init fail: %d\n", rc);
358 return rc;
359 }
360
361 rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn,
362 SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01,
363 SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN,
364 slimbus_select_inst_req_msg_v01_ei, req);
365 if (rc < 0) {
366 dev_err(ctrl->dev, "QMI send req fail %d\n", rc);
367 qmi_txn_cancel(&txn);
368 return rc;
369 }
370
371 rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT);
372 if (rc < 0) {
373 dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc);
374 return rc;
375 }
376 /* Check the response */
377 if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
378 dev_err(ctrl->dev, "QMI request failed 0x%x\n",
379 resp.resp.result);
380 return -EREMOTEIO;
381 }
382
383 return 0;
384}
385
386static void qcom_slim_qmi_power_resp_cb(struct qmi_handle *handle,
387 struct sockaddr_qrtr *sq,
388 struct qmi_txn *txn, const void *data)
389{
390 struct slimbus_power_resp_msg_v01 *resp;
391
392 resp = (struct slimbus_power_resp_msg_v01 *)data;
393 if (resp->resp.result != QMI_RESULT_SUCCESS_V01)
394 pr_err("QMI power request failed 0x%x\n",
395 resp->resp.result);
396
397 complete(&txn->completion);
398}
399
400static int qcom_slim_qmi_send_power_request(struct qcom_slim_ngd_ctrl *ctrl,
401 struct slimbus_power_req_msg_v01 *req)
402{
403 struct slimbus_power_resp_msg_v01 resp = { { 0, 0 } };
404 struct qmi_txn txn;
405 int rc;
406
407 rc = qmi_txn_init(ctrl->qmi.handle, &txn,
408 slimbus_power_resp_msg_v01_ei, &resp);
409
410 rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn,
411 SLIMBUS_QMI_POWER_REQ_V01,
412 SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN,
413 slimbus_power_req_msg_v01_ei, req);
414 if (rc < 0) {
415 dev_err(ctrl->dev, "QMI send req fail %d\n", rc);
416 qmi_txn_cancel(&txn);
417 return rc;
418 }
419
420 rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT);
421 if (rc < 0) {
422 dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc);
423 return rc;
424 }
425
426 /* Check the response */
427 if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
428 dev_err(ctrl->dev, "QMI request failed 0x%x\n",
429 resp.resp.result);
430 return -EREMOTEIO;
431 }
432
433 return 0;
434}
435
436static const struct qmi_msg_handler qcom_slim_qmi_msg_handlers[] = {
437 {
438 .type = QMI_RESPONSE,
439 .msg_id = SLIMBUS_QMI_POWER_RESP_V01,
440 .ei = slimbus_power_resp_msg_v01_ei,
441 .decoded_size = sizeof(struct slimbus_power_resp_msg_v01),
442 .fn = qcom_slim_qmi_power_resp_cb,
443 },
444 {}
445};
446
447static int qcom_slim_qmi_init(struct qcom_slim_ngd_ctrl *ctrl,
448 bool apps_is_master)
449{
450 struct slimbus_select_inst_req_msg_v01 req;
451 struct qmi_handle *handle;
452 int rc;
453
454 handle = devm_kzalloc(ctrl->dev, sizeof(*handle), GFP_KERNEL);
455 if (!handle)
456 return -ENOMEM;
457
458 rc = qmi_handle_init(handle, SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN,
459 NULL, qcom_slim_qmi_msg_handlers);
460 if (rc < 0) {
461 dev_err(ctrl->dev, "QMI client init failed: %d\n", rc);
462 goto qmi_handle_init_failed;
463 }
464
465 rc = kernel_connect(handle->sock,
466 (struct sockaddr *)&ctrl->qmi.svc_info,
467 sizeof(ctrl->qmi.svc_info), 0);
468 if (rc < 0) {
469 dev_err(ctrl->dev, "Remote Service connect failed: %d\n", rc);
470 goto qmi_connect_to_service_failed;
471 }
472
473 /* Instance is 0 based */
474 req.instance = (ctrl->ngd->id >> 1);
475 req.mode_valid = 1;
476
477 /* Mode indicates the role of the ADSP */
478 if (apps_is_master)
479 req.mode = SLIMBUS_MODE_SATELLITE_V01;
480 else
481 req.mode = SLIMBUS_MODE_MASTER_V01;
482
483 ctrl->qmi.handle = handle;
484
485 rc = qcom_slim_qmi_send_select_inst_req(ctrl, &req);
486 if (rc) {
487 dev_err(ctrl->dev, "failed to select h/w instance\n");
488 goto qmi_select_instance_failed;
489 }
490
491 return 0;
492
493qmi_select_instance_failed:
494 ctrl->qmi.handle = NULL;
495qmi_connect_to_service_failed:
496 qmi_handle_release(handle);
497qmi_handle_init_failed:
498 devm_kfree(ctrl->dev, handle);
499 return rc;
500}
501
502static void qcom_slim_qmi_exit(struct qcom_slim_ngd_ctrl *ctrl)
503{
504 if (!ctrl->qmi.handle)
505 return;
506
507 qmi_handle_release(ctrl->qmi.handle);
508 devm_kfree(ctrl->dev, ctrl->qmi.handle);
509 ctrl->qmi.handle = NULL;
510}
511
512static int qcom_slim_qmi_power_request(struct qcom_slim_ngd_ctrl *ctrl,
513 bool active)
514{
515 struct slimbus_power_req_msg_v01 req;
516
517 if (active)
518 req.pm_req = SLIMBUS_PM_ACTIVE_V01;
519 else
520 req.pm_req = SLIMBUS_PM_INACTIVE_V01;
521
522 req.resp_type_valid = 0;
523
524 return qcom_slim_qmi_send_power_request(ctrl, &req);
525}
526
527static u32 *qcom_slim_ngd_tx_msg_get(struct qcom_slim_ngd_ctrl *ctrl, int len,
528 struct completion *comp)
529{
530 struct qcom_slim_ngd_dma_desc *desc;
531 unsigned long flags;
532
533 spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
534
535 if ((ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM == ctrl->tx_head) {
536 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
537 return NULL;
538 }
539 desc = &ctrl->txdesc[ctrl->tx_tail];
540 desc->base = ctrl->tx_base + ctrl->tx_tail * SLIM_MSGQ_BUF_LEN;
541 desc->comp = comp;
542 ctrl->tx_tail = (ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM;
543
544 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
545
546 return desc->base;
547}
548
549static void qcom_slim_ngd_tx_msg_dma_cb(void *args)
550{
551 struct qcom_slim_ngd_dma_desc *desc = args;
552 struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl;
553 unsigned long flags;
554
555 spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
556
557 if (desc->comp) {
558 complete(desc->comp);
559 desc->comp = NULL;
560 }
561
562 ctrl->tx_head = (ctrl->tx_head + 1) % QCOM_SLIM_NGD_DESC_NUM;
563 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
564}
565
566static int qcom_slim_ngd_tx_msg_post(struct qcom_slim_ngd_ctrl *ctrl,
567 void *buf, int len)
568{
569 struct qcom_slim_ngd_dma_desc *desc;
570 unsigned long flags;
571 int index, offset;
572
573 spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
574 offset = buf - ctrl->tx_base;
575 index = offset/SLIM_MSGQ_BUF_LEN;
576
577 desc = &ctrl->txdesc[index];
578 desc->phys = ctrl->tx_phys_base + offset;
579 desc->base = ctrl->tx_base + offset;
580 desc->ctrl = ctrl;
581 len = (len + 3) & 0xfc;
582
583 desc->desc = dmaengine_prep_slave_single(ctrl->dma_tx_channel,
584 desc->phys, len,
585 DMA_MEM_TO_DEV,
586 DMA_PREP_INTERRUPT);
587 if (!desc->desc) {
588 dev_err(ctrl->dev, "unable to prepare channel\n");
589 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
590 return -EINVAL;
591 }
592
593 desc->desc->callback = qcom_slim_ngd_tx_msg_dma_cb;
594 desc->desc->callback_param = desc;
595 desc->desc->cookie = dmaengine_submit(desc->desc);
596 dma_async_issue_pending(ctrl->dma_tx_channel);
597 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
598
599 return 0;
600}
601
602static void qcom_slim_ngd_rx(struct qcom_slim_ngd_ctrl *ctrl, u8 *buf)
603{
604 u8 mc, mt, len;
605
606 mt = SLIM_HEADER_GET_MT(buf[0]);
607 len = SLIM_HEADER_GET_RL(buf[0]);
608 mc = SLIM_HEADER_GET_MC(buf[1]);
609
610 if (mc == SLIM_USR_MC_MASTER_CAPABILITY &&
611 mt == SLIM_MSG_MT_SRC_REFERRED_USER)
612 queue_work(ctrl->mwq, &ctrl->m_work);
613
614 if (mc == SLIM_MSG_MC_REPLY_INFORMATION ||
615 mc == SLIM_MSG_MC_REPLY_VALUE || (mc == SLIM_USR_MC_ADDR_REPLY &&
616 mt == SLIM_MSG_MT_SRC_REFERRED_USER) ||
617 (mc == SLIM_USR_MC_GENERIC_ACK &&
618 mt == SLIM_MSG_MT_SRC_REFERRED_USER)) {
619 slim_msg_response(&ctrl->ctrl, &buf[4], buf[3], len - 4);
620 pm_runtime_mark_last_busy(ctrl->ctrl.dev);
621 }
622}
623
624static void qcom_slim_ngd_rx_msgq_cb(void *args)
625{
626 struct qcom_slim_ngd_dma_desc *desc = args;
627 struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl;
628
629 qcom_slim_ngd_rx(ctrl, (u8 *)desc->base);
630 /* Add descriptor back to the queue */
631 desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel,
632 desc->phys, SLIM_MSGQ_BUF_LEN,
633 DMA_DEV_TO_MEM,
634 DMA_PREP_INTERRUPT);
635 if (!desc->desc) {
636 dev_err(ctrl->dev, "Unable to prepare rx channel\n");
637 return;
638 }
639
640 desc->desc->callback = qcom_slim_ngd_rx_msgq_cb;
641 desc->desc->callback_param = desc;
642 desc->desc->cookie = dmaengine_submit(desc->desc);
643 dma_async_issue_pending(ctrl->dma_rx_channel);
644}
645
646static int qcom_slim_ngd_post_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
647{
648 struct qcom_slim_ngd_dma_desc *desc;
649 int i;
650
651 for (i = 0; i < QCOM_SLIM_NGD_DESC_NUM; i++) {
652 desc = &ctrl->rx_desc[i];
653 desc->phys = ctrl->rx_phys_base + i * SLIM_MSGQ_BUF_LEN;
654 desc->ctrl = ctrl;
655 desc->base = ctrl->rx_base + i * SLIM_MSGQ_BUF_LEN;
656 desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel,
657 desc->phys, SLIM_MSGQ_BUF_LEN,
658 DMA_DEV_TO_MEM,
659 DMA_PREP_INTERRUPT);
660 if (!desc->desc) {
661 dev_err(ctrl->dev, "Unable to prepare rx channel\n");
662 return -EINVAL;
663 }
664
665 desc->desc->callback = qcom_slim_ngd_rx_msgq_cb;
666 desc->desc->callback_param = desc;
667 desc->desc->cookie = dmaengine_submit(desc->desc);
668 }
669 dma_async_issue_pending(ctrl->dma_rx_channel);
670
671 return 0;
672}
673
674static int qcom_slim_ngd_init_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
675{
676 struct device *dev = ctrl->dev;
677 int ret, size;
678
679 ctrl->dma_rx_channel = dma_request_chan(dev, "rx");
680 if (IS_ERR(ctrl->dma_rx_channel)) {
681 dev_err(dev, "Failed to request RX dma channel");
682 ret = PTR_ERR(ctrl->dma_rx_channel);
683 ctrl->dma_rx_channel = NULL;
684 return ret;
685 }
686
687 size = QCOM_SLIM_NGD_DESC_NUM * SLIM_MSGQ_BUF_LEN;
688 ctrl->rx_base = dma_alloc_coherent(dev, size, &ctrl->rx_phys_base,
689 GFP_KERNEL);
690 if (!ctrl->rx_base) {
691 ret = -ENOMEM;
692 goto rel_rx;
693 }
694
695 ret = qcom_slim_ngd_post_rx_msgq(ctrl);
696 if (ret) {
697 dev_err(dev, "post_rx_msgq() failed 0x%x\n", ret);
698 goto rx_post_err;
699 }
700
701 return 0;
702
703rx_post_err:
704 dma_free_coherent(dev, size, ctrl->rx_base, ctrl->rx_phys_base);
705rel_rx:
706 dma_release_channel(ctrl->dma_rx_channel);
707 return ret;
708}
709
710static int qcom_slim_ngd_init_tx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
711{
712 struct device *dev = ctrl->dev;
713 unsigned long flags;
714 int ret = 0;
715 int size;
716
717 ctrl->dma_tx_channel = dma_request_chan(dev, "tx");
718 if (IS_ERR(ctrl->dma_tx_channel)) {
719 dev_err(dev, "Failed to request TX dma channel");
720 ret = PTR_ERR(ctrl->dma_tx_channel);
721 ctrl->dma_tx_channel = NULL;
722 return ret;
723 }
724
725 size = ((QCOM_SLIM_NGD_DESC_NUM + 1) * SLIM_MSGQ_BUF_LEN);
726 ctrl->tx_base = dma_alloc_coherent(dev, size, &ctrl->tx_phys_base,
727 GFP_KERNEL);
728 if (!ctrl->tx_base) {
729 ret = -EINVAL;
730 goto rel_tx;
731 }
732
733 spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
734 ctrl->tx_tail = 0;
735 ctrl->tx_head = 0;
736 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
737
738 return 0;
739rel_tx:
740 dma_release_channel(ctrl->dma_tx_channel);
741 return ret;
742}
743
744static int qcom_slim_ngd_init_dma(struct qcom_slim_ngd_ctrl *ctrl)
745{
746 int ret = 0;
747
748 ret = qcom_slim_ngd_init_rx_msgq(ctrl);
749 if (ret) {
750 dev_err(ctrl->dev, "rx dma init failed\n");
751 return ret;
752 }
753
754 ret = qcom_slim_ngd_init_tx_msgq(ctrl);
755 if (ret)
756 dev_err(ctrl->dev, "tx dma init failed\n");
757
758 return ret;
759}
760
761static irqreturn_t qcom_slim_ngd_interrupt(int irq, void *d)
762{
763 struct qcom_slim_ngd_ctrl *ctrl = d;
764 void __iomem *base = ctrl->ngd->base;
765 u32 stat;
766
767 if (pm_runtime_suspended(ctrl->ctrl.dev)) {
768 dev_warn_once(ctrl->dev, "Interrupt received while suspended\n");
769 return IRQ_NONE;
770 }
771
772 stat = readl(base + NGD_INT_STAT);
773
774 if ((stat & NGD_INT_MSG_BUF_CONTE) ||
775 (stat & NGD_INT_MSG_TX_INVAL) || (stat & NGD_INT_DEV_ERR) ||
776 (stat & NGD_INT_TX_NACKED_2)) {
777 dev_err(ctrl->dev, "Error Interrupt received 0x%x\n", stat);
778 }
779
780 writel(stat, base + NGD_INT_CLR);
781
782 return IRQ_HANDLED;
783}
784
785static int qcom_slim_ngd_xfer_msg(struct slim_controller *sctrl,
786 struct slim_msg_txn *txn)
787{
788 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
789 DECLARE_COMPLETION_ONSTACK(tx_sent);
790 DECLARE_COMPLETION_ONSTACK(done);
791 int ret, i;
792 unsigned long time_left;
793 u8 wbuf[SLIM_MSGQ_BUF_LEN];
794 u8 rbuf[SLIM_MSGQ_BUF_LEN];
795 u32 *pbuf;
796 u8 *puc;
797 u8 la = txn->la;
798 bool usr_msg = false;
799
800 if (txn->mt == SLIM_MSG_MT_CORE &&
801 (txn->mc >= SLIM_MSG_MC_BEGIN_RECONFIGURATION &&
802 txn->mc <= SLIM_MSG_MC_RECONFIGURE_NOW))
803 return 0;
804
805 if (txn->dt == SLIM_MSG_DEST_ENUMADDR)
806 return -EPROTONOSUPPORT;
807
808 if (txn->msg->num_bytes > SLIM_MSGQ_BUF_LEN ||
809 txn->rl > SLIM_MSGQ_BUF_LEN) {
810 dev_err(ctrl->dev, "msg exceeds HW limit\n");
811 return -EINVAL;
812 }
813
814 pbuf = qcom_slim_ngd_tx_msg_get(ctrl, txn->rl, &tx_sent);
815 if (!pbuf) {
816 dev_err(ctrl->dev, "Message buffer unavailable\n");
817 return -ENOMEM;
818 }
819
820 if (txn->mt == SLIM_MSG_MT_CORE &&
821 (txn->mc == SLIM_MSG_MC_CONNECT_SOURCE ||
822 txn->mc == SLIM_MSG_MC_CONNECT_SINK ||
823 txn->mc == SLIM_MSG_MC_DISCONNECT_PORT)) {
824 txn->mt = SLIM_MSG_MT_DEST_REFERRED_USER;
825 switch (txn->mc) {
826 case SLIM_MSG_MC_CONNECT_SOURCE:
827 txn->mc = SLIM_USR_MC_CONNECT_SRC;
828 break;
829 case SLIM_MSG_MC_CONNECT_SINK:
830 txn->mc = SLIM_USR_MC_CONNECT_SINK;
831 break;
832 case SLIM_MSG_MC_DISCONNECT_PORT:
833 txn->mc = SLIM_USR_MC_DISCONNECT_PORT;
834 break;
835 default:
836 return -EINVAL;
837 }
838
839 usr_msg = true;
840 i = 0;
841 wbuf[i++] = txn->la;
842 la = SLIM_LA_MGR;
843 wbuf[i++] = txn->msg->wbuf[0];
844 if (txn->mc != SLIM_USR_MC_DISCONNECT_PORT)
845 wbuf[i++] = txn->msg->wbuf[1];
846
847 txn->comp = &done;
848 ret = slim_alloc_txn_tid(sctrl, txn);
849 if (ret) {
850 dev_err(ctrl->dev, "Unable to allocate TID\n");
851 return ret;
852 }
853
854 wbuf[i++] = txn->tid;
855
856 txn->msg->num_bytes = i;
857 txn->msg->wbuf = wbuf;
858 txn->msg->rbuf = rbuf;
859 txn->rl = txn->msg->num_bytes + 4;
860 }
861
862 /* HW expects length field to be excluded */
863 txn->rl--;
864 puc = (u8 *)pbuf;
865 *pbuf = 0;
866 if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) {
867 *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 0,
868 la);
869 puc += 3;
870 } else {
871 *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 1,
872 la);
873 puc += 2;
874 }
875
876 if (slim_tid_txn(txn->mt, txn->mc))
877 *(puc++) = txn->tid;
878
879 if (slim_ec_txn(txn->mt, txn->mc)) {
880 *(puc++) = (txn->ec & 0xFF);
881 *(puc++) = (txn->ec >> 8) & 0xFF;
882 }
883
884 if (txn->msg && txn->msg->wbuf)
885 memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes);
886
887 mutex_lock(&ctrl->tx_lock);
888 ret = qcom_slim_ngd_tx_msg_post(ctrl, pbuf, txn->rl);
889 if (ret) {
890 mutex_unlock(&ctrl->tx_lock);
891 return ret;
892 }
893
894 time_left = wait_for_completion_timeout(&tx_sent, HZ);
895 if (!time_left) {
896 dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
897 txn->mt);
898 mutex_unlock(&ctrl->tx_lock);
899 return -ETIMEDOUT;
900 }
901
902 if (usr_msg) {
903 time_left = wait_for_completion_timeout(&done, HZ);
904 if (!time_left) {
905 dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x",
906 txn->mc, txn->mt);
907 mutex_unlock(&ctrl->tx_lock);
908 return -ETIMEDOUT;
909 }
910 }
911
912 mutex_unlock(&ctrl->tx_lock);
913 return 0;
914}
915
916static int qcom_slim_ngd_xfer_msg_sync(struct slim_controller *ctrl,
917 struct slim_msg_txn *txn)
918{
919 DECLARE_COMPLETION_ONSTACK(done);
920 int ret;
921 unsigned long time_left;
922
923 ret = pm_runtime_get_sync(ctrl->dev);
924 if (ret < 0)
925 goto pm_put;
926
927 txn->comp = &done;
928
929 ret = qcom_slim_ngd_xfer_msg(ctrl, txn);
930 if (ret)
931 goto pm_put;
932
933 time_left = wait_for_completion_timeout(&done, HZ);
934 if (!time_left) {
935 dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
936 txn->mt);
937 ret = -ETIMEDOUT;
938 goto pm_put;
939 }
940 return 0;
941
942pm_put:
943 pm_runtime_put(ctrl->dev);
944
945 return ret;
946}
947
948static int qcom_slim_calc_coef(struct slim_stream_runtime *rt, int *exp)
949{
950 struct slim_controller *ctrl = rt->dev->ctrl;
951 int coef;
952
953 if (rt->ratem * ctrl->a_framer->superfreq < rt->rate)
954 rt->ratem++;
955
956 coef = rt->ratem;
957 *exp = 0;
958
959 /*
960 * CRM = Cx(2^E) is the formula we are using.
961 * Here C is the coffecient and E is the exponent.
962 * CRM is the Channel Rate Multiplier.
963 * Coefficeint should be either 1 or 3 and exponenet
964 * should be an integer between 0 to 9, inclusive.
965 */
966 while (1) {
967 while ((coef & 0x1) != 0x1) {
968 coef >>= 1;
969 *exp = *exp + 1;
970 }
971
972 if (coef <= 3)
973 break;
974
975 coef++;
976 }
977
978 /*
979 * we rely on the coef value (1 or 3) to set a bit
980 * in the slimbus message packet. This bit is
981 * BIT(5) which is the segment rate coefficient.
982 */
983 if (coef == 1) {
984 if (*exp > 9)
985 return -EIO;
986 coef = 0;
987 } else {
988 if (*exp > 8)
989 return -EIO;
990 coef = 1;
991 }
992
993 return coef;
994}
995
996static int qcom_slim_ngd_enable_stream(struct slim_stream_runtime *rt)
997{
998 struct slim_device *sdev = rt->dev;
999 struct slim_controller *ctrl = sdev->ctrl;
1000 struct slim_val_inf msg = {0};
1001 u8 wbuf[SLIM_MSGQ_BUF_LEN];
1002 u8 rbuf[SLIM_MSGQ_BUF_LEN];
1003 struct slim_msg_txn txn = {0,};
1004 int i, ret;
1005
1006 txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER;
1007 txn.dt = SLIM_MSG_DEST_LOGICALADDR;
1008 txn.la = SLIM_LA_MGR;
1009 txn.ec = 0;
1010 txn.msg = &msg;
1011 txn.msg->num_bytes = 0;
1012 txn.msg->wbuf = wbuf;
1013 txn.msg->rbuf = rbuf;
1014
1015 for (i = 0; i < rt->num_ports; i++) {
1016 struct slim_port *port = &rt->ports[i];
1017
1018 if (txn.msg->num_bytes == 0) {
1019 int exp = 0, coef = 0;
1020
1021 wbuf[txn.msg->num_bytes++] = sdev->laddr;
1022 wbuf[txn.msg->num_bytes] = rt->bps >> 2 |
1023 (port->ch.aux_fmt << 6);
1024
1025 /* calculate coef dynamically */
1026 coef = qcom_slim_calc_coef(rt, &exp);
1027 if (coef < 0) {
1028 dev_err(&sdev->dev,
1029 "%s: error calculating coef %d\n", __func__,
1030 coef);
1031 return -EIO;
1032 }
1033
1034 if (coef)
1035 wbuf[txn.msg->num_bytes] |= BIT(5);
1036
1037 txn.msg->num_bytes++;
1038 wbuf[txn.msg->num_bytes++] = exp << 4 | rt->prot;
1039
1040 if (rt->prot == SLIM_PROTO_ISO)
1041 wbuf[txn.msg->num_bytes++] =
1042 port->ch.prrate |
1043 SLIM_CHANNEL_CONTENT_FL;
1044 else
1045 wbuf[txn.msg->num_bytes++] = port->ch.prrate;
1046
1047 ret = slim_alloc_txn_tid(ctrl, &txn);
1048 if (ret) {
1049 dev_err(&sdev->dev, "Fail to allocate TID\n");
1050 return -ENXIO;
1051 }
1052 wbuf[txn.msg->num_bytes++] = txn.tid;
1053 }
1054 wbuf[txn.msg->num_bytes++] = port->ch.id;
1055 }
1056
1057 txn.mc = SLIM_USR_MC_DEF_ACT_CHAN;
1058 txn.rl = txn.msg->num_bytes + 4;
1059 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
1060 if (ret) {
1061 slim_free_txn_tid(ctrl, &txn);
1062 dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc,
1063 txn.mt);
1064 return ret;
1065 }
1066
1067 txn.mc = SLIM_USR_MC_RECONFIG_NOW;
1068 txn.msg->num_bytes = 2;
1069 wbuf[1] = sdev->laddr;
1070 txn.rl = txn.msg->num_bytes + 4;
1071
1072 ret = slim_alloc_txn_tid(ctrl, &txn);
1073 if (ret) {
1074 dev_err(ctrl->dev, "Fail to allocate TID\n");
1075 return ret;
1076 }
1077
1078 wbuf[0] = txn.tid;
1079 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
1080 if (ret) {
1081 slim_free_txn_tid(ctrl, &txn);
1082 dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc,
1083 txn.mt);
1084 }
1085
1086 return ret;
1087}
1088
1089static int qcom_slim_ngd_get_laddr(struct slim_controller *ctrl,
1090 struct slim_eaddr *ea, u8 *laddr)
1091{
1092 struct slim_val_inf msg = {0};
1093 u8 failed_ea[6] = {0, 0, 0, 0, 0, 0};
1094 struct slim_msg_txn txn;
1095 u8 wbuf[10] = {0};
1096 u8 rbuf[10] = {0};
1097 int ret;
1098
1099 txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER;
1100 txn.dt = SLIM_MSG_DEST_LOGICALADDR;
1101 txn.la = SLIM_LA_MGR;
1102 txn.ec = 0;
1103
1104 txn.mc = SLIM_USR_MC_ADDR_QUERY;
1105 txn.rl = 11;
1106 txn.msg = &msg;
1107 txn.msg->num_bytes = 7;
1108 txn.msg->wbuf = wbuf;
1109 txn.msg->rbuf = rbuf;
1110
1111 ret = slim_alloc_txn_tid(ctrl, &txn);
1112 if (ret < 0)
1113 return ret;
1114
1115 wbuf[0] = (u8)txn.tid;
1116 memcpy(&wbuf[1], ea, sizeof(*ea));
1117
1118 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
1119 if (ret) {
1120 slim_free_txn_tid(ctrl, &txn);
1121 return ret;
1122 }
1123
1124 if (!memcmp(rbuf, failed_ea, 6))
1125 return -ENXIO;
1126
1127 *laddr = rbuf[6];
1128
1129 return ret;
1130}
1131
1132static int qcom_slim_ngd_exit_dma(struct qcom_slim_ngd_ctrl *ctrl)
1133{
1134 if (ctrl->dma_rx_channel) {
1135 dmaengine_terminate_sync(ctrl->dma_rx_channel);
1136 dma_release_channel(ctrl->dma_rx_channel);
1137 }
1138
1139 if (ctrl->dma_tx_channel) {
1140 dmaengine_terminate_sync(ctrl->dma_tx_channel);
1141 dma_release_channel(ctrl->dma_tx_channel);
1142 }
1143
1144 ctrl->dma_tx_channel = ctrl->dma_rx_channel = NULL;
1145
1146 return 0;
1147}
1148
1149static void qcom_slim_ngd_setup(struct qcom_slim_ngd_ctrl *ctrl)
1150{
1151 u32 cfg = readl_relaxed(ctrl->ngd->base);
1152
1153 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN ||
1154 ctrl->state == QCOM_SLIM_NGD_CTRL_ASLEEP)
1155 qcom_slim_ngd_init_dma(ctrl);
1156
1157 /* By default enable message queues */
1158 cfg |= NGD_CFG_RX_MSGQ_EN;
1159 cfg |= NGD_CFG_TX_MSGQ_EN;
1160
1161 /* Enable NGD if it's not already enabled*/
1162 if (!(cfg & NGD_CFG_ENABLE))
1163 cfg |= NGD_CFG_ENABLE;
1164
1165 writel_relaxed(cfg, ctrl->ngd->base);
1166}
1167
1168static int qcom_slim_ngd_power_up(struct qcom_slim_ngd_ctrl *ctrl)
1169{
1170 enum qcom_slim_ngd_state cur_state = ctrl->state;
1171 struct qcom_slim_ngd *ngd = ctrl->ngd;
1172 u32 laddr, rx_msgq;
1173 int ret = 0;
1174 unsigned long time_left;
1175
1176 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) {
1177 time_left = wait_for_completion_timeout(&ctrl->qmi.qmi_comp, HZ);
1178 if (!time_left)
1179 return -EREMOTEIO;
1180 }
1181
1182 if (ctrl->state == QCOM_SLIM_NGD_CTRL_ASLEEP ||
1183 ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) {
1184 ret = qcom_slim_qmi_power_request(ctrl, true);
1185 if (ret) {
1186 dev_err(ctrl->dev, "SLIM QMI power request failed:%d\n",
1187 ret);
1188 return ret;
1189 }
1190 }
1191
1192 ctrl->ver = readl_relaxed(ctrl->base);
1193 /* Version info in 16 MSbits */
1194 ctrl->ver >>= 16;
1195
1196 laddr = readl_relaxed(ngd->base + NGD_STATUS);
1197 if (laddr & NGD_LADDR) {
1198 /*
1199 * external MDM restart case where ADSP itself was active framer
1200 * For example, modem restarted when playback was active
1201 */
1202 if (cur_state == QCOM_SLIM_NGD_CTRL_AWAKE) {
1203 dev_info(ctrl->dev, "Subsys restart: ADSP active framer\n");
1204 return 0;
1205 }
1206 qcom_slim_ngd_setup(ctrl);
1207 return 0;
1208 }
1209
1210 /*
1211 * Reinitialize only when registers are not retained or when enumeration
1212 * is lost for ngd.
1213 */
1214 reinit_completion(&ctrl->reconf);
1215
1216 writel_relaxed(DEF_NGD_INT_MASK, ngd->base + NGD_INT_EN);
1217 rx_msgq = readl_relaxed(ngd->base + NGD_RX_MSGQ_CFG);
1218
1219 writel_relaxed(rx_msgq|SLIM_RX_MSGQ_TIMEOUT_VAL,
1220 ngd->base + NGD_RX_MSGQ_CFG);
1221 qcom_slim_ngd_setup(ctrl);
1222
1223 time_left = wait_for_completion_timeout(&ctrl->reconf, HZ);
1224 if (!time_left) {
1225 dev_err(ctrl->dev, "capability exchange timed-out\n");
1226 return -ETIMEDOUT;
1227 }
1228
1229 return 0;
1230}
1231
1232static void qcom_slim_ngd_notify_slaves(struct qcom_slim_ngd_ctrl *ctrl)
1233{
1234 struct slim_device *sbdev;
1235 struct device_node *node;
1236
1237 for_each_child_of_node(ctrl->ngd->pdev->dev.of_node, node) {
1238 sbdev = of_slim_get_device(&ctrl->ctrl, node);
1239 if (!sbdev)
1240 continue;
1241
1242 if (slim_get_logical_addr(sbdev))
1243 dev_err(ctrl->dev, "Failed to get logical address\n");
1244 }
1245}
1246
1247static void qcom_slim_ngd_master_worker(struct work_struct *work)
1248{
1249 struct qcom_slim_ngd_ctrl *ctrl;
1250 struct slim_msg_txn txn;
1251 struct slim_val_inf msg = {0};
1252 int retries = 0;
1253 u8 wbuf[8];
1254 int ret = 0;
1255
1256 ctrl = container_of(work, struct qcom_slim_ngd_ctrl, m_work);
1257 txn.dt = SLIM_MSG_DEST_LOGICALADDR;
1258 txn.ec = 0;
1259 txn.mc = SLIM_USR_MC_REPORT_SATELLITE;
1260 txn.mt = SLIM_MSG_MT_SRC_REFERRED_USER;
1261 txn.la = SLIM_LA_MGR;
1262 wbuf[0] = SAT_MAGIC_LSB;
1263 wbuf[1] = SAT_MAGIC_MSB;
1264 wbuf[2] = SAT_MSG_VER;
1265 wbuf[3] = SAT_MSG_PROT;
1266 txn.msg = &msg;
1267 txn.msg->wbuf = wbuf;
1268 txn.msg->num_bytes = 4;
1269 txn.rl = 8;
1270
1271 dev_info(ctrl->dev, "SLIM SAT: Rcvd master capability\n");
1272
1273capability_retry:
1274 ret = qcom_slim_ngd_xfer_msg(&ctrl->ctrl, &txn);
1275 if (!ret) {
1276 if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP)
1277 complete(&ctrl->reconf);
1278 else
1279 dev_err(ctrl->dev, "unexpected state:%d\n",
1280 ctrl->state);
1281
1282 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN)
1283 qcom_slim_ngd_notify_slaves(ctrl);
1284
1285 } else if (ret == -EIO) {
1286 dev_err(ctrl->dev, "capability message NACKed, retrying\n");
1287 if (retries < INIT_MX_RETRIES) {
1288 msleep(DEF_RETRY_MS);
1289 retries++;
1290 goto capability_retry;
1291 }
1292 } else {
1293 dev_err(ctrl->dev, "SLIM: capability TX failed:%d\n", ret);
1294 }
1295}
1296
1297static int qcom_slim_ngd_update_device_status(struct device *dev, void *null)
1298{
1299 slim_report_absent(to_slim_device(dev));
1300
1301 return 0;
1302}
1303
1304static int qcom_slim_ngd_runtime_resume(struct device *dev)
1305{
1306 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
1307 int ret = 0;
1308
1309 if (!ctrl->qmi.handle)
1310 return 0;
1311
1312 if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP)
1313 ret = qcom_slim_ngd_power_up(ctrl);
1314 if (ret) {
1315 /* Did SSR cause this power up failure */
1316 if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN)
1317 ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP;
1318 else
1319 dev_err(ctrl->dev, "HW wakeup attempt during SSR\n");
1320 } else {
1321 ctrl->state = QCOM_SLIM_NGD_CTRL_AWAKE;
1322 }
1323
1324 return 0;
1325}
1326
1327static int qcom_slim_ngd_enable(struct qcom_slim_ngd_ctrl *ctrl, bool enable)
1328{
1329 if (enable) {
1330 int ret = qcom_slim_qmi_init(ctrl, false);
1331
1332 if (ret) {
1333 dev_err(ctrl->dev, "qmi init fail, ret:%d, state:%d\n",
1334 ret, ctrl->state);
1335 return ret;
1336 }
1337 /* controller state should be in sync with framework state */
1338 complete(&ctrl->qmi.qmi_comp);
1339 if (!pm_runtime_enabled(ctrl->ctrl.dev) ||
1340 !pm_runtime_suspended(ctrl->ctrl.dev))
1341 qcom_slim_ngd_runtime_resume(ctrl->ctrl.dev);
1342 else
1343 pm_runtime_resume(ctrl->ctrl.dev);
1344
1345 pm_runtime_mark_last_busy(ctrl->ctrl.dev);
1346 pm_runtime_put(ctrl->ctrl.dev);
1347
1348 ret = slim_register_controller(&ctrl->ctrl);
1349 if (ret) {
1350 dev_err(ctrl->dev, "error adding slim controller\n");
1351 return ret;
1352 }
1353
1354 dev_info(ctrl->dev, "SLIM controller Registered\n");
1355 } else {
1356 qcom_slim_qmi_exit(ctrl);
1357 slim_unregister_controller(&ctrl->ctrl);
1358 }
1359
1360 return 0;
1361}
1362
1363static int qcom_slim_ngd_qmi_new_server(struct qmi_handle *hdl,
1364 struct qmi_service *service)
1365{
1366 struct qcom_slim_ngd_qmi *qmi =
1367 container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl);
1368 struct qcom_slim_ngd_ctrl *ctrl =
1369 container_of(qmi, struct qcom_slim_ngd_ctrl, qmi);
1370
1371 qmi->svc_info.sq_family = AF_QIPCRTR;
1372 qmi->svc_info.sq_node = service->node;
1373 qmi->svc_info.sq_port = service->port;
1374
1375 complete(&ctrl->qmi_up);
1376
1377 return 0;
1378}
1379
1380static void qcom_slim_ngd_qmi_del_server(struct qmi_handle *hdl,
1381 struct qmi_service *service)
1382{
1383 struct qcom_slim_ngd_qmi *qmi =
1384 container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl);
1385 struct qcom_slim_ngd_ctrl *ctrl =
1386 container_of(qmi, struct qcom_slim_ngd_ctrl, qmi);
1387
1388 reinit_completion(&ctrl->qmi_up);
1389 qmi->svc_info.sq_node = 0;
1390 qmi->svc_info.sq_port = 0;
1391}
1392
1393static const struct qmi_ops qcom_slim_ngd_qmi_svc_event_ops = {
1394 .new_server = qcom_slim_ngd_qmi_new_server,
1395 .del_server = qcom_slim_ngd_qmi_del_server,
1396};
1397
1398static int qcom_slim_ngd_qmi_svc_event_init(struct qcom_slim_ngd_ctrl *ctrl)
1399{
1400 struct qcom_slim_ngd_qmi *qmi = &ctrl->qmi;
1401 int ret;
1402
1403 ret = qmi_handle_init(&qmi->svc_event_hdl, 0,
1404 &qcom_slim_ngd_qmi_svc_event_ops, NULL);
1405 if (ret < 0) {
1406 dev_err(ctrl->dev, "qmi_handle_init failed: %d\n", ret);
1407 return ret;
1408 }
1409
1410 ret = qmi_add_lookup(&qmi->svc_event_hdl, SLIMBUS_QMI_SVC_ID,
1411 SLIMBUS_QMI_SVC_V1, SLIMBUS_QMI_INS_ID);
1412 if (ret < 0) {
1413 dev_err(ctrl->dev, "qmi_add_lookup failed: %d\n", ret);
1414 qmi_handle_release(&qmi->svc_event_hdl);
1415 }
1416 return ret;
1417}
1418
1419static void qcom_slim_ngd_qmi_svc_event_deinit(struct qcom_slim_ngd_qmi *qmi)
1420{
1421 qmi_handle_release(&qmi->svc_event_hdl);
1422}
1423
1424static struct platform_driver qcom_slim_ngd_driver;
1425#define QCOM_SLIM_NGD_DRV_NAME "qcom,slim-ngd"
1426
1427static const struct of_device_id qcom_slim_ngd_dt_match[] = {
1428 {
1429 .compatible = "qcom,slim-ngd-v1.5.0",
1430 .data = &ngd_v1_5_offset_info,
1431 },{
1432 .compatible = "qcom,slim-ngd-v2.1.0",
1433 .data = &ngd_v1_5_offset_info,
1434 },
1435 {}
1436};
1437
1438MODULE_DEVICE_TABLE(of, qcom_slim_ngd_dt_match);
1439
1440static void qcom_slim_ngd_down(struct qcom_slim_ngd_ctrl *ctrl)
1441{
1442 mutex_lock(&ctrl->ssr_lock);
1443 device_for_each_child(ctrl->ctrl.dev, NULL,
1444 qcom_slim_ngd_update_device_status);
1445 qcom_slim_ngd_enable(ctrl, false);
1446 mutex_unlock(&ctrl->ssr_lock);
1447}
1448
1449static void qcom_slim_ngd_up_worker(struct work_struct *work)
1450{
1451 struct qcom_slim_ngd_ctrl *ctrl;
1452
1453 ctrl = container_of(work, struct qcom_slim_ngd_ctrl, ngd_up_work);
1454
1455 /* Make sure qmi service is up before continuing */
1456 if (!wait_for_completion_interruptible_timeout(&ctrl->qmi_up,
1457 msecs_to_jiffies(MSEC_PER_SEC))) {
1458 dev_err(ctrl->dev, "QMI wait timeout\n");
1459 return;
1460 }
1461
1462 mutex_lock(&ctrl->ssr_lock);
1463 qcom_slim_ngd_enable(ctrl, true);
1464 mutex_unlock(&ctrl->ssr_lock);
1465}
1466
1467static int qcom_slim_ngd_ssr_pdr_notify(struct qcom_slim_ngd_ctrl *ctrl,
1468 unsigned long action)
1469{
1470 switch (action) {
1471 case QCOM_SSR_BEFORE_SHUTDOWN:
1472 case SERVREG_SERVICE_STATE_DOWN:
1473 /* Make sure the last dma xfer is finished */
1474 mutex_lock(&ctrl->tx_lock);
1475 if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN) {
1476 pm_runtime_get_noresume(ctrl->ctrl.dev);
1477 ctrl->state = QCOM_SLIM_NGD_CTRL_DOWN;
1478 qcom_slim_ngd_down(ctrl);
1479 qcom_slim_ngd_exit_dma(ctrl);
1480 }
1481 mutex_unlock(&ctrl->tx_lock);
1482 break;
1483 case QCOM_SSR_AFTER_POWERUP:
1484 case SERVREG_SERVICE_STATE_UP:
1485 schedule_work(&ctrl->ngd_up_work);
1486 break;
1487 default:
1488 break;
1489 }
1490
1491 return NOTIFY_OK;
1492}
1493
1494static int qcom_slim_ngd_ssr_notify(struct notifier_block *nb,
1495 unsigned long action,
1496 void *data)
1497{
1498 struct qcom_slim_ngd_ctrl *ctrl = container_of(nb,
1499 struct qcom_slim_ngd_ctrl, nb);
1500
1501 return qcom_slim_ngd_ssr_pdr_notify(ctrl, action);
1502}
1503
1504static void slim_pd_status(int state, char *svc_path, void *priv)
1505{
1506 struct qcom_slim_ngd_ctrl *ctrl = (struct qcom_slim_ngd_ctrl *)priv;
1507
1508 qcom_slim_ngd_ssr_pdr_notify(ctrl, state);
1509}
1510static int of_qcom_slim_ngd_register(struct device *parent,
1511 struct qcom_slim_ngd_ctrl *ctrl)
1512{
1513 const struct ngd_reg_offset_data *data;
1514 struct qcom_slim_ngd *ngd;
1515 const struct of_device_id *match;
1516 struct device_node *node;
1517 u32 id;
1518 int ret;
1519
1520 match = of_match_node(qcom_slim_ngd_dt_match, parent->of_node);
1521 data = match->data;
1522 for_each_available_child_of_node(parent->of_node, node) {
1523 if (of_property_read_u32(node, "reg", &id))
1524 continue;
1525
1526 ngd = kzalloc(sizeof(*ngd), GFP_KERNEL);
1527 if (!ngd) {
1528 of_node_put(node);
1529 return -ENOMEM;
1530 }
1531
1532 ngd->pdev = platform_device_alloc(QCOM_SLIM_NGD_DRV_NAME, id);
1533 if (!ngd->pdev) {
1534 kfree(ngd);
1535 of_node_put(node);
1536 return -ENOMEM;
1537 }
1538 ngd->id = id;
1539 ngd->pdev->dev.parent = parent;
1540
1541 ret = driver_set_override(&ngd->pdev->dev,
1542 &ngd->pdev->driver_override,
1543 QCOM_SLIM_NGD_DRV_NAME,
1544 strlen(QCOM_SLIM_NGD_DRV_NAME));
1545 if (ret) {
1546 platform_device_put(ngd->pdev);
1547 kfree(ngd);
1548 of_node_put(node);
1549 return ret;
1550 }
1551 ngd->pdev->dev.of_node = node;
1552 ctrl->ngd = ngd;
1553
1554 ret = platform_device_add(ngd->pdev);
1555 if (ret) {
1556 platform_device_put(ngd->pdev);
1557 kfree(ngd);
1558 of_node_put(node);
1559 return ret;
1560 }
1561 ngd->base = ctrl->base + ngd->id * data->offset +
1562 (ngd->id - 1) * data->size;
1563
1564 return 0;
1565 }
1566
1567 return -ENODEV;
1568}
1569
1570static int qcom_slim_ngd_probe(struct platform_device *pdev)
1571{
1572 struct device *dev = &pdev->dev;
1573 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev->parent);
1574 int ret;
1575
1576 ctrl->ctrl.dev = dev;
1577
1578 platform_set_drvdata(pdev, ctrl);
1579 pm_runtime_use_autosuspend(dev);
1580 pm_runtime_set_autosuspend_delay(dev, 100);
1581 pm_runtime_set_suspended(dev);
1582 pm_runtime_enable(dev);
1583 pm_runtime_get_noresume(dev);
1584 ret = qcom_slim_ngd_qmi_svc_event_init(ctrl);
1585 if (ret) {
1586 dev_err(&pdev->dev, "QMI service registration failed:%d", ret);
1587 return ret;
1588 }
1589
1590 INIT_WORK(&ctrl->m_work, qcom_slim_ngd_master_worker);
1591 INIT_WORK(&ctrl->ngd_up_work, qcom_slim_ngd_up_worker);
1592 ctrl->mwq = create_singlethread_workqueue("ngd_master");
1593 if (!ctrl->mwq) {
1594 dev_err(&pdev->dev, "Failed to start master worker\n");
1595 ret = -ENOMEM;
1596 goto wq_err;
1597 }
1598
1599 return 0;
1600wq_err:
1601 qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi);
1602 if (ctrl->mwq)
1603 destroy_workqueue(ctrl->mwq);
1604
1605 return ret;
1606}
1607
1608static int qcom_slim_ngd_ctrl_probe(struct platform_device *pdev)
1609{
1610 struct device *dev = &pdev->dev;
1611 struct qcom_slim_ngd_ctrl *ctrl;
1612 int ret;
1613 struct pdr_service *pds;
1614
1615 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1616 if (!ctrl)
1617 return -ENOMEM;
1618
1619 dev_set_drvdata(dev, ctrl);
1620
1621 ctrl->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1622 if (IS_ERR(ctrl->base))
1623 return PTR_ERR(ctrl->base);
1624
1625 ret = platform_get_irq(pdev, 0);
1626 if (ret < 0)
1627 return ret;
1628
1629 ret = devm_request_irq(dev, ret, qcom_slim_ngd_interrupt,
1630 IRQF_TRIGGER_HIGH, "slim-ngd", ctrl);
1631 if (ret)
1632 return dev_err_probe(&pdev->dev, ret, "request IRQ failed\n");
1633
1634 ctrl->nb.notifier_call = qcom_slim_ngd_ssr_notify;
1635 ctrl->notifier = qcom_register_ssr_notifier("lpass", &ctrl->nb);
1636 if (IS_ERR(ctrl->notifier))
1637 return PTR_ERR(ctrl->notifier);
1638
1639 ctrl->dev = dev;
1640 ctrl->framer.rootfreq = SLIM_ROOT_FREQ >> 3;
1641 ctrl->framer.superfreq =
1642 ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8;
1643
1644 ctrl->ctrl.a_framer = &ctrl->framer;
1645 ctrl->ctrl.clkgear = SLIM_MAX_CLK_GEAR;
1646 ctrl->ctrl.get_laddr = qcom_slim_ngd_get_laddr;
1647 ctrl->ctrl.enable_stream = qcom_slim_ngd_enable_stream;
1648 ctrl->ctrl.xfer_msg = qcom_slim_ngd_xfer_msg;
1649 ctrl->ctrl.wakeup = NULL;
1650 ctrl->state = QCOM_SLIM_NGD_CTRL_DOWN;
1651
1652 mutex_init(&ctrl->tx_lock);
1653 mutex_init(&ctrl->ssr_lock);
1654 spin_lock_init(&ctrl->tx_buf_lock);
1655 init_completion(&ctrl->reconf);
1656 init_completion(&ctrl->qmi.qmi_comp);
1657 init_completion(&ctrl->qmi_up);
1658
1659 ctrl->pdr = pdr_handle_alloc(slim_pd_status, ctrl);
1660 if (IS_ERR(ctrl->pdr)) {
1661 ret = dev_err_probe(dev, PTR_ERR(ctrl->pdr),
1662 "Failed to init PDR handle\n");
1663 goto err_pdr_alloc;
1664 }
1665
1666 pds = pdr_add_lookup(ctrl->pdr, "avs/audio", "msm/adsp/audio_pd");
1667 if (IS_ERR(pds) && PTR_ERR(pds) != -EALREADY) {
1668 ret = dev_err_probe(dev, PTR_ERR(pds), "pdr add lookup failed\n");
1669 goto err_pdr_lookup;
1670 }
1671
1672 platform_driver_register(&qcom_slim_ngd_driver);
1673 return of_qcom_slim_ngd_register(dev, ctrl);
1674
1675err_pdr_alloc:
1676 qcom_unregister_ssr_notifier(ctrl->notifier, &ctrl->nb);
1677
1678err_pdr_lookup:
1679 pdr_handle_release(ctrl->pdr);
1680
1681 return ret;
1682}
1683
1684static void qcom_slim_ngd_ctrl_remove(struct platform_device *pdev)
1685{
1686 platform_driver_unregister(&qcom_slim_ngd_driver);
1687}
1688
1689static void qcom_slim_ngd_remove(struct platform_device *pdev)
1690{
1691 struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev);
1692
1693 pm_runtime_disable(&pdev->dev);
1694 pdr_handle_release(ctrl->pdr);
1695 qcom_unregister_ssr_notifier(ctrl->notifier, &ctrl->nb);
1696 qcom_slim_ngd_enable(ctrl, false);
1697 qcom_slim_ngd_exit_dma(ctrl);
1698 qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi);
1699 if (ctrl->mwq)
1700 destroy_workqueue(ctrl->mwq);
1701
1702 kfree(ctrl->ngd);
1703 ctrl->ngd = NULL;
1704}
1705
1706static int __maybe_unused qcom_slim_ngd_runtime_idle(struct device *dev)
1707{
1708 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
1709
1710 if (ctrl->state == QCOM_SLIM_NGD_CTRL_AWAKE)
1711 ctrl->state = QCOM_SLIM_NGD_CTRL_IDLE;
1712 pm_request_autosuspend(dev);
1713 return -EAGAIN;
1714}
1715
1716static int __maybe_unused qcom_slim_ngd_runtime_suspend(struct device *dev)
1717{
1718 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
1719 int ret = 0;
1720
1721 qcom_slim_ngd_exit_dma(ctrl);
1722 if (!ctrl->qmi.handle)
1723 return 0;
1724
1725 ret = qcom_slim_qmi_power_request(ctrl, false);
1726 if (ret && ret != -EBUSY)
1727 dev_info(ctrl->dev, "slim resource not idle:%d\n", ret);
1728 if (!ret || ret == -ETIMEDOUT)
1729 ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP;
1730
1731 return ret;
1732}
1733
1734static const struct dev_pm_ops qcom_slim_ngd_dev_pm_ops = {
1735 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1736 pm_runtime_force_resume)
1737 SET_RUNTIME_PM_OPS(
1738 qcom_slim_ngd_runtime_suspend,
1739 qcom_slim_ngd_runtime_resume,
1740 qcom_slim_ngd_runtime_idle
1741 )
1742};
1743
1744static struct platform_driver qcom_slim_ngd_ctrl_driver = {
1745 .probe = qcom_slim_ngd_ctrl_probe,
1746 .remove = qcom_slim_ngd_ctrl_remove,
1747 .driver = {
1748 .name = "qcom,slim-ngd-ctrl",
1749 .of_match_table = qcom_slim_ngd_dt_match,
1750 },
1751};
1752
1753static struct platform_driver qcom_slim_ngd_driver = {
1754 .probe = qcom_slim_ngd_probe,
1755 .remove = qcom_slim_ngd_remove,
1756 .driver = {
1757 .name = QCOM_SLIM_NGD_DRV_NAME,
1758 .pm = &qcom_slim_ngd_dev_pm_ops,
1759 },
1760};
1761
1762module_platform_driver(qcom_slim_ngd_ctrl_driver);
1763MODULE_LICENSE("GPL v2");
1764MODULE_DESCRIPTION("Qualcomm SLIMBus NGD controller");