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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek PCIe host controller driver.
4 *
5 * Copyright (c) 2017 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 * Honghui Zhang <honghui.zhang@mediatek.com>
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/iopoll.h>
13#include <linux/irq.h>
14#include <linux/irqchip/chained_irq.h>
15#include <linux/irqdomain.h>
16#include <linux/kernel.h>
17#include <linux/msi.h>
18#include <linux/module.h>
19#include <linux/of_address.h>
20#include <linux/of_pci.h>
21#include <linux/of_platform.h>
22#include <linux/pci.h>
23#include <linux/phy/phy.h>
24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/reset.h>
27
28#include "../pci.h"
29
30/* PCIe shared registers */
31#define PCIE_SYS_CFG 0x00
32#define PCIE_INT_ENABLE 0x0c
33#define PCIE_CFG_ADDR 0x20
34#define PCIE_CFG_DATA 0x24
35
36/* PCIe per port registers */
37#define PCIE_BAR0_SETUP 0x10
38#define PCIE_CLASS 0x34
39#define PCIE_LINK_STATUS 0x50
40
41#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
42#define PCIE_PORT_PERST(x) BIT(1 + (x))
43#define PCIE_PORT_LINKUP BIT(0)
44#define PCIE_BAR_MAP_MAX GENMASK(31, 16)
45
46#define PCIE_BAR_ENABLE BIT(0)
47#define PCIE_REVISION_ID BIT(0)
48#define PCIE_CLASS_CODE (0x60400 << 8)
49#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
50 ((((regn) >> 8) & GENMASK(3, 0)) << 24))
51#define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))
52#define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))
53#define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))
54#define PCIE_CONF_ADDR(regn, fun, dev, bus) \
55 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
56 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
57
58/* MediaTek specific configuration registers */
59#define PCIE_FTS_NUM 0x70c
60#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
61#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
62
63#define PCIE_FC_CREDIT 0x73c
64#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
65#define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
66
67/* PCIe V2 share registers */
68#define PCIE_SYS_CFG_V2 0x0
69#define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
70#define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
71
72/* PCIe V2 per-port registers */
73#define PCIE_MSI_VECTOR 0x0c0
74
75#define PCIE_CONF_VEND_ID 0x100
76#define PCIE_CONF_DEVICE_ID 0x102
77#define PCIE_CONF_CLASS_ID 0x106
78
79#define PCIE_INT_MASK 0x420
80#define INTX_MASK GENMASK(19, 16)
81#define INTX_SHIFT 16
82#define PCIE_INT_STATUS 0x424
83#define MSI_STATUS BIT(23)
84#define PCIE_IMSI_STATUS 0x42c
85#define PCIE_IMSI_ADDR 0x430
86#define MSI_MASK BIT(23)
87#define MTK_MSI_IRQS_NUM 32
88
89#define PCIE_AHB_TRANS_BASE0_L 0x438
90#define PCIE_AHB_TRANS_BASE0_H 0x43c
91#define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
92#define PCIE_AXI_WINDOW0 0x448
93#define WIN_ENABLE BIT(7)
94/*
95 * Define PCIe to AHB window size as 2^33 to support max 8GB address space
96 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
97 * start from 0x40000000).
98 */
99#define PCIE2AHB_SIZE 0x21
100
101/* PCIe V2 configuration transaction header */
102#define PCIE_CFG_HEADER0 0x460
103#define PCIE_CFG_HEADER1 0x464
104#define PCIE_CFG_HEADER2 0x468
105#define PCIE_CFG_WDATA 0x470
106#define PCIE_APP_TLP_REQ 0x488
107#define PCIE_CFG_RDATA 0x48c
108#define APP_CFG_REQ BIT(0)
109#define APP_CPL_STATUS GENMASK(7, 5)
110
111#define CFG_WRRD_TYPE_0 4
112#define CFG_WR_FMT 2
113#define CFG_RD_FMT 0
114
115#define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
116#define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
117#define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
118#define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
119#define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
120#define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
121#define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
122#define CFG_HEADER_DW0(type, fmt) \
123 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
124#define CFG_HEADER_DW1(where, size) \
125 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
126#define CFG_HEADER_DW2(regn, fun, dev, bus) \
127 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
128 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
129
130#define PCIE_RST_CTRL 0x510
131#define PCIE_PHY_RSTB BIT(0)
132#define PCIE_PIPE_SRSTB BIT(1)
133#define PCIE_MAC_SRSTB BIT(2)
134#define PCIE_CRSTB BIT(3)
135#define PCIE_PERSTB BIT(8)
136#define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
137#define PCIE_LINK_STATUS_V2 0x804
138#define PCIE_PORT_LINKUP_V2 BIT(10)
139
140struct mtk_pcie_port;
141
142/**
143 * struct mtk_pcie_soc - differentiate between host generations
144 * @need_fix_class_id: whether this host's class ID needed to be fixed or not
145 * @need_fix_device_id: whether this host's device ID needed to be fixed or not
146 * @device_id: device ID which this host need to be fixed
147 * @ops: pointer to configuration access functions
148 * @startup: pointer to controller setting functions
149 * @setup_irq: pointer to initialize IRQ functions
150 */
151struct mtk_pcie_soc {
152 bool need_fix_class_id;
153 bool need_fix_device_id;
154 unsigned int device_id;
155 struct pci_ops *ops;
156 int (*startup)(struct mtk_pcie_port *port);
157 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
158};
159
160/**
161 * struct mtk_pcie_port - PCIe port information
162 * @base: IO mapped register base
163 * @list: port list
164 * @pcie: pointer to PCIe host info
165 * @reset: pointer to port reset control
166 * @sys_ck: pointer to transaction/data link layer clock
167 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
168 * and RC initiated MMIO access
169 * @axi_ck: pointer to application layer MMIO channel operating clock
170 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
171 * when pcie_mac_ck/pcie_pipe_ck is turned off
172 * @obff_ck: pointer to OBFF functional block operating clock
173 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
174 * @phy: pointer to PHY control block
175 * @slot: port slot
176 * @irq: GIC irq
177 * @irq_domain: legacy INTx IRQ domain
178 * @inner_domain: inner IRQ domain
179 * @msi_domain: MSI IRQ domain
180 * @lock: protect the msi_irq_in_use bitmap
181 * @msi_irq_in_use: bit map for assigned MSI IRQ
182 */
183struct mtk_pcie_port {
184 void __iomem *base;
185 struct list_head list;
186 struct mtk_pcie *pcie;
187 struct reset_control *reset;
188 struct clk *sys_ck;
189 struct clk *ahb_ck;
190 struct clk *axi_ck;
191 struct clk *aux_ck;
192 struct clk *obff_ck;
193 struct clk *pipe_ck;
194 struct phy *phy;
195 u32 slot;
196 int irq;
197 struct irq_domain *irq_domain;
198 struct irq_domain *inner_domain;
199 struct irq_domain *msi_domain;
200 struct mutex lock;
201 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
202};
203
204/**
205 * struct mtk_pcie - PCIe host information
206 * @dev: pointer to PCIe device
207 * @base: IO mapped register base
208 * @free_ck: free-run reference clock
209 * @mem: non-prefetchable memory resource
210 * @ports: pointer to PCIe port information
211 * @soc: pointer to SoC-dependent operations
212 */
213struct mtk_pcie {
214 struct device *dev;
215 void __iomem *base;
216 struct clk *free_ck;
217
218 struct list_head ports;
219 const struct mtk_pcie_soc *soc;
220};
221
222static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
223{
224 struct device *dev = pcie->dev;
225
226 clk_disable_unprepare(pcie->free_ck);
227
228 pm_runtime_put_sync(dev);
229 pm_runtime_disable(dev);
230}
231
232static void mtk_pcie_port_free(struct mtk_pcie_port *port)
233{
234 struct mtk_pcie *pcie = port->pcie;
235 struct device *dev = pcie->dev;
236
237 devm_iounmap(dev, port->base);
238 list_del(&port->list);
239 devm_kfree(dev, port);
240}
241
242static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
243{
244 struct mtk_pcie_port *port, *tmp;
245
246 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
247 phy_power_off(port->phy);
248 phy_exit(port->phy);
249 clk_disable_unprepare(port->pipe_ck);
250 clk_disable_unprepare(port->obff_ck);
251 clk_disable_unprepare(port->axi_ck);
252 clk_disable_unprepare(port->aux_ck);
253 clk_disable_unprepare(port->ahb_ck);
254 clk_disable_unprepare(port->sys_ck);
255 mtk_pcie_port_free(port);
256 }
257
258 mtk_pcie_subsys_powerdown(pcie);
259}
260
261static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
262{
263 u32 val;
264 int err;
265
266 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
267 !(val & APP_CFG_REQ), 10,
268 100 * USEC_PER_MSEC);
269 if (err)
270 return PCIBIOS_SET_FAILED;
271
272 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
273 return PCIBIOS_SET_FAILED;
274
275 return PCIBIOS_SUCCESSFUL;
276}
277
278static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
279 int where, int size, u32 *val)
280{
281 u32 tmp;
282
283 /* Write PCIe configuration transaction header for Cfgrd */
284 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
285 port->base + PCIE_CFG_HEADER0);
286 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
287 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
288 port->base + PCIE_CFG_HEADER2);
289
290 /* Trigger h/w to transmit Cfgrd TLP */
291 tmp = readl(port->base + PCIE_APP_TLP_REQ);
292 tmp |= APP_CFG_REQ;
293 writel(tmp, port->base + PCIE_APP_TLP_REQ);
294
295 /* Check completion status */
296 if (mtk_pcie_check_cfg_cpld(port))
297 return PCIBIOS_SET_FAILED;
298
299 /* Read cpld payload of Cfgrd */
300 *val = readl(port->base + PCIE_CFG_RDATA);
301
302 if (size == 1)
303 *val = (*val >> (8 * (where & 3))) & 0xff;
304 else if (size == 2)
305 *val = (*val >> (8 * (where & 3))) & 0xffff;
306
307 return PCIBIOS_SUCCESSFUL;
308}
309
310static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
311 int where, int size, u32 val)
312{
313 /* Write PCIe configuration transaction header for Cfgwr */
314 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
315 port->base + PCIE_CFG_HEADER0);
316 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
317 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
318 port->base + PCIE_CFG_HEADER2);
319
320 /* Write Cfgwr data */
321 val = val << 8 * (where & 3);
322 writel(val, port->base + PCIE_CFG_WDATA);
323
324 /* Trigger h/w to transmit Cfgwr TLP */
325 val = readl(port->base + PCIE_APP_TLP_REQ);
326 val |= APP_CFG_REQ;
327 writel(val, port->base + PCIE_APP_TLP_REQ);
328
329 /* Check completion status */
330 return mtk_pcie_check_cfg_cpld(port);
331}
332
333static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
334 unsigned int devfn)
335{
336 struct mtk_pcie *pcie = bus->sysdata;
337 struct mtk_pcie_port *port;
338 struct pci_dev *dev = NULL;
339
340 /*
341 * Walk the bus hierarchy to get the devfn value
342 * of the port in the root bus.
343 */
344 while (bus && bus->number) {
345 dev = bus->self;
346 bus = dev->bus;
347 devfn = dev->devfn;
348 }
349
350 list_for_each_entry(port, &pcie->ports, list)
351 if (port->slot == PCI_SLOT(devfn))
352 return port;
353
354 return NULL;
355}
356
357static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
358 int where, int size, u32 *val)
359{
360 struct mtk_pcie_port *port;
361 u32 bn = bus->number;
362 int ret;
363
364 port = mtk_pcie_find_port(bus, devfn);
365 if (!port) {
366 *val = ~0;
367 return PCIBIOS_DEVICE_NOT_FOUND;
368 }
369
370 ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
371 if (ret)
372 *val = ~0;
373
374 return ret;
375}
376
377static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
378 int where, int size, u32 val)
379{
380 struct mtk_pcie_port *port;
381 u32 bn = bus->number;
382
383 port = mtk_pcie_find_port(bus, devfn);
384 if (!port)
385 return PCIBIOS_DEVICE_NOT_FOUND;
386
387 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
388}
389
390static struct pci_ops mtk_pcie_ops_v2 = {
391 .read = mtk_pcie_config_read,
392 .write = mtk_pcie_config_write,
393};
394
395static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
396{
397 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
398 phys_addr_t addr;
399
400 /* MT2712/MT7622 only support 32-bit MSI addresses */
401 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
402 msg->address_hi = 0;
403 msg->address_lo = lower_32_bits(addr);
404
405 msg->data = data->hwirq;
406
407 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",
408 (int)data->hwirq, msg->address_hi, msg->address_lo);
409}
410
411static int mtk_msi_set_affinity(struct irq_data *irq_data,
412 const struct cpumask *mask, bool force)
413{
414 return -EINVAL;
415}
416
417static void mtk_msi_ack_irq(struct irq_data *data)
418{
419 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
420 u32 hwirq = data->hwirq;
421
422 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
423}
424
425static struct irq_chip mtk_msi_bottom_irq_chip = {
426 .name = "MTK MSI",
427 .irq_compose_msi_msg = mtk_compose_msi_msg,
428 .irq_set_affinity = mtk_msi_set_affinity,
429 .irq_ack = mtk_msi_ack_irq,
430};
431
432static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
433 unsigned int nr_irqs, void *args)
434{
435 struct mtk_pcie_port *port = domain->host_data;
436 unsigned long bit;
437
438 WARN_ON(nr_irqs != 1);
439 mutex_lock(&port->lock);
440
441 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
442 if (bit >= MTK_MSI_IRQS_NUM) {
443 mutex_unlock(&port->lock);
444 return -ENOSPC;
445 }
446
447 __set_bit(bit, port->msi_irq_in_use);
448
449 mutex_unlock(&port->lock);
450
451 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,
452 domain->host_data, handle_edge_irq,
453 NULL, NULL);
454
455 return 0;
456}
457
458static void mtk_pcie_irq_domain_free(struct irq_domain *domain,
459 unsigned int virq, unsigned int nr_irqs)
460{
461 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
462 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);
463
464 mutex_lock(&port->lock);
465
466 if (!test_bit(d->hwirq, port->msi_irq_in_use))
467 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",
468 d->hwirq);
469 else
470 __clear_bit(d->hwirq, port->msi_irq_in_use);
471
472 mutex_unlock(&port->lock);
473
474 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
475}
476
477static const struct irq_domain_ops msi_domain_ops = {
478 .alloc = mtk_pcie_irq_domain_alloc,
479 .free = mtk_pcie_irq_domain_free,
480};
481
482static struct irq_chip mtk_msi_irq_chip = {
483 .name = "MTK PCIe MSI",
484 .irq_ack = irq_chip_ack_parent,
485 .irq_mask = pci_msi_mask_irq,
486 .irq_unmask = pci_msi_unmask_irq,
487};
488
489static struct msi_domain_info mtk_msi_domain_info = {
490 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
491 MSI_FLAG_PCI_MSIX),
492 .chip = &mtk_msi_irq_chip,
493};
494
495static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
496{
497 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);
498
499 mutex_init(&port->lock);
500
501 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,
502 &msi_domain_ops, port);
503 if (!port->inner_domain) {
504 dev_err(port->pcie->dev, "failed to create IRQ domain\n");
505 return -ENOMEM;
506 }
507
508 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,
509 port->inner_domain);
510 if (!port->msi_domain) {
511 dev_err(port->pcie->dev, "failed to create MSI domain\n");
512 irq_domain_remove(port->inner_domain);
513 return -ENOMEM;
514 }
515
516 return 0;
517}
518
519static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
520{
521 u32 val;
522 phys_addr_t msg_addr;
523
524 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
525 val = lower_32_bits(msg_addr);
526 writel(val, port->base + PCIE_IMSI_ADDR);
527
528 val = readl(port->base + PCIE_INT_MASK);
529 val &= ~MSI_MASK;
530 writel(val, port->base + PCIE_INT_MASK);
531}
532
533static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
534{
535 struct mtk_pcie_port *port, *tmp;
536
537 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
538 irq_set_chained_handler_and_data(port->irq, NULL, NULL);
539
540 if (port->irq_domain)
541 irq_domain_remove(port->irq_domain);
542
543 if (IS_ENABLED(CONFIG_PCI_MSI)) {
544 if (port->msi_domain)
545 irq_domain_remove(port->msi_domain);
546 if (port->inner_domain)
547 irq_domain_remove(port->inner_domain);
548 }
549
550 irq_dispose_mapping(port->irq);
551 }
552}
553
554static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
555 irq_hw_number_t hwirq)
556{
557 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
558 irq_set_chip_data(irq, domain->host_data);
559
560 return 0;
561}
562
563static const struct irq_domain_ops intx_domain_ops = {
564 .map = mtk_pcie_intx_map,
565};
566
567static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
568 struct device_node *node)
569{
570 struct device *dev = port->pcie->dev;
571 struct device_node *pcie_intc_node;
572 int ret;
573
574 /* Setup INTx */
575 pcie_intc_node = of_get_next_child(node, NULL);
576 if (!pcie_intc_node) {
577 dev_err(dev, "no PCIe Intc node found\n");
578 return -ENODEV;
579 }
580
581 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
582 &intx_domain_ops, port);
583 of_node_put(pcie_intc_node);
584 if (!port->irq_domain) {
585 dev_err(dev, "failed to get INTx IRQ domain\n");
586 return -ENODEV;
587 }
588
589 if (IS_ENABLED(CONFIG_PCI_MSI)) {
590 ret = mtk_pcie_allocate_msi_domains(port);
591 if (ret)
592 return ret;
593 }
594
595 return 0;
596}
597
598static void mtk_pcie_intr_handler(struct irq_desc *desc)
599{
600 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
601 struct irq_chip *irqchip = irq_desc_get_chip(desc);
602 unsigned long status;
603 u32 virq;
604 u32 bit = INTX_SHIFT;
605
606 chained_irq_enter(irqchip, desc);
607
608 status = readl(port->base + PCIE_INT_STATUS);
609 if (status & INTX_MASK) {
610 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
611 /* Clear the INTx */
612 writel(1 << bit, port->base + PCIE_INT_STATUS);
613 virq = irq_find_mapping(port->irq_domain,
614 bit - INTX_SHIFT);
615 generic_handle_irq(virq);
616 }
617 }
618
619 if (IS_ENABLED(CONFIG_PCI_MSI)) {
620 if (status & MSI_STATUS){
621 unsigned long imsi_status;
622
623 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
624 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
625 virq = irq_find_mapping(port->inner_domain, bit);
626 generic_handle_irq(virq);
627 }
628 }
629 /* Clear MSI interrupt status */
630 writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
631 }
632 }
633
634 chained_irq_exit(irqchip, desc);
635}
636
637static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
638 struct device_node *node)
639{
640 struct mtk_pcie *pcie = port->pcie;
641 struct device *dev = pcie->dev;
642 struct platform_device *pdev = to_platform_device(dev);
643 int err;
644
645 err = mtk_pcie_init_irq_domain(port, node);
646 if (err) {
647 dev_err(dev, "failed to init PCIe IRQ domain\n");
648 return err;
649 }
650
651 port->irq = platform_get_irq(pdev, port->slot);
652 if (port->irq < 0)
653 return port->irq;
654
655 irq_set_chained_handler_and_data(port->irq,
656 mtk_pcie_intr_handler, port);
657
658 return 0;
659}
660
661static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
662{
663 struct mtk_pcie *pcie = port->pcie;
664 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
665 struct resource *mem = NULL;
666 struct resource_entry *entry;
667 const struct mtk_pcie_soc *soc = port->pcie->soc;
668 u32 val;
669 int err;
670
671 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
672 if (entry)
673 mem = entry->res;
674 if (!mem)
675 return -EINVAL;
676
677 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
678 if (pcie->base) {
679 val = readl(pcie->base + PCIE_SYS_CFG_V2);
680 val |= PCIE_CSR_LTSSM_EN(port->slot) |
681 PCIE_CSR_ASPM_L1_EN(port->slot);
682 writel(val, pcie->base + PCIE_SYS_CFG_V2);
683 }
684
685 /* Assert all reset signals */
686 writel(0, port->base + PCIE_RST_CTRL);
687
688 /*
689 * Enable PCIe link down reset, if link status changed from link up to
690 * link down, this will reset MAC control registers and configuration
691 * space.
692 */
693 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
694
695 /* De-assert PHY, PE, PIPE, MAC and configuration reset */
696 val = readl(port->base + PCIE_RST_CTRL);
697 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
698 PCIE_MAC_SRSTB | PCIE_CRSTB;
699 writel(val, port->base + PCIE_RST_CTRL);
700
701 /* Set up vendor ID and class code */
702 if (soc->need_fix_class_id) {
703 val = PCI_VENDOR_ID_MEDIATEK;
704 writew(val, port->base + PCIE_CONF_VEND_ID);
705
706 val = PCI_CLASS_BRIDGE_PCI;
707 writew(val, port->base + PCIE_CONF_CLASS_ID);
708 }
709
710 if (soc->need_fix_device_id)
711 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
712
713 /* 100ms timeout value should be enough for Gen1/2 training */
714 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
715 !!(val & PCIE_PORT_LINKUP_V2), 20,
716 100 * USEC_PER_MSEC);
717 if (err)
718 return -ETIMEDOUT;
719
720 /* Set INTx mask */
721 val = readl(port->base + PCIE_INT_MASK);
722 val &= ~INTX_MASK;
723 writel(val, port->base + PCIE_INT_MASK);
724
725 if (IS_ENABLED(CONFIG_PCI_MSI))
726 mtk_pcie_enable_msi(port);
727
728 /* Set AHB to PCIe translation windows */
729 val = lower_32_bits(mem->start) |
730 AHB2PCIE_SIZE(fls(resource_size(mem)));
731 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
732
733 val = upper_32_bits(mem->start);
734 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
735
736 /* Set PCIe to AXI translation memory space.*/
737 val = PCIE2AHB_SIZE | WIN_ENABLE;
738 writel(val, port->base + PCIE_AXI_WINDOW0);
739
740 return 0;
741}
742
743static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
744 unsigned int devfn, int where)
745{
746 struct mtk_pcie *pcie = bus->sysdata;
747
748 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
749 bus->number), pcie->base + PCIE_CFG_ADDR);
750
751 return pcie->base + PCIE_CFG_DATA + (where & 3);
752}
753
754static struct pci_ops mtk_pcie_ops = {
755 .map_bus = mtk_pcie_map_bus,
756 .read = pci_generic_config_read,
757 .write = pci_generic_config_write,
758};
759
760static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
761{
762 struct mtk_pcie *pcie = port->pcie;
763 u32 func = PCI_FUNC(port->slot << 3);
764 u32 slot = PCI_SLOT(port->slot << 3);
765 u32 val;
766 int err;
767
768 /* assert port PERST_N */
769 val = readl(pcie->base + PCIE_SYS_CFG);
770 val |= PCIE_PORT_PERST(port->slot);
771 writel(val, pcie->base + PCIE_SYS_CFG);
772
773 /* de-assert port PERST_N */
774 val = readl(pcie->base + PCIE_SYS_CFG);
775 val &= ~PCIE_PORT_PERST(port->slot);
776 writel(val, pcie->base + PCIE_SYS_CFG);
777
778 /* 100ms timeout value should be enough for Gen1/2 training */
779 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
780 !!(val & PCIE_PORT_LINKUP), 20,
781 100 * USEC_PER_MSEC);
782 if (err)
783 return -ETIMEDOUT;
784
785 /* enable interrupt */
786 val = readl(pcie->base + PCIE_INT_ENABLE);
787 val |= PCIE_PORT_INT_EN(port->slot);
788 writel(val, pcie->base + PCIE_INT_ENABLE);
789
790 /* map to all DDR region. We need to set it before cfg operation. */
791 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
792 port->base + PCIE_BAR0_SETUP);
793
794 /* configure class code and revision ID */
795 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
796
797 /* configure FC credit */
798 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
799 pcie->base + PCIE_CFG_ADDR);
800 val = readl(pcie->base + PCIE_CFG_DATA);
801 val &= ~PCIE_FC_CREDIT_MASK;
802 val |= PCIE_FC_CREDIT_VAL(0x806c);
803 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
804 pcie->base + PCIE_CFG_ADDR);
805 writel(val, pcie->base + PCIE_CFG_DATA);
806
807 /* configure RC FTS number to 250 when it leaves L0s */
808 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
809 pcie->base + PCIE_CFG_ADDR);
810 val = readl(pcie->base + PCIE_CFG_DATA);
811 val &= ~PCIE_FTS_NUM_MASK;
812 val |= PCIE_FTS_NUM_L0(0x50);
813 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
814 pcie->base + PCIE_CFG_ADDR);
815 writel(val, pcie->base + PCIE_CFG_DATA);
816
817 return 0;
818}
819
820static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
821{
822 struct mtk_pcie *pcie = port->pcie;
823 struct device *dev = pcie->dev;
824 int err;
825
826 err = clk_prepare_enable(port->sys_ck);
827 if (err) {
828 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
829 goto err_sys_clk;
830 }
831
832 err = clk_prepare_enable(port->ahb_ck);
833 if (err) {
834 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
835 goto err_ahb_clk;
836 }
837
838 err = clk_prepare_enable(port->aux_ck);
839 if (err) {
840 dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
841 goto err_aux_clk;
842 }
843
844 err = clk_prepare_enable(port->axi_ck);
845 if (err) {
846 dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
847 goto err_axi_clk;
848 }
849
850 err = clk_prepare_enable(port->obff_ck);
851 if (err) {
852 dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
853 goto err_obff_clk;
854 }
855
856 err = clk_prepare_enable(port->pipe_ck);
857 if (err) {
858 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
859 goto err_pipe_clk;
860 }
861
862 reset_control_assert(port->reset);
863 reset_control_deassert(port->reset);
864
865 err = phy_init(port->phy);
866 if (err) {
867 dev_err(dev, "failed to initialize port%d phy\n", port->slot);
868 goto err_phy_init;
869 }
870
871 err = phy_power_on(port->phy);
872 if (err) {
873 dev_err(dev, "failed to power on port%d phy\n", port->slot);
874 goto err_phy_on;
875 }
876
877 if (!pcie->soc->startup(port))
878 return;
879
880 dev_info(dev, "Port%d link down\n", port->slot);
881
882 phy_power_off(port->phy);
883err_phy_on:
884 phy_exit(port->phy);
885err_phy_init:
886 clk_disable_unprepare(port->pipe_ck);
887err_pipe_clk:
888 clk_disable_unprepare(port->obff_ck);
889err_obff_clk:
890 clk_disable_unprepare(port->axi_ck);
891err_axi_clk:
892 clk_disable_unprepare(port->aux_ck);
893err_aux_clk:
894 clk_disable_unprepare(port->ahb_ck);
895err_ahb_clk:
896 clk_disable_unprepare(port->sys_ck);
897err_sys_clk:
898 mtk_pcie_port_free(port);
899}
900
901static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
902 struct device_node *node,
903 int slot)
904{
905 struct mtk_pcie_port *port;
906 struct device *dev = pcie->dev;
907 struct platform_device *pdev = to_platform_device(dev);
908 char name[10];
909 int err;
910
911 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
912 if (!port)
913 return -ENOMEM;
914
915 snprintf(name, sizeof(name), "port%d", slot);
916 port->base = devm_platform_ioremap_resource_byname(pdev, name);
917 if (IS_ERR(port->base)) {
918 dev_err(dev, "failed to map port%d base\n", slot);
919 return PTR_ERR(port->base);
920 }
921
922 snprintf(name, sizeof(name), "sys_ck%d", slot);
923 port->sys_ck = devm_clk_get(dev, name);
924 if (IS_ERR(port->sys_ck)) {
925 dev_err(dev, "failed to get sys_ck%d clock\n", slot);
926 return PTR_ERR(port->sys_ck);
927 }
928
929 /* sys_ck might be divided into the following parts in some chips */
930 snprintf(name, sizeof(name), "ahb_ck%d", slot);
931 port->ahb_ck = devm_clk_get_optional(dev, name);
932 if (IS_ERR(port->ahb_ck))
933 return PTR_ERR(port->ahb_ck);
934
935 snprintf(name, sizeof(name), "axi_ck%d", slot);
936 port->axi_ck = devm_clk_get_optional(dev, name);
937 if (IS_ERR(port->axi_ck))
938 return PTR_ERR(port->axi_ck);
939
940 snprintf(name, sizeof(name), "aux_ck%d", slot);
941 port->aux_ck = devm_clk_get_optional(dev, name);
942 if (IS_ERR(port->aux_ck))
943 return PTR_ERR(port->aux_ck);
944
945 snprintf(name, sizeof(name), "obff_ck%d", slot);
946 port->obff_ck = devm_clk_get_optional(dev, name);
947 if (IS_ERR(port->obff_ck))
948 return PTR_ERR(port->obff_ck);
949
950 snprintf(name, sizeof(name), "pipe_ck%d", slot);
951 port->pipe_ck = devm_clk_get_optional(dev, name);
952 if (IS_ERR(port->pipe_ck))
953 return PTR_ERR(port->pipe_ck);
954
955 snprintf(name, sizeof(name), "pcie-rst%d", slot);
956 port->reset = devm_reset_control_get_optional_exclusive(dev, name);
957 if (PTR_ERR(port->reset) == -EPROBE_DEFER)
958 return PTR_ERR(port->reset);
959
960 /* some platforms may use default PHY setting */
961 snprintf(name, sizeof(name), "pcie-phy%d", slot);
962 port->phy = devm_phy_optional_get(dev, name);
963 if (IS_ERR(port->phy))
964 return PTR_ERR(port->phy);
965
966 port->slot = slot;
967 port->pcie = pcie;
968
969 if (pcie->soc->setup_irq) {
970 err = pcie->soc->setup_irq(port, node);
971 if (err)
972 return err;
973 }
974
975 INIT_LIST_HEAD(&port->list);
976 list_add_tail(&port->list, &pcie->ports);
977
978 return 0;
979}
980
981static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
982{
983 struct device *dev = pcie->dev;
984 struct platform_device *pdev = to_platform_device(dev);
985 struct resource *regs;
986 int err;
987
988 /* get shared registers, which are optional */
989 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
990 if (regs) {
991 pcie->base = devm_ioremap_resource(dev, regs);
992 if (IS_ERR(pcie->base)) {
993 dev_err(dev, "failed to map shared register\n");
994 return PTR_ERR(pcie->base);
995 }
996 }
997
998 pcie->free_ck = devm_clk_get(dev, "free_ck");
999 if (IS_ERR(pcie->free_ck)) {
1000 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
1001 return -EPROBE_DEFER;
1002
1003 pcie->free_ck = NULL;
1004 }
1005
1006 pm_runtime_enable(dev);
1007 pm_runtime_get_sync(dev);
1008
1009 /* enable top level clock */
1010 err = clk_prepare_enable(pcie->free_ck);
1011 if (err) {
1012 dev_err(dev, "failed to enable free_ck\n");
1013 goto err_free_ck;
1014 }
1015
1016 return 0;
1017
1018err_free_ck:
1019 pm_runtime_put_sync(dev);
1020 pm_runtime_disable(dev);
1021
1022 return err;
1023}
1024
1025static int mtk_pcie_setup(struct mtk_pcie *pcie)
1026{
1027 struct device *dev = pcie->dev;
1028 struct device_node *node = dev->of_node, *child;
1029 struct mtk_pcie_port *port, *tmp;
1030 int err;
1031
1032 for_each_available_child_of_node(node, child) {
1033 int slot;
1034
1035 err = of_pci_get_devfn(child);
1036 if (err < 0) {
1037 dev_err(dev, "failed to parse devfn: %d\n", err);
1038 return err;
1039 }
1040
1041 slot = PCI_SLOT(err);
1042
1043 err = mtk_pcie_parse_port(pcie, child, slot);
1044 if (err)
1045 return err;
1046 }
1047
1048 err = mtk_pcie_subsys_powerup(pcie);
1049 if (err)
1050 return err;
1051
1052 /* enable each port, and then check link status */
1053 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1054 mtk_pcie_enable_port(port);
1055
1056 /* power down PCIe subsys if slots are all empty (link down) */
1057 if (list_empty(&pcie->ports))
1058 mtk_pcie_subsys_powerdown(pcie);
1059
1060 return 0;
1061}
1062
1063static int mtk_pcie_probe(struct platform_device *pdev)
1064{
1065 struct device *dev = &pdev->dev;
1066 struct mtk_pcie *pcie;
1067 struct pci_host_bridge *host;
1068 int err;
1069
1070 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1071 if (!host)
1072 return -ENOMEM;
1073
1074 pcie = pci_host_bridge_priv(host);
1075
1076 pcie->dev = dev;
1077 pcie->soc = of_device_get_match_data(dev);
1078 platform_set_drvdata(pdev, pcie);
1079 INIT_LIST_HEAD(&pcie->ports);
1080
1081 err = mtk_pcie_setup(pcie);
1082 if (err)
1083 return err;
1084
1085 host->ops = pcie->soc->ops;
1086 host->sysdata = pcie;
1087
1088 err = pci_host_probe(host);
1089 if (err)
1090 goto put_resources;
1091
1092 return 0;
1093
1094put_resources:
1095 if (!list_empty(&pcie->ports))
1096 mtk_pcie_put_resources(pcie);
1097
1098 return err;
1099}
1100
1101
1102static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
1103{
1104 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1105 struct list_head *windows = &host->windows;
1106
1107 pci_free_resource_list(windows);
1108}
1109
1110static int mtk_pcie_remove(struct platform_device *pdev)
1111{
1112 struct mtk_pcie *pcie = platform_get_drvdata(pdev);
1113 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1114
1115 pci_stop_root_bus(host->bus);
1116 pci_remove_root_bus(host->bus);
1117 mtk_pcie_free_resources(pcie);
1118
1119 mtk_pcie_irq_teardown(pcie);
1120
1121 mtk_pcie_put_resources(pcie);
1122
1123 return 0;
1124}
1125
1126static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
1127{
1128 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1129 struct mtk_pcie_port *port;
1130
1131 if (list_empty(&pcie->ports))
1132 return 0;
1133
1134 list_for_each_entry(port, &pcie->ports, list) {
1135 clk_disable_unprepare(port->pipe_ck);
1136 clk_disable_unprepare(port->obff_ck);
1137 clk_disable_unprepare(port->axi_ck);
1138 clk_disable_unprepare(port->aux_ck);
1139 clk_disable_unprepare(port->ahb_ck);
1140 clk_disable_unprepare(port->sys_ck);
1141 phy_power_off(port->phy);
1142 phy_exit(port->phy);
1143 }
1144
1145 clk_disable_unprepare(pcie->free_ck);
1146
1147 return 0;
1148}
1149
1150static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
1151{
1152 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1153 struct mtk_pcie_port *port, *tmp;
1154
1155 if (list_empty(&pcie->ports))
1156 return 0;
1157
1158 clk_prepare_enable(pcie->free_ck);
1159
1160 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1161 mtk_pcie_enable_port(port);
1162
1163 /* In case of EP was removed while system suspend. */
1164 if (list_empty(&pcie->ports))
1165 clk_disable_unprepare(pcie->free_ck);
1166
1167 return 0;
1168}
1169
1170static const struct dev_pm_ops mtk_pcie_pm_ops = {
1171 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1172 mtk_pcie_resume_noirq)
1173};
1174
1175static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1176 .ops = &mtk_pcie_ops,
1177 .startup = mtk_pcie_startup_port,
1178};
1179
1180static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
1181 .ops = &mtk_pcie_ops_v2,
1182 .startup = mtk_pcie_startup_port_v2,
1183 .setup_irq = mtk_pcie_setup_irq,
1184};
1185
1186static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
1187 .need_fix_class_id = true,
1188 .ops = &mtk_pcie_ops_v2,
1189 .startup = mtk_pcie_startup_port_v2,
1190 .setup_irq = mtk_pcie_setup_irq,
1191};
1192
1193static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
1194 .need_fix_class_id = true,
1195 .need_fix_device_id = true,
1196 .device_id = PCI_DEVICE_ID_MEDIATEK_7629,
1197 .ops = &mtk_pcie_ops_v2,
1198 .startup = mtk_pcie_startup_port_v2,
1199 .setup_irq = mtk_pcie_setup_irq,
1200};
1201
1202static const struct of_device_id mtk_pcie_ids[] = {
1203 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1204 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1205 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1206 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1207 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1208 {},
1209};
1210
1211static struct platform_driver mtk_pcie_driver = {
1212 .probe = mtk_pcie_probe,
1213 .remove = mtk_pcie_remove,
1214 .driver = {
1215 .name = "mtk-pcie",
1216 .of_match_table = mtk_pcie_ids,
1217 .suppress_bind_attrs = true,
1218 .pm = &mtk_pcie_pm_ops,
1219 },
1220};
1221module_platform_driver(mtk_pcie_driver);
1222MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek PCIe host controller driver.
4 *
5 * Copyright (c) 2017 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 * Honghui Zhang <honghui.zhang@mediatek.com>
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/iopoll.h>
13#include <linux/irq.h>
14#include <linux/irqchip/chained_irq.h>
15#include <linux/irqdomain.h>
16#include <linux/kernel.h>
17#include <linux/mfd/syscon.h>
18#include <linux/msi.h>
19#include <linux/module.h>
20#include <linux/of_address.h>
21#include <linux/of_pci.h>
22#include <linux/of_platform.h>
23#include <linux/pci.h>
24#include <linux/phy/phy.h>
25#include <linux/platform_device.h>
26#include <linux/pm_runtime.h>
27#include <linux/regmap.h>
28#include <linux/reset.h>
29
30#include "../pci.h"
31
32/* PCIe shared registers */
33#define PCIE_SYS_CFG 0x00
34#define PCIE_INT_ENABLE 0x0c
35#define PCIE_CFG_ADDR 0x20
36#define PCIE_CFG_DATA 0x24
37
38/* PCIe per port registers */
39#define PCIE_BAR0_SETUP 0x10
40#define PCIE_CLASS 0x34
41#define PCIE_LINK_STATUS 0x50
42
43#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
44#define PCIE_PORT_PERST(x) BIT(1 + (x))
45#define PCIE_PORT_LINKUP BIT(0)
46#define PCIE_BAR_MAP_MAX GENMASK(31, 16)
47
48#define PCIE_BAR_ENABLE BIT(0)
49#define PCIE_REVISION_ID BIT(0)
50#define PCIE_CLASS_CODE (0x60400 << 8)
51#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
52 ((((regn) >> 8) & GENMASK(3, 0)) << 24))
53#define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))
54#define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))
55#define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))
56#define PCIE_CONF_ADDR(regn, fun, dev, bus) \
57 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
58 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
59
60/* MediaTek specific configuration registers */
61#define PCIE_FTS_NUM 0x70c
62#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
63#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
64
65#define PCIE_FC_CREDIT 0x73c
66#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
67#define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
68
69/* PCIe V2 share registers */
70#define PCIE_SYS_CFG_V2 0x0
71#define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
72#define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
73
74/* PCIe V2 per-port registers */
75#define PCIE_MSI_VECTOR 0x0c0
76
77#define PCIE_CONF_VEND_ID 0x100
78#define PCIE_CONF_DEVICE_ID 0x102
79#define PCIE_CONF_CLASS_ID 0x106
80
81#define PCIE_INT_MASK 0x420
82#define INTX_MASK GENMASK(19, 16)
83#define INTX_SHIFT 16
84#define PCIE_INT_STATUS 0x424
85#define MSI_STATUS BIT(23)
86#define PCIE_IMSI_STATUS 0x42c
87#define PCIE_IMSI_ADDR 0x430
88#define MSI_MASK BIT(23)
89#define MTK_MSI_IRQS_NUM 32
90
91#define PCIE_AHB_TRANS_BASE0_L 0x438
92#define PCIE_AHB_TRANS_BASE0_H 0x43c
93#define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
94#define PCIE_AXI_WINDOW0 0x448
95#define WIN_ENABLE BIT(7)
96/*
97 * Define PCIe to AHB window size as 2^33 to support max 8GB address space
98 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
99 * start from 0x40000000).
100 */
101#define PCIE2AHB_SIZE 0x21
102
103/* PCIe V2 configuration transaction header */
104#define PCIE_CFG_HEADER0 0x460
105#define PCIE_CFG_HEADER1 0x464
106#define PCIE_CFG_HEADER2 0x468
107#define PCIE_CFG_WDATA 0x470
108#define PCIE_APP_TLP_REQ 0x488
109#define PCIE_CFG_RDATA 0x48c
110#define APP_CFG_REQ BIT(0)
111#define APP_CPL_STATUS GENMASK(7, 5)
112
113#define CFG_WRRD_TYPE_0 4
114#define CFG_WR_FMT 2
115#define CFG_RD_FMT 0
116
117#define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
118#define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
119#define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
120#define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
121#define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
122#define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
123#define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
124#define CFG_HEADER_DW0(type, fmt) \
125 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
126#define CFG_HEADER_DW1(where, size) \
127 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
128#define CFG_HEADER_DW2(regn, fun, dev, bus) \
129 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
130 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
131
132#define PCIE_RST_CTRL 0x510
133#define PCIE_PHY_RSTB BIT(0)
134#define PCIE_PIPE_SRSTB BIT(1)
135#define PCIE_MAC_SRSTB BIT(2)
136#define PCIE_CRSTB BIT(3)
137#define PCIE_PERSTB BIT(8)
138#define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
139#define PCIE_LINK_STATUS_V2 0x804
140#define PCIE_PORT_LINKUP_V2 BIT(10)
141
142struct mtk_pcie_port;
143
144/**
145 * struct mtk_pcie_soc - differentiate between host generations
146 * @need_fix_class_id: whether this host's class ID needed to be fixed or not
147 * @need_fix_device_id: whether this host's device ID needed to be fixed or not
148 * @no_msi: Bridge has no MSI support, and relies on an external block
149 * @device_id: device ID which this host need to be fixed
150 * @ops: pointer to configuration access functions
151 * @startup: pointer to controller setting functions
152 * @setup_irq: pointer to initialize IRQ functions
153 */
154struct mtk_pcie_soc {
155 bool need_fix_class_id;
156 bool need_fix_device_id;
157 bool no_msi;
158 unsigned int device_id;
159 struct pci_ops *ops;
160 int (*startup)(struct mtk_pcie_port *port);
161 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
162};
163
164/**
165 * struct mtk_pcie_port - PCIe port information
166 * @base: IO mapped register base
167 * @list: port list
168 * @pcie: pointer to PCIe host info
169 * @reset: pointer to port reset control
170 * @sys_ck: pointer to transaction/data link layer clock
171 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
172 * and RC initiated MMIO access
173 * @axi_ck: pointer to application layer MMIO channel operating clock
174 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
175 * when pcie_mac_ck/pcie_pipe_ck is turned off
176 * @obff_ck: pointer to OBFF functional block operating clock
177 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
178 * @phy: pointer to PHY control block
179 * @slot: port slot
180 * @irq: GIC irq
181 * @irq_domain: legacy INTx IRQ domain
182 * @inner_domain: inner IRQ domain
183 * @msi_domain: MSI IRQ domain
184 * @lock: protect the msi_irq_in_use bitmap
185 * @msi_irq_in_use: bit map for assigned MSI IRQ
186 */
187struct mtk_pcie_port {
188 void __iomem *base;
189 struct list_head list;
190 struct mtk_pcie *pcie;
191 struct reset_control *reset;
192 struct clk *sys_ck;
193 struct clk *ahb_ck;
194 struct clk *axi_ck;
195 struct clk *aux_ck;
196 struct clk *obff_ck;
197 struct clk *pipe_ck;
198 struct phy *phy;
199 u32 slot;
200 int irq;
201 struct irq_domain *irq_domain;
202 struct irq_domain *inner_domain;
203 struct irq_domain *msi_domain;
204 struct mutex lock;
205 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
206};
207
208/**
209 * struct mtk_pcie - PCIe host information
210 * @dev: pointer to PCIe device
211 * @base: IO mapped register base
212 * @cfg: IO mapped register map for PCIe config
213 * @free_ck: free-run reference clock
214 * @ports: pointer to PCIe port information
215 * @soc: pointer to SoC-dependent operations
216 */
217struct mtk_pcie {
218 struct device *dev;
219 void __iomem *base;
220 struct regmap *cfg;
221 struct clk *free_ck;
222
223 struct list_head ports;
224 const struct mtk_pcie_soc *soc;
225};
226
227static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
228{
229 struct device *dev = pcie->dev;
230
231 clk_disable_unprepare(pcie->free_ck);
232
233 pm_runtime_put_sync(dev);
234 pm_runtime_disable(dev);
235}
236
237static void mtk_pcie_port_free(struct mtk_pcie_port *port)
238{
239 struct mtk_pcie *pcie = port->pcie;
240 struct device *dev = pcie->dev;
241
242 devm_iounmap(dev, port->base);
243 list_del(&port->list);
244 devm_kfree(dev, port);
245}
246
247static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
248{
249 struct mtk_pcie_port *port, *tmp;
250
251 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
252 phy_power_off(port->phy);
253 phy_exit(port->phy);
254 clk_disable_unprepare(port->pipe_ck);
255 clk_disable_unprepare(port->obff_ck);
256 clk_disable_unprepare(port->axi_ck);
257 clk_disable_unprepare(port->aux_ck);
258 clk_disable_unprepare(port->ahb_ck);
259 clk_disable_unprepare(port->sys_ck);
260 mtk_pcie_port_free(port);
261 }
262
263 mtk_pcie_subsys_powerdown(pcie);
264}
265
266static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
267{
268 u32 val;
269 int err;
270
271 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
272 !(val & APP_CFG_REQ), 10,
273 100 * USEC_PER_MSEC);
274 if (err)
275 return PCIBIOS_SET_FAILED;
276
277 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
278 return PCIBIOS_SET_FAILED;
279
280 return PCIBIOS_SUCCESSFUL;
281}
282
283static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
284 int where, int size, u32 *val)
285{
286 u32 tmp;
287
288 /* Write PCIe configuration transaction header for Cfgrd */
289 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
290 port->base + PCIE_CFG_HEADER0);
291 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
292 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
293 port->base + PCIE_CFG_HEADER2);
294
295 /* Trigger h/w to transmit Cfgrd TLP */
296 tmp = readl(port->base + PCIE_APP_TLP_REQ);
297 tmp |= APP_CFG_REQ;
298 writel(tmp, port->base + PCIE_APP_TLP_REQ);
299
300 /* Check completion status */
301 if (mtk_pcie_check_cfg_cpld(port))
302 return PCIBIOS_SET_FAILED;
303
304 /* Read cpld payload of Cfgrd */
305 *val = readl(port->base + PCIE_CFG_RDATA);
306
307 if (size == 1)
308 *val = (*val >> (8 * (where & 3))) & 0xff;
309 else if (size == 2)
310 *val = (*val >> (8 * (where & 3))) & 0xffff;
311
312 return PCIBIOS_SUCCESSFUL;
313}
314
315static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
316 int where, int size, u32 val)
317{
318 /* Write PCIe configuration transaction header for Cfgwr */
319 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
320 port->base + PCIE_CFG_HEADER0);
321 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
322 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
323 port->base + PCIE_CFG_HEADER2);
324
325 /* Write Cfgwr data */
326 val = val << 8 * (where & 3);
327 writel(val, port->base + PCIE_CFG_WDATA);
328
329 /* Trigger h/w to transmit Cfgwr TLP */
330 val = readl(port->base + PCIE_APP_TLP_REQ);
331 val |= APP_CFG_REQ;
332 writel(val, port->base + PCIE_APP_TLP_REQ);
333
334 /* Check completion status */
335 return mtk_pcie_check_cfg_cpld(port);
336}
337
338static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
339 unsigned int devfn)
340{
341 struct mtk_pcie *pcie = bus->sysdata;
342 struct mtk_pcie_port *port;
343 struct pci_dev *dev = NULL;
344
345 /*
346 * Walk the bus hierarchy to get the devfn value
347 * of the port in the root bus.
348 */
349 while (bus && bus->number) {
350 dev = bus->self;
351 bus = dev->bus;
352 devfn = dev->devfn;
353 }
354
355 list_for_each_entry(port, &pcie->ports, list)
356 if (port->slot == PCI_SLOT(devfn))
357 return port;
358
359 return NULL;
360}
361
362static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
363 int where, int size, u32 *val)
364{
365 struct mtk_pcie_port *port;
366 u32 bn = bus->number;
367
368 port = mtk_pcie_find_port(bus, devfn);
369 if (!port)
370 return PCIBIOS_DEVICE_NOT_FOUND;
371
372 return mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
373}
374
375static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
376 int where, int size, u32 val)
377{
378 struct mtk_pcie_port *port;
379 u32 bn = bus->number;
380
381 port = mtk_pcie_find_port(bus, devfn);
382 if (!port)
383 return PCIBIOS_DEVICE_NOT_FOUND;
384
385 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
386}
387
388static struct pci_ops mtk_pcie_ops_v2 = {
389 .read = mtk_pcie_config_read,
390 .write = mtk_pcie_config_write,
391};
392
393static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
394{
395 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
396 phys_addr_t addr;
397
398 /* MT2712/MT7622 only support 32-bit MSI addresses */
399 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
400 msg->address_hi = 0;
401 msg->address_lo = lower_32_bits(addr);
402
403 msg->data = data->hwirq;
404
405 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",
406 (int)data->hwirq, msg->address_hi, msg->address_lo);
407}
408
409static void mtk_msi_ack_irq(struct irq_data *data)
410{
411 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
412 u32 hwirq = data->hwirq;
413
414 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
415}
416
417static struct irq_chip mtk_msi_bottom_irq_chip = {
418 .name = "MTK MSI",
419 .irq_compose_msi_msg = mtk_compose_msi_msg,
420 .irq_ack = mtk_msi_ack_irq,
421};
422
423static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
424 unsigned int nr_irqs, void *args)
425{
426 struct mtk_pcie_port *port = domain->host_data;
427 unsigned long bit;
428
429 WARN_ON(nr_irqs != 1);
430 mutex_lock(&port->lock);
431
432 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
433 if (bit >= MTK_MSI_IRQS_NUM) {
434 mutex_unlock(&port->lock);
435 return -ENOSPC;
436 }
437
438 __set_bit(bit, port->msi_irq_in_use);
439
440 mutex_unlock(&port->lock);
441
442 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,
443 domain->host_data, handle_edge_irq,
444 NULL, NULL);
445
446 return 0;
447}
448
449static void mtk_pcie_irq_domain_free(struct irq_domain *domain,
450 unsigned int virq, unsigned int nr_irqs)
451{
452 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
453 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);
454
455 mutex_lock(&port->lock);
456
457 if (!test_bit(d->hwirq, port->msi_irq_in_use))
458 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",
459 d->hwirq);
460 else
461 __clear_bit(d->hwirq, port->msi_irq_in_use);
462
463 mutex_unlock(&port->lock);
464
465 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
466}
467
468static const struct irq_domain_ops msi_domain_ops = {
469 .alloc = mtk_pcie_irq_domain_alloc,
470 .free = mtk_pcie_irq_domain_free,
471};
472
473static struct irq_chip mtk_msi_irq_chip = {
474 .name = "MTK PCIe MSI",
475 .irq_ack = irq_chip_ack_parent,
476 .irq_mask = pci_msi_mask_irq,
477 .irq_unmask = pci_msi_unmask_irq,
478};
479
480static struct msi_domain_info mtk_msi_domain_info = {
481 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
482 MSI_FLAG_NO_AFFINITY | MSI_FLAG_PCI_MSIX,
483 .chip = &mtk_msi_irq_chip,
484};
485
486static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
487{
488 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);
489
490 mutex_init(&port->lock);
491
492 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,
493 &msi_domain_ops, port);
494 if (!port->inner_domain) {
495 dev_err(port->pcie->dev, "failed to create IRQ domain\n");
496 return -ENOMEM;
497 }
498
499 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,
500 port->inner_domain);
501 if (!port->msi_domain) {
502 dev_err(port->pcie->dev, "failed to create MSI domain\n");
503 irq_domain_remove(port->inner_domain);
504 return -ENOMEM;
505 }
506
507 return 0;
508}
509
510static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
511{
512 u32 val;
513 phys_addr_t msg_addr;
514
515 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
516 val = lower_32_bits(msg_addr);
517 writel(val, port->base + PCIE_IMSI_ADDR);
518
519 val = readl(port->base + PCIE_INT_MASK);
520 val &= ~MSI_MASK;
521 writel(val, port->base + PCIE_INT_MASK);
522}
523
524static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
525{
526 struct mtk_pcie_port *port, *tmp;
527
528 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
529 irq_set_chained_handler_and_data(port->irq, NULL, NULL);
530
531 if (port->irq_domain)
532 irq_domain_remove(port->irq_domain);
533
534 if (IS_ENABLED(CONFIG_PCI_MSI)) {
535 if (port->msi_domain)
536 irq_domain_remove(port->msi_domain);
537 if (port->inner_domain)
538 irq_domain_remove(port->inner_domain);
539 }
540
541 irq_dispose_mapping(port->irq);
542 }
543}
544
545static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
546 irq_hw_number_t hwirq)
547{
548 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
549 irq_set_chip_data(irq, domain->host_data);
550
551 return 0;
552}
553
554static const struct irq_domain_ops intx_domain_ops = {
555 .map = mtk_pcie_intx_map,
556};
557
558static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
559 struct device_node *node)
560{
561 struct device *dev = port->pcie->dev;
562 struct device_node *pcie_intc_node;
563 int ret;
564
565 /* Setup INTx */
566 pcie_intc_node = of_get_next_child(node, NULL);
567 if (!pcie_intc_node) {
568 dev_err(dev, "no PCIe Intc node found\n");
569 return -ENODEV;
570 }
571
572 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
573 &intx_domain_ops, port);
574 of_node_put(pcie_intc_node);
575 if (!port->irq_domain) {
576 dev_err(dev, "failed to get INTx IRQ domain\n");
577 return -ENODEV;
578 }
579
580 if (IS_ENABLED(CONFIG_PCI_MSI)) {
581 ret = mtk_pcie_allocate_msi_domains(port);
582 if (ret)
583 return ret;
584 }
585
586 return 0;
587}
588
589static void mtk_pcie_intr_handler(struct irq_desc *desc)
590{
591 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
592 struct irq_chip *irqchip = irq_desc_get_chip(desc);
593 unsigned long status;
594 u32 bit = INTX_SHIFT;
595
596 chained_irq_enter(irqchip, desc);
597
598 status = readl(port->base + PCIE_INT_STATUS);
599 if (status & INTX_MASK) {
600 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
601 /* Clear the INTx */
602 writel(1 << bit, port->base + PCIE_INT_STATUS);
603 generic_handle_domain_irq(port->irq_domain,
604 bit - INTX_SHIFT);
605 }
606 }
607
608 if (IS_ENABLED(CONFIG_PCI_MSI)) {
609 if (status & MSI_STATUS){
610 unsigned long imsi_status;
611
612 /*
613 * The interrupt status can be cleared even if the
614 * MSI status remains pending. As such, given the
615 * edge-triggered interrupt type, its status should
616 * be cleared before being dispatched to the
617 * handler of the underlying device.
618 */
619 writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
620 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
621 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM)
622 generic_handle_domain_irq(port->inner_domain, bit);
623 }
624 }
625 }
626
627 chained_irq_exit(irqchip, desc);
628}
629
630static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
631 struct device_node *node)
632{
633 struct mtk_pcie *pcie = port->pcie;
634 struct device *dev = pcie->dev;
635 struct platform_device *pdev = to_platform_device(dev);
636 int err;
637
638 err = mtk_pcie_init_irq_domain(port, node);
639 if (err) {
640 dev_err(dev, "failed to init PCIe IRQ domain\n");
641 return err;
642 }
643
644 if (of_property_present(dev->of_node, "interrupt-names"))
645 port->irq = platform_get_irq_byname(pdev, "pcie_irq");
646 else
647 port->irq = platform_get_irq(pdev, port->slot);
648
649 if (port->irq < 0)
650 return port->irq;
651
652 irq_set_chained_handler_and_data(port->irq,
653 mtk_pcie_intr_handler, port);
654
655 return 0;
656}
657
658static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
659{
660 struct mtk_pcie *pcie = port->pcie;
661 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
662 struct resource *mem = NULL;
663 struct resource_entry *entry;
664 const struct mtk_pcie_soc *soc = port->pcie->soc;
665 u32 val;
666 int err;
667
668 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
669 if (entry)
670 mem = entry->res;
671 if (!mem)
672 return -EINVAL;
673
674 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
675 if (pcie->base) {
676 val = readl(pcie->base + PCIE_SYS_CFG_V2);
677 val |= PCIE_CSR_LTSSM_EN(port->slot) |
678 PCIE_CSR_ASPM_L1_EN(port->slot);
679 writel(val, pcie->base + PCIE_SYS_CFG_V2);
680 } else if (pcie->cfg) {
681 val = PCIE_CSR_LTSSM_EN(port->slot) |
682 PCIE_CSR_ASPM_L1_EN(port->slot);
683 regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);
684 }
685
686 /* Assert all reset signals */
687 writel(0, port->base + PCIE_RST_CTRL);
688
689 /*
690 * Enable PCIe link down reset, if link status changed from link up to
691 * link down, this will reset MAC control registers and configuration
692 * space.
693 */
694 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
695
696 /*
697 * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
698 * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
699 * be delayed 100ms (TPVPERL) for the power and clock to become stable.
700 */
701 msleep(100);
702
703 /* De-assert PHY, PE, PIPE, MAC and configuration reset */
704 val = readl(port->base + PCIE_RST_CTRL);
705 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
706 PCIE_MAC_SRSTB | PCIE_CRSTB;
707 writel(val, port->base + PCIE_RST_CTRL);
708
709 /* Set up vendor ID and class code */
710 if (soc->need_fix_class_id) {
711 val = PCI_VENDOR_ID_MEDIATEK;
712 writew(val, port->base + PCIE_CONF_VEND_ID);
713
714 val = PCI_CLASS_BRIDGE_PCI;
715 writew(val, port->base + PCIE_CONF_CLASS_ID);
716 }
717
718 if (soc->need_fix_device_id)
719 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
720
721 /* 100ms timeout value should be enough for Gen1/2 training */
722 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
723 !!(val & PCIE_PORT_LINKUP_V2), 20,
724 100 * USEC_PER_MSEC);
725 if (err)
726 return -ETIMEDOUT;
727
728 /* Set INTx mask */
729 val = readl(port->base + PCIE_INT_MASK);
730 val &= ~INTX_MASK;
731 writel(val, port->base + PCIE_INT_MASK);
732
733 if (IS_ENABLED(CONFIG_PCI_MSI))
734 mtk_pcie_enable_msi(port);
735
736 /* Set AHB to PCIe translation windows */
737 val = lower_32_bits(mem->start) |
738 AHB2PCIE_SIZE(fls(resource_size(mem)));
739 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
740
741 val = upper_32_bits(mem->start);
742 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
743
744 /* Set PCIe to AXI translation memory space.*/
745 val = PCIE2AHB_SIZE | WIN_ENABLE;
746 writel(val, port->base + PCIE_AXI_WINDOW0);
747
748 return 0;
749}
750
751static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
752 unsigned int devfn, int where)
753{
754 struct mtk_pcie *pcie = bus->sysdata;
755
756 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
757 bus->number), pcie->base + PCIE_CFG_ADDR);
758
759 return pcie->base + PCIE_CFG_DATA + (where & 3);
760}
761
762static struct pci_ops mtk_pcie_ops = {
763 .map_bus = mtk_pcie_map_bus,
764 .read = pci_generic_config_read,
765 .write = pci_generic_config_write,
766};
767
768static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
769{
770 struct mtk_pcie *pcie = port->pcie;
771 u32 func = PCI_FUNC(port->slot);
772 u32 slot = PCI_SLOT(port->slot << 3);
773 u32 val;
774 int err;
775
776 /* assert port PERST_N */
777 val = readl(pcie->base + PCIE_SYS_CFG);
778 val |= PCIE_PORT_PERST(port->slot);
779 writel(val, pcie->base + PCIE_SYS_CFG);
780
781 /* de-assert port PERST_N */
782 val = readl(pcie->base + PCIE_SYS_CFG);
783 val &= ~PCIE_PORT_PERST(port->slot);
784 writel(val, pcie->base + PCIE_SYS_CFG);
785
786 /* 100ms timeout value should be enough for Gen1/2 training */
787 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
788 !!(val & PCIE_PORT_LINKUP), 20,
789 100 * USEC_PER_MSEC);
790 if (err)
791 return -ETIMEDOUT;
792
793 /* enable interrupt */
794 val = readl(pcie->base + PCIE_INT_ENABLE);
795 val |= PCIE_PORT_INT_EN(port->slot);
796 writel(val, pcie->base + PCIE_INT_ENABLE);
797
798 /* map to all DDR region. We need to set it before cfg operation. */
799 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
800 port->base + PCIE_BAR0_SETUP);
801
802 /* configure class code and revision ID */
803 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
804
805 /* configure FC credit */
806 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
807 pcie->base + PCIE_CFG_ADDR);
808 val = readl(pcie->base + PCIE_CFG_DATA);
809 val &= ~PCIE_FC_CREDIT_MASK;
810 val |= PCIE_FC_CREDIT_VAL(0x806c);
811 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
812 pcie->base + PCIE_CFG_ADDR);
813 writel(val, pcie->base + PCIE_CFG_DATA);
814
815 /* configure RC FTS number to 250 when it leaves L0s */
816 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
817 pcie->base + PCIE_CFG_ADDR);
818 val = readl(pcie->base + PCIE_CFG_DATA);
819 val &= ~PCIE_FTS_NUM_MASK;
820 val |= PCIE_FTS_NUM_L0(0x50);
821 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
822 pcie->base + PCIE_CFG_ADDR);
823 writel(val, pcie->base + PCIE_CFG_DATA);
824
825 return 0;
826}
827
828static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
829{
830 struct mtk_pcie *pcie = port->pcie;
831 struct device *dev = pcie->dev;
832 int err;
833
834 err = clk_prepare_enable(port->sys_ck);
835 if (err) {
836 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
837 goto err_sys_clk;
838 }
839
840 err = clk_prepare_enable(port->ahb_ck);
841 if (err) {
842 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
843 goto err_ahb_clk;
844 }
845
846 err = clk_prepare_enable(port->aux_ck);
847 if (err) {
848 dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
849 goto err_aux_clk;
850 }
851
852 err = clk_prepare_enable(port->axi_ck);
853 if (err) {
854 dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
855 goto err_axi_clk;
856 }
857
858 err = clk_prepare_enable(port->obff_ck);
859 if (err) {
860 dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
861 goto err_obff_clk;
862 }
863
864 err = clk_prepare_enable(port->pipe_ck);
865 if (err) {
866 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
867 goto err_pipe_clk;
868 }
869
870 reset_control_assert(port->reset);
871 reset_control_deassert(port->reset);
872
873 err = phy_init(port->phy);
874 if (err) {
875 dev_err(dev, "failed to initialize port%d phy\n", port->slot);
876 goto err_phy_init;
877 }
878
879 err = phy_power_on(port->phy);
880 if (err) {
881 dev_err(dev, "failed to power on port%d phy\n", port->slot);
882 goto err_phy_on;
883 }
884
885 if (!pcie->soc->startup(port))
886 return;
887
888 dev_info(dev, "Port%d link down\n", port->slot);
889
890 phy_power_off(port->phy);
891err_phy_on:
892 phy_exit(port->phy);
893err_phy_init:
894 clk_disable_unprepare(port->pipe_ck);
895err_pipe_clk:
896 clk_disable_unprepare(port->obff_ck);
897err_obff_clk:
898 clk_disable_unprepare(port->axi_ck);
899err_axi_clk:
900 clk_disable_unprepare(port->aux_ck);
901err_aux_clk:
902 clk_disable_unprepare(port->ahb_ck);
903err_ahb_clk:
904 clk_disable_unprepare(port->sys_ck);
905err_sys_clk:
906 mtk_pcie_port_free(port);
907}
908
909static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
910 struct device_node *node,
911 int slot)
912{
913 struct mtk_pcie_port *port;
914 struct device *dev = pcie->dev;
915 struct platform_device *pdev = to_platform_device(dev);
916 char name[10];
917 int err;
918
919 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
920 if (!port)
921 return -ENOMEM;
922
923 snprintf(name, sizeof(name), "port%d", slot);
924 port->base = devm_platform_ioremap_resource_byname(pdev, name);
925 if (IS_ERR(port->base)) {
926 dev_err(dev, "failed to map port%d base\n", slot);
927 return PTR_ERR(port->base);
928 }
929
930 snprintf(name, sizeof(name), "sys_ck%d", slot);
931 port->sys_ck = devm_clk_get(dev, name);
932 if (IS_ERR(port->sys_ck)) {
933 dev_err(dev, "failed to get sys_ck%d clock\n", slot);
934 return PTR_ERR(port->sys_ck);
935 }
936
937 /* sys_ck might be divided into the following parts in some chips */
938 snprintf(name, sizeof(name), "ahb_ck%d", slot);
939 port->ahb_ck = devm_clk_get_optional(dev, name);
940 if (IS_ERR(port->ahb_ck))
941 return PTR_ERR(port->ahb_ck);
942
943 snprintf(name, sizeof(name), "axi_ck%d", slot);
944 port->axi_ck = devm_clk_get_optional(dev, name);
945 if (IS_ERR(port->axi_ck))
946 return PTR_ERR(port->axi_ck);
947
948 snprintf(name, sizeof(name), "aux_ck%d", slot);
949 port->aux_ck = devm_clk_get_optional(dev, name);
950 if (IS_ERR(port->aux_ck))
951 return PTR_ERR(port->aux_ck);
952
953 snprintf(name, sizeof(name), "obff_ck%d", slot);
954 port->obff_ck = devm_clk_get_optional(dev, name);
955 if (IS_ERR(port->obff_ck))
956 return PTR_ERR(port->obff_ck);
957
958 snprintf(name, sizeof(name), "pipe_ck%d", slot);
959 port->pipe_ck = devm_clk_get_optional(dev, name);
960 if (IS_ERR(port->pipe_ck))
961 return PTR_ERR(port->pipe_ck);
962
963 snprintf(name, sizeof(name), "pcie-rst%d", slot);
964 port->reset = devm_reset_control_get_optional_exclusive(dev, name);
965 if (PTR_ERR(port->reset) == -EPROBE_DEFER)
966 return PTR_ERR(port->reset);
967
968 /* some platforms may use default PHY setting */
969 snprintf(name, sizeof(name), "pcie-phy%d", slot);
970 port->phy = devm_phy_optional_get(dev, name);
971 if (IS_ERR(port->phy))
972 return PTR_ERR(port->phy);
973
974 port->slot = slot;
975 port->pcie = pcie;
976
977 if (pcie->soc->setup_irq) {
978 err = pcie->soc->setup_irq(port, node);
979 if (err)
980 return err;
981 }
982
983 INIT_LIST_HEAD(&port->list);
984 list_add_tail(&port->list, &pcie->ports);
985
986 return 0;
987}
988
989static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
990{
991 struct device *dev = pcie->dev;
992 struct platform_device *pdev = to_platform_device(dev);
993 struct resource *regs;
994 struct device_node *cfg_node;
995 int err;
996
997 /* get shared registers, which are optional */
998 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
999 if (regs) {
1000 pcie->base = devm_ioremap_resource(dev, regs);
1001 if (IS_ERR(pcie->base))
1002 return PTR_ERR(pcie->base);
1003 }
1004
1005 cfg_node = of_find_compatible_node(NULL, NULL,
1006 "mediatek,generic-pciecfg");
1007 if (cfg_node) {
1008 pcie->cfg = syscon_node_to_regmap(cfg_node);
1009 of_node_put(cfg_node);
1010 if (IS_ERR(pcie->cfg))
1011 return PTR_ERR(pcie->cfg);
1012 }
1013
1014 pcie->free_ck = devm_clk_get(dev, "free_ck");
1015 if (IS_ERR(pcie->free_ck)) {
1016 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
1017 return -EPROBE_DEFER;
1018
1019 pcie->free_ck = NULL;
1020 }
1021
1022 pm_runtime_enable(dev);
1023 pm_runtime_get_sync(dev);
1024
1025 /* enable top level clock */
1026 err = clk_prepare_enable(pcie->free_ck);
1027 if (err) {
1028 dev_err(dev, "failed to enable free_ck\n");
1029 goto err_free_ck;
1030 }
1031
1032 return 0;
1033
1034err_free_ck:
1035 pm_runtime_put_sync(dev);
1036 pm_runtime_disable(dev);
1037
1038 return err;
1039}
1040
1041static int mtk_pcie_setup(struct mtk_pcie *pcie)
1042{
1043 struct device *dev = pcie->dev;
1044 struct device_node *node = dev->of_node, *child;
1045 struct mtk_pcie_port *port, *tmp;
1046 int err, slot;
1047
1048 slot = of_get_pci_domain_nr(dev->of_node);
1049 if (slot < 0) {
1050 for_each_available_child_of_node(node, child) {
1051 err = of_pci_get_devfn(child);
1052 if (err < 0) {
1053 dev_err(dev, "failed to get devfn: %d\n", err);
1054 goto error_put_node;
1055 }
1056
1057 slot = PCI_SLOT(err);
1058
1059 err = mtk_pcie_parse_port(pcie, child, slot);
1060 if (err)
1061 goto error_put_node;
1062 }
1063 } else {
1064 err = mtk_pcie_parse_port(pcie, node, slot);
1065 if (err)
1066 return err;
1067 }
1068
1069 err = mtk_pcie_subsys_powerup(pcie);
1070 if (err)
1071 return err;
1072
1073 /* enable each port, and then check link status */
1074 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1075 mtk_pcie_enable_port(port);
1076
1077 /* power down PCIe subsys if slots are all empty (link down) */
1078 if (list_empty(&pcie->ports))
1079 mtk_pcie_subsys_powerdown(pcie);
1080
1081 return 0;
1082error_put_node:
1083 of_node_put(child);
1084 return err;
1085}
1086
1087static int mtk_pcie_probe(struct platform_device *pdev)
1088{
1089 struct device *dev = &pdev->dev;
1090 struct mtk_pcie *pcie;
1091 struct pci_host_bridge *host;
1092 int err;
1093
1094 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1095 if (!host)
1096 return -ENOMEM;
1097
1098 pcie = pci_host_bridge_priv(host);
1099
1100 pcie->dev = dev;
1101 pcie->soc = of_device_get_match_data(dev);
1102 platform_set_drvdata(pdev, pcie);
1103 INIT_LIST_HEAD(&pcie->ports);
1104
1105 err = mtk_pcie_setup(pcie);
1106 if (err)
1107 return err;
1108
1109 host->ops = pcie->soc->ops;
1110 host->sysdata = pcie;
1111 host->msi_domain = pcie->soc->no_msi;
1112
1113 err = pci_host_probe(host);
1114 if (err)
1115 goto put_resources;
1116
1117 return 0;
1118
1119put_resources:
1120 if (!list_empty(&pcie->ports))
1121 mtk_pcie_put_resources(pcie);
1122
1123 return err;
1124}
1125
1126
1127static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
1128{
1129 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1130 struct list_head *windows = &host->windows;
1131
1132 pci_free_resource_list(windows);
1133}
1134
1135static void mtk_pcie_remove(struct platform_device *pdev)
1136{
1137 struct mtk_pcie *pcie = platform_get_drvdata(pdev);
1138 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1139
1140 pci_stop_root_bus(host->bus);
1141 pci_remove_root_bus(host->bus);
1142 mtk_pcie_free_resources(pcie);
1143
1144 mtk_pcie_irq_teardown(pcie);
1145
1146 mtk_pcie_put_resources(pcie);
1147}
1148
1149static int mtk_pcie_suspend_noirq(struct device *dev)
1150{
1151 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1152 struct mtk_pcie_port *port;
1153
1154 if (list_empty(&pcie->ports))
1155 return 0;
1156
1157 list_for_each_entry(port, &pcie->ports, list) {
1158 clk_disable_unprepare(port->pipe_ck);
1159 clk_disable_unprepare(port->obff_ck);
1160 clk_disable_unprepare(port->axi_ck);
1161 clk_disable_unprepare(port->aux_ck);
1162 clk_disable_unprepare(port->ahb_ck);
1163 clk_disable_unprepare(port->sys_ck);
1164 phy_power_off(port->phy);
1165 phy_exit(port->phy);
1166 }
1167
1168 clk_disable_unprepare(pcie->free_ck);
1169
1170 return 0;
1171}
1172
1173static int mtk_pcie_resume_noirq(struct device *dev)
1174{
1175 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1176 struct mtk_pcie_port *port, *tmp;
1177
1178 if (list_empty(&pcie->ports))
1179 return 0;
1180
1181 clk_prepare_enable(pcie->free_ck);
1182
1183 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1184 mtk_pcie_enable_port(port);
1185
1186 /* In case of EP was removed while system suspend. */
1187 if (list_empty(&pcie->ports))
1188 clk_disable_unprepare(pcie->free_ck);
1189
1190 return 0;
1191}
1192
1193static const struct dev_pm_ops mtk_pcie_pm_ops = {
1194 NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1195 mtk_pcie_resume_noirq)
1196};
1197
1198static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1199 .no_msi = true,
1200 .ops = &mtk_pcie_ops,
1201 .startup = mtk_pcie_startup_port,
1202};
1203
1204static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
1205 .ops = &mtk_pcie_ops_v2,
1206 .startup = mtk_pcie_startup_port_v2,
1207 .setup_irq = mtk_pcie_setup_irq,
1208};
1209
1210static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
1211 .need_fix_class_id = true,
1212 .ops = &mtk_pcie_ops_v2,
1213 .startup = mtk_pcie_startup_port_v2,
1214 .setup_irq = mtk_pcie_setup_irq,
1215};
1216
1217static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
1218 .need_fix_class_id = true,
1219 .need_fix_device_id = true,
1220 .device_id = PCI_DEVICE_ID_MEDIATEK_7629,
1221 .ops = &mtk_pcie_ops_v2,
1222 .startup = mtk_pcie_startup_port_v2,
1223 .setup_irq = mtk_pcie_setup_irq,
1224};
1225
1226static const struct of_device_id mtk_pcie_ids[] = {
1227 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1228 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1229 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1230 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1231 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1232 {},
1233};
1234MODULE_DEVICE_TABLE(of, mtk_pcie_ids);
1235
1236static struct platform_driver mtk_pcie_driver = {
1237 .probe = mtk_pcie_probe,
1238 .remove = mtk_pcie_remove,
1239 .driver = {
1240 .name = "mtk-pcie",
1241 .of_match_table = mtk_pcie_ids,
1242 .suppress_bind_attrs = true,
1243 .pm = &mtk_pcie_pm_ops,
1244 },
1245};
1246module_platform_driver(mtk_pcie_driver);
1247MODULE_DESCRIPTION("MediaTek PCIe host controller driver");
1248MODULE_LICENSE("GPL v2");