1// SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * iio/adc/max1363.c
   4  * Copyright (C) 2008-2010 Jonathan Cameron
   5  *
   6  * based on linux/drivers/i2c/chips/max123x
   7  * Copyright (C) 2002-2004 Stefan Eletzhofer
   8  *
   9  * based on linux/drivers/acron/char/pcf8583.c
  10  * Copyright (C) 2000 Russell King
  11  *
  12  * Driver for max1363 and similar chips.
  13  */
  14
  15#include <linux/interrupt.h>
 
  16#include <linux/device.h>
  17#include <linux/kernel.h>
  18#include <linux/sysfs.h>
  19#include <linux/list.h>
  20#include <linux/i2c.h>
  21#include <linux/regulator/consumer.h>
  22#include <linux/slab.h>
  23#include <linux/err.h>
  24#include <linux/module.h>
  25#include <linux/mod_devicetable.h>
  26#include <linux/property.h>
 
  27
  28#include <linux/iio/iio.h>
  29#include <linux/iio/sysfs.h>
  30#include <linux/iio/events.h>
  31#include <linux/iio/buffer.h>
  32#include <linux/iio/driver.h>
  33#include <linux/iio/kfifo_buf.h>
  34#include <linux/iio/trigger_consumer.h>
  35#include <linux/iio/triggered_buffer.h>
  36
  37#define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
  38
  39/* There is a fair bit more defined here than currently
  40 * used, but the intention is to support everything these
  41 * chips do in the long run */
  42
  43/* see data sheets */
  44/* max1363 and max1236, max1237, max1238, max1239 */
  45#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD	0x00
  46#define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF	0x20
  47#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT	0x40
  48#define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT	0x60
  49#define MAX1363_SETUP_POWER_UP_INT_REF		0x10
  50#define MAX1363_SETUP_POWER_DOWN_INT_REF	0x00
  51
  52/* think about including max11600 etc - more settings */
  53#define MAX1363_SETUP_EXT_CLOCK			0x08
  54#define MAX1363_SETUP_INT_CLOCK			0x00
  55#define MAX1363_SETUP_UNIPOLAR			0x00
  56#define MAX1363_SETUP_BIPOLAR			0x04
  57#define MAX1363_SETUP_RESET			0x00
  58#define MAX1363_SETUP_NORESET			0x02
  59/* max1363 only - though don't care on others.
  60 * For now monitor modes are not implemented as the relevant
  61 * line is not connected on my test board.
  62 * The definitions are here as I intend to add this soon.
  63 */
  64#define MAX1363_SETUP_MONITOR_SETUP		0x01
  65
  66/* Specific to the max1363 */
  67#define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
  68#define MAX1363_MON_INT_ENABLE			0x01
  69
  70/* defined for readability reasons */
  71/* All chips */
  72#define MAX1363_CONFIG_BYTE(a) ((a))
  73
  74#define MAX1363_CONFIG_SE			0x01
  75#define MAX1363_CONFIG_DE			0x00
  76#define MAX1363_CONFIG_SCAN_TO_CS		0x00
  77#define MAX1363_CONFIG_SCAN_SINGLE_8		0x20
  78#define MAX1363_CONFIG_SCAN_MONITOR_MODE	0x40
  79#define MAX1363_CONFIG_SCAN_SINGLE_1		0x60
  80/* max123{6-9} only */
  81#define MAX1236_SCAN_MID_TO_CHANNEL		0x40
  82
  83/* max1363 only - merely part of channel selects or don't care for others */
  84#define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
  85
  86#define MAX1363_CHANNEL_SEL(a) ((a) << 1)
  87
  88/* max1363 strictly 0x06 - but doesn't matter */
  89#define MAX1363_CHANNEL_SEL_MASK		0x1E
  90#define MAX1363_SCAN_MASK			0x60
  91#define MAX1363_SE_DE_MASK			0x01
  92
  93#define MAX1363_MAX_CHANNELS 25
  94/**
  95 * struct max1363_mode - scan mode information
  96 * @conf:	The corresponding value of the configuration register
  97 * @modemask:	Bit mask corresponding to channels enabled in this mode
  98 */
  99struct max1363_mode {
 100	int8_t		conf;
 101	DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
 102};
 103
 104/* This must be maintained along side the max1363_mode_table in max1363_core */
 105enum max1363_modes {
 106	/* Single read of a single channel */
 107	_s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
 108	/* Differential single read */
 109	d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
 110	d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
 111	/* Scan to channel and mid to channel where overlapping */
 112	s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
 113	s6to7, s0to7, s6to8, s0to8, s6to9,
 114	s0to9, s6to10, s0to10, s6to11, s0to11,
 115	/* Differential scan to channel and mid to channel where overlapping */
 116	d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
 117	d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
 118	d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
 119	d7m6to11m10, d1m0to11m10,
 120};
 121
 122/**
 123 * struct max1363_chip_info - chip specifc information
 124 * @info:		iio core function callbacks structure
 125 * @channels:		channel specification
 126 * @num_channels:       number of channels
 127 * @mode_list:		array of available scan modes
 128 * @default_mode:	the scan mode in which the chip starts up
 129 * @int_vref_mv:	the internal reference voltage
 130 * @num_modes:		number of modes
 131 * @bits:		accuracy of the adc in bits
 132 */
 133struct max1363_chip_info {
 134	const struct iio_info		*info;
 135	const struct iio_chan_spec	*channels;
 136	int				num_channels;
 137	const enum max1363_modes	*mode_list;
 138	enum max1363_modes		default_mode;
 139	u16				int_vref_mv;
 140	u8				num_modes;
 141	u8				bits;
 142};
 143
 144/**
 145 * struct max1363_state - driver instance specific data
 146 * @client:		i2c_client
 147 * @setupbyte:		cache of current device setup byte
 148 * @configbyte:		cache of current device config byte
 149 * @chip_info:		chip model specific constants, available modes, etc.
 150 * @current_mode:	the scan mode of this chip
 151 * @requestedmask:	a valid requested set of channels
 152 * @reg:		supply regulator
 153 * @lock:		lock to ensure state is consistent
 154 * @monitor_on:		whether monitor mode is enabled
 155 * @monitor_speed:	parameter corresponding to device monitor speed setting
 156 * @mask_high:		bitmask for enabled high thresholds
 157 * @mask_low:		bitmask for enabled low thresholds
 158 * @thresh_high:	high threshold values
 159 * @thresh_low:		low threshold values
 160 * @vref:		Reference voltage regulator
 161 * @vref_uv:		Actual (external or internal) reference voltage
 162 * @send:		function used to send data to the chip
 163 * @recv:		function used to receive data from the chip
 164 */
 165struct max1363_state {
 166	struct i2c_client		*client;
 167	u8				setupbyte;
 168	u8				configbyte;
 169	const struct max1363_chip_info	*chip_info;
 170	const struct max1363_mode	*current_mode;
 171	u32				requestedmask;
 172	struct regulator		*reg;
 173	struct mutex			lock;
 174
 175	/* Using monitor modes and buffer at the same time is
 176	   currently not supported */
 177	bool				monitor_on;
 178	unsigned int			monitor_speed:3;
 179	u8				mask_high;
 180	u8				mask_low;
 181	/* 4x unipolar first then the fours bipolar ones */
 182	s16				thresh_high[8];
 183	s16				thresh_low[8];
 184	struct regulator		*vref;
 185	u32				vref_uv;
 186	int				(*send)(const struct i2c_client *client,
 187						const char *buf, int count);
 188	int				(*recv)(const struct i2c_client *client,
 189						char *buf, int count);
 190};
 191
 192#define MAX1363_MODE_SINGLE(_num, _mask) {				\
 193		.conf = MAX1363_CHANNEL_SEL(_num)			\
 194			| MAX1363_CONFIG_SCAN_SINGLE_1			\
 195			| MAX1363_CONFIG_SE,				\
 196			.modemask[0] = _mask,				\
 197			}
 198
 199#define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) {			\
 200		.conf = MAX1363_CHANNEL_SEL(_num)			\
 201			| MAX1363_CONFIG_SCAN_TO_CS			\
 202			| MAX1363_CONFIG_SE,				\
 203			.modemask[0] = _mask,				\
 204			}
 205
 206/* note not available for max1363 hence naming */
 207#define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) {		\
 208		.conf = MAX1363_CHANNEL_SEL(_num)			\
 209			| MAX1236_SCAN_MID_TO_CHANNEL			\
 210			| MAX1363_CONFIG_SE,				\
 211			.modemask[0] = _mask				\
 212}
 213
 214#define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) {			\
 215		.conf = MAX1363_CHANNEL_SEL(_nump)			\
 216			| MAX1363_CONFIG_SCAN_SINGLE_1			\
 217			| MAX1363_CONFIG_DE,				\
 218			.modemask[0] = _mask				\
 219			}
 220
 221/* Can't think how to automate naming so specify for now */
 222#define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) {	\
 223		.conf = MAX1363_CHANNEL_SEL(_num)			\
 224			| MAX1363_CONFIG_SCAN_TO_CS			\
 225			| MAX1363_CONFIG_DE,				\
 226			.modemask[0] = _mask				\
 227			}
 228
 229/* note only available for max1363 hence naming */
 230#define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) {	\
 231		.conf = MAX1363_CHANNEL_SEL(_num)			\
 232			| MAX1236_SCAN_MID_TO_CHANNEL			\
 233			| MAX1363_CONFIG_SE,				\
 234			.modemask[0] = _mask				\
 235}
 236
 237static const struct max1363_mode max1363_mode_table[] = {
 238	/* All of the single channel options first */
 239	MAX1363_MODE_SINGLE(0, 1 << 0),
 240	MAX1363_MODE_SINGLE(1, 1 << 1),
 241	MAX1363_MODE_SINGLE(2, 1 << 2),
 242	MAX1363_MODE_SINGLE(3, 1 << 3),
 243	MAX1363_MODE_SINGLE(4, 1 << 4),
 244	MAX1363_MODE_SINGLE(5, 1 << 5),
 245	MAX1363_MODE_SINGLE(6, 1 << 6),
 246	MAX1363_MODE_SINGLE(7, 1 << 7),
 247	MAX1363_MODE_SINGLE(8, 1 << 8),
 248	MAX1363_MODE_SINGLE(9, 1 << 9),
 249	MAX1363_MODE_SINGLE(10, 1 << 10),
 250	MAX1363_MODE_SINGLE(11, 1 << 11),
 251
 252	MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
 253	MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
 254	MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
 255	MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
 256	MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
 257	MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
 258	MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
 259	MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
 260	MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
 261	MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
 262	MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
 263	MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
 264
 265	/* The multichannel scans next */
 266	MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
 267	MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
 268	MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
 269	MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
 270	MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
 271	MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
 272	MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
 273	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
 274	MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
 275	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
 276	MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
 277	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
 278	MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
 279	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
 280	MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
 281	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
 282	MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
 283
 284	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
 285	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
 286	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
 287	MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
 288	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
 289	MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
 290	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
 291	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
 292	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
 293	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
 294	MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
 295	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
 296	MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
 297	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
 298};
 299
 300static const struct max1363_mode
 301*max1363_match_mode(const unsigned long *mask,
 302	const struct max1363_chip_info *ci)
 303{
 304	int i;
 305	if (mask)
 306		for (i = 0; i < ci->num_modes; i++)
 307			if (bitmap_subset(mask,
 308					  max1363_mode_table[ci->mode_list[i]].
 309					  modemask,
 310					  MAX1363_MAX_CHANNELS))
 311				return &max1363_mode_table[ci->mode_list[i]];
 312	return NULL;
 313}
 314
 315static int max1363_smbus_send(const struct i2c_client *client, const char *buf,
 316		int count)
 317{
 318	int i, err;
 319
 320	for (i = err = 0; err == 0 && i < count; ++i)
 321		err = i2c_smbus_write_byte(client, buf[i]);
 322
 323	return err ? err : count;
 324}
 325
 326static int max1363_smbus_recv(const struct i2c_client *client, char *buf,
 327		int count)
 328{
 329	int i, ret;
 330
 331	for (i = 0; i < count; ++i) {
 332		ret = i2c_smbus_read_byte(client);
 333		if (ret < 0)
 334			return ret;
 335		buf[i] = ret;
 336	}
 337
 338	return count;
 339}
 340
 341static int max1363_write_basic_config(struct max1363_state *st)
 342{
 343	u8 tx_buf[2] = { st->setupbyte, st->configbyte };
 344
 345	return st->send(st->client, tx_buf, 2);
 346}
 347
 348static int max1363_set_scan_mode(struct max1363_state *st)
 349{
 350	st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
 351			    | MAX1363_SCAN_MASK
 352			    | MAX1363_SE_DE_MASK);
 353	st->configbyte |= st->current_mode->conf;
 354
 355	return max1363_write_basic_config(st);
 356}
 357
 358static int max1363_read_single_chan(struct iio_dev *indio_dev,
 359				    struct iio_chan_spec const *chan,
 360				    int *val,
 361				    long m)
 362{
 363	int ret = 0;
 364	s32 data;
 365	u8 rxbuf[2];
 366	struct max1363_state *st = iio_priv(indio_dev);
 367	struct i2c_client *client = st->client;
 368
 369	ret = iio_device_claim_direct_mode(indio_dev);
 370	if (ret)
 371		return ret;
 372	mutex_lock(&st->lock);
 373
 374	/*
 375	 * If monitor mode is enabled, the method for reading a single
 376	 * channel will have to be rather different and has not yet
 377	 * been implemented.
 378	 *
 379	 * Also, cannot read directly if buffered capture enabled.
 380	 */
 381	if (st->monitor_on) {
 382		ret = -EBUSY;
 383		goto error_ret;
 384	}
 385
 386	/* Check to see if current scan mode is correct */
 387	if (st->current_mode != &max1363_mode_table[chan->address]) {
 388		/* Update scan mode if needed */
 389		st->current_mode = &max1363_mode_table[chan->address];
 390		ret = max1363_set_scan_mode(st);
 391		if (ret < 0)
 392			goto error_ret;
 393	}
 394	if (st->chip_info->bits != 8) {
 395		/* Get reading */
 396		data = st->recv(client, rxbuf, 2);
 397		if (data < 0) {
 398			ret = data;
 399			goto error_ret;
 400		}
 401		data = (rxbuf[1] | rxbuf[0] << 8) &
 402		  ((1 << st->chip_info->bits) - 1);
 403	} else {
 404		/* Get reading */
 405		data = st->recv(client, rxbuf, 1);
 406		if (data < 0) {
 407			ret = data;
 408			goto error_ret;
 409		}
 410		data = rxbuf[0];
 411	}
 412	*val = data;
 
 413
 414error_ret:
 415	mutex_unlock(&st->lock);
 416	iio_device_release_direct_mode(indio_dev);
 417	return ret;
 418
 
 
 
 419}
 420
 421static int max1363_read_raw(struct iio_dev *indio_dev,
 422			    struct iio_chan_spec const *chan,
 423			    int *val,
 424			    int *val2,
 425			    long m)
 426{
 427	struct max1363_state *st = iio_priv(indio_dev);
 428	int ret;
 429
 430	switch (m) {
 431	case IIO_CHAN_INFO_RAW:
 432		ret = max1363_read_single_chan(indio_dev, chan, val, m);
 433		if (ret < 0)
 434			return ret;
 435		return IIO_VAL_INT;
 436	case IIO_CHAN_INFO_SCALE:
 437		*val = st->vref_uv / 1000;
 438		*val2 = st->chip_info->bits;
 439		return IIO_VAL_FRACTIONAL_LOG2;
 440	default:
 441		return -EINVAL;
 442	}
 443	return 0;
 444}
 445
 446/* Applies to max1363 */
 447static const enum max1363_modes max1363_mode_list[] = {
 448	_s0, _s1, _s2, _s3,
 449	s0to1, s0to2, s0to3,
 450	d0m1, d2m3, d1m0, d3m2,
 451	d0m1to2m3, d1m0to3m2,
 452};
 453
 454static const struct iio_event_spec max1363_events[] = {
 455	{
 456		.type = IIO_EV_TYPE_THRESH,
 457		.dir = IIO_EV_DIR_RISING,
 458		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
 459			BIT(IIO_EV_INFO_ENABLE),
 460	}, {
 461		.type = IIO_EV_TYPE_THRESH,
 462		.dir = IIO_EV_DIR_FALLING,
 463		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
 464			BIT(IIO_EV_INFO_ENABLE),
 465	},
 466};
 467
 468#define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec)	\
 469	{								\
 470		.type = IIO_VOLTAGE,					\
 471		.indexed = 1,						\
 472		.channel = num,						\
 473		.address = addr,					\
 474		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
 475		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
 476		.datasheet_name = "AIN"#num,				\
 477		.scan_type = {						\
 478			.sign = 'u',					\
 479			.realbits = bits,				\
 480			.storagebits = (bits > 8) ? 16 : 8,		\
 481			.endianness = IIO_BE,				\
 482		},							\
 483		.scan_index = si,					\
 484		.event_spec = ev_spec,					\
 485		.num_event_specs = num_ev_spec,				\
 486	}
 487
 488/* bipolar channel */
 489#define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec)	\
 490	{								\
 491		.type = IIO_VOLTAGE,					\
 492		.differential = 1,					\
 493		.indexed = 1,						\
 494		.channel = num,						\
 495		.channel2 = num2,					\
 496		.address = addr,					\
 497		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
 498		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
 499		.datasheet_name = "AIN"#num"-AIN"#num2,			\
 500		.scan_type = {						\
 501			.sign = 's',					\
 502			.realbits = bits,				\
 503			.storagebits = (bits > 8) ? 16 : 8,		\
 504			.endianness = IIO_BE,				\
 505		},							\
 506		.scan_index = si,					\
 507		.event_spec = ev_spec,					\
 508		.num_event_specs = num_ev_spec,				\
 509	}
 510
 511#define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) {			\
 512	MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec),		\
 513	MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec),		\
 514	MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec),		\
 515	MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec),		\
 516	MAX1363_CHAN_B(0, 1, d0m1, 4, bits, ev_spec, num_ev_spec),	\
 517	MAX1363_CHAN_B(2, 3, d2m3, 5, bits, ev_spec, num_ev_spec),	\
 518	MAX1363_CHAN_B(1, 0, d1m0, 6, bits, ev_spec, num_ev_spec),	\
 519	MAX1363_CHAN_B(3, 2, d3m2, 7, bits, ev_spec, num_ev_spec),	\
 520	IIO_CHAN_SOFT_TIMESTAMP(8)					\
 521	}
 522
 523static const struct iio_chan_spec max1036_channels[] =
 524	MAX1363_4X_CHANS(8, NULL, 0);
 525static const struct iio_chan_spec max1136_channels[] =
 526	MAX1363_4X_CHANS(10, NULL, 0);
 527static const struct iio_chan_spec max1236_channels[] =
 528	MAX1363_4X_CHANS(12, NULL, 0);
 529static const struct iio_chan_spec max1361_channels[] =
 530	MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events));
 531static const struct iio_chan_spec max1363_channels[] =
 532	MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events));
 533
 534/* Applies to max1236, max1237 */
 535static const enum max1363_modes max1236_mode_list[] = {
 536	_s0, _s1, _s2, _s3,
 537	s0to1, s0to2, s0to3,
 538	d0m1, d2m3, d1m0, d3m2,
 539	d0m1to2m3, d1m0to3m2,
 540	s2to3,
 541};
 542
 543/* Applies to max1238, max1239 */
 544static const enum max1363_modes max1238_mode_list[] = {
 545	_s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
 546	s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
 547	s0to7, s0to8, s0to9, s0to10, s0to11,
 548	d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
 549	d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
 550	d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
 551	d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
 552	s6to7, s6to8, s6to9, s6to10, s6to11,
 553	d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
 554};
 555
 556#define MAX1363_12X_CHANS(bits) {				\
 557	MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0),		\
 558	MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0),		\
 559	MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0),		\
 560	MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0),		\
 561	MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0),		\
 562	MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0),		\
 563	MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0),		\
 564	MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0),		\
 565	MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0),		\
 566	MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0),		\
 567	MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0),		\
 568	MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0),		\
 569	MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0),		\
 570	MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0),		\
 571	MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0),		\
 572	MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0),		\
 573	MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0),		\
 574	MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0),	\
 575	MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0),		\
 576	MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0),		\
 577	MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0),		\
 578	MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0),		\
 579	MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0),		\
 580	MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0),	\
 581	IIO_CHAN_SOFT_TIMESTAMP(24)				\
 582	}
 583static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
 584static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
 585static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
 586
 587static const enum max1363_modes max11607_mode_list[] = {
 588	_s0, _s1, _s2, _s3,
 589	s0to1, s0to2, s0to3,
 590	s2to3,
 591	d0m1, d2m3, d1m0, d3m2,
 592	d0m1to2m3, d1m0to3m2,
 593};
 594
 595static const enum max1363_modes max11608_mode_list[] = {
 596	_s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
 597	s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
 598	s6to7,
 599	d0m1, d2m3, d4m5, d6m7,
 600	d1m0, d3m2, d5m4, d7m6,
 601	d0m1to2m3, d0m1to4m5, d0m1to6m7,
 602	d1m0to3m2, d1m0to5m4, d1m0to7m6,
 603};
 604
 605#define MAX1363_8X_CHANS(bits) {			\
 606	MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0),	\
 607	MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0),	\
 608	MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0),	\
 609	MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0),	\
 610	MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0),	\
 611	MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0),	\
 612	MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0),	\
 613	MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0),	\
 614	MAX1363_CHAN_B(0, 1, d0m1, 8, bits, NULL, 0),	\
 615	MAX1363_CHAN_B(2, 3, d2m3, 9, bits, NULL, 0),	\
 616	MAX1363_CHAN_B(4, 5, d4m5, 10, bits, NULL, 0),	\
 617	MAX1363_CHAN_B(6, 7, d6m7, 11, bits, NULL, 0),	\
 618	MAX1363_CHAN_B(1, 0, d1m0, 12, bits, NULL, 0),	\
 619	MAX1363_CHAN_B(3, 2, d3m2, 13, bits, NULL, 0),	\
 620	MAX1363_CHAN_B(5, 4, d5m4, 14, bits, NULL, 0),	\
 621	MAX1363_CHAN_B(7, 6, d7m6, 15, bits, NULL, 0),	\
 622	IIO_CHAN_SOFT_TIMESTAMP(16)			\
 623}
 624static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
 625static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
 626static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
 627
 628static const enum max1363_modes max11644_mode_list[] = {
 629	_s0, _s1, s0to1, d0m1, d1m0,
 630};
 631
 632#define MAX1363_2X_CHANS(bits) {			\
 633	MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0),	\
 634	MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0),	\
 635	MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0),	\
 636	MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0),	\
 637	IIO_CHAN_SOFT_TIMESTAMP(4)			\
 638	}
 639
 640static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
 641static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
 642
 643enum { max1361,
 644       max1362,
 645       max1363,
 646       max1364,
 647       max1036,
 648       max1037,
 649       max1038,
 650       max1039,
 651       max1136,
 652       max1137,
 653       max1138,
 654       max1139,
 655       max1236,
 656       max1237,
 657       max1238,
 658       max1239,
 659       max11600,
 660       max11601,
 661       max11602,
 662       max11603,
 663       max11604,
 664       max11605,
 665       max11606,
 666       max11607,
 667       max11608,
 668       max11609,
 669       max11610,
 670       max11611,
 671       max11612,
 672       max11613,
 673       max11614,
 674       max11615,
 675       max11616,
 676       max11617,
 677       max11644,
 678       max11645,
 679       max11646,
 680       max11647
 681};
 682
 683static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
 684					      8300, 4200, 2000, 1000 };
 685
 686static ssize_t max1363_monitor_show_freq(struct device *dev,
 687					struct device_attribute *attr,
 688					char *buf)
 689{
 690	struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
 691	return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
 692}
 693
 694static ssize_t max1363_monitor_store_freq(struct device *dev,
 695					struct device_attribute *attr,
 696					const char *buf,
 697					size_t len)
 698{
 699	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 700	struct max1363_state *st = iio_priv(indio_dev);
 701	int i, ret;
 702	unsigned long val;
 703	bool found = false;
 704
 705	ret = kstrtoul(buf, 10, &val);
 706	if (ret)
 707		return -EINVAL;
 708	for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
 709		if (val == max1363_monitor_speeds[i]) {
 710			found = true;
 711			break;
 712		}
 713	if (!found)
 714		return -EINVAL;
 715
 716	mutex_lock(&st->lock);
 717	st->monitor_speed = i;
 718	mutex_unlock(&st->lock);
 719
 720	return 0;
 721}
 722
 723static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
 724			max1363_monitor_show_freq,
 725			max1363_monitor_store_freq);
 726
 727static IIO_CONST_ATTR(sampling_frequency_available,
 728		"133000 665000 33300 16600 8300 4200 2000 1000");
 729
 730static int max1363_read_thresh(struct iio_dev *indio_dev,
 731	const struct iio_chan_spec *chan, enum iio_event_type type,
 732	enum iio_event_direction dir, enum iio_event_info info, int *val,
 733	int *val2)
 734{
 735	struct max1363_state *st = iio_priv(indio_dev);
 736	if (dir == IIO_EV_DIR_FALLING)
 737		*val = st->thresh_low[chan->channel];
 738	else
 739		*val = st->thresh_high[chan->channel];
 740	return IIO_VAL_INT;
 741}
 742
 743static int max1363_write_thresh(struct iio_dev *indio_dev,
 744	const struct iio_chan_spec *chan, enum iio_event_type type,
 745	enum iio_event_direction dir, enum iio_event_info info, int val,
 746	int val2)
 747{
 748	struct max1363_state *st = iio_priv(indio_dev);
 749	/* make it handle signed correctly as well */
 750	switch (st->chip_info->bits) {
 751	case 10:
 752		if (val > 0x3FF)
 753			return -EINVAL;
 754		break;
 755	case 12:
 756		if (val > 0xFFF)
 757			return -EINVAL;
 758		break;
 759	}
 760
 761	switch (dir) {
 762	case IIO_EV_DIR_FALLING:
 763		st->thresh_low[chan->channel] = val;
 764		break;
 765	case IIO_EV_DIR_RISING:
 766		st->thresh_high[chan->channel] = val;
 767		break;
 768	default:
 769		return -EINVAL;
 770	}
 771
 772	return 0;
 773}
 774
 775static const u64 max1363_event_codes[] = {
 776	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
 777			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
 778	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
 779			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
 780	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
 781			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
 782	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
 783			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
 784	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
 785			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
 786	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
 787			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
 788	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
 789			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
 790	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
 791			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
 792};
 793
 794static irqreturn_t max1363_event_handler(int irq, void *private)
 795{
 796	struct iio_dev *indio_dev = private;
 797	struct max1363_state *st = iio_priv(indio_dev);
 798	s64 timestamp = iio_get_time_ns(indio_dev);
 799	unsigned long mask, loc;
 800	u8 rx;
 801	u8 tx[2] = { st->setupbyte,
 802		     MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
 803
 804	st->recv(st->client, &rx, 1);
 805	mask = rx;
 806	for_each_set_bit(loc, &mask, 8)
 807		iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
 808	st->send(st->client, tx, 2);
 809
 810	return IRQ_HANDLED;
 811}
 812
 813static int max1363_read_event_config(struct iio_dev *indio_dev,
 814	const struct iio_chan_spec *chan, enum iio_event_type type,
 815	enum iio_event_direction dir)
 816{
 817	struct max1363_state *st = iio_priv(indio_dev);
 818	int val;
 819	int number = chan->channel;
 820
 821	mutex_lock(&st->lock);
 822	if (dir == IIO_EV_DIR_FALLING)
 823		val = (1 << number) & st->mask_low;
 824	else
 825		val = (1 << number) & st->mask_high;
 826	mutex_unlock(&st->lock);
 827
 828	return val;
 829}
 830
 831static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
 832{
 833	u8 *tx_buf;
 834	int ret, i = 3, j;
 835	unsigned long numelements;
 836	int len;
 837	const long *modemask;
 838
 839	if (!enabled) {
 840		/* transition to buffered capture is not currently supported */
 841		st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
 842		st->configbyte &= ~MAX1363_SCAN_MASK;
 843		st->monitor_on = false;
 844		return max1363_write_basic_config(st);
 845	}
 846
 847	/* Ensure we are in the relevant mode */
 848	st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
 849	st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
 850			    | MAX1363_SCAN_MASK
 851			| MAX1363_SE_DE_MASK);
 852	st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
 853	if ((st->mask_low | st->mask_high) & 0x0F) {
 854		st->configbyte |= max1363_mode_table[s0to3].conf;
 855		modemask = max1363_mode_table[s0to3].modemask;
 856	} else if ((st->mask_low | st->mask_high) & 0x30) {
 857		st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
 858		modemask = max1363_mode_table[d0m1to2m3].modemask;
 859	} else {
 860		st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
 861		modemask = max1363_mode_table[d1m0to3m2].modemask;
 862	}
 863	numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
 864	len = 3 * numelements + 3;
 865	tx_buf = kmalloc(len, GFP_KERNEL);
 866	if (!tx_buf) {
 867		ret = -ENOMEM;
 868		goto error_ret;
 869	}
 870	tx_buf[0] = st->configbyte;
 871	tx_buf[1] = st->setupbyte;
 872	tx_buf[2] = (st->monitor_speed << 1);
 873
 874	/*
 875	 * So we need to do yet another bit of nefarious scan mode
 876	 * setup to match what we need.
 877	 */
 878	for (j = 0; j < 8; j++)
 879		if (test_bit(j, modemask)) {
 880			/* Establish the mode is in the scan */
 881			if (st->mask_low & (1 << j)) {
 882				tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
 883				tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
 884			} else if (j < 4) {
 885				tx_buf[i] = 0;
 886				tx_buf[i + 1] = 0;
 887			} else {
 888				tx_buf[i] = 0x80;
 889				tx_buf[i + 1] = 0;
 890			}
 891			if (st->mask_high & (1 << j)) {
 892				tx_buf[i + 1] |=
 893					(st->thresh_high[j] >> 8) & 0x0F;
 894				tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
 895			} else if (j < 4) {
 896				tx_buf[i + 1] |= 0x0F;
 897				tx_buf[i + 2] = 0xFF;
 898			} else {
 899				tx_buf[i + 1] |= 0x07;
 900				tx_buf[i + 2] = 0xFF;
 901			}
 902			i += 3;
 903		}
 904
 905
 906	ret = st->send(st->client, tx_buf, len);
 907	if (ret < 0)
 908		goto error_ret;
 909	if (ret != len) {
 910		ret = -EIO;
 911		goto error_ret;
 912	}
 913
 914	/*
 915	 * Now that we hopefully have sensible thresholds in place it is
 916	 * time to turn the interrupts on.
 917	 * It is unclear from the data sheet if this should be necessary
 918	 * (i.e. whether monitor mode setup is atomic) but it appears to
 919	 * be in practice.
 920	 */
 921	tx_buf[0] = st->setupbyte;
 922	tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
 923	ret = st->send(st->client, tx_buf, 2);
 924	if (ret < 0)
 925		goto error_ret;
 926	if (ret != 2) {
 927		ret = -EIO;
 928		goto error_ret;
 929	}
 930	ret = 0;
 931	st->monitor_on = true;
 932error_ret:
 933
 934	kfree(tx_buf);
 935
 936	return ret;
 937}
 938
 939/*
 940 * To keep this manageable we always use one of 3 scan modes.
 941 * Scan 0...3, 0-1,2-3 and 1-0,3-2
 942 */
 943
 944static inline int __max1363_check_event_mask(int thismask, int checkmask)
 945{
 946	int ret = 0;
 947	/* Is it unipolar */
 948	if (thismask < 4) {
 949		if (checkmask & ~0x0F) {
 950			ret = -EBUSY;
 951			goto error_ret;
 952		}
 953	} else if (thismask < 6) {
 954		if (checkmask & ~0x30) {
 955			ret = -EBUSY;
 956			goto error_ret;
 957		}
 958	} else if (checkmask & ~0xC0)
 959		ret = -EBUSY;
 960error_ret:
 961	return ret;
 962}
 963
 964static int max1363_write_event_config(struct iio_dev *indio_dev,
 965	const struct iio_chan_spec *chan, enum iio_event_type type,
 966	enum iio_event_direction dir, int state)
 967{
 968	int ret = 0;
 969	struct max1363_state *st = iio_priv(indio_dev);
 970	u16 unifiedmask;
 971	int number = chan->channel;
 972
 973	ret = iio_device_claim_direct_mode(indio_dev);
 974	if (ret)
 975		return ret;
 976	mutex_lock(&st->lock);
 977
 978	unifiedmask = st->mask_low | st->mask_high;
 979	if (dir == IIO_EV_DIR_FALLING) {
 980
 981		if (state == 0)
 982			st->mask_low &= ~(1 << number);
 983		else {
 984			ret = __max1363_check_event_mask((1 << number),
 985							 unifiedmask);
 986			if (ret)
 987				goto error_ret;
 988			st->mask_low |= (1 << number);
 989		}
 990	} else {
 991		if (state == 0)
 992			st->mask_high &= ~(1 << number);
 993		else {
 994			ret = __max1363_check_event_mask((1 << number),
 995							 unifiedmask);
 996			if (ret)
 997				goto error_ret;
 998			st->mask_high |= (1 << number);
 
 
 
 
 
 
 
 
 
 
 
 999		}
1000	}
1001
1002	max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
1003error_ret:
1004	mutex_unlock(&st->lock);
1005	iio_device_release_direct_mode(indio_dev);
1006
1007	return ret;
1008}
1009
1010/*
1011 * As with scan_elements, only certain sets of these can
1012 * be combined.
1013 */
1014static struct attribute *max1363_event_attributes[] = {
1015	&iio_dev_attr_sampling_frequency.dev_attr.attr,
1016	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
1017	NULL,
1018};
1019
1020static const struct attribute_group max1363_event_attribute_group = {
1021	.attrs = max1363_event_attributes,
1022};
1023
1024static int max1363_update_scan_mode(struct iio_dev *indio_dev,
1025				    const unsigned long *scan_mask)
1026{
1027	struct max1363_state *st = iio_priv(indio_dev);
1028
1029	/*
1030	 * Need to figure out the current mode based upon the requested
1031	 * scan mask in iio_dev
1032	 */
1033	st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
1034	if (!st->current_mode)
1035		return -EINVAL;
1036	max1363_set_scan_mode(st);
1037	return 0;
1038}
1039
1040static const struct iio_info max1238_info = {
1041	.read_raw = &max1363_read_raw,
1042	.update_scan_mode = &max1363_update_scan_mode,
1043};
1044
1045static const struct iio_info max1363_info = {
1046	.read_event_value = &max1363_read_thresh,
1047	.write_event_value = &max1363_write_thresh,
1048	.read_event_config = &max1363_read_event_config,
1049	.write_event_config = &max1363_write_event_config,
1050	.read_raw = &max1363_read_raw,
1051	.update_scan_mode = &max1363_update_scan_mode,
1052	.event_attrs = &max1363_event_attribute_group,
1053};
1054
1055/* max1363 and max1368 tested - rest from data sheet */
1056static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1057	[max1361] = {
1058		.bits = 10,
1059		.int_vref_mv = 2048,
1060		.mode_list = max1363_mode_list,
1061		.num_modes = ARRAY_SIZE(max1363_mode_list),
1062		.default_mode = s0to3,
1063		.channels = max1361_channels,
1064		.num_channels = ARRAY_SIZE(max1361_channels),
1065		.info = &max1363_info,
1066	},
1067	[max1362] = {
1068		.bits = 10,
1069		.int_vref_mv = 4096,
1070		.mode_list = max1363_mode_list,
1071		.num_modes = ARRAY_SIZE(max1363_mode_list),
1072		.default_mode = s0to3,
1073		.channels = max1361_channels,
1074		.num_channels = ARRAY_SIZE(max1361_channels),
1075		.info = &max1363_info,
1076	},
1077	[max1363] = {
1078		.bits = 12,
1079		.int_vref_mv = 2048,
1080		.mode_list = max1363_mode_list,
1081		.num_modes = ARRAY_SIZE(max1363_mode_list),
1082		.default_mode = s0to3,
1083		.channels = max1363_channels,
1084		.num_channels = ARRAY_SIZE(max1363_channels),
1085		.info = &max1363_info,
1086	},
1087	[max1364] = {
1088		.bits = 12,
1089		.int_vref_mv = 4096,
1090		.mode_list = max1363_mode_list,
1091		.num_modes = ARRAY_SIZE(max1363_mode_list),
1092		.default_mode = s0to3,
1093		.channels = max1363_channels,
1094		.num_channels = ARRAY_SIZE(max1363_channels),
1095		.info = &max1363_info,
1096	},
1097	[max1036] = {
1098		.bits = 8,
1099		.int_vref_mv = 4096,
1100		.mode_list = max1236_mode_list,
1101		.num_modes = ARRAY_SIZE(max1236_mode_list),
1102		.default_mode = s0to3,
1103		.info = &max1238_info,
1104		.channels = max1036_channels,
1105		.num_channels = ARRAY_SIZE(max1036_channels),
1106	},
1107	[max1037] = {
1108		.bits = 8,
1109		.int_vref_mv = 2048,
1110		.mode_list = max1236_mode_list,
1111		.num_modes = ARRAY_SIZE(max1236_mode_list),
1112		.default_mode = s0to3,
1113		.info = &max1238_info,
1114		.channels = max1036_channels,
1115		.num_channels = ARRAY_SIZE(max1036_channels),
1116	},
1117	[max1038] = {
1118		.bits = 8,
1119		.int_vref_mv = 4096,
1120		.mode_list = max1238_mode_list,
1121		.num_modes = ARRAY_SIZE(max1238_mode_list),
1122		.default_mode = s0to11,
1123		.info = &max1238_info,
1124		.channels = max1038_channels,
1125		.num_channels = ARRAY_SIZE(max1038_channels),
1126	},
1127	[max1039] = {
1128		.bits = 8,
1129		.int_vref_mv = 2048,
1130		.mode_list = max1238_mode_list,
1131		.num_modes = ARRAY_SIZE(max1238_mode_list),
1132		.default_mode = s0to11,
1133		.info = &max1238_info,
1134		.channels = max1038_channels,
1135		.num_channels = ARRAY_SIZE(max1038_channels),
1136	},
1137	[max1136] = {
1138		.bits = 10,
1139		.int_vref_mv = 4096,
1140		.mode_list = max1236_mode_list,
1141		.num_modes = ARRAY_SIZE(max1236_mode_list),
1142		.default_mode = s0to3,
1143		.info = &max1238_info,
1144		.channels = max1136_channels,
1145		.num_channels = ARRAY_SIZE(max1136_channels),
1146	},
1147	[max1137] = {
1148		.bits = 10,
1149		.int_vref_mv = 2048,
1150		.mode_list = max1236_mode_list,
1151		.num_modes = ARRAY_SIZE(max1236_mode_list),
1152		.default_mode = s0to3,
1153		.info = &max1238_info,
1154		.channels = max1136_channels,
1155		.num_channels = ARRAY_SIZE(max1136_channels),
1156	},
1157	[max1138] = {
1158		.bits = 10,
1159		.int_vref_mv = 4096,
1160		.mode_list = max1238_mode_list,
1161		.num_modes = ARRAY_SIZE(max1238_mode_list),
1162		.default_mode = s0to11,
1163		.info = &max1238_info,
1164		.channels = max1138_channels,
1165		.num_channels = ARRAY_SIZE(max1138_channels),
1166	},
1167	[max1139] = {
1168		.bits = 10,
1169		.int_vref_mv = 2048,
1170		.mode_list = max1238_mode_list,
1171		.num_modes = ARRAY_SIZE(max1238_mode_list),
1172		.default_mode = s0to11,
1173		.info = &max1238_info,
1174		.channels = max1138_channels,
1175		.num_channels = ARRAY_SIZE(max1138_channels),
1176	},
1177	[max1236] = {
1178		.bits = 12,
1179		.int_vref_mv = 4096,
1180		.mode_list = max1236_mode_list,
1181		.num_modes = ARRAY_SIZE(max1236_mode_list),
1182		.default_mode = s0to3,
1183		.info = &max1238_info,
1184		.channels = max1236_channels,
1185		.num_channels = ARRAY_SIZE(max1236_channels),
1186	},
1187	[max1237] = {
1188		.bits = 12,
1189		.int_vref_mv = 2048,
1190		.mode_list = max1236_mode_list,
1191		.num_modes = ARRAY_SIZE(max1236_mode_list),
1192		.default_mode = s0to3,
1193		.info = &max1238_info,
1194		.channels = max1236_channels,
1195		.num_channels = ARRAY_SIZE(max1236_channels),
1196	},
1197	[max1238] = {
1198		.bits = 12,
1199		.int_vref_mv = 4096,
1200		.mode_list = max1238_mode_list,
1201		.num_modes = ARRAY_SIZE(max1238_mode_list),
1202		.default_mode = s0to11,
1203		.info = &max1238_info,
1204		.channels = max1238_channels,
1205		.num_channels = ARRAY_SIZE(max1238_channels),
1206	},
1207	[max1239] = {
1208		.bits = 12,
1209		.int_vref_mv = 2048,
1210		.mode_list = max1238_mode_list,
1211		.num_modes = ARRAY_SIZE(max1238_mode_list),
1212		.default_mode = s0to11,
1213		.info = &max1238_info,
1214		.channels = max1238_channels,
1215		.num_channels = ARRAY_SIZE(max1238_channels),
1216	},
1217	[max11600] = {
1218		.bits = 8,
1219		.int_vref_mv = 4096,
1220		.mode_list = max11607_mode_list,
1221		.num_modes = ARRAY_SIZE(max11607_mode_list),
1222		.default_mode = s0to3,
1223		.info = &max1238_info,
1224		.channels = max1036_channels,
1225		.num_channels = ARRAY_SIZE(max1036_channels),
1226	},
1227	[max11601] = {
1228		.bits = 8,
1229		.int_vref_mv = 2048,
1230		.mode_list = max11607_mode_list,
1231		.num_modes = ARRAY_SIZE(max11607_mode_list),
1232		.default_mode = s0to3,
1233		.info = &max1238_info,
1234		.channels = max1036_channels,
1235		.num_channels = ARRAY_SIZE(max1036_channels),
1236	},
1237	[max11602] = {
1238		.bits = 8,
1239		.int_vref_mv = 4096,
1240		.mode_list = max11608_mode_list,
1241		.num_modes = ARRAY_SIZE(max11608_mode_list),
1242		.default_mode = s0to7,
1243		.info = &max1238_info,
1244		.channels = max11602_channels,
1245		.num_channels = ARRAY_SIZE(max11602_channels),
1246	},
1247	[max11603] = {
1248		.bits = 8,
1249		.int_vref_mv = 2048,
1250		.mode_list = max11608_mode_list,
1251		.num_modes = ARRAY_SIZE(max11608_mode_list),
1252		.default_mode = s0to7,
1253		.info = &max1238_info,
1254		.channels = max11602_channels,
1255		.num_channels = ARRAY_SIZE(max11602_channels),
1256	},
1257	[max11604] = {
1258		.bits = 8,
1259		.int_vref_mv = 4096,
1260		.mode_list = max1238_mode_list,
1261		.num_modes = ARRAY_SIZE(max1238_mode_list),
1262		.default_mode = s0to11,
1263		.info = &max1238_info,
1264		.channels = max1038_channels,
1265		.num_channels = ARRAY_SIZE(max1038_channels),
1266	},
1267	[max11605] = {
1268		.bits = 8,
1269		.int_vref_mv = 2048,
1270		.mode_list = max1238_mode_list,
1271		.num_modes = ARRAY_SIZE(max1238_mode_list),
1272		.default_mode = s0to11,
1273		.info = &max1238_info,
1274		.channels = max1038_channels,
1275		.num_channels = ARRAY_SIZE(max1038_channels),
1276	},
1277	[max11606] = {
1278		.bits = 10,
1279		.int_vref_mv = 4096,
1280		.mode_list = max11607_mode_list,
1281		.num_modes = ARRAY_SIZE(max11607_mode_list),
1282		.default_mode = s0to3,
1283		.info = &max1238_info,
1284		.channels = max1136_channels,
1285		.num_channels = ARRAY_SIZE(max1136_channels),
1286	},
1287	[max11607] = {
1288		.bits = 10,
1289		.int_vref_mv = 2048,
1290		.mode_list = max11607_mode_list,
1291		.num_modes = ARRAY_SIZE(max11607_mode_list),
1292		.default_mode = s0to3,
1293		.info = &max1238_info,
1294		.channels = max1136_channels,
1295		.num_channels = ARRAY_SIZE(max1136_channels),
1296	},
1297	[max11608] = {
1298		.bits = 10,
1299		.int_vref_mv = 4096,
1300		.mode_list = max11608_mode_list,
1301		.num_modes = ARRAY_SIZE(max11608_mode_list),
1302		.default_mode = s0to7,
1303		.info = &max1238_info,
1304		.channels = max11608_channels,
1305		.num_channels = ARRAY_SIZE(max11608_channels),
1306	},
1307	[max11609] = {
1308		.bits = 10,
1309		.int_vref_mv = 2048,
1310		.mode_list = max11608_mode_list,
1311		.num_modes = ARRAY_SIZE(max11608_mode_list),
1312		.default_mode = s0to7,
1313		.info = &max1238_info,
1314		.channels = max11608_channels,
1315		.num_channels = ARRAY_SIZE(max11608_channels),
1316	},
1317	[max11610] = {
1318		.bits = 10,
1319		.int_vref_mv = 4096,
1320		.mode_list = max1238_mode_list,
1321		.num_modes = ARRAY_SIZE(max1238_mode_list),
1322		.default_mode = s0to11,
1323		.info = &max1238_info,
1324		.channels = max1138_channels,
1325		.num_channels = ARRAY_SIZE(max1138_channels),
1326	},
1327	[max11611] = {
1328		.bits = 10,
1329		.int_vref_mv = 2048,
1330		.mode_list = max1238_mode_list,
1331		.num_modes = ARRAY_SIZE(max1238_mode_list),
1332		.default_mode = s0to11,
1333		.info = &max1238_info,
1334		.channels = max1138_channels,
1335		.num_channels = ARRAY_SIZE(max1138_channels),
1336	},
1337	[max11612] = {
1338		.bits = 12,
1339		.int_vref_mv = 4096,
1340		.mode_list = max11607_mode_list,
1341		.num_modes = ARRAY_SIZE(max11607_mode_list),
1342		.default_mode = s0to3,
1343		.info = &max1238_info,
1344		.channels = max1363_channels,
1345		.num_channels = ARRAY_SIZE(max1363_channels),
1346	},
1347	[max11613] = {
1348		.bits = 12,
1349		.int_vref_mv = 2048,
1350		.mode_list = max11607_mode_list,
1351		.num_modes = ARRAY_SIZE(max11607_mode_list),
1352		.default_mode = s0to3,
1353		.info = &max1238_info,
1354		.channels = max1363_channels,
1355		.num_channels = ARRAY_SIZE(max1363_channels),
1356	},
1357	[max11614] = {
1358		.bits = 12,
1359		.int_vref_mv = 4096,
1360		.mode_list = max11608_mode_list,
1361		.num_modes = ARRAY_SIZE(max11608_mode_list),
1362		.default_mode = s0to7,
1363		.info = &max1238_info,
1364		.channels = max11614_channels,
1365		.num_channels = ARRAY_SIZE(max11614_channels),
1366	},
1367	[max11615] = {
1368		.bits = 12,
1369		.int_vref_mv = 2048,
1370		.mode_list = max11608_mode_list,
1371		.num_modes = ARRAY_SIZE(max11608_mode_list),
1372		.default_mode = s0to7,
1373		.info = &max1238_info,
1374		.channels = max11614_channels,
1375		.num_channels = ARRAY_SIZE(max11614_channels),
1376	},
1377	[max11616] = {
1378		.bits = 12,
1379		.int_vref_mv = 4096,
1380		.mode_list = max1238_mode_list,
1381		.num_modes = ARRAY_SIZE(max1238_mode_list),
1382		.default_mode = s0to11,
1383		.info = &max1238_info,
1384		.channels = max1238_channels,
1385		.num_channels = ARRAY_SIZE(max1238_channels),
1386	},
1387	[max11617] = {
1388		.bits = 12,
1389		.int_vref_mv = 2048,
1390		.mode_list = max1238_mode_list,
1391		.num_modes = ARRAY_SIZE(max1238_mode_list),
1392		.default_mode = s0to11,
1393		.info = &max1238_info,
1394		.channels = max1238_channels,
1395		.num_channels = ARRAY_SIZE(max1238_channels),
1396	},
1397	[max11644] = {
1398		.bits = 12,
1399		.int_vref_mv = 4096,
1400		.mode_list = max11644_mode_list,
1401		.num_modes = ARRAY_SIZE(max11644_mode_list),
1402		.default_mode = s0to1,
1403		.info = &max1238_info,
1404		.channels = max11644_channels,
1405		.num_channels = ARRAY_SIZE(max11644_channels),
1406	},
1407	[max11645] = {
1408		.bits = 12,
1409		.int_vref_mv = 2048,
1410		.mode_list = max11644_mode_list,
1411		.num_modes = ARRAY_SIZE(max11644_mode_list),
1412		.default_mode = s0to1,
1413		.info = &max1238_info,
1414		.channels = max11644_channels,
1415		.num_channels = ARRAY_SIZE(max11644_channels),
1416	},
1417	[max11646] = {
1418		.bits = 10,
1419		.int_vref_mv = 4096,
1420		.mode_list = max11644_mode_list,
1421		.num_modes = ARRAY_SIZE(max11644_mode_list),
1422		.default_mode = s0to1,
1423		.info = &max1238_info,
1424		.channels = max11646_channels,
1425		.num_channels = ARRAY_SIZE(max11646_channels),
1426	},
1427	[max11647] = {
1428		.bits = 10,
1429		.int_vref_mv = 2048,
1430		.mode_list = max11644_mode_list,
1431		.num_modes = ARRAY_SIZE(max11644_mode_list),
1432		.default_mode = s0to1,
1433		.info = &max1238_info,
1434		.channels = max11646_channels,
1435		.num_channels = ARRAY_SIZE(max11646_channels),
1436	},
1437};
1438
1439static int max1363_initial_setup(struct max1363_state *st)
1440{
1441	st->setupbyte = MAX1363_SETUP_INT_CLOCK
1442		| MAX1363_SETUP_UNIPOLAR
1443		| MAX1363_SETUP_NORESET;
1444
1445	if (st->vref)
1446		st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1447	else
1448		st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1449		  | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1450
1451	/* Set scan mode writes the config anyway so wait until then */
1452	st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1453	st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1454	st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1455
1456	return max1363_set_scan_mode(st);
1457}
1458
1459static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1460{
1461	struct max1363_state *st = iio_priv(indio_dev);
1462	unsigned long *masks;
1463	int i;
1464
1465	masks = devm_kzalloc(&indio_dev->dev,
1466			array3_size(BITS_TO_LONGS(MAX1363_MAX_CHANNELS),
1467				    sizeof(long),
1468				    st->chip_info->num_modes + 1),
1469			GFP_KERNEL);
1470	if (!masks)
1471		return -ENOMEM;
1472
1473	for (i = 0; i < st->chip_info->num_modes; i++)
1474		bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1475			    max1363_mode_table[st->chip_info->mode_list[i]]
1476			    .modemask, MAX1363_MAX_CHANNELS);
1477
1478	indio_dev->available_scan_masks = masks;
1479
1480	return 0;
1481}
1482
1483static irqreturn_t max1363_trigger_handler(int irq, void *p)
1484{
1485	struct iio_poll_func *pf = p;
1486	struct iio_dev *indio_dev = pf->indio_dev;
1487	struct max1363_state *st = iio_priv(indio_dev);
1488	__u8 *rxbuf;
1489	int b_sent;
1490	size_t d_size;
1491	unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1492					      MAX1363_MAX_CHANNELS);
1493
1494	/* Ensure the timestamp is 8 byte aligned */
1495	if (st->chip_info->bits != 8)
1496		d_size = numvals*2;
1497	else
1498		d_size = numvals;
1499	if (indio_dev->scan_timestamp) {
1500		d_size += sizeof(s64);
1501		if (d_size % sizeof(s64))
1502			d_size += sizeof(s64) - (d_size % sizeof(s64));
1503	}
1504	/* Monitor mode prevents reading. Whilst not currently implemented
1505	 * might as well have this test in here in the meantime as it does
1506	 * no harm.
1507	 */
1508	if (numvals == 0)
1509		goto done;
1510
1511	rxbuf = kmalloc(d_size,	GFP_KERNEL);
1512	if (rxbuf == NULL)
1513		goto done;
1514	if (st->chip_info->bits != 8)
1515		b_sent = st->recv(st->client, rxbuf, numvals * 2);
1516	else
1517		b_sent = st->recv(st->client, rxbuf, numvals);
1518	if (b_sent < 0)
1519		goto done_free;
1520
1521	iio_push_to_buffers_with_timestamp(indio_dev, rxbuf,
1522					   iio_get_time_ns(indio_dev));
1523
1524done_free:
1525	kfree(rxbuf);
1526done:
1527	iio_trigger_notify_done(indio_dev->trig);
1528
1529	return IRQ_HANDLED;
1530}
1531
1532#define MAX1363_COMPATIBLE(of_compatible, cfg) {		\
1533			.compatible = of_compatible,		\
1534			.data = &max1363_chip_info_tbl[cfg],	\
1535}
1536
1537static const struct of_device_id max1363_of_match[] = {
1538	MAX1363_COMPATIBLE("maxim,max1361", max1361),
1539	MAX1363_COMPATIBLE("maxim,max1362", max1362),
1540	MAX1363_COMPATIBLE("maxim,max1363", max1363),
1541	MAX1363_COMPATIBLE("maxim,max1364", max1364),
1542	MAX1363_COMPATIBLE("maxim,max1036", max1036),
1543	MAX1363_COMPATIBLE("maxim,max1037", max1037),
1544	MAX1363_COMPATIBLE("maxim,max1038", max1038),
1545	MAX1363_COMPATIBLE("maxim,max1039", max1039),
1546	MAX1363_COMPATIBLE("maxim,max1136", max1136),
1547	MAX1363_COMPATIBLE("maxim,max1137", max1137),
1548	MAX1363_COMPATIBLE("maxim,max1138", max1138),
1549	MAX1363_COMPATIBLE("maxim,max1139", max1139),
1550	MAX1363_COMPATIBLE("maxim,max1236", max1236),
1551	MAX1363_COMPATIBLE("maxim,max1237", max1237),
1552	MAX1363_COMPATIBLE("maxim,max1238", max1238),
1553	MAX1363_COMPATIBLE("maxim,max1239", max1239),
1554	MAX1363_COMPATIBLE("maxim,max11600", max11600),
1555	MAX1363_COMPATIBLE("maxim,max11601", max11601),
1556	MAX1363_COMPATIBLE("maxim,max11602", max11602),
1557	MAX1363_COMPATIBLE("maxim,max11603", max11603),
1558	MAX1363_COMPATIBLE("maxim,max11604", max11604),
1559	MAX1363_COMPATIBLE("maxim,max11605", max11605),
1560	MAX1363_COMPATIBLE("maxim,max11606", max11606),
1561	MAX1363_COMPATIBLE("maxim,max11607", max11607),
1562	MAX1363_COMPATIBLE("maxim,max11608", max11608),
1563	MAX1363_COMPATIBLE("maxim,max11609", max11609),
1564	MAX1363_COMPATIBLE("maxim,max11610", max11610),
1565	MAX1363_COMPATIBLE("maxim,max11611", max11611),
1566	MAX1363_COMPATIBLE("maxim,max11612", max11612),
1567	MAX1363_COMPATIBLE("maxim,max11613", max11613),
1568	MAX1363_COMPATIBLE("maxim,max11614", max11614),
1569	MAX1363_COMPATIBLE("maxim,max11615", max11615),
1570	MAX1363_COMPATIBLE("maxim,max11616", max11616),
1571	MAX1363_COMPATIBLE("maxim,max11617", max11617),
1572	MAX1363_COMPATIBLE("maxim,max11644", max11644),
1573	MAX1363_COMPATIBLE("maxim,max11645", max11645),
1574	MAX1363_COMPATIBLE("maxim,max11646", max11646),
1575	MAX1363_COMPATIBLE("maxim,max11647", max11647),
1576	{ /* sentinel */ }
1577};
1578MODULE_DEVICE_TABLE(of, max1363_of_match);
1579
1580static int max1363_probe(struct i2c_client *client,
1581			 const struct i2c_device_id *id)
1582{
 
1583	int ret;
1584	struct max1363_state *st;
1585	struct iio_dev *indio_dev;
1586	struct regulator *vref;
1587
1588	indio_dev = devm_iio_device_alloc(&client->dev,
1589					  sizeof(struct max1363_state));
1590	if (!indio_dev)
1591		return -ENOMEM;
1592
1593	ret = iio_map_array_register(indio_dev, client->dev.platform_data);
1594	if (ret < 0)
1595		return ret;
1596
1597	st = iio_priv(indio_dev);
1598
1599	mutex_init(&st->lock);
1600	st->reg = devm_regulator_get(&client->dev, "vcc");
1601	if (IS_ERR(st->reg)) {
1602		ret = PTR_ERR(st->reg);
1603		goto error_unregister_map;
1604	}
1605
1606	ret = regulator_enable(st->reg);
1607	if (ret)
1608		goto error_unregister_map;
1609
1610	/* this is only used for device removal purposes */
1611	i2c_set_clientdata(client, indio_dev);
1612
1613	st->chip_info = device_get_match_data(&client->dev);
1614	if (!st->chip_info)
1615		st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1616	st->client = client;
1617
1618	st->vref_uv = st->chip_info->int_vref_mv * 1000;
1619	vref = devm_regulator_get_optional(&client->dev, "vref");
1620	if (!IS_ERR(vref)) {
1621		int vref_uv;
1622
1623		ret = regulator_enable(vref);
1624		if (ret)
1625			goto error_disable_reg;
1626		st->vref = vref;
1627		vref_uv = regulator_get_voltage(vref);
1628		if (vref_uv <= 0) {
1629			ret = -EINVAL;
1630			goto error_disable_reg;
1631		}
1632		st->vref_uv = vref_uv;
1633	}
1634
1635	if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1636		st->send = i2c_master_send;
1637		st->recv = i2c_master_recv;
1638	} else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE)
1639			&& st->chip_info->bits == 8) {
1640		st->send = max1363_smbus_send;
1641		st->recv = max1363_smbus_recv;
1642	} else {
1643		ret = -EOPNOTSUPP;
1644		goto error_disable_reg;
1645	}
1646
1647	ret = max1363_alloc_scan_masks(indio_dev);
1648	if (ret)
1649		goto error_disable_reg;
1650
1651	indio_dev->name = id->name;
1652	indio_dev->channels = st->chip_info->channels;
1653	indio_dev->num_channels = st->chip_info->num_channels;
1654	indio_dev->info = st->chip_info->info;
1655	indio_dev->modes = INDIO_DIRECT_MODE;
1656	ret = max1363_initial_setup(st);
1657	if (ret < 0)
1658		goto error_disable_reg;
1659
1660	ret = iio_triggered_buffer_setup(indio_dev, NULL,
1661		&max1363_trigger_handler, NULL);
1662	if (ret)
1663		goto error_disable_reg;
1664
1665	if (client->irq) {
1666		ret = devm_request_threaded_irq(&client->dev, st->client->irq,
1667					   NULL,
1668					   &max1363_event_handler,
1669					   IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1670					   "max1363_event",
1671					   indio_dev);
1672
1673		if (ret)
1674			goto error_uninit_buffer;
1675	}
1676
1677	ret = iio_device_register(indio_dev);
1678	if (ret < 0)
1679		goto error_uninit_buffer;
1680
1681	return 0;
1682
1683error_uninit_buffer:
1684	iio_triggered_buffer_cleanup(indio_dev);
1685error_disable_reg:
1686	if (st->vref)
1687		regulator_disable(st->vref);
1688	regulator_disable(st->reg);
1689error_unregister_map:
1690	iio_map_array_unregister(indio_dev);
1691	return ret;
1692}
1693
1694static int max1363_remove(struct i2c_client *client)
1695{
1696	struct iio_dev *indio_dev = i2c_get_clientdata(client);
1697	struct max1363_state *st = iio_priv(indio_dev);
1698
1699	iio_device_unregister(indio_dev);
1700	iio_triggered_buffer_cleanup(indio_dev);
1701	if (st->vref)
1702		regulator_disable(st->vref);
1703	regulator_disable(st->reg);
1704	iio_map_array_unregister(indio_dev);
1705
1706	return 0;
1707}
1708
1709static const struct i2c_device_id max1363_id[] = {
1710	{ "max1361", max1361 },
1711	{ "max1362", max1362 },
1712	{ "max1363", max1363 },
1713	{ "max1364", max1364 },
1714	{ "max1036", max1036 },
1715	{ "max1037", max1037 },
1716	{ "max1038", max1038 },
1717	{ "max1039", max1039 },
1718	{ "max1136", max1136 },
1719	{ "max1137", max1137 },
1720	{ "max1138", max1138 },
1721	{ "max1139", max1139 },
1722	{ "max1236", max1236 },
1723	{ "max1237", max1237 },
1724	{ "max1238", max1238 },
1725	{ "max1239", max1239 },
1726	{ "max11600", max11600 },
1727	{ "max11601", max11601 },
1728	{ "max11602", max11602 },
1729	{ "max11603", max11603 },
1730	{ "max11604", max11604 },
1731	{ "max11605", max11605 },
1732	{ "max11606", max11606 },
1733	{ "max11607", max11607 },
1734	{ "max11608", max11608 },
1735	{ "max11609", max11609 },
1736	{ "max11610", max11610 },
1737	{ "max11611", max11611 },
1738	{ "max11612", max11612 },
1739	{ "max11613", max11613 },
1740	{ "max11614", max11614 },
1741	{ "max11615", max11615 },
1742	{ "max11616", max11616 },
1743	{ "max11617", max11617 },
1744	{ "max11644", max11644 },
1745	{ "max11645", max11645 },
1746	{ "max11646", max11646 },
1747	{ "max11647", max11647 },
1748	{}
1749};
1750
1751MODULE_DEVICE_TABLE(i2c, max1363_id);
1752
1753static struct i2c_driver max1363_driver = {
1754	.driver = {
1755		.name = "max1363",
1756		.of_match_table = max1363_of_match,
1757	},
1758	.probe = max1363_probe,
1759	.remove = max1363_remove,
1760	.id_table = max1363_id,
1761};
1762module_i2c_driver(max1363_driver);
1763
1764MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1765MODULE_DESCRIPTION("Maxim 1363 ADC");
1766MODULE_LICENSE("GPL v2");