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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Analog Devices AD7466/7/8 AD7476/5/7/8 (A) SPI ADC driver
4 * TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver
5 *
6 * Copyright 2010 Analog Devices Inc.
7 */
8
9#include <linux/device.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/sysfs.h>
13#include <linux/spi/spi.h>
14#include <linux/regulator/consumer.h>
15#include <linux/gpio/consumer.h>
16#include <linux/err.h>
17#include <linux/module.h>
18#include <linux/bitops.h>
19#include <linux/delay.h>
20
21#include <linux/iio/iio.h>
22#include <linux/iio/sysfs.h>
23#include <linux/iio/buffer.h>
24#include <linux/iio/trigger_consumer.h>
25#include <linux/iio/triggered_buffer.h>
26
27struct ad7476_state;
28
29struct ad7476_chip_info {
30 unsigned int int_vref_uv;
31 struct iio_chan_spec channel[2];
32 /* channels used when convst gpio is defined */
33 struct iio_chan_spec convst_channel[2];
34 void (*reset)(struct ad7476_state *);
35};
36
37struct ad7476_state {
38 struct spi_device *spi;
39 const struct ad7476_chip_info *chip_info;
40 struct regulator *reg;
41 struct gpio_desc *convst_gpio;
42 struct spi_transfer xfer;
43 struct spi_message msg;
44 /*
45 * DMA (thus cache coherency maintenance) requires the
46 * transfer buffers to live in their own cache lines.
47 * Make the buffer large enough for one 16 bit sample and one 64 bit
48 * aligned 64 bit timestamp.
49 */
50 unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)]
51 ____cacheline_aligned;
52};
53
54enum ad7476_supported_device_ids {
55 ID_AD7091R,
56 ID_AD7276,
57 ID_AD7277,
58 ID_AD7278,
59 ID_AD7466,
60 ID_AD7467,
61 ID_AD7468,
62 ID_AD7495,
63 ID_AD7940,
64 ID_ADC081S,
65 ID_ADC101S,
66 ID_ADC121S,
67 ID_ADS7866,
68 ID_ADS7867,
69 ID_ADS7868,
70};
71
72static void ad7091_convst(struct ad7476_state *st)
73{
74 if (!st->convst_gpio)
75 return;
76
77 gpiod_set_value(st->convst_gpio, 0);
78 udelay(1); /* CONVST pulse width: 10 ns min */
79 gpiod_set_value(st->convst_gpio, 1);
80 udelay(1); /* Conversion time: 650 ns max */
81}
82
83static irqreturn_t ad7476_trigger_handler(int irq, void *p)
84{
85 struct iio_poll_func *pf = p;
86 struct iio_dev *indio_dev = pf->indio_dev;
87 struct ad7476_state *st = iio_priv(indio_dev);
88 int b_sent;
89
90 ad7091_convst(st);
91
92 b_sent = spi_sync(st->spi, &st->msg);
93 if (b_sent < 0)
94 goto done;
95
96 iio_push_to_buffers_with_timestamp(indio_dev, st->data,
97 iio_get_time_ns(indio_dev));
98done:
99 iio_trigger_notify_done(indio_dev->trig);
100
101 return IRQ_HANDLED;
102}
103
104static void ad7091_reset(struct ad7476_state *st)
105{
106 /* Any transfers with 8 scl cycles will reset the device */
107 spi_read(st->spi, st->data, 1);
108}
109
110static int ad7476_scan_direct(struct ad7476_state *st)
111{
112 int ret;
113
114 ad7091_convst(st);
115
116 ret = spi_sync(st->spi, &st->msg);
117 if (ret)
118 return ret;
119
120 return be16_to_cpup((__be16 *)st->data);
121}
122
123static int ad7476_read_raw(struct iio_dev *indio_dev,
124 struct iio_chan_spec const *chan,
125 int *val,
126 int *val2,
127 long m)
128{
129 int ret;
130 struct ad7476_state *st = iio_priv(indio_dev);
131 int scale_uv;
132
133 switch (m) {
134 case IIO_CHAN_INFO_RAW:
135 ret = iio_device_claim_direct_mode(indio_dev);
136 if (ret)
137 return ret;
138 ret = ad7476_scan_direct(st);
139 iio_device_release_direct_mode(indio_dev);
140
141 if (ret < 0)
142 return ret;
143 *val = (ret >> st->chip_info->channel[0].scan_type.shift) &
144 GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0);
145 return IIO_VAL_INT;
146 case IIO_CHAN_INFO_SCALE:
147 if (!st->chip_info->int_vref_uv) {
148 scale_uv = regulator_get_voltage(st->reg);
149 if (scale_uv < 0)
150 return scale_uv;
151 } else {
152 scale_uv = st->chip_info->int_vref_uv;
153 }
154 *val = scale_uv / 1000;
155 *val2 = chan->scan_type.realbits;
156 return IIO_VAL_FRACTIONAL_LOG2;
157 }
158 return -EINVAL;
159}
160
161#define _AD7476_CHAN(bits, _shift, _info_mask_sep) \
162 { \
163 .type = IIO_VOLTAGE, \
164 .indexed = 1, \
165 .info_mask_separate = _info_mask_sep, \
166 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
167 .scan_type = { \
168 .sign = 'u', \
169 .realbits = (bits), \
170 .storagebits = 16, \
171 .shift = (_shift), \
172 .endianness = IIO_BE, \
173 }, \
174}
175
176#define ADC081S_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
177 BIT(IIO_CHAN_INFO_RAW))
178#define AD7476_CHAN(bits) _AD7476_CHAN((bits), 13 - (bits), \
179 BIT(IIO_CHAN_INFO_RAW))
180#define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \
181 BIT(IIO_CHAN_INFO_RAW))
182#define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0)
183#define AD7091R_CONVST_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), \
184 BIT(IIO_CHAN_INFO_RAW))
185#define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
186 BIT(IIO_CHAN_INFO_RAW))
187
188static const struct ad7476_chip_info ad7476_chip_info_tbl[] = {
189 [ID_AD7091R] = {
190 .channel[0] = AD7091R_CHAN(12),
191 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
192 .convst_channel[0] = AD7091R_CONVST_CHAN(12),
193 .convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
194 .reset = ad7091_reset,
195 },
196 [ID_AD7276] = {
197 .channel[0] = AD7940_CHAN(12),
198 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
199 },
200 [ID_AD7277] = {
201 .channel[0] = AD7940_CHAN(10),
202 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
203 },
204 [ID_AD7278] = {
205 .channel[0] = AD7940_CHAN(8),
206 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
207 },
208 [ID_AD7466] = {
209 .channel[0] = AD7476_CHAN(12),
210 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
211 },
212 [ID_AD7467] = {
213 .channel[0] = AD7476_CHAN(10),
214 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
215 },
216 [ID_AD7468] = {
217 .channel[0] = AD7476_CHAN(8),
218 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
219 },
220 [ID_AD7495] = {
221 .channel[0] = AD7476_CHAN(12),
222 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
223 .int_vref_uv = 2500000,
224 },
225 [ID_AD7940] = {
226 .channel[0] = AD7940_CHAN(14),
227 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
228 },
229 [ID_ADC081S] = {
230 .channel[0] = ADC081S_CHAN(8),
231 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
232 },
233 [ID_ADC101S] = {
234 .channel[0] = ADC081S_CHAN(10),
235 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
236 },
237 [ID_ADC121S] = {
238 .channel[0] = ADC081S_CHAN(12),
239 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
240 },
241 [ID_ADS7866] = {
242 .channel[0] = ADS786X_CHAN(12),
243 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
244 },
245 [ID_ADS7867] = {
246 .channel[0] = ADS786X_CHAN(10),
247 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
248 },
249 [ID_ADS7868] = {
250 .channel[0] = ADS786X_CHAN(8),
251 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
252 },
253};
254
255static const struct iio_info ad7476_info = {
256 .read_raw = &ad7476_read_raw,
257};
258
259static void ad7476_reg_disable(void *data)
260{
261 struct ad7476_state *st = data;
262
263 regulator_disable(st->reg);
264}
265
266static int ad7476_probe(struct spi_device *spi)
267{
268 struct ad7476_state *st;
269 struct iio_dev *indio_dev;
270 int ret;
271
272 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
273 if (!indio_dev)
274 return -ENOMEM;
275
276 st = iio_priv(indio_dev);
277 st->chip_info =
278 &ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data];
279
280 st->reg = devm_regulator_get(&spi->dev, "vcc");
281 if (IS_ERR(st->reg))
282 return PTR_ERR(st->reg);
283
284 ret = regulator_enable(st->reg);
285 if (ret)
286 return ret;
287
288 ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable,
289 st);
290 if (ret)
291 return ret;
292
293 st->convst_gpio = devm_gpiod_get_optional(&spi->dev,
294 "adi,conversion-start",
295 GPIOD_OUT_LOW);
296 if (IS_ERR(st->convst_gpio))
297 return PTR_ERR(st->convst_gpio);
298
299 spi_set_drvdata(spi, indio_dev);
300
301 st->spi = spi;
302
303 indio_dev->name = spi_get_device_id(spi)->name;
304 indio_dev->modes = INDIO_DIRECT_MODE;
305 indio_dev->channels = st->chip_info->channel;
306 indio_dev->num_channels = 2;
307 indio_dev->info = &ad7476_info;
308
309 if (st->convst_gpio)
310 indio_dev->channels = st->chip_info->convst_channel;
311 /* Setup default message */
312
313 st->xfer.rx_buf = &st->data;
314 st->xfer.len = st->chip_info->channel[0].scan_type.storagebits / 8;
315
316 spi_message_init(&st->msg);
317 spi_message_add_tail(&st->xfer, &st->msg);
318
319 ret = iio_triggered_buffer_setup(indio_dev, NULL,
320 &ad7476_trigger_handler, NULL);
321 if (ret)
322 goto error_disable_reg;
323
324 if (st->chip_info->reset)
325 st->chip_info->reset(st);
326
327 ret = iio_device_register(indio_dev);
328 if (ret)
329 goto error_ring_unregister;
330 return 0;
331
332error_ring_unregister:
333 iio_triggered_buffer_cleanup(indio_dev);
334error_disable_reg:
335 regulator_disable(st->reg);
336
337 return ret;
338}
339
340static const struct spi_device_id ad7476_id[] = {
341 {"ad7091", ID_AD7091R},
342 {"ad7091r", ID_AD7091R},
343 {"ad7273", ID_AD7277},
344 {"ad7274", ID_AD7276},
345 {"ad7276", ID_AD7276},
346 {"ad7277", ID_AD7277},
347 {"ad7278", ID_AD7278},
348 {"ad7466", ID_AD7466},
349 {"ad7467", ID_AD7467},
350 {"ad7468", ID_AD7468},
351 {"ad7475", ID_AD7466},
352 {"ad7476", ID_AD7466},
353 {"ad7476a", ID_AD7466},
354 {"ad7477", ID_AD7467},
355 {"ad7477a", ID_AD7467},
356 {"ad7478", ID_AD7468},
357 {"ad7478a", ID_AD7468},
358 {"ad7495", ID_AD7495},
359 {"ad7910", ID_AD7467},
360 {"ad7920", ID_AD7466},
361 {"ad7940", ID_AD7940},
362 {"adc081s", ID_ADC081S},
363 {"adc101s", ID_ADC101S},
364 {"adc121s", ID_ADC121S},
365 {"ads7866", ID_ADS7866},
366 {"ads7867", ID_ADS7867},
367 {"ads7868", ID_ADS7868},
368 {}
369};
370MODULE_DEVICE_TABLE(spi, ad7476_id);
371
372static struct spi_driver ad7476_driver = {
373 .driver = {
374 .name = "ad7476",
375 },
376 .probe = ad7476_probe,
377 .id_table = ad7476_id,
378};
379module_spi_driver(ad7476_driver);
380
381MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
382MODULE_DESCRIPTION("Analog Devices AD7476 and similar 1-channel ADCs");
383MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Analog Devices AD7466/7/8 AD7476/5/7/8 (A) SPI ADC driver
4 * TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver
5 *
6 * Copyright 2010 Analog Devices Inc.
7 */
8
9#include <linux/device.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/sysfs.h>
13#include <linux/spi/spi.h>
14#include <linux/regulator/consumer.h>
15#include <linux/gpio/consumer.h>
16#include <linux/err.h>
17#include <linux/module.h>
18#include <linux/bitops.h>
19#include <linux/delay.h>
20
21#include <linux/iio/iio.h>
22#include <linux/iio/sysfs.h>
23#include <linux/iio/buffer.h>
24#include <linux/iio/trigger_consumer.h>
25#include <linux/iio/triggered_buffer.h>
26
27struct ad7476_state;
28
29struct ad7476_chip_info {
30 unsigned int int_vref_uv;
31 struct iio_chan_spec channel[2];
32 /* channels used when convst gpio is defined */
33 struct iio_chan_spec convst_channel[2];
34 void (*reset)(struct ad7476_state *);
35 bool has_vref;
36 bool has_vdrive;
37};
38
39struct ad7476_state {
40 struct spi_device *spi;
41 const struct ad7476_chip_info *chip_info;
42 struct regulator *ref_reg;
43 struct gpio_desc *convst_gpio;
44 struct spi_transfer xfer;
45 struct spi_message msg;
46 /*
47 * DMA (thus cache coherency maintenance) may require the
48 * transfer buffers to live in their own cache lines.
49 * Make the buffer large enough for one 16 bit sample and one 64 bit
50 * aligned 64 bit timestamp.
51 */
52 unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN);
53};
54
55enum ad7476_supported_device_ids {
56 ID_AD7091,
57 ID_AD7091R,
58 ID_AD7273,
59 ID_AD7274,
60 ID_AD7276,
61 ID_AD7277,
62 ID_AD7278,
63 ID_AD7466,
64 ID_AD7467,
65 ID_AD7468,
66 ID_AD7475,
67 ID_AD7495,
68 ID_AD7940,
69 ID_ADC081S,
70 ID_ADC101S,
71 ID_ADC121S,
72 ID_ADS7866,
73 ID_ADS7867,
74 ID_ADS7868,
75 ID_LTC2314_14,
76};
77
78static void ad7091_convst(struct ad7476_state *st)
79{
80 if (!st->convst_gpio)
81 return;
82
83 gpiod_set_value(st->convst_gpio, 0);
84 udelay(1); /* CONVST pulse width: 10 ns min */
85 gpiod_set_value(st->convst_gpio, 1);
86 udelay(1); /* Conversion time: 650 ns max */
87}
88
89static irqreturn_t ad7476_trigger_handler(int irq, void *p)
90{
91 struct iio_poll_func *pf = p;
92 struct iio_dev *indio_dev = pf->indio_dev;
93 struct ad7476_state *st = iio_priv(indio_dev);
94 int b_sent;
95
96 ad7091_convst(st);
97
98 b_sent = spi_sync(st->spi, &st->msg);
99 if (b_sent < 0)
100 goto done;
101
102 iio_push_to_buffers_with_timestamp(indio_dev, st->data,
103 iio_get_time_ns(indio_dev));
104done:
105 iio_trigger_notify_done(indio_dev->trig);
106
107 return IRQ_HANDLED;
108}
109
110static void ad7091_reset(struct ad7476_state *st)
111{
112 /* Any transfers with 8 scl cycles will reset the device */
113 spi_read(st->spi, st->data, 1);
114}
115
116static int ad7476_scan_direct(struct ad7476_state *st)
117{
118 int ret;
119
120 ad7091_convst(st);
121
122 ret = spi_sync(st->spi, &st->msg);
123 if (ret)
124 return ret;
125
126 return be16_to_cpup((__be16 *)st->data);
127}
128
129static int ad7476_read_raw(struct iio_dev *indio_dev,
130 struct iio_chan_spec const *chan,
131 int *val,
132 int *val2,
133 long m)
134{
135 int ret;
136 struct ad7476_state *st = iio_priv(indio_dev);
137 int scale_uv;
138
139 switch (m) {
140 case IIO_CHAN_INFO_RAW:
141 ret = iio_device_claim_direct_mode(indio_dev);
142 if (ret)
143 return ret;
144 ret = ad7476_scan_direct(st);
145 iio_device_release_direct_mode(indio_dev);
146
147 if (ret < 0)
148 return ret;
149 *val = (ret >> st->chip_info->channel[0].scan_type.shift) &
150 GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0);
151 return IIO_VAL_INT;
152 case IIO_CHAN_INFO_SCALE:
153 if (st->ref_reg) {
154 scale_uv = regulator_get_voltage(st->ref_reg);
155 if (scale_uv < 0)
156 return scale_uv;
157 } else {
158 scale_uv = st->chip_info->int_vref_uv;
159 }
160 *val = scale_uv / 1000;
161 *val2 = chan->scan_type.realbits;
162 return IIO_VAL_FRACTIONAL_LOG2;
163 }
164 return -EINVAL;
165}
166
167#define _AD7476_CHAN(bits, _shift, _info_mask_sep) \
168 { \
169 .type = IIO_VOLTAGE, \
170 .indexed = 1, \
171 .info_mask_separate = _info_mask_sep, \
172 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
173 .scan_type = { \
174 .sign = 'u', \
175 .realbits = (bits), \
176 .storagebits = 16, \
177 .shift = (_shift), \
178 .endianness = IIO_BE, \
179 }, \
180}
181
182#define ADC081S_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
183 BIT(IIO_CHAN_INFO_RAW))
184#define AD7476_CHAN(bits) _AD7476_CHAN((bits), 13 - (bits), \
185 BIT(IIO_CHAN_INFO_RAW))
186#define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \
187 BIT(IIO_CHAN_INFO_RAW))
188#define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0)
189#define AD7091R_CONVST_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), \
190 BIT(IIO_CHAN_INFO_RAW))
191#define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
192 BIT(IIO_CHAN_INFO_RAW))
193
194static const struct ad7476_chip_info ad7476_chip_info_tbl[] = {
195 [ID_AD7091] = {
196 .channel[0] = AD7091R_CHAN(12),
197 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
198 .convst_channel[0] = AD7091R_CONVST_CHAN(12),
199 .convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
200 .reset = ad7091_reset,
201 },
202 [ID_AD7091R] = {
203 .channel[0] = AD7091R_CHAN(12),
204 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
205 .convst_channel[0] = AD7091R_CONVST_CHAN(12),
206 .convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
207 .int_vref_uv = 2500000,
208 .has_vref = true,
209 .reset = ad7091_reset,
210 },
211 [ID_AD7273] = {
212 .channel[0] = AD7940_CHAN(10),
213 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
214 .has_vref = true,
215 },
216 [ID_AD7274] = {
217 .channel[0] = AD7940_CHAN(12),
218 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
219 .has_vref = true,
220 },
221 [ID_AD7276] = {
222 .channel[0] = AD7940_CHAN(12),
223 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
224 },
225 [ID_AD7277] = {
226 .channel[0] = AD7940_CHAN(10),
227 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
228 },
229 [ID_AD7278] = {
230 .channel[0] = AD7940_CHAN(8),
231 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
232 },
233 [ID_AD7466] = {
234 .channel[0] = AD7476_CHAN(12),
235 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
236 },
237 [ID_AD7467] = {
238 .channel[0] = AD7476_CHAN(10),
239 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
240 },
241 [ID_AD7468] = {
242 .channel[0] = AD7476_CHAN(8),
243 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
244 },
245 [ID_AD7475] = {
246 .channel[0] = AD7476_CHAN(12),
247 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
248 .has_vref = true,
249 .has_vdrive = true,
250 },
251 [ID_AD7495] = {
252 .channel[0] = AD7476_CHAN(12),
253 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
254 .int_vref_uv = 2500000,
255 .has_vdrive = true,
256 },
257 [ID_AD7940] = {
258 .channel[0] = AD7940_CHAN(14),
259 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
260 },
261 [ID_ADC081S] = {
262 .channel[0] = ADC081S_CHAN(8),
263 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
264 },
265 [ID_ADC101S] = {
266 .channel[0] = ADC081S_CHAN(10),
267 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
268 },
269 [ID_ADC121S] = {
270 .channel[0] = ADC081S_CHAN(12),
271 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
272 },
273 [ID_ADS7866] = {
274 .channel[0] = ADS786X_CHAN(12),
275 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
276 },
277 [ID_ADS7867] = {
278 .channel[0] = ADS786X_CHAN(10),
279 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
280 },
281 [ID_ADS7868] = {
282 .channel[0] = ADS786X_CHAN(8),
283 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
284 },
285 [ID_LTC2314_14] = {
286 .channel[0] = AD7940_CHAN(14),
287 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
288 .has_vref = true,
289 },
290};
291
292static const struct iio_info ad7476_info = {
293 .read_raw = &ad7476_read_raw,
294};
295
296static void ad7476_reg_disable(void *data)
297{
298 struct regulator *reg = data;
299
300 regulator_disable(reg);
301}
302
303static int ad7476_probe(struct spi_device *spi)
304{
305 struct ad7476_state *st;
306 struct iio_dev *indio_dev;
307 struct regulator *reg;
308 int ret;
309
310 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
311 if (!indio_dev)
312 return -ENOMEM;
313
314 st = iio_priv(indio_dev);
315 st->chip_info =
316 &ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data];
317
318 reg = devm_regulator_get(&spi->dev, "vcc");
319 if (IS_ERR(reg))
320 return PTR_ERR(reg);
321
322 ret = regulator_enable(reg);
323 if (ret)
324 return ret;
325
326 ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable, reg);
327 if (ret)
328 return ret;
329
330 /* Either vcc or vref (below) as appropriate */
331 if (!st->chip_info->int_vref_uv)
332 st->ref_reg = reg;
333
334 if (st->chip_info->has_vref) {
335
336 /* If a device has an internal reference vref is optional */
337 if (st->chip_info->int_vref_uv) {
338 reg = devm_regulator_get_optional(&spi->dev, "vref");
339 if (IS_ERR(reg) && (PTR_ERR(reg) != -ENODEV))
340 return PTR_ERR(reg);
341 } else {
342 reg = devm_regulator_get(&spi->dev, "vref");
343 if (IS_ERR(reg))
344 return PTR_ERR(reg);
345 }
346
347 if (!IS_ERR(reg)) {
348 ret = regulator_enable(reg);
349 if (ret)
350 return ret;
351
352 ret = devm_add_action_or_reset(&spi->dev,
353 ad7476_reg_disable,
354 reg);
355 if (ret)
356 return ret;
357 st->ref_reg = reg;
358 } else {
359 /*
360 * Can only get here if device supports both internal
361 * and external reference, but the regulator connected
362 * to the external reference is not connected.
363 * Set the reference regulator pointer to NULL to
364 * indicate this.
365 */
366 st->ref_reg = NULL;
367 }
368 }
369
370 if (st->chip_info->has_vdrive) {
371 ret = devm_regulator_get_enable(&spi->dev, "vdrive");
372 if (ret)
373 return ret;
374 }
375
376 st->convst_gpio = devm_gpiod_get_optional(&spi->dev,
377 "adi,conversion-start",
378 GPIOD_OUT_LOW);
379 if (IS_ERR(st->convst_gpio))
380 return PTR_ERR(st->convst_gpio);
381
382 st->spi = spi;
383
384 indio_dev->name = spi_get_device_id(spi)->name;
385 indio_dev->modes = INDIO_DIRECT_MODE;
386 indio_dev->channels = st->chip_info->channel;
387 indio_dev->num_channels = 2;
388 indio_dev->info = &ad7476_info;
389
390 if (st->convst_gpio)
391 indio_dev->channels = st->chip_info->convst_channel;
392 /* Setup default message */
393
394 st->xfer.rx_buf = &st->data;
395 st->xfer.len = st->chip_info->channel[0].scan_type.storagebits / 8;
396
397 spi_message_init(&st->msg);
398 spi_message_add_tail(&st->xfer, &st->msg);
399
400 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
401 &ad7476_trigger_handler, NULL);
402 if (ret)
403 return ret;
404
405 if (st->chip_info->reset)
406 st->chip_info->reset(st);
407
408 return devm_iio_device_register(&spi->dev, indio_dev);
409}
410
411static const struct spi_device_id ad7476_id[] = {
412 { "ad7091", ID_AD7091 },
413 { "ad7091r", ID_AD7091R },
414 { "ad7273", ID_AD7273 },
415 { "ad7274", ID_AD7274 },
416 { "ad7276", ID_AD7276},
417 { "ad7277", ID_AD7277 },
418 { "ad7278", ID_AD7278 },
419 { "ad7466", ID_AD7466 },
420 { "ad7467", ID_AD7467 },
421 { "ad7468", ID_AD7468 },
422 { "ad7475", ID_AD7475 },
423 { "ad7476", ID_AD7466 },
424 { "ad7476a", ID_AD7466 },
425 { "ad7477", ID_AD7467 },
426 { "ad7477a", ID_AD7467 },
427 { "ad7478", ID_AD7468 },
428 { "ad7478a", ID_AD7468 },
429 { "ad7495", ID_AD7495 },
430 { "ad7910", ID_AD7467 },
431 { "ad7920", ID_AD7466 },
432 { "ad7940", ID_AD7940 },
433 { "adc081s", ID_ADC081S },
434 { "adc101s", ID_ADC101S },
435 { "adc121s", ID_ADC121S },
436 { "ads7866", ID_ADS7866 },
437 { "ads7867", ID_ADS7867 },
438 { "ads7868", ID_ADS7868 },
439 { "ltc2314-14", ID_LTC2314_14 },
440 { }
441};
442MODULE_DEVICE_TABLE(spi, ad7476_id);
443
444static struct spi_driver ad7476_driver = {
445 .driver = {
446 .name = "ad7476",
447 },
448 .probe = ad7476_probe,
449 .id_table = ad7476_id,
450};
451module_spi_driver(ad7476_driver);
452
453MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
454MODULE_DESCRIPTION("Analog Devices AD7476 and similar 1-channel ADCs");
455MODULE_LICENSE("GPL v2");