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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Tegra host1x driver
4 *
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
6 */
7
8#include <linux/clk.h>
9#include <linux/dma-mapping.h>
10#include <linux/io.h>
11#include <linux/list.h>
12#include <linux/module.h>
13#include <linux/of_device.h>
14#include <linux/of.h>
15#include <linux/slab.h>
16
17#define CREATE_TRACE_POINTS
18#include <trace/events/host1x.h>
19#undef CREATE_TRACE_POINTS
20
21#include "bus.h"
22#include "channel.h"
23#include "debug.h"
24#include "dev.h"
25#include "intr.h"
26
27#include "hw/host1x01.h"
28#include "hw/host1x02.h"
29#include "hw/host1x04.h"
30#include "hw/host1x05.h"
31#include "hw/host1x06.h"
32#include "hw/host1x07.h"
33
34void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
35{
36 writel(v, host1x->hv_regs + r);
37}
38
39u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
40{
41 return readl(host1x->hv_regs + r);
42}
43
44void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
45{
46 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
47
48 writel(v, sync_regs + r);
49}
50
51u32 host1x_sync_readl(struct host1x *host1x, u32 r)
52{
53 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
54
55 return readl(sync_regs + r);
56}
57
58void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
59{
60 writel(v, ch->regs + r);
61}
62
63u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
64{
65 return readl(ch->regs + r);
66}
67
68static const struct host1x_info host1x01_info = {
69 .nb_channels = 8,
70 .nb_pts = 32,
71 .nb_mlocks = 16,
72 .nb_bases = 8,
73 .init = host1x01_init,
74 .sync_offset = 0x3000,
75 .dma_mask = DMA_BIT_MASK(32),
76 .has_wide_gather = false,
77 .has_hypervisor = false,
78 .num_sid_entries = 0,
79 .sid_table = NULL,
80};
81
82static const struct host1x_info host1x02_info = {
83 .nb_channels = 9,
84 .nb_pts = 32,
85 .nb_mlocks = 16,
86 .nb_bases = 12,
87 .init = host1x02_init,
88 .sync_offset = 0x3000,
89 .dma_mask = DMA_BIT_MASK(32),
90 .has_wide_gather = false,
91 .has_hypervisor = false,
92 .num_sid_entries = 0,
93 .sid_table = NULL,
94};
95
96static const struct host1x_info host1x04_info = {
97 .nb_channels = 12,
98 .nb_pts = 192,
99 .nb_mlocks = 16,
100 .nb_bases = 64,
101 .init = host1x04_init,
102 .sync_offset = 0x2100,
103 .dma_mask = DMA_BIT_MASK(34),
104 .has_wide_gather = false,
105 .has_hypervisor = false,
106 .num_sid_entries = 0,
107 .sid_table = NULL,
108};
109
110static const struct host1x_info host1x05_info = {
111 .nb_channels = 14,
112 .nb_pts = 192,
113 .nb_mlocks = 16,
114 .nb_bases = 64,
115 .init = host1x05_init,
116 .sync_offset = 0x2100,
117 .dma_mask = DMA_BIT_MASK(34),
118 .has_wide_gather = false,
119 .has_hypervisor = false,
120 .num_sid_entries = 0,
121 .sid_table = NULL,
122};
123
124static const struct host1x_sid_entry tegra186_sid_table[] = {
125 {
126 /* VIC */
127 .base = 0x1af0,
128 .offset = 0x30,
129 .limit = 0x34
130 },
131};
132
133static const struct host1x_info host1x06_info = {
134 .nb_channels = 63,
135 .nb_pts = 576,
136 .nb_mlocks = 24,
137 .nb_bases = 16,
138 .init = host1x06_init,
139 .sync_offset = 0x0,
140 .dma_mask = DMA_BIT_MASK(40),
141 .has_wide_gather = true,
142 .has_hypervisor = true,
143 .num_sid_entries = ARRAY_SIZE(tegra186_sid_table),
144 .sid_table = tegra186_sid_table,
145};
146
147static const struct host1x_sid_entry tegra194_sid_table[] = {
148 {
149 /* VIC */
150 .base = 0x1af0,
151 .offset = 0x30,
152 .limit = 0x34
153 },
154};
155
156static const struct host1x_info host1x07_info = {
157 .nb_channels = 63,
158 .nb_pts = 704,
159 .nb_mlocks = 32,
160 .nb_bases = 0,
161 .init = host1x07_init,
162 .sync_offset = 0x0,
163 .dma_mask = DMA_BIT_MASK(40),
164 .has_wide_gather = true,
165 .has_hypervisor = true,
166 .num_sid_entries = ARRAY_SIZE(tegra194_sid_table),
167 .sid_table = tegra194_sid_table,
168};
169
170static const struct of_device_id host1x_of_match[] = {
171 { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
172 { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
173 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
174 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
175 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
176 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
177 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
178 { },
179};
180MODULE_DEVICE_TABLE(of, host1x_of_match);
181
182static void host1x_setup_sid_table(struct host1x *host)
183{
184 const struct host1x_info *info = host->info;
185 unsigned int i;
186
187 for (i = 0; i < info->num_sid_entries; i++) {
188 const struct host1x_sid_entry *entry = &info->sid_table[i];
189
190 host1x_hypervisor_writel(host, entry->offset, entry->base);
191 host1x_hypervisor_writel(host, entry->limit, entry->base + 4);
192 }
193}
194
195static bool host1x_wants_iommu(struct host1x *host1x)
196{
197 /*
198 * If we support addressing a maximum of 32 bits of physical memory
199 * and if the host1x firewall is enabled, there's no need to enable
200 * IOMMU support. This can happen for example on Tegra20, Tegra30
201 * and Tegra114.
202 *
203 * Tegra124 and later can address up to 34 bits of physical memory and
204 * many platforms come equipped with more than 2 GiB of system memory,
205 * which requires crossing the 4 GiB boundary. But there's a catch: on
206 * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can
207 * only address up to 32 bits of memory in GATHER opcodes, which means
208 * that command buffers need to either be in the first 2 GiB of system
209 * memory (which could quickly lead to memory exhaustion), or command
210 * buffers need to be treated differently from other buffers (which is
211 * not possible with the current ABI).
212 *
213 * A third option is to use the IOMMU in these cases to make sure all
214 * buffers will be mapped into a 32-bit IOVA space that host1x can
215 * address. This allows all of the system memory to be used and works
216 * within the limitations of the host1x on these SoCs.
217 *
218 * In summary, default to enable IOMMU on Tegra124 and later. For any
219 * of the earlier SoCs, only use the IOMMU for additional safety when
220 * the host1x firewall is disabled.
221 */
222 if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) {
223 if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL))
224 return false;
225 }
226
227 return true;
228}
229
230static struct iommu_domain *host1x_iommu_attach(struct host1x *host)
231{
232 struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev);
233 int err;
234
235 /*
236 * We may not always want to enable IOMMU support (for example if the
237 * host1x firewall is already enabled and we don't support addressing
238 * more than 32 bits of physical memory), so check for that first.
239 *
240 * Similarly, if host1x is already attached to an IOMMU (via the DMA
241 * API), don't try to attach again.
242 */
243 if (!host1x_wants_iommu(host) || domain)
244 return domain;
245
246 host->group = iommu_group_get(host->dev);
247 if (host->group) {
248 struct iommu_domain_geometry *geometry;
249 dma_addr_t start, end;
250 unsigned long order;
251
252 err = iova_cache_get();
253 if (err < 0)
254 goto put_group;
255
256 host->domain = iommu_domain_alloc(&platform_bus_type);
257 if (!host->domain) {
258 err = -ENOMEM;
259 goto put_cache;
260 }
261
262 err = iommu_attach_group(host->domain, host->group);
263 if (err) {
264 if (err == -ENODEV)
265 err = 0;
266
267 goto free_domain;
268 }
269
270 geometry = &host->domain->geometry;
271 start = geometry->aperture_start & host->info->dma_mask;
272 end = geometry->aperture_end & host->info->dma_mask;
273
274 order = __ffs(host->domain->pgsize_bitmap);
275 init_iova_domain(&host->iova, 1UL << order, start >> order);
276 host->iova_end = end;
277
278 domain = host->domain;
279 }
280
281 return domain;
282
283free_domain:
284 iommu_domain_free(host->domain);
285 host->domain = NULL;
286put_cache:
287 iova_cache_put();
288put_group:
289 iommu_group_put(host->group);
290 host->group = NULL;
291
292 return ERR_PTR(err);
293}
294
295static int host1x_iommu_init(struct host1x *host)
296{
297 u64 mask = host->info->dma_mask;
298 struct iommu_domain *domain;
299 int err;
300
301 domain = host1x_iommu_attach(host);
302 if (IS_ERR(domain)) {
303 err = PTR_ERR(domain);
304 dev_err(host->dev, "failed to attach to IOMMU: %d\n", err);
305 return err;
306 }
307
308 /*
309 * If we're not behind an IOMMU make sure we don't get push buffers
310 * that are allocated outside of the range addressable by the GATHER
311 * opcode.
312 *
313 * Newer generations of Tegra (Tegra186 and later) support a wide
314 * variant of the GATHER opcode that allows addressing more bits.
315 */
316 if (!domain && !host->info->has_wide_gather)
317 mask = DMA_BIT_MASK(32);
318
319 err = dma_coerce_mask_and_coherent(host->dev, mask);
320 if (err < 0) {
321 dev_err(host->dev, "failed to set DMA mask: %d\n", err);
322 return err;
323 }
324
325 return 0;
326}
327
328static void host1x_iommu_exit(struct host1x *host)
329{
330 if (host->domain) {
331 put_iova_domain(&host->iova);
332 iommu_detach_group(host->domain, host->group);
333
334 iommu_domain_free(host->domain);
335 host->domain = NULL;
336
337 iova_cache_put();
338
339 iommu_group_put(host->group);
340 host->group = NULL;
341 }
342}
343
344static int host1x_probe(struct platform_device *pdev)
345{
346 struct host1x *host;
347 struct resource *regs, *hv_regs = NULL;
348 int syncpt_irq;
349 int err;
350
351 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
352 if (!host)
353 return -ENOMEM;
354
355 host->info = of_device_get_match_data(&pdev->dev);
356
357 if (host->info->has_hypervisor) {
358 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm");
359 if (!regs) {
360 dev_err(&pdev->dev, "failed to get vm registers\n");
361 return -ENXIO;
362 }
363
364 hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
365 "hypervisor");
366 if (!hv_regs) {
367 dev_err(&pdev->dev,
368 "failed to get hypervisor registers\n");
369 return -ENXIO;
370 }
371 } else {
372 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
373 if (!regs) {
374 dev_err(&pdev->dev, "failed to get registers\n");
375 return -ENXIO;
376 }
377 }
378
379 syncpt_irq = platform_get_irq(pdev, 0);
380 if (syncpt_irq < 0)
381 return syncpt_irq;
382
383 mutex_init(&host->devices_lock);
384 INIT_LIST_HEAD(&host->devices);
385 INIT_LIST_HEAD(&host->list);
386 host->dev = &pdev->dev;
387
388 /* set common host1x device data */
389 platform_set_drvdata(pdev, host);
390
391 host->regs = devm_ioremap_resource(&pdev->dev, regs);
392 if (IS_ERR(host->regs))
393 return PTR_ERR(host->regs);
394
395 if (host->info->has_hypervisor) {
396 host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs);
397 if (IS_ERR(host->hv_regs))
398 return PTR_ERR(host->hv_regs);
399 }
400
401 host->dev->dma_parms = &host->dma_parms;
402 dma_set_max_seg_size(host->dev, UINT_MAX);
403
404 if (host->info->init) {
405 err = host->info->init(host);
406 if (err)
407 return err;
408 }
409
410 host->clk = devm_clk_get(&pdev->dev, NULL);
411 if (IS_ERR(host->clk)) {
412 err = PTR_ERR(host->clk);
413
414 if (err != -EPROBE_DEFER)
415 dev_err(&pdev->dev, "failed to get clock: %d\n", err);
416
417 return err;
418 }
419
420 host->rst = devm_reset_control_get(&pdev->dev, "host1x");
421 if (IS_ERR(host->rst)) {
422 err = PTR_ERR(host->rst);
423 dev_err(&pdev->dev, "failed to get reset: %d\n", err);
424 return err;
425 }
426
427 err = host1x_iommu_init(host);
428 if (err < 0) {
429 dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err);
430 return err;
431 }
432
433 err = host1x_channel_list_init(&host->channel_list,
434 host->info->nb_channels);
435 if (err) {
436 dev_err(&pdev->dev, "failed to initialize channel list\n");
437 goto iommu_exit;
438 }
439
440 err = clk_prepare_enable(host->clk);
441 if (err < 0) {
442 dev_err(&pdev->dev, "failed to enable clock\n");
443 goto free_channels;
444 }
445
446 err = reset_control_deassert(host->rst);
447 if (err < 0) {
448 dev_err(&pdev->dev, "failed to deassert reset: %d\n", err);
449 goto unprepare_disable;
450 }
451
452 err = host1x_syncpt_init(host);
453 if (err) {
454 dev_err(&pdev->dev, "failed to initialize syncpts\n");
455 goto reset_assert;
456 }
457
458 err = host1x_intr_init(host, syncpt_irq);
459 if (err) {
460 dev_err(&pdev->dev, "failed to initialize interrupts\n");
461 goto deinit_syncpt;
462 }
463
464 host1x_debug_init(host);
465
466 if (host->info->has_hypervisor)
467 host1x_setup_sid_table(host);
468
469 err = host1x_register(host);
470 if (err < 0)
471 goto deinit_debugfs;
472
473 err = devm_of_platform_populate(&pdev->dev);
474 if (err < 0)
475 goto unregister;
476
477 return 0;
478
479unregister:
480 host1x_unregister(host);
481deinit_debugfs:
482 host1x_debug_deinit(host);
483 host1x_intr_deinit(host);
484deinit_syncpt:
485 host1x_syncpt_deinit(host);
486reset_assert:
487 reset_control_assert(host->rst);
488unprepare_disable:
489 clk_disable_unprepare(host->clk);
490free_channels:
491 host1x_channel_list_free(&host->channel_list);
492iommu_exit:
493 host1x_iommu_exit(host);
494
495 return err;
496}
497
498static int host1x_remove(struct platform_device *pdev)
499{
500 struct host1x *host = platform_get_drvdata(pdev);
501
502 host1x_unregister(host);
503 host1x_debug_deinit(host);
504 host1x_intr_deinit(host);
505 host1x_syncpt_deinit(host);
506 reset_control_assert(host->rst);
507 clk_disable_unprepare(host->clk);
508 host1x_iommu_exit(host);
509
510 return 0;
511}
512
513static struct platform_driver tegra_host1x_driver = {
514 .driver = {
515 .name = "tegra-host1x",
516 .of_match_table = host1x_of_match,
517 },
518 .probe = host1x_probe,
519 .remove = host1x_remove,
520};
521
522static struct platform_driver * const drivers[] = {
523 &tegra_host1x_driver,
524 &tegra_mipi_driver,
525};
526
527static int __init tegra_host1x_init(void)
528{
529 int err;
530
531 err = bus_register(&host1x_bus_type);
532 if (err < 0)
533 return err;
534
535 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
536 if (err < 0)
537 bus_unregister(&host1x_bus_type);
538
539 return err;
540}
541module_init(tegra_host1x_init);
542
543static void __exit tegra_host1x_exit(void)
544{
545 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
546 bus_unregister(&host1x_bus_type);
547}
548module_exit(tegra_host1x_exit);
549
550/**
551 * host1x_get_dma_mask() - query the supported DMA mask for host1x
552 * @host1x: host1x instance
553 *
554 * Note that this returns the supported DMA mask for host1x, which can be
555 * different from the applicable DMA mask under certain circumstances.
556 */
557u64 host1x_get_dma_mask(struct host1x *host1x)
558{
559 return host1x->info->dma_mask;
560}
561EXPORT_SYMBOL(host1x_get_dma_mask);
562
563MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
564MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
565MODULE_DESCRIPTION("Host1x driver for Tegra products");
566MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Tegra host1x driver
4 *
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
6 */
7
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/dma-mapping.h>
11#include <linux/io.h>
12#include <linux/list.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_platform.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/slab.h>
19
20#include <soc/tegra/common.h>
21
22#define CREATE_TRACE_POINTS
23#include <trace/events/host1x.h>
24#undef CREATE_TRACE_POINTS
25
26#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
27#include <asm/dma-iommu.h>
28#endif
29
30#include "bus.h"
31#include "channel.h"
32#include "context.h"
33#include "debug.h"
34#include "dev.h"
35#include "intr.h"
36
37#include "hw/host1x01.h"
38#include "hw/host1x02.h"
39#include "hw/host1x04.h"
40#include "hw/host1x05.h"
41#include "hw/host1x06.h"
42#include "hw/host1x07.h"
43#include "hw/host1x08.h"
44
45void host1x_common_writel(struct host1x *host1x, u32 v, u32 r)
46{
47 writel(v, host1x->common_regs + r);
48}
49
50void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
51{
52 writel(v, host1x->hv_regs + r);
53}
54
55u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
56{
57 return readl(host1x->hv_regs + r);
58}
59
60void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
61{
62 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
63
64 writel(v, sync_regs + r);
65}
66
67u32 host1x_sync_readl(struct host1x *host1x, u32 r)
68{
69 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
70
71 return readl(sync_regs + r);
72}
73
74void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
75{
76 writel(v, ch->regs + r);
77}
78
79u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
80{
81 return readl(ch->regs + r);
82}
83
84static const struct host1x_info host1x01_info = {
85 .nb_channels = 8,
86 .nb_pts = 32,
87 .nb_mlocks = 16,
88 .nb_bases = 8,
89 .init = host1x01_init,
90 .sync_offset = 0x3000,
91 .dma_mask = DMA_BIT_MASK(32),
92 .has_wide_gather = false,
93 .has_hypervisor = false,
94 .num_sid_entries = 0,
95 .sid_table = NULL,
96 .reserve_vblank_syncpts = true,
97};
98
99static const struct host1x_info host1x02_info = {
100 .nb_channels = 9,
101 .nb_pts = 32,
102 .nb_mlocks = 16,
103 .nb_bases = 12,
104 .init = host1x02_init,
105 .sync_offset = 0x3000,
106 .dma_mask = DMA_BIT_MASK(32),
107 .has_wide_gather = false,
108 .has_hypervisor = false,
109 .num_sid_entries = 0,
110 .sid_table = NULL,
111 .reserve_vblank_syncpts = true,
112};
113
114static const struct host1x_info host1x04_info = {
115 .nb_channels = 12,
116 .nb_pts = 192,
117 .nb_mlocks = 16,
118 .nb_bases = 64,
119 .init = host1x04_init,
120 .sync_offset = 0x2100,
121 .dma_mask = DMA_BIT_MASK(34),
122 .has_wide_gather = false,
123 .has_hypervisor = false,
124 .num_sid_entries = 0,
125 .sid_table = NULL,
126 .reserve_vblank_syncpts = false,
127};
128
129static const struct host1x_info host1x05_info = {
130 .nb_channels = 14,
131 .nb_pts = 192,
132 .nb_mlocks = 16,
133 .nb_bases = 64,
134 .init = host1x05_init,
135 .sync_offset = 0x2100,
136 .dma_mask = DMA_BIT_MASK(34),
137 .has_wide_gather = false,
138 .has_hypervisor = false,
139 .num_sid_entries = 0,
140 .sid_table = NULL,
141 .reserve_vblank_syncpts = false,
142};
143
144static const struct host1x_sid_entry tegra186_sid_table[] = {
145 { /* SE1 */ .base = 0x1ac8, .offset = 0x90, .limit = 0x90 },
146 { /* SE2 */ .base = 0x1ad0, .offset = 0x90, .limit = 0x90 },
147 { /* SE3 */ .base = 0x1ad8, .offset = 0x90, .limit = 0x90 },
148 { /* SE4 */ .base = 0x1ae0, .offset = 0x90, .limit = 0x90 },
149 { /* ISP */ .base = 0x1ae8, .offset = 0x50, .limit = 0x50 },
150 { /* VIC */ .base = 0x1af0, .offset = 0x30, .limit = 0x34 },
151 { /* NVENC */ .base = 0x1af8, .offset = 0x30, .limit = 0x34 },
152 { /* NVDEC */ .base = 0x1b00, .offset = 0x30, .limit = 0x34 },
153 { /* NVJPG */ .base = 0x1b08, .offset = 0x30, .limit = 0x34 },
154 { /* TSEC */ .base = 0x1b10, .offset = 0x30, .limit = 0x34 },
155 { /* TSECB */ .base = 0x1b18, .offset = 0x30, .limit = 0x34 },
156 { /* VI 0 */ .base = 0x1b80, .offset = 0x10000, .limit = 0x10000 },
157 { /* VI 1 */ .base = 0x1b88, .offset = 0x20000, .limit = 0x20000 },
158 { /* VI 2 */ .base = 0x1b90, .offset = 0x30000, .limit = 0x30000 },
159 { /* VI 3 */ .base = 0x1b98, .offset = 0x40000, .limit = 0x40000 },
160 { /* VI 4 */ .base = 0x1ba0, .offset = 0x50000, .limit = 0x50000 },
161 { /* VI 5 */ .base = 0x1ba8, .offset = 0x60000, .limit = 0x60000 },
162 { /* VI 6 */ .base = 0x1bb0, .offset = 0x70000, .limit = 0x70000 },
163 { /* VI 7 */ .base = 0x1bb8, .offset = 0x80000, .limit = 0x80000 },
164 { /* VI 8 */ .base = 0x1bc0, .offset = 0x90000, .limit = 0x90000 },
165 { /* VI 9 */ .base = 0x1bc8, .offset = 0xa0000, .limit = 0xa0000 },
166 { /* VI 10 */ .base = 0x1bd0, .offset = 0xb0000, .limit = 0xb0000 },
167 { /* VI 11 */ .base = 0x1bd8, .offset = 0xc0000, .limit = 0xc0000 },
168};
169
170static const struct host1x_info host1x06_info = {
171 .nb_channels = 63,
172 .nb_pts = 576,
173 .nb_mlocks = 24,
174 .nb_bases = 16,
175 .init = host1x06_init,
176 .sync_offset = 0x0,
177 .dma_mask = DMA_BIT_MASK(40),
178 .has_wide_gather = true,
179 .has_hypervisor = true,
180 .num_sid_entries = ARRAY_SIZE(tegra186_sid_table),
181 .sid_table = tegra186_sid_table,
182 .reserve_vblank_syncpts = false,
183 .skip_reset_assert = true,
184};
185
186static const struct host1x_sid_entry tegra194_sid_table[] = {
187 { /* SE1 */ .base = 0x1ac8, .offset = 0x90, .limit = 0x90 },
188 { /* SE2 */ .base = 0x1ad0, .offset = 0x90, .limit = 0x90 },
189 { /* SE3 */ .base = 0x1ad8, .offset = 0x90, .limit = 0x90 },
190 { /* SE4 */ .base = 0x1ae0, .offset = 0x90, .limit = 0x90 },
191 { /* ISP */ .base = 0x1ae8, .offset = 0x800, .limit = 0x800 },
192 { /* VIC */ .base = 0x1af0, .offset = 0x30, .limit = 0x34 },
193 { /* NVENC */ .base = 0x1af8, .offset = 0x30, .limit = 0x34 },
194 { /* NVDEC */ .base = 0x1b00, .offset = 0x30, .limit = 0x34 },
195 { /* NVJPG */ .base = 0x1b08, .offset = 0x30, .limit = 0x34 },
196 { /* TSEC */ .base = 0x1b10, .offset = 0x30, .limit = 0x34 },
197 { /* TSECB */ .base = 0x1b18, .offset = 0x30, .limit = 0x34 },
198 { /* VI */ .base = 0x1b80, .offset = 0x800, .limit = 0x800 },
199 { /* VI_THI */ .base = 0x1b88, .offset = 0x30, .limit = 0x34 },
200 { /* ISP_THI */ .base = 0x1b90, .offset = 0x30, .limit = 0x34 },
201 { /* PVA0_CLUSTER */ .base = 0x1b98, .offset = 0x0, .limit = 0x0 },
202 { /* PVA0_CLUSTER */ .base = 0x1ba0, .offset = 0x0, .limit = 0x0 },
203 { /* NVDLA0 */ .base = 0x1ba8, .offset = 0x30, .limit = 0x34 },
204 { /* NVDLA1 */ .base = 0x1bb0, .offset = 0x30, .limit = 0x34 },
205 { /* NVENC1 */ .base = 0x1bb8, .offset = 0x30, .limit = 0x34 },
206 { /* NVDEC1 */ .base = 0x1bc0, .offset = 0x30, .limit = 0x34 },
207};
208
209static const struct host1x_info host1x07_info = {
210 .nb_channels = 63,
211 .nb_pts = 704,
212 .nb_mlocks = 32,
213 .nb_bases = 0,
214 .init = host1x07_init,
215 .sync_offset = 0x0,
216 .dma_mask = DMA_BIT_MASK(40),
217 .has_wide_gather = true,
218 .has_hypervisor = true,
219 .num_sid_entries = ARRAY_SIZE(tegra194_sid_table),
220 .sid_table = tegra194_sid_table,
221 .reserve_vblank_syncpts = false,
222};
223
224/*
225 * Tegra234 has two stream ID protection tables, one for setting stream IDs
226 * through the channel path via SETSTREAMID, and one for setting them via
227 * MMIO. We program each engine's data stream ID in the channel path table
228 * and firmware stream ID in the MMIO path table.
229 */
230static const struct host1x_sid_entry tegra234_sid_table[] = {
231 { /* SE1 MMIO */ .base = 0x1650, .offset = 0x90, .limit = 0x90 },
232 { /* SE1 ch */ .base = 0x1730, .offset = 0x90, .limit = 0x90 },
233 { /* SE2 MMIO */ .base = 0x1658, .offset = 0x90, .limit = 0x90 },
234 { /* SE2 ch */ .base = 0x1738, .offset = 0x90, .limit = 0x90 },
235 { /* SE4 MMIO */ .base = 0x1660, .offset = 0x90, .limit = 0x90 },
236 { /* SE4 ch */ .base = 0x1740, .offset = 0x90, .limit = 0x90 },
237 { /* ISP MMIO */ .base = 0x1680, .offset = 0x800, .limit = 0x800 },
238 { /* VIC MMIO */ .base = 0x1688, .offset = 0x34, .limit = 0x34 },
239 { /* VIC ch */ .base = 0x17b8, .offset = 0x30, .limit = 0x30 },
240 { /* NVENC MMIO */ .base = 0x1690, .offset = 0x34, .limit = 0x34 },
241 { /* NVENC ch */ .base = 0x17c0, .offset = 0x30, .limit = 0x30 },
242 { /* NVDEC MMIO */ .base = 0x1698, .offset = 0x34, .limit = 0x34 },
243 { /* NVDEC ch */ .base = 0x17c8, .offset = 0x30, .limit = 0x30 },
244 { /* NVJPG MMIO */ .base = 0x16a0, .offset = 0x34, .limit = 0x34 },
245 { /* NVJPG ch */ .base = 0x17d0, .offset = 0x30, .limit = 0x30 },
246 { /* TSEC MMIO */ .base = 0x16a8, .offset = 0x30, .limit = 0x34 },
247 { /* NVJPG1 MMIO */ .base = 0x16b0, .offset = 0x34, .limit = 0x34 },
248 { /* NVJPG1 ch */ .base = 0x17a8, .offset = 0x30, .limit = 0x30 },
249 { /* VI MMIO */ .base = 0x16b8, .offset = 0x800, .limit = 0x800 },
250 { /* VI_THI MMIO */ .base = 0x16c0, .offset = 0x30, .limit = 0x34 },
251 { /* ISP_THI MMIO */ .base = 0x16c8, .offset = 0x30, .limit = 0x34 },
252 { /* NVDLA MMIO */ .base = 0x16d8, .offset = 0x30, .limit = 0x34 },
253 { /* NVDLA ch */ .base = 0x17e0, .offset = 0x30, .limit = 0x34 },
254 { /* NVDLA1 MMIO */ .base = 0x16e0, .offset = 0x30, .limit = 0x34 },
255 { /* NVDLA1 ch */ .base = 0x17e8, .offset = 0x30, .limit = 0x34 },
256 { /* OFA MMIO */ .base = 0x16e8, .offset = 0x34, .limit = 0x34 },
257 { /* OFA ch */ .base = 0x1768, .offset = 0x30, .limit = 0x30 },
258 { /* VI2 MMIO */ .base = 0x16f0, .offset = 0x800, .limit = 0x800 },
259 { /* VI2_THI MMIO */ .base = 0x16f8, .offset = 0x30, .limit = 0x34 },
260};
261
262static const struct host1x_info host1x08_info = {
263 .nb_channels = 63,
264 .nb_pts = 1024,
265 .nb_mlocks = 24,
266 .nb_bases = 0,
267 .init = host1x08_init,
268 .sync_offset = 0x0,
269 .dma_mask = DMA_BIT_MASK(40),
270 .has_wide_gather = true,
271 .has_hypervisor = true,
272 .has_common = true,
273 .num_sid_entries = ARRAY_SIZE(tegra234_sid_table),
274 .sid_table = tegra234_sid_table,
275 .streamid_vm_table = { 0x1004, 128 },
276 .classid_vm_table = { 0x1404, 25 },
277 .mmio_vm_table = { 0x1504, 25 },
278 .reserve_vblank_syncpts = false,
279};
280
281static const struct of_device_id host1x_of_match[] = {
282 { .compatible = "nvidia,tegra234-host1x", .data = &host1x08_info, },
283 { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
284 { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
285 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
286 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
287 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
288 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
289 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
290 { },
291};
292MODULE_DEVICE_TABLE(of, host1x_of_match);
293
294static void host1x_setup_virtualization_tables(struct host1x *host)
295{
296 const struct host1x_info *info = host->info;
297 unsigned int i;
298
299 if (!info->has_hypervisor)
300 return;
301
302 for (i = 0; i < info->num_sid_entries; i++) {
303 const struct host1x_sid_entry *entry = &info->sid_table[i];
304
305 host1x_hypervisor_writel(host, entry->offset, entry->base);
306 host1x_hypervisor_writel(host, entry->limit, entry->base + 4);
307 }
308
309 for (i = 0; i < info->streamid_vm_table.count; i++) {
310 /* Allow access to all stream IDs to all VMs. */
311 host1x_hypervisor_writel(host, 0xff, info->streamid_vm_table.base + 4 * i);
312 }
313
314 for (i = 0; i < info->classid_vm_table.count; i++) {
315 /* Allow access to all classes to all VMs. */
316 host1x_hypervisor_writel(host, 0xff, info->classid_vm_table.base + 4 * i);
317 }
318
319 for (i = 0; i < info->mmio_vm_table.count; i++) {
320 /* Use VM1 (that's us) as originator VMID for engine MMIO accesses. */
321 host1x_hypervisor_writel(host, 0x1, info->mmio_vm_table.base + 4 * i);
322 }
323}
324
325static bool host1x_wants_iommu(struct host1x *host1x)
326{
327 /* Our IOMMU usage policy doesn't currently play well with GART */
328 if (of_machine_is_compatible("nvidia,tegra20"))
329 return false;
330
331 /*
332 * If we support addressing a maximum of 32 bits of physical memory
333 * and if the host1x firewall is enabled, there's no need to enable
334 * IOMMU support. This can happen for example on Tegra20, Tegra30
335 * and Tegra114.
336 *
337 * Tegra124 and later can address up to 34 bits of physical memory and
338 * many platforms come equipped with more than 2 GiB of system memory,
339 * which requires crossing the 4 GiB boundary. But there's a catch: on
340 * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can
341 * only address up to 32 bits of memory in GATHER opcodes, which means
342 * that command buffers need to either be in the first 2 GiB of system
343 * memory (which could quickly lead to memory exhaustion), or command
344 * buffers need to be treated differently from other buffers (which is
345 * not possible with the current ABI).
346 *
347 * A third option is to use the IOMMU in these cases to make sure all
348 * buffers will be mapped into a 32-bit IOVA space that host1x can
349 * address. This allows all of the system memory to be used and works
350 * within the limitations of the host1x on these SoCs.
351 *
352 * In summary, default to enable IOMMU on Tegra124 and later. For any
353 * of the earlier SoCs, only use the IOMMU for additional safety when
354 * the host1x firewall is disabled.
355 */
356 if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) {
357 if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL))
358 return false;
359 }
360
361 return true;
362}
363
364static struct iommu_domain *host1x_iommu_attach(struct host1x *host)
365{
366 struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev);
367 int err;
368
369#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
370 if (host->dev->archdata.mapping) {
371 struct dma_iommu_mapping *mapping =
372 to_dma_iommu_mapping(host->dev);
373 arm_iommu_detach_device(host->dev);
374 arm_iommu_release_mapping(mapping);
375
376 domain = iommu_get_domain_for_dev(host->dev);
377 }
378#endif
379
380 /*
381 * We may not always want to enable IOMMU support (for example if the
382 * host1x firewall is already enabled and we don't support addressing
383 * more than 32 bits of physical memory), so check for that first.
384 *
385 * Similarly, if host1x is already attached to an IOMMU (via the DMA
386 * API), don't try to attach again.
387 */
388 if (!host1x_wants_iommu(host) || domain)
389 return domain;
390
391 host->group = iommu_group_get(host->dev);
392 if (host->group) {
393 struct iommu_domain_geometry *geometry;
394 dma_addr_t start, end;
395 unsigned long order;
396
397 err = iova_cache_get();
398 if (err < 0)
399 goto put_group;
400
401 host->domain = iommu_paging_domain_alloc(host->dev);
402 if (IS_ERR(host->domain)) {
403 err = PTR_ERR(host->domain);
404 host->domain = NULL;
405 goto put_cache;
406 }
407
408 err = iommu_attach_group(host->domain, host->group);
409 if (err) {
410 if (err == -ENODEV)
411 err = 0;
412
413 goto free_domain;
414 }
415
416 geometry = &host->domain->geometry;
417 start = geometry->aperture_start & host->info->dma_mask;
418 end = geometry->aperture_end & host->info->dma_mask;
419
420 order = __ffs(host->domain->pgsize_bitmap);
421 init_iova_domain(&host->iova, 1UL << order, start >> order);
422 host->iova_end = end;
423
424 domain = host->domain;
425 }
426
427 return domain;
428
429free_domain:
430 iommu_domain_free(host->domain);
431 host->domain = NULL;
432put_cache:
433 iova_cache_put();
434put_group:
435 iommu_group_put(host->group);
436 host->group = NULL;
437
438 return ERR_PTR(err);
439}
440
441static int host1x_iommu_init(struct host1x *host)
442{
443 u64 mask = host->info->dma_mask;
444 struct iommu_domain *domain;
445 int err;
446
447 domain = host1x_iommu_attach(host);
448 if (IS_ERR(domain)) {
449 err = PTR_ERR(domain);
450 dev_err(host->dev, "failed to attach to IOMMU: %d\n", err);
451 return err;
452 }
453
454 /*
455 * If we're not behind an IOMMU make sure we don't get push buffers
456 * that are allocated outside of the range addressable by the GATHER
457 * opcode.
458 *
459 * Newer generations of Tegra (Tegra186 and later) support a wide
460 * variant of the GATHER opcode that allows addressing more bits.
461 */
462 if (!domain && !host->info->has_wide_gather)
463 mask = DMA_BIT_MASK(32);
464
465 err = dma_coerce_mask_and_coherent(host->dev, mask);
466 if (err < 0) {
467 dev_err(host->dev, "failed to set DMA mask: %d\n", err);
468 return err;
469 }
470
471 return 0;
472}
473
474static void host1x_iommu_exit(struct host1x *host)
475{
476 if (host->domain) {
477 put_iova_domain(&host->iova);
478 iommu_detach_group(host->domain, host->group);
479
480 iommu_domain_free(host->domain);
481 host->domain = NULL;
482
483 iova_cache_put();
484
485 iommu_group_put(host->group);
486 host->group = NULL;
487 }
488}
489
490static int host1x_get_resets(struct host1x *host)
491{
492 int err;
493
494 host->resets[0].id = "mc";
495 host->resets[1].id = "host1x";
496 host->nresets = ARRAY_SIZE(host->resets);
497
498 err = devm_reset_control_bulk_get_optional_exclusive_released(
499 host->dev, host->nresets, host->resets);
500 if (err) {
501 dev_err(host->dev, "failed to get reset: %d\n", err);
502 return err;
503 }
504
505 return 0;
506}
507
508static int host1x_probe(struct platform_device *pdev)
509{
510 struct host1x *host;
511 int err, i;
512
513 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
514 if (!host)
515 return -ENOMEM;
516
517 host->info = of_device_get_match_data(&pdev->dev);
518
519 if (host->info->has_hypervisor) {
520 host->regs = devm_platform_ioremap_resource_byname(pdev, "vm");
521 if (IS_ERR(host->regs))
522 return PTR_ERR(host->regs);
523
524 host->hv_regs = devm_platform_ioremap_resource_byname(pdev, "hypervisor");
525 if (IS_ERR(host->hv_regs))
526 return PTR_ERR(host->hv_regs);
527
528 if (host->info->has_common) {
529 host->common_regs = devm_platform_ioremap_resource_byname(pdev, "common");
530 if (IS_ERR(host->common_regs))
531 return PTR_ERR(host->common_regs);
532 }
533 } else {
534 host->regs = devm_platform_ioremap_resource(pdev, 0);
535 if (IS_ERR(host->regs))
536 return PTR_ERR(host->regs);
537 }
538
539 for (i = 0; i < ARRAY_SIZE(host->syncpt_irqs); i++) {
540 char irq_name[] = "syncptX";
541
542 sprintf(irq_name, "syncpt%d", i);
543
544 err = platform_get_irq_byname_optional(pdev, irq_name);
545 if (err == -ENXIO)
546 break;
547 if (err < 0)
548 return err;
549
550 host->syncpt_irqs[i] = err;
551 }
552
553 host->num_syncpt_irqs = i;
554
555 /* Device tree without irq names */
556 if (i == 0) {
557 host->syncpt_irqs[0] = platform_get_irq(pdev, 0);
558 if (host->syncpt_irqs[0] < 0)
559 return host->syncpt_irqs[0];
560
561 host->num_syncpt_irqs = 1;
562 }
563
564 mutex_init(&host->devices_lock);
565 INIT_LIST_HEAD(&host->devices);
566 INIT_LIST_HEAD(&host->list);
567 host->dev = &pdev->dev;
568
569 /* set common host1x device data */
570 platform_set_drvdata(pdev, host);
571
572 host->dev->dma_parms = &host->dma_parms;
573 dma_set_max_seg_size(host->dev, UINT_MAX);
574
575 if (host->info->init) {
576 err = host->info->init(host);
577 if (err)
578 return err;
579 }
580
581 host->clk = devm_clk_get(&pdev->dev, NULL);
582 if (IS_ERR(host->clk)) {
583 err = PTR_ERR(host->clk);
584
585 if (err != -EPROBE_DEFER)
586 dev_err(&pdev->dev, "failed to get clock: %d\n", err);
587
588 return err;
589 }
590
591 err = host1x_get_resets(host);
592 if (err)
593 return err;
594
595 host1x_bo_cache_init(&host->cache);
596
597 err = host1x_iommu_init(host);
598 if (err < 0) {
599 dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err);
600 goto destroy_cache;
601 }
602
603 err = host1x_channel_list_init(&host->channel_list,
604 host->info->nb_channels);
605 if (err) {
606 dev_err(&pdev->dev, "failed to initialize channel list\n");
607 goto iommu_exit;
608 }
609
610 err = host1x_memory_context_list_init(host);
611 if (err) {
612 dev_err(&pdev->dev, "failed to initialize context list\n");
613 goto free_channels;
614 }
615
616 err = host1x_syncpt_init(host);
617 if (err) {
618 dev_err(&pdev->dev, "failed to initialize syncpts\n");
619 goto free_contexts;
620 }
621
622 mutex_init(&host->intr_mutex);
623
624 pm_runtime_enable(&pdev->dev);
625
626 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
627 if (err)
628 goto pm_disable;
629
630 /* the driver's code isn't ready yet for the dynamic RPM */
631 err = pm_runtime_resume_and_get(&pdev->dev);
632 if (err)
633 goto pm_disable;
634
635 err = host1x_intr_init(host);
636 if (err) {
637 dev_err(&pdev->dev, "failed to initialize interrupts\n");
638 goto pm_put;
639 }
640
641 host1x_debug_init(host);
642
643 err = host1x_register(host);
644 if (err < 0)
645 goto deinit_debugfs;
646
647 err = devm_of_platform_populate(&pdev->dev);
648 if (err < 0)
649 goto unregister;
650
651 return 0;
652
653unregister:
654 host1x_unregister(host);
655deinit_debugfs:
656 host1x_debug_deinit(host);
657 host1x_intr_deinit(host);
658pm_put:
659 pm_runtime_put_sync_suspend(&pdev->dev);
660pm_disable:
661 pm_runtime_disable(&pdev->dev);
662 host1x_syncpt_deinit(host);
663free_contexts:
664 host1x_memory_context_list_free(&host->context_list);
665free_channels:
666 host1x_channel_list_free(&host->channel_list);
667iommu_exit:
668 host1x_iommu_exit(host);
669destroy_cache:
670 host1x_bo_cache_destroy(&host->cache);
671
672 return err;
673}
674
675static void host1x_remove(struct platform_device *pdev)
676{
677 struct host1x *host = platform_get_drvdata(pdev);
678
679 host1x_unregister(host);
680 host1x_debug_deinit(host);
681
682 pm_runtime_force_suspend(&pdev->dev);
683
684 host1x_intr_deinit(host);
685 host1x_syncpt_deinit(host);
686 host1x_memory_context_list_free(&host->context_list);
687 host1x_channel_list_free(&host->channel_list);
688 host1x_iommu_exit(host);
689 host1x_bo_cache_destroy(&host->cache);
690}
691
692static int __maybe_unused host1x_runtime_suspend(struct device *dev)
693{
694 struct host1x *host = dev_get_drvdata(dev);
695 int err;
696
697 host1x_channel_stop_all(host);
698 host1x_intr_stop(host);
699 host1x_syncpt_save(host);
700
701 if (!host->info->skip_reset_assert) {
702 err = reset_control_bulk_assert(host->nresets, host->resets);
703 if (err) {
704 dev_err(dev, "failed to assert reset: %d\n", err);
705 goto resume_host1x;
706 }
707
708 usleep_range(1000, 2000);
709 }
710
711 clk_disable_unprepare(host->clk);
712 reset_control_bulk_release(host->nresets, host->resets);
713
714 return 0;
715
716resume_host1x:
717 host1x_setup_virtualization_tables(host);
718 host1x_syncpt_restore(host);
719 host1x_intr_start(host);
720
721 return err;
722}
723
724static int __maybe_unused host1x_runtime_resume(struct device *dev)
725{
726 struct host1x *host = dev_get_drvdata(dev);
727 int err;
728
729 err = reset_control_bulk_acquire(host->nresets, host->resets);
730 if (err) {
731 dev_err(dev, "failed to acquire reset: %d\n", err);
732 return err;
733 }
734
735 err = clk_prepare_enable(host->clk);
736 if (err) {
737 dev_err(dev, "failed to enable clock: %d\n", err);
738 goto release_reset;
739 }
740
741 err = reset_control_bulk_deassert(host->nresets, host->resets);
742 if (err < 0) {
743 dev_err(dev, "failed to deassert reset: %d\n", err);
744 goto disable_clk;
745 }
746
747 host1x_setup_virtualization_tables(host);
748 host1x_syncpt_restore(host);
749 host1x_intr_start(host);
750
751 return 0;
752
753disable_clk:
754 clk_disable_unprepare(host->clk);
755release_reset:
756 reset_control_bulk_release(host->nresets, host->resets);
757
758 return err;
759}
760
761static const struct dev_pm_ops host1x_pm_ops = {
762 SET_RUNTIME_PM_OPS(host1x_runtime_suspend, host1x_runtime_resume,
763 NULL)
764 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
765};
766
767static struct platform_driver tegra_host1x_driver = {
768 .driver = {
769 .name = "tegra-host1x",
770 .of_match_table = host1x_of_match,
771 .pm = &host1x_pm_ops,
772 },
773 .probe = host1x_probe,
774 .remove = host1x_remove,
775};
776
777static struct platform_driver * const drivers[] = {
778 &tegra_host1x_driver,
779 &tegra_mipi_driver,
780};
781
782static int __init tegra_host1x_init(void)
783{
784 int err;
785
786 err = bus_register(&host1x_bus_type);
787 if (err < 0)
788 return err;
789
790 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
791 if (err < 0)
792 bus_unregister(&host1x_bus_type);
793
794 return err;
795}
796module_init(tegra_host1x_init);
797
798static void __exit tegra_host1x_exit(void)
799{
800 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
801 bus_unregister(&host1x_bus_type);
802}
803module_exit(tegra_host1x_exit);
804
805/**
806 * host1x_get_dma_mask() - query the supported DMA mask for host1x
807 * @host1x: host1x instance
808 *
809 * Note that this returns the supported DMA mask for host1x, which can be
810 * different from the applicable DMA mask under certain circumstances.
811 */
812u64 host1x_get_dma_mask(struct host1x *host1x)
813{
814 return host1x->info->dma_mask;
815}
816EXPORT_SYMBOL(host1x_get_dma_mask);
817
818MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
819MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
820MODULE_DESCRIPTION("Host1x driver for Tegra products");
821MODULE_LICENSE("GPL");