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1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __KGD_PP_INTERFACE_H__
25#define __KGD_PP_INTERFACE_H__
26
27extern const struct amdgpu_ip_block_version pp_smu_ip_block;
28
29struct amd_vce_state {
30 /* vce clocks */
31 u32 evclk;
32 u32 ecclk;
33 /* gpu clocks */
34 u32 sclk;
35 u32 mclk;
36 u8 clk_idx;
37 u8 pstate;
38};
39
40
41enum amd_dpm_forced_level {
42 AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
43 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
44 AMD_DPM_FORCED_LEVEL_LOW = 0x4,
45 AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
46 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
47 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
48 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
49 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
50 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
51};
52
53enum amd_pm_state_type {
54 /* not used for dpm */
55 POWER_STATE_TYPE_DEFAULT,
56 POWER_STATE_TYPE_POWERSAVE,
57 /* user selectable states */
58 POWER_STATE_TYPE_BATTERY,
59 POWER_STATE_TYPE_BALANCED,
60 POWER_STATE_TYPE_PERFORMANCE,
61 /* internal states */
62 POWER_STATE_TYPE_INTERNAL_UVD,
63 POWER_STATE_TYPE_INTERNAL_UVD_SD,
64 POWER_STATE_TYPE_INTERNAL_UVD_HD,
65 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
66 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
67 POWER_STATE_TYPE_INTERNAL_BOOT,
68 POWER_STATE_TYPE_INTERNAL_THERMAL,
69 POWER_STATE_TYPE_INTERNAL_ACPI,
70 POWER_STATE_TYPE_INTERNAL_ULV,
71 POWER_STATE_TYPE_INTERNAL_3DPERF,
72};
73
74#define AMD_MAX_VCE_LEVELS 6
75
76enum amd_vce_level {
77 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
78 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
79 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
80 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
81 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
82 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
83};
84
85enum amd_fan_ctrl_mode {
86 AMD_FAN_CTRL_NONE = 0,
87 AMD_FAN_CTRL_MANUAL = 1,
88 AMD_FAN_CTRL_AUTO = 2,
89};
90
91enum pp_clock_type {
92 PP_SCLK,
93 PP_MCLK,
94 PP_PCIE,
95 PP_SOCCLK,
96 PP_FCLK,
97 PP_DCEFCLK,
98 OD_SCLK,
99 OD_MCLK,
100 OD_VDDC_CURVE,
101 OD_RANGE,
102};
103
104enum amd_pp_sensors {
105 AMDGPU_PP_SENSOR_GFX_SCLK = 0,
106 AMDGPU_PP_SENSOR_VDDNB,
107 AMDGPU_PP_SENSOR_VDDGFX,
108 AMDGPU_PP_SENSOR_UVD_VCLK,
109 AMDGPU_PP_SENSOR_UVD_DCLK,
110 AMDGPU_PP_SENSOR_VCE_ECCLK,
111 AMDGPU_PP_SENSOR_GPU_LOAD,
112 AMDGPU_PP_SENSOR_MEM_LOAD,
113 AMDGPU_PP_SENSOR_GFX_MCLK,
114 AMDGPU_PP_SENSOR_GPU_TEMP,
115 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
116 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
117 AMDGPU_PP_SENSOR_MEM_TEMP,
118 AMDGPU_PP_SENSOR_VCE_POWER,
119 AMDGPU_PP_SENSOR_UVD_POWER,
120 AMDGPU_PP_SENSOR_GPU_POWER,
121 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
122 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
123 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
124 AMDGPU_PP_SENSOR_MIN_FAN_RPM,
125 AMDGPU_PP_SENSOR_MAX_FAN_RPM,
126 AMDGPU_PP_SENSOR_VCN_POWER_STATE,
127};
128
129enum amd_pp_task {
130 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
131 AMD_PP_TASK_ENABLE_USER_STATE,
132 AMD_PP_TASK_READJUST_POWER_STATE,
133 AMD_PP_TASK_COMPLETE_INIT,
134 AMD_PP_TASK_MAX
135};
136
137enum PP_SMC_POWER_PROFILE {
138 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
139 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
140 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2,
141 PP_SMC_POWER_PROFILE_VIDEO = 0x3,
142 PP_SMC_POWER_PROFILE_VR = 0x4,
143 PP_SMC_POWER_PROFILE_COMPUTE = 0x5,
144 PP_SMC_POWER_PROFILE_CUSTOM = 0x6,
145 PP_SMC_POWER_PROFILE_COUNT,
146};
147
148enum {
149 PP_GROUP_UNKNOWN = 0,
150 PP_GROUP_GFX = 1,
151 PP_GROUP_SYS,
152 PP_GROUP_MAX
153};
154
155enum PP_OD_DPM_TABLE_COMMAND {
156 PP_OD_EDIT_SCLK_VDDC_TABLE,
157 PP_OD_EDIT_MCLK_VDDC_TABLE,
158 PP_OD_EDIT_VDDC_CURVE,
159 PP_OD_RESTORE_DEFAULT_TABLE,
160 PP_OD_COMMIT_DPM_TABLE
161};
162
163struct pp_states_info {
164 uint32_t nums;
165 uint32_t states[16];
166};
167
168enum PP_HWMON_TEMP {
169 PP_TEMP_EDGE = 0,
170 PP_TEMP_JUNCTION,
171 PP_TEMP_MEM,
172 PP_TEMP_MAX
173};
174
175enum pp_mp1_state {
176 PP_MP1_STATE_NONE,
177 PP_MP1_STATE_SHUTDOWN,
178 PP_MP1_STATE_UNLOAD,
179 PP_MP1_STATE_RESET,
180};
181
182enum pp_df_cstate {
183 DF_CSTATE_DISALLOW = 0,
184 DF_CSTATE_ALLOW,
185};
186
187#define PP_GROUP_MASK 0xF0000000
188#define PP_GROUP_SHIFT 28
189
190#define PP_BLOCK_MASK 0x0FFFFF00
191#define PP_BLOCK_SHIFT 8
192
193#define PP_BLOCK_GFX_CG 0x01
194#define PP_BLOCK_GFX_MG 0x02
195#define PP_BLOCK_GFX_3D 0x04
196#define PP_BLOCK_GFX_RLC 0x08
197#define PP_BLOCK_GFX_CP 0x10
198#define PP_BLOCK_SYS_BIF 0x01
199#define PP_BLOCK_SYS_MC 0x02
200#define PP_BLOCK_SYS_ROM 0x04
201#define PP_BLOCK_SYS_DRM 0x08
202#define PP_BLOCK_SYS_HDP 0x10
203#define PP_BLOCK_SYS_SDMA 0x20
204
205#define PP_STATE_MASK 0x0000000F
206#define PP_STATE_SHIFT 0
207#define PP_STATE_SUPPORT_MASK 0x000000F0
208#define PP_STATE_SUPPORT_SHIFT 0
209
210#define PP_STATE_CG 0x01
211#define PP_STATE_LS 0x02
212#define PP_STATE_DS 0x04
213#define PP_STATE_SD 0x08
214#define PP_STATE_SUPPORT_CG 0x10
215#define PP_STATE_SUPPORT_LS 0x20
216#define PP_STATE_SUPPORT_DS 0x40
217#define PP_STATE_SUPPORT_SD 0x80
218
219#define PP_CG_MSG_ID(group, block, support, state) \
220 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
221 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
222
223#define XGMI_MODE_PSTATE_D3 0
224#define XGMI_MODE_PSTATE_D0 1
225
226struct seq_file;
227enum amd_pp_clock_type;
228struct amd_pp_simple_clock_info;
229struct amd_pp_display_configuration;
230struct amd_pp_clock_info;
231struct pp_display_clock_request;
232struct pp_clock_levels_with_voltage;
233struct pp_clock_levels_with_latency;
234struct amd_pp_clocks;
235
236struct amd_pm_funcs {
237/* export for dpm on ci and si */
238 int (*pre_set_power_state)(void *handle);
239 int (*set_power_state)(void *handle);
240 void (*post_set_power_state)(void *handle);
241 void (*display_configuration_changed)(void *handle);
242 void (*print_power_state)(void *handle, void *ps);
243 bool (*vblank_too_short)(void *handle);
244 void (*enable_bapm)(void *handle, bool enable);
245 int (*check_state_equal)(void *handle,
246 void *cps,
247 void *rps,
248 bool *equal);
249/* export for sysfs */
250 void (*set_fan_control_mode)(void *handle, u32 mode);
251 u32 (*get_fan_control_mode)(void *handle);
252 int (*set_fan_speed_percent)(void *handle, u32 speed);
253 int (*get_fan_speed_percent)(void *handle, u32 *speed);
254 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
255 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
256 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
257 int (*get_sclk_od)(void *handle);
258 int (*set_sclk_od)(void *handle, uint32_t value);
259 int (*get_mclk_od)(void *handle);
260 int (*set_mclk_od)(void *handle, uint32_t value);
261 int (*read_sensor)(void *handle, int idx, void *value, int *size);
262 enum amd_dpm_forced_level (*get_performance_level)(void *handle);
263 enum amd_pm_state_type (*get_current_power_state)(void *handle);
264 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
265 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
266 int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
267 int (*get_pp_table)(void *handle, char **table);
268 int (*set_pp_table)(void *handle, const char *buf, size_t size);
269 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
270 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
271/* export to amdgpu */
272 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
273 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
274 enum amd_pm_state_type *user_state);
275 int (*load_firmware)(void *handle);
276 int (*wait_for_fw_loading_complete)(void *handle);
277 int (*set_powergating_by_smu)(void *handle,
278 uint32_t block_type, bool gate);
279 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
280 int (*set_power_limit)(void *handle, uint32_t n);
281 int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
282 int (*get_power_profile_mode)(void *handle, char *buf);
283 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
284 int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
285 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
286 int (*smu_i2c_bus_access)(void *handle, bool acquire);
287/* export to DC */
288 u32 (*get_sclk)(void *handle, bool low);
289 u32 (*get_mclk)(void *handle, bool low);
290 int (*display_configuration_change)(void *handle,
291 const struct amd_pp_display_configuration *input);
292 int (*get_display_power_level)(void *handle,
293 struct amd_pp_simple_clock_info *output);
294 int (*get_current_clocks)(void *handle,
295 struct amd_pp_clock_info *clocks);
296 int (*get_clock_by_type)(void *handle,
297 enum amd_pp_clock_type type,
298 struct amd_pp_clocks *clocks);
299 int (*get_clock_by_type_with_latency)(void *handle,
300 enum amd_pp_clock_type type,
301 struct pp_clock_levels_with_latency *clocks);
302 int (*get_clock_by_type_with_voltage)(void *handle,
303 enum amd_pp_clock_type type,
304 struct pp_clock_levels_with_voltage *clocks);
305 int (*set_watermarks_for_clocks_ranges)(void *handle,
306 void *clock_ranges);
307 int (*display_clock_voltage_request)(void *handle,
308 struct pp_display_clock_request *clock);
309 int (*get_display_mode_validation_clocks)(void *handle,
310 struct amd_pp_simple_clock_info *clocks);
311 int (*notify_smu_enable_pwe)(void *handle);
312 int (*enable_mgpu_fan_boost)(void *handle);
313 int (*set_active_display_count)(void *handle, uint32_t count);
314 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
315 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
316 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
317 int (*get_asic_baco_capability)(void *handle, bool *cap);
318 int (*get_asic_baco_state)(void *handle, int *state);
319 int (*set_asic_baco_state)(void *handle, int state);
320 int (*get_ppfeature_status)(void *handle, char *buf);
321 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
322 int (*asic_reset_mode_2)(void *handle);
323 int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
324 int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
325};
326
327#endif
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __KGD_PP_INTERFACE_H__
25#define __KGD_PP_INTERFACE_H__
26
27extern const struct amdgpu_ip_block_version pp_smu_ip_block;
28extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
29extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
30extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
31extern const struct amdgpu_ip_block_version smu_v14_0_ip_block;
32
33enum smu_event_type {
34 SMU_EVENT_RESET_COMPLETE = 0,
35};
36
37struct amd_vce_state {
38 /* vce clocks */
39 u32 evclk;
40 u32 ecclk;
41 /* gpu clocks */
42 u32 sclk;
43 u32 mclk;
44 u8 clk_idx;
45 u8 pstate;
46};
47
48
49enum amd_dpm_forced_level {
50 AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
51 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
52 AMD_DPM_FORCED_LEVEL_LOW = 0x4,
53 AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
54 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
56 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
57 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
58 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
59 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
60};
61
62enum amd_pm_state_type {
63 /* not used for dpm */
64 POWER_STATE_TYPE_DEFAULT,
65 POWER_STATE_TYPE_POWERSAVE,
66 /* user selectable states */
67 POWER_STATE_TYPE_BATTERY,
68 POWER_STATE_TYPE_BALANCED,
69 POWER_STATE_TYPE_PERFORMANCE,
70 /* internal states */
71 POWER_STATE_TYPE_INTERNAL_UVD,
72 POWER_STATE_TYPE_INTERNAL_UVD_SD,
73 POWER_STATE_TYPE_INTERNAL_UVD_HD,
74 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
75 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
76 POWER_STATE_TYPE_INTERNAL_BOOT,
77 POWER_STATE_TYPE_INTERNAL_THERMAL,
78 POWER_STATE_TYPE_INTERNAL_ACPI,
79 POWER_STATE_TYPE_INTERNAL_ULV,
80 POWER_STATE_TYPE_INTERNAL_3DPERF,
81};
82
83#define AMD_MAX_VCE_LEVELS 6
84
85enum amd_vce_level {
86 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
87 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
88 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
89 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
90 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
91 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
92};
93
94enum amd_fan_ctrl_mode {
95 AMD_FAN_CTRL_NONE = 0,
96 AMD_FAN_CTRL_MANUAL = 1,
97 AMD_FAN_CTRL_AUTO = 2,
98};
99
100enum pp_clock_type {
101 PP_SCLK,
102 PP_MCLK,
103 PP_PCIE,
104 PP_SOCCLK,
105 PP_FCLK,
106 PP_DCEFCLK,
107 PP_VCLK,
108 PP_VCLK1,
109 PP_DCLK,
110 PP_DCLK1,
111 OD_SCLK,
112 OD_MCLK,
113 OD_VDDC_CURVE,
114 OD_RANGE,
115 OD_VDDGFX_OFFSET,
116 OD_CCLK,
117 OD_FAN_CURVE,
118 OD_ACOUSTIC_LIMIT,
119 OD_ACOUSTIC_TARGET,
120 OD_FAN_TARGET_TEMPERATURE,
121 OD_FAN_MINIMUM_PWM,
122 OD_FAN_ZERO_RPM_ENABLE,
123 OD_FAN_ZERO_RPM_STOP_TEMP,
124};
125
126enum amd_pp_sensors {
127 AMDGPU_PP_SENSOR_GFX_SCLK = 0,
128 AMDGPU_PP_SENSOR_CPU_CLK,
129 AMDGPU_PP_SENSOR_VDDNB,
130 AMDGPU_PP_SENSOR_VDDGFX,
131 AMDGPU_PP_SENSOR_UVD_VCLK,
132 AMDGPU_PP_SENSOR_UVD_DCLK,
133 AMDGPU_PP_SENSOR_VCE_ECCLK,
134 AMDGPU_PP_SENSOR_GPU_LOAD,
135 AMDGPU_PP_SENSOR_MEM_LOAD,
136 AMDGPU_PP_SENSOR_GFX_MCLK,
137 AMDGPU_PP_SENSOR_GPU_TEMP,
138 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
139 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
140 AMDGPU_PP_SENSOR_MEM_TEMP,
141 AMDGPU_PP_SENSOR_VCE_POWER,
142 AMDGPU_PP_SENSOR_UVD_POWER,
143 AMDGPU_PP_SENSOR_GPU_AVG_POWER,
144 AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
145 AMDGPU_PP_SENSOR_SS_APU_SHARE,
146 AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
147 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
148 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
149 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
150 AMDGPU_PP_SENSOR_MIN_FAN_RPM,
151 AMDGPU_PP_SENSOR_MAX_FAN_RPM,
152 AMDGPU_PP_SENSOR_VCN_POWER_STATE,
153 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
154 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
155 AMDGPU_PP_SENSOR_VCN_LOAD,
156};
157
158enum amd_pp_task {
159 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
160 AMD_PP_TASK_ENABLE_USER_STATE,
161 AMD_PP_TASK_READJUST_POWER_STATE,
162 AMD_PP_TASK_COMPLETE_INIT,
163 AMD_PP_TASK_MAX
164};
165
166enum PP_SMC_POWER_PROFILE {
167 PP_SMC_POWER_PROFILE_UNKNOWN = -1,
168 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
169 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
170 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2,
171 PP_SMC_POWER_PROFILE_VIDEO = 0x3,
172 PP_SMC_POWER_PROFILE_VR = 0x4,
173 PP_SMC_POWER_PROFILE_COMPUTE = 0x5,
174 PP_SMC_POWER_PROFILE_CUSTOM = 0x6,
175 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7,
176 PP_SMC_POWER_PROFILE_CAPPED = 0x8,
177 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9,
178 PP_SMC_POWER_PROFILE_COUNT,
179};
180
181extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
182
183
184
185enum {
186 PP_GROUP_UNKNOWN = 0,
187 PP_GROUP_GFX = 1,
188 PP_GROUP_SYS,
189 PP_GROUP_MAX
190};
191
192enum PP_OD_DPM_TABLE_COMMAND {
193 PP_OD_EDIT_SCLK_VDDC_TABLE,
194 PP_OD_EDIT_MCLK_VDDC_TABLE,
195 PP_OD_EDIT_CCLK_VDDC_TABLE,
196 PP_OD_EDIT_VDDC_CURVE,
197 PP_OD_RESTORE_DEFAULT_TABLE,
198 PP_OD_COMMIT_DPM_TABLE,
199 PP_OD_EDIT_VDDGFX_OFFSET,
200 PP_OD_EDIT_FAN_CURVE,
201 PP_OD_EDIT_ACOUSTIC_LIMIT,
202 PP_OD_EDIT_ACOUSTIC_TARGET,
203 PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
204 PP_OD_EDIT_FAN_MINIMUM_PWM,
205 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE,
206 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP,
207};
208
209struct pp_states_info {
210 uint32_t nums;
211 uint32_t states[16];
212};
213
214enum PP_HWMON_TEMP {
215 PP_TEMP_EDGE = 0,
216 PP_TEMP_JUNCTION,
217 PP_TEMP_MEM,
218 PP_TEMP_MAX
219};
220
221enum pp_mp1_state {
222 PP_MP1_STATE_NONE,
223 PP_MP1_STATE_SHUTDOWN,
224 PP_MP1_STATE_UNLOAD,
225 PP_MP1_STATE_RESET,
226 PP_MP1_STATE_FLR,
227};
228
229enum pp_df_cstate {
230 DF_CSTATE_DISALLOW = 0,
231 DF_CSTATE_ALLOW,
232};
233
234/**
235 * DOC: amdgpu_pp_power
236 *
237 * APU power is managed to system-level requirements through the PPT
238 * (package power tracking) feature. PPT is intended to limit power to the
239 * requirements of the power source and could be dynamically updated to
240 * maximize APU performance within the system power budget.
241 *
242 * Two types of power measurement can be requested, where supported, with
243 * :c:type:`enum pp_power_type <pp_power_type>`.
244 */
245
246/**
247 * enum pp_power_limit_level - Used to query the power limits
248 *
249 * @PP_PWR_LIMIT_MIN: Minimum Power Limit
250 * @PP_PWR_LIMIT_CURRENT: Current Power Limit
251 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
252 * @PP_PWR_LIMIT_MAX: Maximum Power Limit
253 */
254enum pp_power_limit_level {
255 PP_PWR_LIMIT_MIN = -1,
256 PP_PWR_LIMIT_CURRENT,
257 PP_PWR_LIMIT_DEFAULT,
258 PP_PWR_LIMIT_MAX,
259};
260
261/**
262 * enum pp_power_type - Used to specify the type of the requested power
263 *
264 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
265 * moving average of APU power (default ~5000 ms).
266 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
267 * where supported.
268 */
269enum pp_power_type {
270 PP_PWR_TYPE_SUSTAINED,
271 PP_PWR_TYPE_FAST,
272};
273
274enum pp_xgmi_plpd_mode {
275 XGMI_PLPD_NONE = -1,
276 XGMI_PLPD_DISALLOW,
277 XGMI_PLPD_DEFAULT,
278 XGMI_PLPD_OPTIMIZED,
279 XGMI_PLPD_COUNT,
280};
281
282enum pp_pm_policy {
283 PP_PM_POLICY_NONE = -1,
284 PP_PM_POLICY_SOC_PSTATE = 0,
285 PP_PM_POLICY_XGMI_PLPD,
286 PP_PM_POLICY_NUM,
287};
288
289enum pp_policy_soc_pstate {
290 SOC_PSTATE_DEFAULT = 0,
291 SOC_PSTATE_0,
292 SOC_PSTATE_1,
293 SOC_PSTATE_2,
294 SOC_PSTAT_COUNT,
295};
296
297#define PP_POLICY_MAX_LEVELS 5
298
299#define PP_GROUP_MASK 0xF0000000
300#define PP_GROUP_SHIFT 28
301
302#define PP_BLOCK_MASK 0x0FFFFF00
303#define PP_BLOCK_SHIFT 8
304
305#define PP_BLOCK_GFX_CG 0x01
306#define PP_BLOCK_GFX_MG 0x02
307#define PP_BLOCK_GFX_3D 0x04
308#define PP_BLOCK_GFX_RLC 0x08
309#define PP_BLOCK_GFX_CP 0x10
310#define PP_BLOCK_SYS_BIF 0x01
311#define PP_BLOCK_SYS_MC 0x02
312#define PP_BLOCK_SYS_ROM 0x04
313#define PP_BLOCK_SYS_DRM 0x08
314#define PP_BLOCK_SYS_HDP 0x10
315#define PP_BLOCK_SYS_SDMA 0x20
316
317#define PP_STATE_MASK 0x0000000F
318#define PP_STATE_SHIFT 0
319#define PP_STATE_SUPPORT_MASK 0x000000F0
320#define PP_STATE_SUPPORT_SHIFT 0
321
322#define PP_STATE_CG 0x01
323#define PP_STATE_LS 0x02
324#define PP_STATE_DS 0x04
325#define PP_STATE_SD 0x08
326#define PP_STATE_SUPPORT_CG 0x10
327#define PP_STATE_SUPPORT_LS 0x20
328#define PP_STATE_SUPPORT_DS 0x40
329#define PP_STATE_SUPPORT_SD 0x80
330
331#define PP_CG_MSG_ID(group, block, support, state) \
332 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
333 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
334
335#define XGMI_MODE_PSTATE_D3 0
336#define XGMI_MODE_PSTATE_D0 1
337
338#define NUM_HBM_INSTANCES 4
339#define NUM_XGMI_LINKS 8
340#define MAX_GFX_CLKS 8
341#define MAX_CLKS 4
342#define NUM_VCN 4
343#define NUM_JPEG_ENG 32
344#define MAX_XCC 8
345#define NUM_XCP 8
346struct seq_file;
347enum amd_pp_clock_type;
348struct amd_pp_simple_clock_info;
349struct amd_pp_display_configuration;
350struct amd_pp_clock_info;
351struct pp_display_clock_request;
352struct pp_clock_levels_with_voltage;
353struct pp_clock_levels_with_latency;
354struct amd_pp_clocks;
355struct pp_smu_wm_range_sets;
356struct pp_smu_nv_clock_table;
357struct dpm_clocks;
358
359struct amdgpu_xcp_metrics {
360 /* Utilization Instantaneous (%) */
361 uint32_t gfx_busy_inst[MAX_XCC];
362 uint16_t jpeg_busy[NUM_JPEG_ENG];
363 uint16_t vcn_busy[NUM_VCN];
364 /* Utilization Accumulated (%) */
365 uint64_t gfx_busy_acc[MAX_XCC];
366};
367
368struct amdgpu_xcp_metrics_v1_1 {
369 /* Utilization Instantaneous (%) */
370 uint32_t gfx_busy_inst[MAX_XCC];
371 uint16_t jpeg_busy[NUM_JPEG_ENG];
372 uint16_t vcn_busy[NUM_VCN];
373 /* Utilization Accumulated (%) */
374 uint64_t gfx_busy_acc[MAX_XCC];
375 /* Total App Clock Counter Accumulated */
376 uint64_t gfx_below_host_limit_acc[MAX_XCC];
377};
378
379struct amd_pm_funcs {
380/* export for dpm on ci and si */
381 int (*pre_set_power_state)(void *handle);
382 int (*set_power_state)(void *handle);
383 void (*post_set_power_state)(void *handle);
384 void (*display_configuration_changed)(void *handle);
385 void (*print_power_state)(void *handle, void *ps);
386 bool (*vblank_too_short)(void *handle);
387 void (*enable_bapm)(void *handle, bool enable);
388 int (*check_state_equal)(void *handle,
389 void *cps,
390 void *rps,
391 bool *equal);
392/* export for sysfs */
393 int (*set_fan_control_mode)(void *handle, u32 mode);
394 int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
395 int (*set_fan_speed_pwm)(void *handle, u32 speed);
396 int (*get_fan_speed_pwm)(void *handle, u32 *speed);
397 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
398 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
399 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
400 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
401 int (*get_sclk_od)(void *handle);
402 int (*set_sclk_od)(void *handle, uint32_t value);
403 int (*get_mclk_od)(void *handle);
404 int (*set_mclk_od)(void *handle, uint32_t value);
405 int (*read_sensor)(void *handle, int idx, void *value, int *size);
406 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);
407 int (*set_apu_thermal_limit)(void *handle, uint32_t limit);
408 enum amd_dpm_forced_level (*get_performance_level)(void *handle);
409 enum amd_pm_state_type (*get_current_power_state)(void *handle);
410 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
411 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
412 int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
413 int (*get_pp_table)(void *handle, char **table);
414 int (*set_pp_table)(void *handle, const char *buf, size_t size);
415 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
416 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
417/* export to amdgpu */
418 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
419 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
420 enum amd_pm_state_type *user_state);
421 int (*load_firmware)(void *handle);
422 int (*wait_for_fw_loading_complete)(void *handle);
423 int (*set_powergating_by_smu)(void *handle,
424 uint32_t block_type, bool gate);
425 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
426 int (*set_power_limit)(void *handle, uint32_t n);
427 int (*get_power_limit)(void *handle, uint32_t *limit,
428 enum pp_power_limit_level pp_limit_level,
429 enum pp_power_type power_type);
430 int (*get_power_profile_mode)(void *handle, char *buf);
431 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
432 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
433 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
434 long *input, uint32_t size);
435 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
436 int (*smu_i2c_bus_access)(void *handle, bool acquire);
437 int (*gfx_state_change_set)(void *handle, uint32_t state);
438/* export to DC */
439 u32 (*get_sclk)(void *handle, bool low);
440 u32 (*get_mclk)(void *handle, bool low);
441 int (*display_configuration_change)(void *handle,
442 const struct amd_pp_display_configuration *input);
443 int (*get_display_power_level)(void *handle,
444 struct amd_pp_simple_clock_info *output);
445 int (*get_current_clocks)(void *handle,
446 struct amd_pp_clock_info *clocks);
447 int (*get_clock_by_type)(void *handle,
448 enum amd_pp_clock_type type,
449 struct amd_pp_clocks *clocks);
450 int (*get_clock_by_type_with_latency)(void *handle,
451 enum amd_pp_clock_type type,
452 struct pp_clock_levels_with_latency *clocks);
453 int (*get_clock_by_type_with_voltage)(void *handle,
454 enum amd_pp_clock_type type,
455 struct pp_clock_levels_with_voltage *clocks);
456 int (*set_watermarks_for_clocks_ranges)(void *handle,
457 void *clock_ranges);
458 int (*display_clock_voltage_request)(void *handle,
459 struct pp_display_clock_request *clock);
460 int (*get_display_mode_validation_clocks)(void *handle,
461 struct amd_pp_simple_clock_info *clocks);
462 int (*notify_smu_enable_pwe)(void *handle);
463 int (*enable_mgpu_fan_boost)(void *handle);
464 int (*set_active_display_count)(void *handle, uint32_t count);
465 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
466 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
467 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
468 int (*get_asic_baco_capability)(void *handle);
469 int (*get_asic_baco_state)(void *handle, int *state);
470 int (*set_asic_baco_state)(void *handle, int state);
471 int (*get_ppfeature_status)(void *handle, char *buf);
472 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
473 int (*asic_reset_mode_2)(void *handle);
474 int (*asic_reset_enable_gfx_features)(void *handle);
475 int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
476 int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
477 ssize_t (*get_gpu_metrics)(void *handle, void **table);
478 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size);
479 int (*set_watermarks_for_clock_ranges)(void *handle,
480 struct pp_smu_wm_range_sets *ranges);
481 int (*display_disable_memory_clock_switch)(void *handle,
482 bool disable_memory_clock_switch);
483 int (*get_max_sustainable_clocks_by_dc)(void *handle,
484 struct pp_smu_nv_clock_table *max_clocks);
485 int (*get_uclk_dpm_states)(void *handle,
486 unsigned int *clock_values_in_khz,
487 unsigned int *num_states);
488 int (*get_dpm_clock_table)(void *handle,
489 struct dpm_clocks *clock_table);
490 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
491 void (*pm_compute_clocks)(void *handle);
492 int (*notify_rlc_state)(void *handle, bool en);
493};
494
495struct metrics_table_header {
496 uint16_t structure_size;
497 uint8_t format_revision;
498 uint8_t content_revision;
499};
500
501/*
502 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
503 * Use gpu_metrics_v1_1 or later instead.
504 */
505struct gpu_metrics_v1_0 {
506 struct metrics_table_header common_header;
507
508 /* Driver attached timestamp (in ns) */
509 uint64_t system_clock_counter;
510
511 /* Temperature */
512 uint16_t temperature_edge;
513 uint16_t temperature_hotspot;
514 uint16_t temperature_mem;
515 uint16_t temperature_vrgfx;
516 uint16_t temperature_vrsoc;
517 uint16_t temperature_vrmem;
518
519 /* Utilization */
520 uint16_t average_gfx_activity;
521 uint16_t average_umc_activity; // memory controller
522 uint16_t average_mm_activity; // UVD or VCN
523
524 /* Power/Energy */
525 uint16_t average_socket_power;
526 uint32_t energy_accumulator;
527
528 /* Average clocks */
529 uint16_t average_gfxclk_frequency;
530 uint16_t average_socclk_frequency;
531 uint16_t average_uclk_frequency;
532 uint16_t average_vclk0_frequency;
533 uint16_t average_dclk0_frequency;
534 uint16_t average_vclk1_frequency;
535 uint16_t average_dclk1_frequency;
536
537 /* Current clocks */
538 uint16_t current_gfxclk;
539 uint16_t current_socclk;
540 uint16_t current_uclk;
541 uint16_t current_vclk0;
542 uint16_t current_dclk0;
543 uint16_t current_vclk1;
544 uint16_t current_dclk1;
545
546 /* Throttle status */
547 uint32_t throttle_status;
548
549 /* Fans */
550 uint16_t current_fan_speed;
551
552 /* Link width/speed */
553 uint8_t pcie_link_width;
554 uint8_t pcie_link_speed; // in 0.1 GT/s
555};
556
557struct gpu_metrics_v1_1 {
558 struct metrics_table_header common_header;
559
560 /* Temperature */
561 uint16_t temperature_edge;
562 uint16_t temperature_hotspot;
563 uint16_t temperature_mem;
564 uint16_t temperature_vrgfx;
565 uint16_t temperature_vrsoc;
566 uint16_t temperature_vrmem;
567
568 /* Utilization */
569 uint16_t average_gfx_activity;
570 uint16_t average_umc_activity; // memory controller
571 uint16_t average_mm_activity; // UVD or VCN
572
573 /* Power/Energy */
574 uint16_t average_socket_power;
575 uint64_t energy_accumulator;
576
577 /* Driver attached timestamp (in ns) */
578 uint64_t system_clock_counter;
579
580 /* Average clocks */
581 uint16_t average_gfxclk_frequency;
582 uint16_t average_socclk_frequency;
583 uint16_t average_uclk_frequency;
584 uint16_t average_vclk0_frequency;
585 uint16_t average_dclk0_frequency;
586 uint16_t average_vclk1_frequency;
587 uint16_t average_dclk1_frequency;
588
589 /* Current clocks */
590 uint16_t current_gfxclk;
591 uint16_t current_socclk;
592 uint16_t current_uclk;
593 uint16_t current_vclk0;
594 uint16_t current_dclk0;
595 uint16_t current_vclk1;
596 uint16_t current_dclk1;
597
598 /* Throttle status */
599 uint32_t throttle_status;
600
601 /* Fans */
602 uint16_t current_fan_speed;
603
604 /* Link width/speed */
605 uint16_t pcie_link_width;
606 uint16_t pcie_link_speed; // in 0.1 GT/s
607
608 uint16_t padding;
609
610 uint32_t gfx_activity_acc;
611 uint32_t mem_activity_acc;
612
613 uint16_t temperature_hbm[NUM_HBM_INSTANCES];
614};
615
616struct gpu_metrics_v1_2 {
617 struct metrics_table_header common_header;
618
619 /* Temperature */
620 uint16_t temperature_edge;
621 uint16_t temperature_hotspot;
622 uint16_t temperature_mem;
623 uint16_t temperature_vrgfx;
624 uint16_t temperature_vrsoc;
625 uint16_t temperature_vrmem;
626
627 /* Utilization */
628 uint16_t average_gfx_activity;
629 uint16_t average_umc_activity; // memory controller
630 uint16_t average_mm_activity; // UVD or VCN
631
632 /* Power/Energy */
633 uint16_t average_socket_power;
634 uint64_t energy_accumulator;
635
636 /* Driver attached timestamp (in ns) */
637 uint64_t system_clock_counter;
638
639 /* Average clocks */
640 uint16_t average_gfxclk_frequency;
641 uint16_t average_socclk_frequency;
642 uint16_t average_uclk_frequency;
643 uint16_t average_vclk0_frequency;
644 uint16_t average_dclk0_frequency;
645 uint16_t average_vclk1_frequency;
646 uint16_t average_dclk1_frequency;
647
648 /* Current clocks */
649 uint16_t current_gfxclk;
650 uint16_t current_socclk;
651 uint16_t current_uclk;
652 uint16_t current_vclk0;
653 uint16_t current_dclk0;
654 uint16_t current_vclk1;
655 uint16_t current_dclk1;
656
657 /* Throttle status (ASIC dependent) */
658 uint32_t throttle_status;
659
660 /* Fans */
661 uint16_t current_fan_speed;
662
663 /* Link width/speed */
664 uint16_t pcie_link_width;
665 uint16_t pcie_link_speed; // in 0.1 GT/s
666
667 uint16_t padding;
668
669 uint32_t gfx_activity_acc;
670 uint32_t mem_activity_acc;
671
672 uint16_t temperature_hbm[NUM_HBM_INSTANCES];
673
674 /* PMFW attached timestamp (10ns resolution) */
675 uint64_t firmware_timestamp;
676};
677
678struct gpu_metrics_v1_3 {
679 struct metrics_table_header common_header;
680
681 /* Temperature */
682 uint16_t temperature_edge;
683 uint16_t temperature_hotspot;
684 uint16_t temperature_mem;
685 uint16_t temperature_vrgfx;
686 uint16_t temperature_vrsoc;
687 uint16_t temperature_vrmem;
688
689 /* Utilization */
690 uint16_t average_gfx_activity;
691 uint16_t average_umc_activity; // memory controller
692 uint16_t average_mm_activity; // UVD or VCN
693
694 /* Power/Energy */
695 uint16_t average_socket_power;
696 uint64_t energy_accumulator;
697
698 /* Driver attached timestamp (in ns) */
699 uint64_t system_clock_counter;
700
701 /* Average clocks */
702 uint16_t average_gfxclk_frequency;
703 uint16_t average_socclk_frequency;
704 uint16_t average_uclk_frequency;
705 uint16_t average_vclk0_frequency;
706 uint16_t average_dclk0_frequency;
707 uint16_t average_vclk1_frequency;
708 uint16_t average_dclk1_frequency;
709
710 /* Current clocks */
711 uint16_t current_gfxclk;
712 uint16_t current_socclk;
713 uint16_t current_uclk;
714 uint16_t current_vclk0;
715 uint16_t current_dclk0;
716 uint16_t current_vclk1;
717 uint16_t current_dclk1;
718
719 /* Throttle status */
720 uint32_t throttle_status;
721
722 /* Fans */
723 uint16_t current_fan_speed;
724
725 /* Link width/speed */
726 uint16_t pcie_link_width;
727 uint16_t pcie_link_speed; // in 0.1 GT/s
728
729 uint16_t padding;
730
731 uint32_t gfx_activity_acc;
732 uint32_t mem_activity_acc;
733
734 uint16_t temperature_hbm[NUM_HBM_INSTANCES];
735
736 /* PMFW attached timestamp (10ns resolution) */
737 uint64_t firmware_timestamp;
738
739 /* Voltage (mV) */
740 uint16_t voltage_soc;
741 uint16_t voltage_gfx;
742 uint16_t voltage_mem;
743
744 uint16_t padding1;
745
746 /* Throttle status (ASIC independent) */
747 uint64_t indep_throttle_status;
748};
749
750struct gpu_metrics_v1_4 {
751 struct metrics_table_header common_header;
752
753 /* Temperature (Celsius) */
754 uint16_t temperature_hotspot;
755 uint16_t temperature_mem;
756 uint16_t temperature_vrsoc;
757
758 /* Power (Watts) */
759 uint16_t curr_socket_power;
760
761 /* Utilization (%) */
762 uint16_t average_gfx_activity;
763 uint16_t average_umc_activity; // memory controller
764 uint16_t vcn_activity[NUM_VCN];
765
766 /* Energy (15.259uJ (2^-16) units) */
767 uint64_t energy_accumulator;
768
769 /* Driver attached timestamp (in ns) */
770 uint64_t system_clock_counter;
771
772 /* Throttle status */
773 uint32_t throttle_status;
774
775 /* Clock Lock Status. Each bit corresponds to clock instance */
776 uint32_t gfxclk_lock_status;
777
778 /* Link width (number of lanes) and speed (in 0.1 GT/s) */
779 uint16_t pcie_link_width;
780 uint16_t pcie_link_speed;
781
782 /* XGMI bus width and bitrate (in Gbps) */
783 uint16_t xgmi_link_width;
784 uint16_t xgmi_link_speed;
785
786 /* Utilization Accumulated (%) */
787 uint32_t gfx_activity_acc;
788 uint32_t mem_activity_acc;
789
790 /*PCIE accumulated bandwidth (GB/sec) */
791 uint64_t pcie_bandwidth_acc;
792
793 /*PCIE instantaneous bandwidth (GB/sec) */
794 uint64_t pcie_bandwidth_inst;
795
796 /* PCIE L0 to recovery state transition accumulated count */
797 uint64_t pcie_l0_to_recov_count_acc;
798
799 /* PCIE replay accumulated count */
800 uint64_t pcie_replay_count_acc;
801
802 /* PCIE replay rollover accumulated count */
803 uint64_t pcie_replay_rover_count_acc;
804
805 /* XGMI accumulated data transfer size(KiloBytes) */
806 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
807 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
808
809 /* PMFW attached timestamp (10ns resolution) */
810 uint64_t firmware_timestamp;
811
812 /* Current clocks (Mhz) */
813 uint16_t current_gfxclk[MAX_GFX_CLKS];
814 uint16_t current_socclk[MAX_CLKS];
815 uint16_t current_vclk0[MAX_CLKS];
816 uint16_t current_dclk0[MAX_CLKS];
817 uint16_t current_uclk;
818
819 uint16_t padding;
820};
821
822struct gpu_metrics_v1_5 {
823 struct metrics_table_header common_header;
824
825 /* Temperature (Celsius) */
826 uint16_t temperature_hotspot;
827 uint16_t temperature_mem;
828 uint16_t temperature_vrsoc;
829
830 /* Power (Watts) */
831 uint16_t curr_socket_power;
832
833 /* Utilization (%) */
834 uint16_t average_gfx_activity;
835 uint16_t average_umc_activity; // memory controller
836 uint16_t vcn_activity[NUM_VCN];
837 uint16_t jpeg_activity[NUM_JPEG_ENG];
838
839 /* Energy (15.259uJ (2^-16) units) */
840 uint64_t energy_accumulator;
841
842 /* Driver attached timestamp (in ns) */
843 uint64_t system_clock_counter;
844
845 /* Throttle status */
846 uint32_t throttle_status;
847
848 /* Clock Lock Status. Each bit corresponds to clock instance */
849 uint32_t gfxclk_lock_status;
850
851 /* Link width (number of lanes) and speed (in 0.1 GT/s) */
852 uint16_t pcie_link_width;
853 uint16_t pcie_link_speed;
854
855 /* XGMI bus width and bitrate (in Gbps) */
856 uint16_t xgmi_link_width;
857 uint16_t xgmi_link_speed;
858
859 /* Utilization Accumulated (%) */
860 uint32_t gfx_activity_acc;
861 uint32_t mem_activity_acc;
862
863 /*PCIE accumulated bandwidth (GB/sec) */
864 uint64_t pcie_bandwidth_acc;
865
866 /*PCIE instantaneous bandwidth (GB/sec) */
867 uint64_t pcie_bandwidth_inst;
868
869 /* PCIE L0 to recovery state transition accumulated count */
870 uint64_t pcie_l0_to_recov_count_acc;
871
872 /* PCIE replay accumulated count */
873 uint64_t pcie_replay_count_acc;
874
875 /* PCIE replay rollover accumulated count */
876 uint64_t pcie_replay_rover_count_acc;
877
878 /* PCIE NAK sent accumulated count */
879 uint32_t pcie_nak_sent_count_acc;
880
881 /* PCIE NAK received accumulated count */
882 uint32_t pcie_nak_rcvd_count_acc;
883
884 /* XGMI accumulated data transfer size(KiloBytes) */
885 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
886 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
887
888 /* PMFW attached timestamp (10ns resolution) */
889 uint64_t firmware_timestamp;
890
891 /* Current clocks (Mhz) */
892 uint16_t current_gfxclk[MAX_GFX_CLKS];
893 uint16_t current_socclk[MAX_CLKS];
894 uint16_t current_vclk0[MAX_CLKS];
895 uint16_t current_dclk0[MAX_CLKS];
896 uint16_t current_uclk;
897
898 uint16_t padding;
899};
900
901struct gpu_metrics_v1_6 {
902 struct metrics_table_header common_header;
903
904 /* Temperature (Celsius) */
905 uint16_t temperature_hotspot;
906 uint16_t temperature_mem;
907 uint16_t temperature_vrsoc;
908
909 /* Power (Watts) */
910 uint16_t curr_socket_power;
911
912 /* Utilization (%) */
913 uint16_t average_gfx_activity;
914 uint16_t average_umc_activity; // memory controller
915
916 /* Energy (15.259uJ (2^-16) units) */
917 uint64_t energy_accumulator;
918
919 /* Driver attached timestamp (in ns) */
920 uint64_t system_clock_counter;
921
922 /* Accumulation cycle counter */
923 uint32_t accumulation_counter;
924
925 /* Accumulated throttler residencies */
926 uint32_t prochot_residency_acc;
927 uint32_t ppt_residency_acc;
928 uint32_t socket_thm_residency_acc;
929 uint32_t vr_thm_residency_acc;
930 uint32_t hbm_thm_residency_acc;
931
932 /* Clock Lock Status. Each bit corresponds to clock instance */
933 uint32_t gfxclk_lock_status;
934
935 /* Link width (number of lanes) and speed (in 0.1 GT/s) */
936 uint16_t pcie_link_width;
937 uint16_t pcie_link_speed;
938
939 /* XGMI bus width and bitrate (in Gbps) */
940 uint16_t xgmi_link_width;
941 uint16_t xgmi_link_speed;
942
943 /* Utilization Accumulated (%) */
944 uint32_t gfx_activity_acc;
945 uint32_t mem_activity_acc;
946
947 /*PCIE accumulated bandwidth (GB/sec) */
948 uint64_t pcie_bandwidth_acc;
949
950 /*PCIE instantaneous bandwidth (GB/sec) */
951 uint64_t pcie_bandwidth_inst;
952
953 /* PCIE L0 to recovery state transition accumulated count */
954 uint64_t pcie_l0_to_recov_count_acc;
955
956 /* PCIE replay accumulated count */
957 uint64_t pcie_replay_count_acc;
958
959 /* PCIE replay rollover accumulated count */
960 uint64_t pcie_replay_rover_count_acc;
961
962 /* PCIE NAK sent accumulated count */
963 uint32_t pcie_nak_sent_count_acc;
964
965 /* PCIE NAK received accumulated count */
966 uint32_t pcie_nak_rcvd_count_acc;
967
968 /* XGMI accumulated data transfer size(KiloBytes) */
969 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
970 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
971
972 /* PMFW attached timestamp (10ns resolution) */
973 uint64_t firmware_timestamp;
974
975 /* Current clocks (Mhz) */
976 uint16_t current_gfxclk[MAX_GFX_CLKS];
977 uint16_t current_socclk[MAX_CLKS];
978 uint16_t current_vclk0[MAX_CLKS];
979 uint16_t current_dclk0[MAX_CLKS];
980 uint16_t current_uclk;
981
982 /* Number of current partition */
983 uint16_t num_partition;
984
985 /* XCP metrics stats */
986 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP];
987
988 /* PCIE other end recovery counter */
989 uint32_t pcie_lc_perf_other_end_recovery;
990};
991
992struct gpu_metrics_v1_7 {
993 struct metrics_table_header common_header;
994
995 /* Temperature (Celsius) */
996 uint16_t temperature_hotspot;
997 uint16_t temperature_mem;
998 uint16_t temperature_vrsoc;
999
1000 /* Power (Watts) */
1001 uint16_t curr_socket_power;
1002
1003 /* Utilization (%) */
1004 uint16_t average_gfx_activity;
1005 uint16_t average_umc_activity; // memory controller
1006
1007 /* VRAM max bandwidthi (in GB/sec) at max memory clock */
1008 uint64_t mem_max_bandwidth;
1009
1010 /* Energy (15.259uJ (2^-16) units) */
1011 uint64_t energy_accumulator;
1012
1013 /* Driver attached timestamp (in ns) */
1014 uint64_t system_clock_counter;
1015
1016 /* Accumulation cycle counter */
1017 uint32_t accumulation_counter;
1018
1019 /* Accumulated throttler residencies */
1020 uint32_t prochot_residency_acc;
1021 uint32_t ppt_residency_acc;
1022 uint32_t socket_thm_residency_acc;
1023 uint32_t vr_thm_residency_acc;
1024 uint32_t hbm_thm_residency_acc;
1025
1026 /* Clock Lock Status. Each bit corresponds to clock instance */
1027 uint32_t gfxclk_lock_status;
1028
1029 /* Link width (number of lanes) and speed (in 0.1 GT/s) */
1030 uint16_t pcie_link_width;
1031 uint16_t pcie_link_speed;
1032
1033 /* XGMI bus width and bitrate (in Gbps) */
1034 uint16_t xgmi_link_width;
1035 uint16_t xgmi_link_speed;
1036
1037 /* Utilization Accumulated (%) */
1038 uint32_t gfx_activity_acc;
1039 uint32_t mem_activity_acc;
1040
1041 /*PCIE accumulated bandwidth (GB/sec) */
1042 uint64_t pcie_bandwidth_acc;
1043
1044 /*PCIE instantaneous bandwidth (GB/sec) */
1045 uint64_t pcie_bandwidth_inst;
1046
1047 /* PCIE L0 to recovery state transition accumulated count */
1048 uint64_t pcie_l0_to_recov_count_acc;
1049
1050 /* PCIE replay accumulated count */
1051 uint64_t pcie_replay_count_acc;
1052
1053 /* PCIE replay rollover accumulated count */
1054 uint64_t pcie_replay_rover_count_acc;
1055
1056 /* PCIE NAK sent accumulated count */
1057 uint32_t pcie_nak_sent_count_acc;
1058
1059 /* PCIE NAK received accumulated count */
1060 uint32_t pcie_nak_rcvd_count_acc;
1061
1062 /* XGMI accumulated data transfer size(KiloBytes) */
1063 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
1064 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
1065
1066 /* XGMI link status(active/inactive) */
1067 uint16_t xgmi_link_status[NUM_XGMI_LINKS];
1068
1069 uint16_t padding;
1070
1071 /* PMFW attached timestamp (10ns resolution) */
1072 uint64_t firmware_timestamp;
1073
1074 /* Current clocks (Mhz) */
1075 uint16_t current_gfxclk[MAX_GFX_CLKS];
1076 uint16_t current_socclk[MAX_CLKS];
1077 uint16_t current_vclk0[MAX_CLKS];
1078 uint16_t current_dclk0[MAX_CLKS];
1079 uint16_t current_uclk;
1080
1081 /* Number of current partition */
1082 uint16_t num_partition;
1083
1084 /* XCP metrics stats */
1085 struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP];
1086
1087 /* PCIE other end recovery counter */
1088 uint32_t pcie_lc_perf_other_end_recovery;
1089};
1090
1091/*
1092 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
1093 * Use gpu_metrics_v2_1 or later instead.
1094 */
1095struct gpu_metrics_v2_0 {
1096 struct metrics_table_header common_header;
1097
1098 /* Driver attached timestamp (in ns) */
1099 uint64_t system_clock_counter;
1100
1101 /* Temperature */
1102 uint16_t temperature_gfx; // gfx temperature on APUs
1103 uint16_t temperature_soc; // soc temperature on APUs
1104 uint16_t temperature_core[8]; // CPU core temperature on APUs
1105 uint16_t temperature_l3[2];
1106
1107 /* Utilization */
1108 uint16_t average_gfx_activity;
1109 uint16_t average_mm_activity; // UVD or VCN
1110
1111 /* Power/Energy */
1112 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1113 uint16_t average_cpu_power;
1114 uint16_t average_soc_power;
1115 uint16_t average_gfx_power;
1116 uint16_t average_core_power[8]; // CPU core power on APUs
1117
1118 /* Average clocks */
1119 uint16_t average_gfxclk_frequency;
1120 uint16_t average_socclk_frequency;
1121 uint16_t average_uclk_frequency;
1122 uint16_t average_fclk_frequency;
1123 uint16_t average_vclk_frequency;
1124 uint16_t average_dclk_frequency;
1125
1126 /* Current clocks */
1127 uint16_t current_gfxclk;
1128 uint16_t current_socclk;
1129 uint16_t current_uclk;
1130 uint16_t current_fclk;
1131 uint16_t current_vclk;
1132 uint16_t current_dclk;
1133 uint16_t current_coreclk[8]; // CPU core clocks
1134 uint16_t current_l3clk[2];
1135
1136 /* Throttle status */
1137 uint32_t throttle_status;
1138
1139 /* Fans */
1140 uint16_t fan_pwm;
1141
1142 uint16_t padding;
1143};
1144
1145struct gpu_metrics_v2_1 {
1146 struct metrics_table_header common_header;
1147
1148 /* Temperature */
1149 uint16_t temperature_gfx; // gfx temperature on APUs
1150 uint16_t temperature_soc; // soc temperature on APUs
1151 uint16_t temperature_core[8]; // CPU core temperature on APUs
1152 uint16_t temperature_l3[2];
1153
1154 /* Utilization */
1155 uint16_t average_gfx_activity;
1156 uint16_t average_mm_activity; // UVD or VCN
1157
1158 /* Driver attached timestamp (in ns) */
1159 uint64_t system_clock_counter;
1160
1161 /* Power/Energy */
1162 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1163 uint16_t average_cpu_power;
1164 uint16_t average_soc_power;
1165 uint16_t average_gfx_power;
1166 uint16_t average_core_power[8]; // CPU core power on APUs
1167
1168 /* Average clocks */
1169 uint16_t average_gfxclk_frequency;
1170 uint16_t average_socclk_frequency;
1171 uint16_t average_uclk_frequency;
1172 uint16_t average_fclk_frequency;
1173 uint16_t average_vclk_frequency;
1174 uint16_t average_dclk_frequency;
1175
1176 /* Current clocks */
1177 uint16_t current_gfxclk;
1178 uint16_t current_socclk;
1179 uint16_t current_uclk;
1180 uint16_t current_fclk;
1181 uint16_t current_vclk;
1182 uint16_t current_dclk;
1183 uint16_t current_coreclk[8]; // CPU core clocks
1184 uint16_t current_l3clk[2];
1185
1186 /* Throttle status */
1187 uint32_t throttle_status;
1188
1189 /* Fans */
1190 uint16_t fan_pwm;
1191
1192 uint16_t padding[3];
1193};
1194
1195struct gpu_metrics_v2_2 {
1196 struct metrics_table_header common_header;
1197
1198 /* Temperature */
1199 uint16_t temperature_gfx; // gfx temperature on APUs
1200 uint16_t temperature_soc; // soc temperature on APUs
1201 uint16_t temperature_core[8]; // CPU core temperature on APUs
1202 uint16_t temperature_l3[2];
1203
1204 /* Utilization */
1205 uint16_t average_gfx_activity;
1206 uint16_t average_mm_activity; // UVD or VCN
1207
1208 /* Driver attached timestamp (in ns) */
1209 uint64_t system_clock_counter;
1210
1211 /* Power/Energy */
1212 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1213 uint16_t average_cpu_power;
1214 uint16_t average_soc_power;
1215 uint16_t average_gfx_power;
1216 uint16_t average_core_power[8]; // CPU core power on APUs
1217
1218 /* Average clocks */
1219 uint16_t average_gfxclk_frequency;
1220 uint16_t average_socclk_frequency;
1221 uint16_t average_uclk_frequency;
1222 uint16_t average_fclk_frequency;
1223 uint16_t average_vclk_frequency;
1224 uint16_t average_dclk_frequency;
1225
1226 /* Current clocks */
1227 uint16_t current_gfxclk;
1228 uint16_t current_socclk;
1229 uint16_t current_uclk;
1230 uint16_t current_fclk;
1231 uint16_t current_vclk;
1232 uint16_t current_dclk;
1233 uint16_t current_coreclk[8]; // CPU core clocks
1234 uint16_t current_l3clk[2];
1235
1236 /* Throttle status (ASIC dependent) */
1237 uint32_t throttle_status;
1238
1239 /* Fans */
1240 uint16_t fan_pwm;
1241
1242 uint16_t padding[3];
1243
1244 /* Throttle status (ASIC independent) */
1245 uint64_t indep_throttle_status;
1246};
1247
1248struct gpu_metrics_v2_3 {
1249 struct metrics_table_header common_header;
1250
1251 /* Temperature */
1252 uint16_t temperature_gfx; // gfx temperature on APUs
1253 uint16_t temperature_soc; // soc temperature on APUs
1254 uint16_t temperature_core[8]; // CPU core temperature on APUs
1255 uint16_t temperature_l3[2];
1256
1257 /* Utilization */
1258 uint16_t average_gfx_activity;
1259 uint16_t average_mm_activity; // UVD or VCN
1260
1261 /* Driver attached timestamp (in ns) */
1262 uint64_t system_clock_counter;
1263
1264 /* Power/Energy */
1265 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1266 uint16_t average_cpu_power;
1267 uint16_t average_soc_power;
1268 uint16_t average_gfx_power;
1269 uint16_t average_core_power[8]; // CPU core power on APUs
1270
1271 /* Average clocks */
1272 uint16_t average_gfxclk_frequency;
1273 uint16_t average_socclk_frequency;
1274 uint16_t average_uclk_frequency;
1275 uint16_t average_fclk_frequency;
1276 uint16_t average_vclk_frequency;
1277 uint16_t average_dclk_frequency;
1278
1279 /* Current clocks */
1280 uint16_t current_gfxclk;
1281 uint16_t current_socclk;
1282 uint16_t current_uclk;
1283 uint16_t current_fclk;
1284 uint16_t current_vclk;
1285 uint16_t current_dclk;
1286 uint16_t current_coreclk[8]; // CPU core clocks
1287 uint16_t current_l3clk[2];
1288
1289 /* Throttle status (ASIC dependent) */
1290 uint32_t throttle_status;
1291
1292 /* Fans */
1293 uint16_t fan_pwm;
1294
1295 uint16_t padding[3];
1296
1297 /* Throttle status (ASIC independent) */
1298 uint64_t indep_throttle_status;
1299
1300 /* Average Temperature */
1301 uint16_t average_temperature_gfx; // average gfx temperature on APUs
1302 uint16_t average_temperature_soc; // average soc temperature on APUs
1303 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs
1304 uint16_t average_temperature_l3[2];
1305};
1306
1307struct gpu_metrics_v2_4 {
1308 struct metrics_table_header common_header;
1309
1310 /* Temperature (unit: centi-Celsius) */
1311 uint16_t temperature_gfx;
1312 uint16_t temperature_soc;
1313 uint16_t temperature_core[8];
1314 uint16_t temperature_l3[2];
1315
1316 /* Utilization (unit: centi) */
1317 uint16_t average_gfx_activity;
1318 uint16_t average_mm_activity;
1319
1320 /* Driver attached timestamp (in ns) */
1321 uint64_t system_clock_counter;
1322
1323 /* Power/Energy (unit: mW) */
1324 uint16_t average_socket_power;
1325 uint16_t average_cpu_power;
1326 uint16_t average_soc_power;
1327 uint16_t average_gfx_power;
1328 uint16_t average_core_power[8];
1329
1330 /* Average clocks (unit: MHz) */
1331 uint16_t average_gfxclk_frequency;
1332 uint16_t average_socclk_frequency;
1333 uint16_t average_uclk_frequency;
1334 uint16_t average_fclk_frequency;
1335 uint16_t average_vclk_frequency;
1336 uint16_t average_dclk_frequency;
1337
1338 /* Current clocks (unit: MHz) */
1339 uint16_t current_gfxclk;
1340 uint16_t current_socclk;
1341 uint16_t current_uclk;
1342 uint16_t current_fclk;
1343 uint16_t current_vclk;
1344 uint16_t current_dclk;
1345 uint16_t current_coreclk[8];
1346 uint16_t current_l3clk[2];
1347
1348 /* Throttle status (ASIC dependent) */
1349 uint32_t throttle_status;
1350
1351 /* Fans */
1352 uint16_t fan_pwm;
1353
1354 uint16_t padding[3];
1355
1356 /* Throttle status (ASIC independent) */
1357 uint64_t indep_throttle_status;
1358
1359 /* Average Temperature (unit: centi-Celsius) */
1360 uint16_t average_temperature_gfx;
1361 uint16_t average_temperature_soc;
1362 uint16_t average_temperature_core[8];
1363 uint16_t average_temperature_l3[2];
1364
1365 /* Power/Voltage (unit: mV) */
1366 uint16_t average_cpu_voltage;
1367 uint16_t average_soc_voltage;
1368 uint16_t average_gfx_voltage;
1369
1370 /* Power/Current (unit: mA) */
1371 uint16_t average_cpu_current;
1372 uint16_t average_soc_current;
1373 uint16_t average_gfx_current;
1374};
1375
1376struct gpu_metrics_v3_0 {
1377 struct metrics_table_header common_header;
1378
1379 /* Temperature */
1380 /* gfx temperature on APUs */
1381 uint16_t temperature_gfx;
1382 /* soc temperature on APUs */
1383 uint16_t temperature_soc;
1384 /* CPU core temperature on APUs */
1385 uint16_t temperature_core[16];
1386 /* skin temperature on APUs */
1387 uint16_t temperature_skin;
1388
1389 /* Utilization */
1390 /* time filtered GFX busy % [0-100] */
1391 uint16_t average_gfx_activity;
1392 /* time filtered VCN busy % [0-100] */
1393 uint16_t average_vcn_activity;
1394 /* time filtered IPU per-column busy % [0-100] */
1395 uint16_t average_ipu_activity[8];
1396 /* time filtered per-core C0 residency % [0-100]*/
1397 uint16_t average_core_c0_activity[16];
1398 /* time filtered DRAM read bandwidth [MB/sec] */
1399 uint16_t average_dram_reads;
1400 /* time filtered DRAM write bandwidth [MB/sec] */
1401 uint16_t average_dram_writes;
1402 /* time filtered IPU read bandwidth [MB/sec] */
1403 uint16_t average_ipu_reads;
1404 /* time filtered IPU write bandwidth [MB/sec] */
1405 uint16_t average_ipu_writes;
1406
1407 /* Driver attached timestamp (in ns) */
1408 uint64_t system_clock_counter;
1409
1410 /* Power/Energy */
1411 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */
1412 uint32_t average_socket_power;
1413 /* time filtered IPU power [mW] */
1414 uint16_t average_ipu_power;
1415 /* time filtered APU power [mW] */
1416 uint32_t average_apu_power;
1417 /* time filtered GFX power [mW] */
1418 uint32_t average_gfx_power;
1419 /* time filtered dGPU power [mW] */
1420 uint32_t average_dgpu_power;
1421 /* time filtered sum of core power across all cores in the socket [mW] */
1422 uint32_t average_all_core_power;
1423 /* calculated core power [mW] */
1424 uint16_t average_core_power[16];
1425 /* time filtered total system power [mW] */
1426 uint16_t average_sys_power;
1427 /* maximum IRM defined STAPM power limit [mW] */
1428 uint16_t stapm_power_limit;
1429 /* time filtered STAPM power limit [mW] */
1430 uint16_t current_stapm_power_limit;
1431
1432 /* time filtered clocks [MHz] */
1433 uint16_t average_gfxclk_frequency;
1434 uint16_t average_socclk_frequency;
1435 uint16_t average_vpeclk_frequency;
1436 uint16_t average_ipuclk_frequency;
1437 uint16_t average_fclk_frequency;
1438 uint16_t average_vclk_frequency;
1439 uint16_t average_uclk_frequency;
1440 uint16_t average_mpipu_frequency;
1441
1442 /* Current clocks */
1443 /* target core frequency [MHz] */
1444 uint16_t current_coreclk[16];
1445 /* CCLK frequency limit enforced on classic cores [MHz] */
1446 uint16_t current_core_maxfreq;
1447 /* GFXCLK frequency limit enforced on GFX [MHz] */
1448 uint16_t current_gfx_maxfreq;
1449
1450 /* Throttle Residency (ASIC dependent) */
1451 uint32_t throttle_residency_prochot;
1452 uint32_t throttle_residency_spl;
1453 uint32_t throttle_residency_fppt;
1454 uint32_t throttle_residency_sppt;
1455 uint32_t throttle_residency_thm_core;
1456 uint32_t throttle_residency_thm_gfx;
1457 uint32_t throttle_residency_thm_soc;
1458
1459 /* Metrics table alpha filter time constant [us] */
1460 uint32_t time_filter_alphavalue;
1461};
1462
1463struct amdgpu_pmmetrics_header {
1464 uint16_t structure_size;
1465 uint16_t pad;
1466 uint32_t mp1_ip_discovery_version;
1467 uint32_t pmfw_version;
1468 uint32_t pmmetrics_version;
1469};
1470
1471struct amdgpu_pm_metrics {
1472 struct amdgpu_pmmetrics_header common_header;
1473
1474 uint8_t data[];
1475};
1476
1477#endif