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1/****************************************************************************\
2*
3* File Name atomfirmware.h
4* Project This is an interface header file between atombios and OS GPU drivers for SoC15 products
5*
6* Description header file of general definitions for OS nd pre-OS video drivers
7*
8* Copyright 2014 Advanced Micro Devices, Inc.
9*
10* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
11* and associated documentation files (the "Software"), to deal in the Software without restriction,
12* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
13* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
14* subject to the following conditions:
15*
16* The above copyright notice and this permission notice shall be included in all copies or substantial
17* portions of the Software.
18*
19* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25* OTHER DEALINGS IN THE SOFTWARE.
26*
27\****************************************************************************/
28
29/*IMPORTANT NOTES
30* If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file.
31* If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file.
32* If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h.
33*/
34
35#ifndef _ATOMFIRMWARE_H_
36#define _ATOMFIRMWARE_H_
37
38enum atom_bios_header_version_def{
39 ATOM_MAJOR_VERSION =0x0003,
40 ATOM_MINOR_VERSION =0x0003,
41};
42
43#ifdef _H2INC
44 #ifndef uint32_t
45 typedef unsigned long uint32_t;
46 #endif
47
48 #ifndef uint16_t
49 typedef unsigned short uint16_t;
50 #endif
51
52 #ifndef uint8_t
53 typedef unsigned char uint8_t;
54 #endif
55#endif
56
57enum atom_crtc_def{
58 ATOM_CRTC1 =0,
59 ATOM_CRTC2 =1,
60 ATOM_CRTC3 =2,
61 ATOM_CRTC4 =3,
62 ATOM_CRTC5 =4,
63 ATOM_CRTC6 =5,
64 ATOM_CRTC_INVALID =0xff,
65};
66
67enum atom_ppll_def{
68 ATOM_PPLL0 =2,
69 ATOM_GCK_DFS =8,
70 ATOM_FCH_CLK =9,
71 ATOM_DP_DTO =11,
72 ATOM_COMBOPHY_PLL0 =20,
73 ATOM_COMBOPHY_PLL1 =21,
74 ATOM_COMBOPHY_PLL2 =22,
75 ATOM_COMBOPHY_PLL3 =23,
76 ATOM_COMBOPHY_PLL4 =24,
77 ATOM_COMBOPHY_PLL5 =25,
78 ATOM_PPLL_INVALID =0xff,
79};
80
81// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
82enum atom_dig_def{
83 ASIC_INT_DIG1_ENCODER_ID =0x03,
84 ASIC_INT_DIG2_ENCODER_ID =0x09,
85 ASIC_INT_DIG3_ENCODER_ID =0x0a,
86 ASIC_INT_DIG4_ENCODER_ID =0x0b,
87 ASIC_INT_DIG5_ENCODER_ID =0x0c,
88 ASIC_INT_DIG6_ENCODER_ID =0x0d,
89 ASIC_INT_DIG7_ENCODER_ID =0x0e,
90};
91
92//ucEncoderMode
93enum atom_encode_mode_def
94{
95 ATOM_ENCODER_MODE_DP =0,
96 ATOM_ENCODER_MODE_DP_SST =0,
97 ATOM_ENCODER_MODE_LVDS =1,
98 ATOM_ENCODER_MODE_DVI =2,
99 ATOM_ENCODER_MODE_HDMI =3,
100 ATOM_ENCODER_MODE_DP_AUDIO =5,
101 ATOM_ENCODER_MODE_DP_MST =5,
102 ATOM_ENCODER_MODE_CRT =15,
103 ATOM_ENCODER_MODE_DVO =16,
104};
105
106enum atom_encoder_refclk_src_def{
107 ENCODER_REFCLK_SRC_P1PLL =0,
108 ENCODER_REFCLK_SRC_P2PLL =1,
109 ENCODER_REFCLK_SRC_P3PLL =2,
110 ENCODER_REFCLK_SRC_EXTCLK =3,
111 ENCODER_REFCLK_SRC_INVALID =0xff,
112};
113
114enum atom_scaler_def{
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/
118};
119
120enum atom_operation_def{
121 ATOM_DISABLE = 0,
122 ATOM_ENABLE = 1,
123 ATOM_INIT = 7,
124 ATOM_GET_STATUS = 8,
125};
126
127enum atom_embedded_display_op_def{
128 ATOM_LCD_BL_OFF = 2,
129 ATOM_LCD_BL_OM = 3,
130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4,
131 ATOM_LCD_SELFTEST_START = 5,
132 ATOM_LCD_SELFTEST_STOP = 6,
133};
134
135enum atom_spread_spectrum_mode{
136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01,
137 ATOM_SS_DOWN_SPREAD_MODE = 0x00,
138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01,
139 ATOM_INT_OR_EXT_SS_MASK = 0x02,
140 ATOM_INTERNAL_SS_MASK = 0x00,
141 ATOM_EXTERNAL_SS_MASK = 0x02,
142};
143
144/* define panel bit per color */
145enum atom_panel_bit_per_color{
146 PANEL_BPC_UNDEFINE =0x00,
147 PANEL_6BIT_PER_COLOR =0x01,
148 PANEL_8BIT_PER_COLOR =0x02,
149 PANEL_10BIT_PER_COLOR =0x03,
150 PANEL_12BIT_PER_COLOR =0x04,
151 PANEL_16BIT_PER_COLOR =0x05,
152};
153
154//ucVoltageType
155enum atom_voltage_type
156{
157 VOLTAGE_TYPE_VDDC = 1,
158 VOLTAGE_TYPE_MVDDC = 2,
159 VOLTAGE_TYPE_MVDDQ = 3,
160 VOLTAGE_TYPE_VDDCI = 4,
161 VOLTAGE_TYPE_VDDGFX = 5,
162 VOLTAGE_TYPE_PCC = 6,
163 VOLTAGE_TYPE_MVPP = 7,
164 VOLTAGE_TYPE_LEDDPM = 8,
165 VOLTAGE_TYPE_PCC_MVDD = 9,
166 VOLTAGE_TYPE_PCIE_VDDC = 10,
167 VOLTAGE_TYPE_PCIE_VDDR = 11,
168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
178};
179
180enum atom_dgpu_vram_type {
181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60,
183 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70,
184};
185
186enum atom_dp_vs_preemph_def{
187 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
188 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
189 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
190 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
191 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
192 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
193 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
194 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
195 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
196 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
197};
198
199
200/*
201enum atom_string_def{
202asic_bus_type_pcie_string = "PCI_EXPRESS",
203atom_fire_gl_string = "FGL",
204atom_bios_string = "ATOM"
205};
206*/
207
208#pragma pack(1) /* BIOS data must use byte aligment*/
209
210enum atombios_image_offset{
211OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048,
212OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002,
213OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94,
214MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/
215OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f,
216OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e,
217};
218
219/****************************************************************************
220* Common header for all tables (Data table, Command function).
221* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.
222* And the pointer actually points to this header.
223****************************************************************************/
224
225struct atom_common_table_header
226{
227 uint16_t structuresize;
228 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible
229 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change
230};
231
232/****************************************************************************
233* Structure stores the ROM header.
234****************************************************************************/
235struct atom_rom_header_v2_2
236{
237 struct atom_common_table_header table_header;
238 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
239 uint16_t bios_segment_address;
240 uint16_t protectedmodeoffset;
241 uint16_t configfilenameoffset;
242 uint16_t crc_block_offset;
243 uint16_t vbios_bootupmessageoffset;
244 uint16_t int10_offset;
245 uint16_t pcibusdevinitcode;
246 uint16_t iobaseaddress;
247 uint16_t subsystem_vendor_id;
248 uint16_t subsystem_id;
249 uint16_t pci_info_offset;
250 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position
251 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position
252 uint16_t reserved;
253 uint32_t pspdirtableoffset;
254};
255
256/*==============================hw function portion======================================================================*/
257
258
259/****************************************************************************
260* Structures used in Command.mtb, each function name is not given here since those function could change from time to time
261* The real functionality of each function is associated with the parameter structure version when defined
262* For all internal cmd function definitions, please reference to atomstruct.h
263****************************************************************************/
264struct atom_master_list_of_command_functions_v2_1{
265 uint16_t asic_init; //Function
266 uint16_t cmd_function1; //used as an internal one
267 uint16_t cmd_function2; //used as an internal one
268 uint16_t cmd_function3; //used as an internal one
269 uint16_t digxencodercontrol; //Function
270 uint16_t cmd_function5; //used as an internal one
271 uint16_t cmd_function6; //used as an internal one
272 uint16_t cmd_function7; //used as an internal one
273 uint16_t cmd_function8; //used as an internal one
274 uint16_t cmd_function9; //used as an internal one
275 uint16_t setengineclock; //Function
276 uint16_t setmemoryclock; //Function
277 uint16_t setpixelclock; //Function
278 uint16_t enabledisppowergating; //Function
279 uint16_t cmd_function14; //used as an internal one
280 uint16_t cmd_function15; //used as an internal one
281 uint16_t cmd_function16; //used as an internal one
282 uint16_t cmd_function17; //used as an internal one
283 uint16_t cmd_function18; //used as an internal one
284 uint16_t cmd_function19; //used as an internal one
285 uint16_t cmd_function20; //used as an internal one
286 uint16_t cmd_function21; //used as an internal one
287 uint16_t cmd_function22; //used as an internal one
288 uint16_t cmd_function23; //used as an internal one
289 uint16_t cmd_function24; //used as an internal one
290 uint16_t cmd_function25; //used as an internal one
291 uint16_t cmd_function26; //used as an internal one
292 uint16_t cmd_function27; //used as an internal one
293 uint16_t cmd_function28; //used as an internal one
294 uint16_t cmd_function29; //used as an internal one
295 uint16_t cmd_function30; //used as an internal one
296 uint16_t cmd_function31; //used as an internal one
297 uint16_t cmd_function32; //used as an internal one
298 uint16_t cmd_function33; //used as an internal one
299 uint16_t blankcrtc; //Function
300 uint16_t enablecrtc; //Function
301 uint16_t cmd_function36; //used as an internal one
302 uint16_t cmd_function37; //used as an internal one
303 uint16_t cmd_function38; //used as an internal one
304 uint16_t cmd_function39; //used as an internal one
305 uint16_t cmd_function40; //used as an internal one
306 uint16_t getsmuclockinfo; //Function
307 uint16_t selectcrtc_source; //Function
308 uint16_t cmd_function43; //used as an internal one
309 uint16_t cmd_function44; //used as an internal one
310 uint16_t cmd_function45; //used as an internal one
311 uint16_t setdceclock; //Function
312 uint16_t getmemoryclock; //Function
313 uint16_t getengineclock; //Function
314 uint16_t setcrtc_usingdtdtiming; //Function
315 uint16_t externalencodercontrol; //Function
316 uint16_t cmd_function51; //used as an internal one
317 uint16_t cmd_function52; //used as an internal one
318 uint16_t cmd_function53; //used as an internal one
319 uint16_t processi2cchanneltransaction;//Function
320 uint16_t cmd_function55; //used as an internal one
321 uint16_t cmd_function56; //used as an internal one
322 uint16_t cmd_function57; //used as an internal one
323 uint16_t cmd_function58; //used as an internal one
324 uint16_t cmd_function59; //used as an internal one
325 uint16_t computegpuclockparam; //Function
326 uint16_t cmd_function61; //used as an internal one
327 uint16_t cmd_function62; //used as an internal one
328 uint16_t dynamicmemorysettings; //Function function
329 uint16_t memorytraining; //Function function
330 uint16_t cmd_function65; //used as an internal one
331 uint16_t cmd_function66; //used as an internal one
332 uint16_t setvoltage; //Function
333 uint16_t cmd_function68; //used as an internal one
334 uint16_t readefusevalue; //Function
335 uint16_t cmd_function70; //used as an internal one
336 uint16_t cmd_function71; //used as an internal one
337 uint16_t cmd_function72; //used as an internal one
338 uint16_t cmd_function73; //used as an internal one
339 uint16_t cmd_function74; //used as an internal one
340 uint16_t cmd_function75; //used as an internal one
341 uint16_t dig1transmittercontrol; //Function
342 uint16_t cmd_function77; //used as an internal one
343 uint16_t processauxchanneltransaction;//Function
344 uint16_t cmd_function79; //used as an internal one
345 uint16_t getvoltageinfo; //Function
346};
347
348struct atom_master_command_function_v2_1
349{
350 struct atom_common_table_header table_header;
351 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions;
352};
353
354/****************************************************************************
355* Structures used in every command function
356****************************************************************************/
357struct atom_function_attribute
358{
359 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
360 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
361 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util
362};
363
364
365/****************************************************************************
366* Common header for all hw functions.
367* Every function pointed by _master_list_of_hw_function has this common header.
368* And the pointer actually points to this header.
369****************************************************************************/
370struct atom_rom_hw_function_header
371{
372 struct atom_common_table_header func_header;
373 struct atom_function_attribute func_attrib;
374};
375
376
377/*==============================sw data table portion======================================================================*/
378/****************************************************************************
379* Structures used in data.mtb, each data table name is not given here since those data table could change from time to time
380* The real name of each table is given when its data structure version is defined
381****************************************************************************/
382struct atom_master_list_of_data_tables_v2_1{
383 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/
384 uint16_t multimedia_info;
385 uint16_t smc_dpm_info;
386 uint16_t sw_datatable3;
387 uint16_t firmwareinfo; /* Shared by various SW components */
388 uint16_t sw_datatable5;
389 uint16_t lcd_info; /* Shared by various SW components */
390 uint16_t sw_datatable7;
391 uint16_t smu_info;
392 uint16_t sw_datatable9;
393 uint16_t sw_datatable10;
394 uint16_t vram_usagebyfirmware; /* Shared by various SW components */
395 uint16_t gpio_pin_lut; /* Shared by various SW components */
396 uint16_t sw_datatable13;
397 uint16_t gfx_info;
398 uint16_t powerplayinfo; /* Shared by various SW components */
399 uint16_t sw_datatable16;
400 uint16_t sw_datatable17;
401 uint16_t sw_datatable18;
402 uint16_t sw_datatable19;
403 uint16_t sw_datatable20;
404 uint16_t sw_datatable21;
405 uint16_t displayobjectinfo; /* Shared by various SW components */
406 uint16_t indirectioaccess; /* used as an internal one */
407 uint16_t umc_info; /* Shared by various SW components */
408 uint16_t sw_datatable25;
409 uint16_t sw_datatable26;
410 uint16_t dce_info; /* Shared by various SW components */
411 uint16_t vram_info; /* Shared by various SW components */
412 uint16_t sw_datatable29;
413 uint16_t integratedsysteminfo; /* Shared by various SW components */
414 uint16_t asic_profiling_info; /* Shared by various SW components */
415 uint16_t voltageobject_info; /* shared by various SW components */
416 uint16_t sw_datatable33;
417 uint16_t sw_datatable34;
418};
419
420
421struct atom_master_data_table_v2_1
422{
423 struct atom_common_table_header table_header;
424 struct atom_master_list_of_data_tables_v2_1 listOfdatatables;
425};
426
427
428struct atom_dtd_format
429{
430 uint16_t pixclk;
431 uint16_t h_active;
432 uint16_t h_blanking_time;
433 uint16_t v_active;
434 uint16_t v_blanking_time;
435 uint16_t h_sync_offset;
436 uint16_t h_sync_width;
437 uint16_t v_sync_offset;
438 uint16_t v_syncwidth;
439 uint16_t reserved;
440 uint16_t reserved0;
441 uint8_t h_border;
442 uint8_t v_border;
443 uint16_t miscinfo;
444 uint8_t atom_mode_id;
445 uint8_t refreshrate;
446};
447
448/* atom_dtd_format.modemiscinfo defintion */
449enum atom_dtd_format_modemiscinfo{
450 ATOM_HSYNC_POLARITY = 0x0002,
451 ATOM_VSYNC_POLARITY = 0x0004,
452 ATOM_H_REPLICATIONBY2 = 0x0010,
453 ATOM_V_REPLICATIONBY2 = 0x0020,
454 ATOM_INTERLACE = 0x0080,
455 ATOM_COMPOSITESYNC = 0x0040,
456};
457
458
459/* utilitypipeline
460 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
461 * the location of it can't change
462*/
463
464
465/*
466 ***************************************************************************
467 Data Table firmwareinfo structure
468 ***************************************************************************
469*/
470
471struct atom_firmware_info_v3_1
472{
473 struct atom_common_table_header table_header;
474 uint32_t firmware_revision;
475 uint32_t bootup_sclk_in10khz;
476 uint32_t bootup_mclk_in10khz;
477 uint32_t firmware_capability; // enum atombios_firmware_capability
478 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
479 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
480 uint16_t bootup_vddc_mv;
481 uint16_t bootup_vddci_mv;
482 uint16_t bootup_mvddc_mv;
483 uint16_t bootup_vddgfx_mv;
484 uint8_t mem_module_id;
485 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
486 uint8_t reserved1[2];
487 uint32_t mc_baseaddr_high;
488 uint32_t mc_baseaddr_low;
489 uint32_t reserved2[6];
490};
491
492/* Total 32bit cap indication */
493enum atombios_firmware_capability
494{
495 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
496 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002,
497 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040,
498 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080,
499 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
500 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200,
501 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400,
502};
503
504enum atom_cooling_solution_id{
505 AIR_COOLING = 0x00,
506 LIQUID_COOLING = 0x01
507};
508
509struct atom_firmware_info_v3_2 {
510 struct atom_common_table_header table_header;
511 uint32_t firmware_revision;
512 uint32_t bootup_sclk_in10khz;
513 uint32_t bootup_mclk_in10khz;
514 uint32_t firmware_capability; // enum atombios_firmware_capability
515 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
516 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
517 uint16_t bootup_vddc_mv;
518 uint16_t bootup_vddci_mv;
519 uint16_t bootup_mvddc_mv;
520 uint16_t bootup_vddgfx_mv;
521 uint8_t mem_module_id;
522 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
523 uint8_t reserved1[2];
524 uint32_t mc_baseaddr_high;
525 uint32_t mc_baseaddr_low;
526 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
527 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
528 uint8_t board_i2c_feature_slave_addr;
529 uint8_t reserved3;
530 uint16_t bootup_mvddq_mv;
531 uint16_t bootup_mvpp_mv;
532 uint32_t zfbstartaddrin16mb;
533 uint32_t reserved2[3];
534};
535
536struct atom_firmware_info_v3_3
537{
538 struct atom_common_table_header table_header;
539 uint32_t firmware_revision;
540 uint32_t bootup_sclk_in10khz;
541 uint32_t bootup_mclk_in10khz;
542 uint32_t firmware_capability; // enum atombios_firmware_capability
543 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
544 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
545 uint16_t bootup_vddc_mv;
546 uint16_t bootup_vddci_mv;
547 uint16_t bootup_mvddc_mv;
548 uint16_t bootup_vddgfx_mv;
549 uint8_t mem_module_id;
550 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
551 uint8_t reserved1[2];
552 uint32_t mc_baseaddr_high;
553 uint32_t mc_baseaddr_low;
554 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
555 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
556 uint8_t board_i2c_feature_slave_addr;
557 uint8_t reserved3;
558 uint16_t bootup_mvddq_mv;
559 uint16_t bootup_mvpp_mv;
560 uint32_t zfbstartaddrin16mb;
561 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
562 uint32_t reserved2[2];
563};
564
565struct atom_firmware_info_v3_4 {
566 struct atom_common_table_header table_header;
567 uint32_t firmware_revision;
568 uint32_t bootup_sclk_in10khz;
569 uint32_t bootup_mclk_in10khz;
570 uint32_t firmware_capability; // enum atombios_firmware_capability
571 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
572 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
573 uint16_t bootup_vddc_mv;
574 uint16_t bootup_vddci_mv;
575 uint16_t bootup_mvddc_mv;
576 uint16_t bootup_vddgfx_mv;
577 uint8_t mem_module_id;
578 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
579 uint8_t reserved1[2];
580 uint32_t mc_baseaddr_high;
581 uint32_t mc_baseaddr_low;
582 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
583 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
584 uint8_t board_i2c_feature_slave_addr;
585 uint8_t reserved3;
586 uint16_t bootup_mvddq_mv;
587 uint16_t bootup_mvpp_mv;
588 uint32_t zfbstartaddrin16mb;
589 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
590 uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2)
591 uint16_t hw_bootup_vddgfx_mv; // hw default vddgfx voltage level decide by board strap
592 uint16_t hw_bootup_vddc_mv; // hw default vddc voltage level decide by board strap
593 uint16_t hw_bootup_mvddc_mv; // hw default mvddc voltage level decide by board strap
594 uint16_t hw_bootup_vddci_mv; // hw default vddci voltage level decide by board strap
595 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
596 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
597 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb.
598 uint32_t reserved[5];
599};
600
601/*
602 ***************************************************************************
603 Data Table lcd_info structure
604 ***************************************************************************
605*/
606
607struct lcd_info_v2_1
608{
609 struct atom_common_table_header table_header;
610 struct atom_dtd_format lcd_timing;
611 uint16_t backlight_pwm;
612 uint16_t special_handle_cap;
613 uint16_t panel_misc;
614 uint16_t lvds_max_slink_pclk;
615 uint16_t lvds_ss_percentage;
616 uint16_t lvds_ss_rate_10hz;
617 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
618 uint8_t pwr_on_de_to_vary_bl;
619 uint8_t pwr_down_vary_bloff_to_de;
620 uint8_t pwr_down_de_to_digoff;
621 uint8_t pwr_off_delay;
622 uint8_t pwr_on_vary_bl_to_blon;
623 uint8_t pwr_down_bloff_to_vary_bloff;
624 uint8_t panel_bpc;
625 uint8_t dpcd_edp_config_cap;
626 uint8_t dpcd_max_link_rate;
627 uint8_t dpcd_max_lane_count;
628 uint8_t dpcd_max_downspread;
629 uint8_t min_allowed_bl_level;
630 uint8_t max_allowed_bl_level;
631 uint8_t bootup_bl_level;
632 uint8_t dplvdsrxid;
633 uint32_t reserved1[8];
634};
635
636/* lcd_info_v2_1.panel_misc defintion */
637enum atom_lcd_info_panel_misc{
638 ATOM_PANEL_MISC_FPDI =0x0002,
639};
640
641//uceDPToLVDSRxId
642enum atom_lcd_info_dptolvds_rx_id
643{
644 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
645 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init
646 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init
647};
648
649
650/*
651 ***************************************************************************
652 Data Table gpio_pin_lut structure
653 ***************************************************************************
654*/
655
656struct atom_gpio_pin_assignment
657{
658 uint32_t data_a_reg_index;
659 uint8_t gpio_bitshift;
660 uint8_t gpio_mask_bitshift;
661 uint8_t gpio_id;
662 uint8_t reserved;
663};
664
665/* atom_gpio_pin_assignment.gpio_id definition */
666enum atom_gpio_pin_assignment_gpio_id {
667 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */
668 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */
669 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */
670
671 /* gpio_id pre-define id for multiple usage */
672 /* GPIO use to control PCIE_VDDC in certain SLT board */
673 PCIE_VDDC_CONTROL_GPIO_PINID = 56,
674 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */
675 PP_AC_DC_SWITCH_GPIO_PINID = 60,
676 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */
677 VDDC_VRHOT_GPIO_PINID = 61,
678 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */
679 VDDC_PCC_GPIO_PINID = 62,
680 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */
681 EFUSE_CUT_ENABLE_GPIO_PINID = 63,
682 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */
683 DRAM_SELF_REFRESH_GPIO_PINID = 64,
684 /* Thermal interrupt output->system thermal chip GPIO pin */
685 THERMAL_INT_OUTPUT_GPIO_PINID =65,
686};
687
688
689struct atom_gpio_pin_lut_v2_1
690{
691 struct atom_common_table_header table_header;
692 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */
693 struct atom_gpio_pin_assignment gpio_pin[8];
694};
695
696
697/*
698 ***************************************************************************
699 Data Table vram_usagebyfirmware structure
700 ***************************************************************************
701*/
702
703struct vram_usagebyfirmware_v2_1
704{
705 struct atom_common_table_header table_header;
706 uint32_t start_address_in_kb;
707 uint16_t used_by_firmware_in_kb;
708 uint16_t used_by_driver_in_kb;
709};
710
711
712/*
713 ***************************************************************************
714 Data Table displayobjectinfo structure
715 ***************************************************************************
716*/
717
718enum atom_object_record_type_id
719{
720 ATOM_I2C_RECORD_TYPE =1,
721 ATOM_HPD_INT_RECORD_TYPE =2,
722 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9,
723 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16,
724 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17,
725 ATOM_ENCODER_CAP_RECORD_TYPE=20,
726 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21,
727 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22,
728 ATOM_RECORD_END_TYPE =0xFF,
729};
730
731struct atom_common_record_header
732{
733 uint8_t record_type; //An emun to indicate the record type
734 uint8_t record_size; //The size of the whole record in byte
735};
736
737struct atom_i2c_record
738{
739 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE
740 uint8_t i2c_id;
741 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC
742};
743
744struct atom_hpd_int_record
745{
746 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE
747 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info
748 uint8_t plugin_pin_state;
749};
750
751// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
752enum atom_encoder_caps_def
753{
754 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
755 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not.
756 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
757 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not.
758 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board.
759 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type.
760};
761
762struct atom_encoder_caps_record
763{
764 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE
765 uint32_t encodercaps;
766};
767
768enum atom_connector_caps_def
769{
770 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display
771 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq
772};
773
774struct atom_disp_connector_caps_record
775{
776 struct atom_common_record_header record_header;
777 uint32_t connectcaps;
778};
779
780//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
781struct atom_gpio_pin_control_pair
782{
783 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
784 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
785};
786
787struct atom_object_gpio_cntl_record
788{
789 struct atom_common_record_header record_header;
790 uint8_t flag; // Future expnadibility
791 uint8_t number_of_pins; // Number of GPIO pins used to control the object
792 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
793};
794
795//Definitions for GPIO pin state
796enum atom_gpio_pin_control_pinstate_def
797{
798 GPIO_PIN_TYPE_INPUT = 0x00,
799 GPIO_PIN_TYPE_OUTPUT = 0x10,
800 GPIO_PIN_TYPE_HW_CONTROL = 0x20,
801
802//For GPIO_PIN_TYPE_OUTPUT the following is defined
803 GPIO_PIN_OUTPUT_STATE_MASK = 0x01,
804 GPIO_PIN_OUTPUT_STATE_SHIFT = 0,
805 GPIO_PIN_STATE_ACTIVE_LOW = 0x0,
806 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1,
807};
808
809// Indexes to GPIO array in GLSync record
810// GLSync record is for Frame Lock/Gen Lock feature.
811enum atom_glsync_record_gpio_index_def
812{
813 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0,
814 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1,
815 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2,
816 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3,
817 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4,
818 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5,
819 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6,
820 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7,
821 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8,
822 ATOM_GPIO_INDEX_GLSYNC_MAX = 9,
823};
824
825
826struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
827{
828 struct atom_common_record_header record_header;
829 uint8_t hpd_pin_map[8];
830};
831
832struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
833{
834 struct atom_common_record_header record_header;
835 uint8_t aux_ddc_map[8];
836};
837
838struct atom_connector_forced_tmds_cap_record
839{
840 struct atom_common_record_header record_header;
841 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
842 uint8_t maxtmdsclkrate_in2_5mhz;
843 uint8_t reserved;
844};
845
846struct atom_connector_layout_info
847{
848 uint16_t connectorobjid;
849 uint8_t connector_type;
850 uint8_t position;
851};
852
853// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
854enum atom_connector_layout_info_connector_type_def
855{
856 CONNECTOR_TYPE_DVI_D = 1,
857
858 CONNECTOR_TYPE_HDMI = 4,
859 CONNECTOR_TYPE_DISPLAY_PORT = 5,
860 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6,
861};
862
863struct atom_bracket_layout_record
864{
865 struct atom_common_record_header record_header;
866 uint8_t bracketlen;
867 uint8_t bracketwidth;
868 uint8_t conn_num;
869 uint8_t reserved;
870 struct atom_connector_layout_info conn_info[1];
871};
872
873enum atom_display_device_tag_def{
874 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
875 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008,
876 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080,
877 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200,
878 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400,
879 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800,
880 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040,
881 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8,
882};
883
884struct atom_display_object_path_v2
885{
886 uint16_t display_objid; //Connector Object ID or Misc Object ID
887 uint16_t disp_recordoffset;
888 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder
889 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view;
890 uint16_t encoder_recordoffset;
891 uint16_t extencoder_recordoffset;
892 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first
893 uint8_t priority_id;
894 uint8_t reserved;
895};
896
897struct display_object_info_table_v1_4
898{
899 struct atom_common_table_header table_header;
900 uint16_t supporteddevices;
901 uint8_t number_of_path;
902 uint8_t reserved;
903 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
904};
905
906
907/*
908 ***************************************************************************
909 Data Table dce_info structure
910 ***************************************************************************
911*/
912struct atom_display_controller_info_v4_1
913{
914 struct atom_common_table_header table_header;
915 uint32_t display_caps;
916 uint32_t bootup_dispclk_10khz;
917 uint16_t dce_refclk_10khz;
918 uint16_t i2c_engine_refclk_10khz;
919 uint16_t dvi_ss_percentage; // in unit of 0.001%
920 uint16_t dvi_ss_rate_10hz;
921 uint16_t hdmi_ss_percentage; // in unit of 0.001%
922 uint16_t hdmi_ss_rate_10hz;
923 uint16_t dp_ss_percentage; // in unit of 0.001%
924 uint16_t dp_ss_rate_10hz;
925 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
926 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
927 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
928 uint8_t ss_reserved;
929 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
930 uint8_t reserved1[3];
931 uint16_t dpphy_refclk_10khz;
932 uint16_t reserved2;
933 uint8_t dceip_min_ver;
934 uint8_t dceip_max_ver;
935 uint8_t max_disp_pipe_num;
936 uint8_t max_vbios_active_disp_pipe_num;
937 uint8_t max_ppll_num;
938 uint8_t max_disp_phy_num;
939 uint8_t max_aux_pairs;
940 uint8_t remotedisplayconfig;
941 uint8_t reserved3[8];
942};
943
944struct atom_display_controller_info_v4_2
945{
946 struct atom_common_table_header table_header;
947 uint32_t display_caps;
948 uint32_t bootup_dispclk_10khz;
949 uint16_t dce_refclk_10khz;
950 uint16_t i2c_engine_refclk_10khz;
951 uint16_t dvi_ss_percentage; // in unit of 0.001%
952 uint16_t dvi_ss_rate_10hz;
953 uint16_t hdmi_ss_percentage; // in unit of 0.001%
954 uint16_t hdmi_ss_rate_10hz;
955 uint16_t dp_ss_percentage; // in unit of 0.001%
956 uint16_t dp_ss_rate_10hz;
957 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
958 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
959 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
960 uint8_t ss_reserved;
961 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
962 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
963 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
964 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
965 uint16_t dpphy_refclk_10khz;
966 uint16_t reserved2;
967 uint8_t dcnip_min_ver;
968 uint8_t dcnip_max_ver;
969 uint8_t max_disp_pipe_num;
970 uint8_t max_vbios_active_disp_pipe_num;
971 uint8_t max_ppll_num;
972 uint8_t max_disp_phy_num;
973 uint8_t max_aux_pairs;
974 uint8_t remotedisplayconfig;
975 uint8_t reserved3[8];
976};
977
978struct atom_display_controller_info_v4_4 {
979 struct atom_common_table_header table_header;
980 uint32_t display_caps;
981 uint32_t bootup_dispclk_10khz;
982 uint16_t dce_refclk_10khz;
983 uint16_t i2c_engine_refclk_10khz;
984 uint16_t dvi_ss_percentage; // in unit of 0.001%
985 uint16_t dvi_ss_rate_10hz;
986 uint16_t hdmi_ss_percentage; // in unit of 0.001%
987 uint16_t hdmi_ss_rate_10hz;
988 uint16_t dp_ss_percentage; // in unit of 0.001%
989 uint16_t dp_ss_rate_10hz;
990 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
991 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
992 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
993 uint8_t ss_reserved;
994 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
995 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
996 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
997 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
998 uint16_t dpphy_refclk_10khz;
999 uint16_t hw_chip_id;
1000 uint8_t dcnip_min_ver;
1001 uint8_t dcnip_max_ver;
1002 uint8_t max_disp_pipe_num;
1003 uint8_t max_vbios_active_disp_pipum;
1004 uint8_t max_ppll_num;
1005 uint8_t max_disp_phy_num;
1006 uint8_t max_aux_pairs;
1007 uint8_t remotedisplayconfig;
1008 uint32_t dispclk_pll_vco_freq;
1009 uint32_t dp_ref_clk_freq;
1010 uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us)
1011 uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us)
1012 uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us)
1013 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx
1014 uint16_t dc_golden_table_ver;
1015 uint32_t reserved3[3];
1016};
1017
1018struct atom_dc_golden_table_v1
1019{
1020 uint32_t aux_dphy_rx_control0_val;
1021 uint32_t aux_dphy_tx_control_val;
1022 uint32_t aux_dphy_rx_control1_val;
1023 uint32_t dc_gpio_aux_ctrl_0_val;
1024 uint32_t dc_gpio_aux_ctrl_1_val;
1025 uint32_t dc_gpio_aux_ctrl_2_val;
1026 uint32_t dc_gpio_aux_ctrl_3_val;
1027 uint32_t dc_gpio_aux_ctrl_4_val;
1028 uint32_t dc_gpio_aux_ctrl_5_val;
1029 uint32_t reserved[23];
1030};
1031
1032enum dce_info_caps_def
1033{
1034 // only for VBIOS
1035 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02,
1036 // only for VBIOS
1037 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04,
1038 // only for VBIOS
1039 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08,
1040
1041};
1042
1043/*
1044 ***************************************************************************
1045 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure
1046 ***************************************************************************
1047*/
1048struct atom_ext_display_path
1049{
1050 uint16_t device_tag; //A bit vector to show what devices are supported
1051 uint16_t device_acpi_enum; //16bit device ACPI id.
1052 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions
1053 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
1054 uint8_t hpdlut_index; //An index into external HPD pin LUT
1055 uint16_t ext_encoder_objid; //external encoder object id
1056 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping
1057 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
1058 uint16_t caps;
1059 uint16_t reserved;
1060};
1061
1062//usCaps
1063enum ext_display_path_cap_def {
1064 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE = 0x0001,
1065 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = 0x0002,
1066 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007C,
1067 EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x01 << 2), //PI redriver chip
1068 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip
1069 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip
1070};
1071
1072struct atom_external_display_connection_info
1073{
1074 struct atom_common_table_header table_header;
1075 uint8_t guid[16]; // a GUID is a 16 byte long string
1076 struct atom_ext_display_path path[7]; // total of fixed 7 entries.
1077 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0.
1078 uint8_t stereopinid; // use for eDP panel
1079 uint8_t remotedisplayconfig;
1080 uint8_t edptolvdsrxid;
1081 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value
1082 uint8_t reserved[3]; // for potential expansion
1083};
1084
1085/*
1086 ***************************************************************************
1087 Data Table integratedsysteminfo structure
1088 ***************************************************************************
1089*/
1090
1091struct atom_camera_dphy_timing_param
1092{
1093 uint8_t profile_id; // SENSOR_PROFILES
1094 uint32_t param;
1095};
1096
1097struct atom_camera_dphy_elec_param
1098{
1099 uint16_t param[3];
1100};
1101
1102struct atom_camera_module_info
1103{
1104 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
1105 uint8_t module_name[8];
1106 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor
1107};
1108
1109struct atom_camera_flashlight_info
1110{
1111 uint8_t flashlight_id; // 0: Rear, 1: Front
1112 uint8_t name[8];
1113};
1114
1115struct atom_camera_data
1116{
1117 uint32_t versionCode;
1118 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max
1119 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max
1120 struct atom_camera_dphy_elec_param dphy_param;
1121 uint32_t crc_val; // CRC
1122};
1123
1124
1125struct atom_14nm_dpphy_dvihdmi_tuningset
1126{
1127 uint32_t max_symclk_in10khz;
1128 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1129 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1130 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1131 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1132 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1133 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1134 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1135};
1136
1137struct atom_14nm_dpphy_dp_setting{
1138 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1139 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1140 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1141 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1142};
1143
1144struct atom_14nm_dpphy_dp_tuningset{
1145 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1146 uint8_t version;
1147 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset
1148 uint16_t reserved;
1149 struct atom_14nm_dpphy_dp_setting dptuning[10];
1150};
1151
1152struct atom_14nm_dig_transmitter_info_header_v4_0{
1153 struct atom_common_table_header table_header;
1154 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl
1155 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl
1156 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl
1157};
1158
1159struct atom_14nm_combphy_tmds_vs_set
1160{
1161 uint8_t sym_clk;
1162 uint8_t dig_mode;
1163 uint8_t phy_sel;
1164 uint16_t common_mar_deemph_nom__margin_deemph_val;
1165 uint8_t common_seldeemph60__deemph_6db_4_val;
1166 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1167 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1168 uint8_t margin_deemph_lane0__deemph_sel_val;
1169};
1170
1171struct atom_DCN_dpphy_dvihdmi_tuningset
1172{
1173 uint32_t max_symclk_in10khz;
1174 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1175 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1176 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1177 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1178 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1179 uint8_t reserved1;
1180 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1181 uint8_t reserved2;
1182};
1183
1184struct atom_DCN_dpphy_dp_setting{
1185 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1186 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1187 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1188 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1189 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1190};
1191
1192struct atom_DCN_dpphy_dp_tuningset{
1193 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1194 uint8_t version;
1195 uint16_t table_size; // size of atom_14nm_dpphy_dp_setting
1196 uint16_t reserved;
1197 struct atom_DCN_dpphy_dp_setting dptunings[10];
1198};
1199
1200struct atom_i2c_reg_info {
1201 uint8_t ucI2cRegIndex;
1202 uint8_t ucI2cRegVal;
1203};
1204
1205struct atom_hdmi_retimer_redriver_set {
1206 uint8_t HdmiSlvAddr;
1207 uint8_t HdmiRegNum;
1208 uint8_t Hdmi6GRegNum;
1209 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use
1210 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use.
1211};
1212
1213struct atom_integrated_system_info_v1_11
1214{
1215 struct atom_common_table_header table_header;
1216 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1217 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1218 uint32_t system_config;
1219 uint32_t cpucapinfo;
1220 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1221 uint16_t gpuclk_ss_type;
1222 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1%
1223 uint16_t lvds_ss_rate_10hz;
1224 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1225 uint16_t hdmi_ss_rate_10hz;
1226 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1227 uint16_t dvi_ss_rate_10hz;
1228 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1229 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def
1230 uint16_t backlight_pwm_hz; // pwm frequency in hz
1231 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1232 uint8_t umachannelnumber; // number of memory channels
1233 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1234 uint8_t pwr_on_de_to_vary_bl;
1235 uint8_t pwr_down_vary_bloff_to_de;
1236 uint8_t pwr_down_de_to_digoff;
1237 uint8_t pwr_off_delay;
1238 uint8_t pwr_on_vary_bl_to_blon;
1239 uint8_t pwr_down_bloff_to_vary_bloff;
1240 uint8_t min_allowed_bl_level;
1241 uint8_t htc_hyst_limit;
1242 uint8_t htc_tmp_limit;
1243 uint8_t reserved1;
1244 uint8_t reserved2;
1245 struct atom_external_display_connection_info extdispconninfo;
1246 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset;
1247 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset;
1248 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset;
1249 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set
1250 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set
1251 struct atom_camera_data camera_info;
1252 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
1253 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
1254 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1255 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
1256 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set
1257 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set
1258 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set
1259 uint32_t reserved[66];
1260};
1261
1262struct atom_integrated_system_info_v1_12
1263{
1264 struct atom_common_table_header table_header;
1265 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1266 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1267 uint32_t system_config;
1268 uint32_t cpucapinfo;
1269 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1270 uint16_t gpuclk_ss_type;
1271 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1%
1272 uint16_t lvds_ss_rate_10hz;
1273 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1274 uint16_t hdmi_ss_rate_10hz;
1275 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1276 uint16_t dvi_ss_rate_10hz;
1277 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1278 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def
1279 uint16_t backlight_pwm_hz; // pwm frequency in hz
1280 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1281 uint8_t umachannelnumber; // number of memory channels
1282 uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms //
1283 uint8_t pwr_on_de_to_vary_bl;
1284 uint8_t pwr_down_vary_bloff_to_de;
1285 uint8_t pwr_down_de_to_digoff;
1286 uint8_t pwr_off_delay;
1287 uint8_t pwr_on_vary_bl_to_blon;
1288 uint8_t pwr_down_bloff_to_vary_bloff;
1289 uint8_t min_allowed_bl_level;
1290 uint8_t htc_hyst_limit;
1291 uint8_t htc_tmp_limit;
1292 uint8_t reserved1;
1293 uint8_t reserved2;
1294 struct atom_external_display_connection_info extdispconninfo;
1295 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset;
1296 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset;
1297 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset;
1298 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set
1299 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set
1300 struct atom_camera_data camera_info;
1301 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
1302 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
1303 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1304 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
1305 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set
1306 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set
1307 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set
1308 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset;
1309 uint32_t reserved[63];
1310};
1311
1312// system_config
1313enum atom_system_vbiosmisc_def{
1314 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1315};
1316
1317
1318// gpucapinfo
1319enum atom_system_gpucapinf_def{
1320 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10,
1321};
1322
1323//dpphy_override
1324enum atom_sysinfo_dpphy_override_def{
1325 ATOM_ENABLE_DVI_TUNINGSET = 0x01,
1326 ATOM_ENABLE_HDMI_TUNINGSET = 0x02,
1327 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04,
1328 ATOM_ENABLE_DP_TUNINGSET = 0x08,
1329 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10,
1330};
1331
1332//lvds_misc
1333enum atom_sys_info_lvds_misc_def
1334{
1335 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01,
1336 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04,
1337 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08,
1338};
1339
1340
1341//memorytype DMI Type 17 offset 12h - Memory Type
1342enum atom_dmi_t17_mem_type_def{
1343 OtherMemType = 0x01, ///< Assign 01 to Other
1344 UnknownMemType, ///< Assign 02 to Unknown
1345 DramMemType, ///< Assign 03 to DRAM
1346 EdramMemType, ///< Assign 04 to EDRAM
1347 VramMemType, ///< Assign 05 to VRAM
1348 SramMemType, ///< Assign 06 to SRAM
1349 RamMemType, ///< Assign 07 to RAM
1350 RomMemType, ///< Assign 08 to ROM
1351 FlashMemType, ///< Assign 09 to Flash
1352 EepromMemType, ///< Assign 10 to EEPROM
1353 FepromMemType, ///< Assign 11 to FEPROM
1354 EpromMemType, ///< Assign 12 to EPROM
1355 CdramMemType, ///< Assign 13 to CDRAM
1356 ThreeDramMemType, ///< Assign 14 to 3DRAM
1357 SdramMemType, ///< Assign 15 to SDRAM
1358 SgramMemType, ///< Assign 16 to SGRAM
1359 RdramMemType, ///< Assign 17 to RDRAM
1360 DdrMemType, ///< Assign 18 to DDR
1361 Ddr2MemType, ///< Assign 19 to DDR2
1362 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
1363 Ddr3MemType = 0x18, ///< Assign 24 to DDR3
1364 Fbd2MemType, ///< Assign 25 to FBD2
1365 Ddr4MemType, ///< Assign 26 to DDR4
1366 LpDdrMemType, ///< Assign 27 to LPDDR
1367 LpDdr2MemType, ///< Assign 28 to LPDDR2
1368 LpDdr3MemType, ///< Assign 29 to LPDDR3
1369 LpDdr4MemType, ///< Assign 30 to LPDDR4
1370};
1371
1372
1373// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable
1374struct atom_fusion_system_info_v4
1375{
1376 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
1377 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable
1378};
1379
1380
1381/*
1382 ***************************************************************************
1383 Data Table gfx_info structure
1384 ***************************************************************************
1385*/
1386
1387struct atom_gfx_info_v2_2
1388{
1389 struct atom_common_table_header table_header;
1390 uint8_t gfxip_min_ver;
1391 uint8_t gfxip_max_ver;
1392 uint8_t max_shader_engines;
1393 uint8_t max_tile_pipes;
1394 uint8_t max_cu_per_sh;
1395 uint8_t max_sh_per_se;
1396 uint8_t max_backends_per_se;
1397 uint8_t max_texture_channel_caches;
1398 uint32_t regaddr_cp_dma_src_addr;
1399 uint32_t regaddr_cp_dma_src_addr_hi;
1400 uint32_t regaddr_cp_dma_dst_addr;
1401 uint32_t regaddr_cp_dma_dst_addr_hi;
1402 uint32_t regaddr_cp_dma_command;
1403 uint32_t regaddr_cp_status;
1404 uint32_t regaddr_rlc_gpu_clock_32;
1405 uint32_t rlc_gpu_timer_refclk;
1406};
1407
1408struct atom_gfx_info_v2_3 {
1409 struct atom_common_table_header table_header;
1410 uint8_t gfxip_min_ver;
1411 uint8_t gfxip_max_ver;
1412 uint8_t max_shader_engines;
1413 uint8_t max_tile_pipes;
1414 uint8_t max_cu_per_sh;
1415 uint8_t max_sh_per_se;
1416 uint8_t max_backends_per_se;
1417 uint8_t max_texture_channel_caches;
1418 uint32_t regaddr_cp_dma_src_addr;
1419 uint32_t regaddr_cp_dma_src_addr_hi;
1420 uint32_t regaddr_cp_dma_dst_addr;
1421 uint32_t regaddr_cp_dma_dst_addr_hi;
1422 uint32_t regaddr_cp_dma_command;
1423 uint32_t regaddr_cp_status;
1424 uint32_t regaddr_rlc_gpu_clock_32;
1425 uint32_t rlc_gpu_timer_refclk;
1426 uint8_t active_cu_per_sh;
1427 uint8_t active_rb_per_se;
1428 uint16_t gcgoldenoffset;
1429 uint32_t rm21_sram_vmin_value;
1430};
1431
1432struct atom_gfx_info_v2_4
1433{
1434 struct atom_common_table_header table_header;
1435 uint8_t gfxip_min_ver;
1436 uint8_t gfxip_max_ver;
1437 uint8_t max_shader_engines;
1438 uint8_t reserved;
1439 uint8_t max_cu_per_sh;
1440 uint8_t max_sh_per_se;
1441 uint8_t max_backends_per_se;
1442 uint8_t max_texture_channel_caches;
1443 uint32_t regaddr_cp_dma_src_addr;
1444 uint32_t regaddr_cp_dma_src_addr_hi;
1445 uint32_t regaddr_cp_dma_dst_addr;
1446 uint32_t regaddr_cp_dma_dst_addr_hi;
1447 uint32_t regaddr_cp_dma_command;
1448 uint32_t regaddr_cp_status;
1449 uint32_t regaddr_rlc_gpu_clock_32;
1450 uint32_t rlc_gpu_timer_refclk;
1451 uint8_t active_cu_per_sh;
1452 uint8_t active_rb_per_se;
1453 uint16_t gcgoldenoffset;
1454 uint16_t gc_num_gprs;
1455 uint16_t gc_gsprim_buff_depth;
1456 uint16_t gc_parameter_cache_depth;
1457 uint16_t gc_wave_size;
1458 uint16_t gc_max_waves_per_simd;
1459 uint16_t gc_lds_size;
1460 uint8_t gc_num_max_gs_thds;
1461 uint8_t gc_gs_table_depth;
1462 uint8_t gc_double_offchip_lds_buffer;
1463 uint8_t gc_max_scratch_slots_per_cu;
1464 uint32_t sram_rm_fuses_val;
1465 uint32_t sram_custom_rm_fuses_val;
1466};
1467
1468/*
1469 ***************************************************************************
1470 Data Table smu_info structure
1471 ***************************************************************************
1472*/
1473struct atom_smu_info_v3_1
1474{
1475 struct atom_common_table_header table_header;
1476 uint8_t smuip_min_ver;
1477 uint8_t smuip_max_ver;
1478 uint8_t smu_rsd1;
1479 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1480 uint16_t sclk_ss_percentage;
1481 uint16_t sclk_ss_rate_10hz;
1482 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1483 uint16_t gpuclk_ss_rate_10hz;
1484 uint32_t core_refclk_10khz;
1485 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1486 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1487 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1488 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1489 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1490 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1491 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1492 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1493};
1494
1495struct atom_smu_info_v3_2 {
1496 struct atom_common_table_header table_header;
1497 uint8_t smuip_min_ver;
1498 uint8_t smuip_max_ver;
1499 uint8_t smu_rsd1;
1500 uint8_t gpuclk_ss_mode;
1501 uint16_t sclk_ss_percentage;
1502 uint16_t sclk_ss_rate_10hz;
1503 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1504 uint16_t gpuclk_ss_rate_10hz;
1505 uint32_t core_refclk_10khz;
1506 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1507 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1508 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1509 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1510 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1511 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1512 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1513 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1514 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1515 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1516 uint16_t smugoldenoffset;
1517 uint32_t gpupll_vco_freq_10khz;
1518 uint32_t bootup_smnclk_10khz;
1519 uint32_t bootup_socclk_10khz;
1520 uint32_t bootup_mp0clk_10khz;
1521 uint32_t bootup_mp1clk_10khz;
1522 uint32_t bootup_lclk_10khz;
1523 uint32_t bootup_dcefclk_10khz;
1524 uint32_t ctf_threshold_override_value;
1525 uint32_t reserved[5];
1526};
1527
1528struct atom_smu_info_v3_3 {
1529 struct atom_common_table_header table_header;
1530 uint8_t smuip_min_ver;
1531 uint8_t smuip_max_ver;
1532 uint8_t waflclk_ss_mode;
1533 uint8_t gpuclk_ss_mode;
1534 uint16_t sclk_ss_percentage;
1535 uint16_t sclk_ss_rate_10hz;
1536 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1537 uint16_t gpuclk_ss_rate_10hz;
1538 uint32_t core_refclk_10khz;
1539 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1540 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1541 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1542 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1543 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1544 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1545 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1546 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1547 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1548 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1549 uint16_t smugoldenoffset;
1550 uint32_t gpupll_vco_freq_10khz;
1551 uint32_t bootup_smnclk_10khz;
1552 uint32_t bootup_socclk_10khz;
1553 uint32_t bootup_mp0clk_10khz;
1554 uint32_t bootup_mp1clk_10khz;
1555 uint32_t bootup_lclk_10khz;
1556 uint32_t bootup_dcefclk_10khz;
1557 uint32_t ctf_threshold_override_value;
1558 uint32_t syspll3_0_vco_freq_10khz;
1559 uint32_t syspll3_1_vco_freq_10khz;
1560 uint32_t bootup_fclk_10khz;
1561 uint32_t bootup_waflclk_10khz;
1562 uint32_t smu_info_caps;
1563 uint16_t waflclk_ss_percentage; // in unit of 0.001%
1564 uint16_t smuinitoffset;
1565 uint32_t reserved;
1566};
1567
1568/*
1569 ***************************************************************************
1570 Data Table smc_dpm_info structure
1571 ***************************************************************************
1572 */
1573struct atom_smc_dpm_info_v4_1
1574{
1575 struct atom_common_table_header table_header;
1576 uint8_t liquid1_i2c_address;
1577 uint8_t liquid2_i2c_address;
1578 uint8_t vr_i2c_address;
1579 uint8_t plx_i2c_address;
1580
1581 uint8_t liquid_i2c_linescl;
1582 uint8_t liquid_i2c_linesda;
1583 uint8_t vr_i2c_linescl;
1584 uint8_t vr_i2c_linesda;
1585
1586 uint8_t plx_i2c_linescl;
1587 uint8_t plx_i2c_linesda;
1588 uint8_t vrsensorpresent;
1589 uint8_t liquidsensorpresent;
1590
1591 uint16_t maxvoltagestepgfx;
1592 uint16_t maxvoltagestepsoc;
1593
1594 uint8_t vddgfxvrmapping;
1595 uint8_t vddsocvrmapping;
1596 uint8_t vddmem0vrmapping;
1597 uint8_t vddmem1vrmapping;
1598
1599 uint8_t gfxulvphasesheddingmask;
1600 uint8_t soculvphasesheddingmask;
1601 uint8_t padding8_v[2];
1602
1603 uint16_t gfxmaxcurrent;
1604 uint8_t gfxoffset;
1605 uint8_t padding_telemetrygfx;
1606
1607 uint16_t socmaxcurrent;
1608 uint8_t socoffset;
1609 uint8_t padding_telemetrysoc;
1610
1611 uint16_t mem0maxcurrent;
1612 uint8_t mem0offset;
1613 uint8_t padding_telemetrymem0;
1614
1615 uint16_t mem1maxcurrent;
1616 uint8_t mem1offset;
1617 uint8_t padding_telemetrymem1;
1618
1619 uint8_t acdcgpio;
1620 uint8_t acdcpolarity;
1621 uint8_t vr0hotgpio;
1622 uint8_t vr0hotpolarity;
1623
1624 uint8_t vr1hotgpio;
1625 uint8_t vr1hotpolarity;
1626 uint8_t padding1;
1627 uint8_t padding2;
1628
1629 uint8_t ledpin0;
1630 uint8_t ledpin1;
1631 uint8_t ledpin2;
1632 uint8_t padding8_4;
1633
1634 uint8_t pllgfxclkspreadenabled;
1635 uint8_t pllgfxclkspreadpercent;
1636 uint16_t pllgfxclkspreadfreq;
1637
1638 uint8_t uclkspreadenabled;
1639 uint8_t uclkspreadpercent;
1640 uint16_t uclkspreadfreq;
1641
1642 uint8_t socclkspreadenabled;
1643 uint8_t socclkspreadpercent;
1644 uint16_t socclkspreadfreq;
1645
1646 uint8_t acggfxclkspreadenabled;
1647 uint8_t acggfxclkspreadpercent;
1648 uint16_t acggfxclkspreadfreq;
1649
1650 uint8_t Vr2_I2C_address;
1651 uint8_t padding_vr2[3];
1652
1653 uint32_t boardreserved[9];
1654};
1655
1656/*
1657 ***************************************************************************
1658 Data Table smc_dpm_info structure
1659 ***************************************************************************
1660 */
1661struct atom_smc_dpm_info_v4_3
1662{
1663 struct atom_common_table_header table_header;
1664 uint8_t liquid1_i2c_address;
1665 uint8_t liquid2_i2c_address;
1666 uint8_t vr_i2c_address;
1667 uint8_t plx_i2c_address;
1668
1669 uint8_t liquid_i2c_linescl;
1670 uint8_t liquid_i2c_linesda;
1671 uint8_t vr_i2c_linescl;
1672 uint8_t vr_i2c_linesda;
1673
1674 uint8_t plx_i2c_linescl;
1675 uint8_t plx_i2c_linesda;
1676 uint8_t vrsensorpresent;
1677 uint8_t liquidsensorpresent;
1678
1679 uint16_t maxvoltagestepgfx;
1680 uint16_t maxvoltagestepsoc;
1681
1682 uint8_t vddgfxvrmapping;
1683 uint8_t vddsocvrmapping;
1684 uint8_t vddmem0vrmapping;
1685 uint8_t vddmem1vrmapping;
1686
1687 uint8_t gfxulvphasesheddingmask;
1688 uint8_t soculvphasesheddingmask;
1689 uint8_t externalsensorpresent;
1690 uint8_t padding8_v;
1691
1692 uint16_t gfxmaxcurrent;
1693 uint8_t gfxoffset;
1694 uint8_t padding_telemetrygfx;
1695
1696 uint16_t socmaxcurrent;
1697 uint8_t socoffset;
1698 uint8_t padding_telemetrysoc;
1699
1700 uint16_t mem0maxcurrent;
1701 uint8_t mem0offset;
1702 uint8_t padding_telemetrymem0;
1703
1704 uint16_t mem1maxcurrent;
1705 uint8_t mem1offset;
1706 uint8_t padding_telemetrymem1;
1707
1708 uint8_t acdcgpio;
1709 uint8_t acdcpolarity;
1710 uint8_t vr0hotgpio;
1711 uint8_t vr0hotpolarity;
1712
1713 uint8_t vr1hotgpio;
1714 uint8_t vr1hotpolarity;
1715 uint8_t padding1;
1716 uint8_t padding2;
1717
1718 uint8_t ledpin0;
1719 uint8_t ledpin1;
1720 uint8_t ledpin2;
1721 uint8_t padding8_4;
1722
1723 uint8_t pllgfxclkspreadenabled;
1724 uint8_t pllgfxclkspreadpercent;
1725 uint16_t pllgfxclkspreadfreq;
1726
1727 uint8_t uclkspreadenabled;
1728 uint8_t uclkspreadpercent;
1729 uint16_t uclkspreadfreq;
1730
1731 uint8_t fclkspreadenabled;
1732 uint8_t fclkspreadpercent;
1733 uint16_t fclkspreadfreq;
1734
1735 uint8_t fllgfxclkspreadenabled;
1736 uint8_t fllgfxclkspreadpercent;
1737 uint16_t fllgfxclkspreadfreq;
1738
1739 uint32_t boardreserved[10];
1740};
1741
1742struct smudpm_i2ccontrollerconfig_t {
1743 uint32_t enabled;
1744 uint32_t slaveaddress;
1745 uint32_t controllerport;
1746 uint32_t controllername;
1747 uint32_t thermalthrottler;
1748 uint32_t i2cprotocol;
1749 uint32_t i2cspeed;
1750};
1751
1752struct atom_smc_dpm_info_v4_4
1753{
1754 struct atom_common_table_header table_header;
1755 uint32_t i2c_padding[3];
1756
1757 uint16_t maxvoltagestepgfx;
1758 uint16_t maxvoltagestepsoc;
1759
1760 uint8_t vddgfxvrmapping;
1761 uint8_t vddsocvrmapping;
1762 uint8_t vddmem0vrmapping;
1763 uint8_t vddmem1vrmapping;
1764
1765 uint8_t gfxulvphasesheddingmask;
1766 uint8_t soculvphasesheddingmask;
1767 uint8_t externalsensorpresent;
1768 uint8_t padding8_v;
1769
1770 uint16_t gfxmaxcurrent;
1771 uint8_t gfxoffset;
1772 uint8_t padding_telemetrygfx;
1773
1774 uint16_t socmaxcurrent;
1775 uint8_t socoffset;
1776 uint8_t padding_telemetrysoc;
1777
1778 uint16_t mem0maxcurrent;
1779 uint8_t mem0offset;
1780 uint8_t padding_telemetrymem0;
1781
1782 uint16_t mem1maxcurrent;
1783 uint8_t mem1offset;
1784 uint8_t padding_telemetrymem1;
1785
1786
1787 uint8_t acdcgpio;
1788 uint8_t acdcpolarity;
1789 uint8_t vr0hotgpio;
1790 uint8_t vr0hotpolarity;
1791
1792 uint8_t vr1hotgpio;
1793 uint8_t vr1hotpolarity;
1794 uint8_t padding1;
1795 uint8_t padding2;
1796
1797
1798 uint8_t ledpin0;
1799 uint8_t ledpin1;
1800 uint8_t ledpin2;
1801 uint8_t padding8_4;
1802
1803
1804 uint8_t pllgfxclkspreadenabled;
1805 uint8_t pllgfxclkspreadpercent;
1806 uint16_t pllgfxclkspreadfreq;
1807
1808
1809 uint8_t uclkspreadenabled;
1810 uint8_t uclkspreadpercent;
1811 uint16_t uclkspreadfreq;
1812
1813
1814 uint8_t fclkspreadenabled;
1815 uint8_t fclkspreadpercent;
1816 uint16_t fclkspreadfreq;
1817
1818
1819 uint8_t fllgfxclkspreadenabled;
1820 uint8_t fllgfxclkspreadpercent;
1821 uint16_t fllgfxclkspreadfreq;
1822
1823
1824 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7];
1825
1826
1827 uint32_t boardreserved[10];
1828};
1829
1830enum smudpm_v4_5_i2ccontrollername_e{
1831 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0,
1832 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC,
1833 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI,
1834 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD,
1835 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0,
1836 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1,
1837 SMC_V4_5_I2C_CONTROLLER_NAME_PLX,
1838 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE,
1839 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT,
1840};
1841
1842enum smudpm_v4_5_i2ccontrollerthrottler_e{
1843 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
1844 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX,
1845 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC,
1846 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI,
1847 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD,
1848 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0,
1849 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1,
1850 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX,
1851 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT,
1852};
1853
1854enum smudpm_v4_5_i2ccontrollerprotocol_e{
1855 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0,
1856 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1,
1857 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0,
1858 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1,
1859 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0,
1860 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1,
1861 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT,
1862};
1863
1864struct smudpm_i2c_controller_config_v2
1865{
1866 uint8_t Enabled;
1867 uint8_t Speed;
1868 uint8_t Padding[2];
1869 uint32_t SlaveAddress;
1870 uint8_t ControllerPort;
1871 uint8_t ControllerName;
1872 uint8_t ThermalThrotter;
1873 uint8_t I2cProtocol;
1874};
1875
1876struct atom_smc_dpm_info_v4_5
1877{
1878 struct atom_common_table_header table_header;
1879 // SECTION: BOARD PARAMETERS
1880 // I2C Control
1881 struct smudpm_i2c_controller_config_v2 I2cControllers[8];
1882
1883 // SVI2 Board Parameters
1884 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
1885 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
1886
1887 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
1888 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
1889 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
1890 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
1891
1892 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1893 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1894 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
1895 uint8_t Padding8_V;
1896
1897 // Telemetry Settings
1898 uint16_t GfxMaxCurrent; // in Amps
1899 uint8_t GfxOffset; // in Amps
1900 uint8_t Padding_TelemetryGfx;
1901 uint16_t SocMaxCurrent; // in Amps
1902 uint8_t SocOffset; // in Amps
1903 uint8_t Padding_TelemetrySoc;
1904
1905 uint16_t Mem0MaxCurrent; // in Amps
1906 uint8_t Mem0Offset; // in Amps
1907 uint8_t Padding_TelemetryMem0;
1908
1909 uint16_t Mem1MaxCurrent; // in Amps
1910 uint8_t Mem1Offset; // in Amps
1911 uint8_t Padding_TelemetryMem1;
1912
1913 // GPIO Settings
1914 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
1915 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
1916 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
1917 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
1918
1919 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
1920 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
1921 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
1922 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
1923
1924 // LED Display Settings
1925 uint8_t LedPin0; // GPIO number for LedPin[0]
1926 uint8_t LedPin1; // GPIO number for LedPin[1]
1927 uint8_t LedPin2; // GPIO number for LedPin[2]
1928 uint8_t padding8_4;
1929
1930 // GFXCLK PLL Spread Spectrum
1931 uint8_t PllGfxclkSpreadEnabled; // on or off
1932 uint8_t PllGfxclkSpreadPercent; // Q4.4
1933 uint16_t PllGfxclkSpreadFreq; // kHz
1934
1935 // GFXCLK DFLL Spread Spectrum
1936 uint8_t DfllGfxclkSpreadEnabled; // on or off
1937 uint8_t DfllGfxclkSpreadPercent; // Q4.4
1938 uint16_t DfllGfxclkSpreadFreq; // kHz
1939
1940 // UCLK Spread Spectrum
1941 uint8_t UclkSpreadEnabled; // on or off
1942 uint8_t UclkSpreadPercent; // Q4.4
1943 uint16_t UclkSpreadFreq; // kHz
1944
1945 // SOCCLK Spread Spectrum
1946 uint8_t SoclkSpreadEnabled; // on or off
1947 uint8_t SocclkSpreadPercent; // Q4.4
1948 uint16_t SocclkSpreadFreq; // kHz
1949
1950 // Total board power
1951 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
1952 uint16_t BoardPadding;
1953
1954 // Mvdd Svi2 Div Ratio Setting
1955 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
1956
1957 uint32_t BoardReserved[9];
1958
1959};
1960
1961struct atom_smc_dpm_info_v4_6
1962{
1963 struct atom_common_table_header table_header;
1964 // section: board parameters
1965 uint32_t i2c_padding[3]; // old i2c control are moved to new area
1966
1967 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
1968 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
1969
1970 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields
1971 uint8_t vddsocvrmapping; // use vr_mapping* bitfields
1972 uint8_t vddmemvrmapping; // use vr_mapping* bitfields
1973 uint8_t boardvrmapping; // use vr_mapping* bitfields
1974
1975 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
1976 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in)
1977 uint8_t padding8_v[2];
1978
1979 // telemetry settings
1980 uint16_t gfxmaxcurrent; // in amps
1981 uint8_t gfxoffset; // in amps
1982 uint8_t padding_telemetrygfx;
1983
1984 uint16_t socmaxcurrent; // in amps
1985 uint8_t socoffset; // in amps
1986 uint8_t padding_telemetrysoc;
1987
1988 uint16_t memmaxcurrent; // in amps
1989 uint8_t memoffset; // in amps
1990 uint8_t padding_telemetrymem;
1991
1992 uint16_t boardmaxcurrent; // in amps
1993 uint8_t boardoffset; // in amps
1994 uint8_t padding_telemetryboardinput;
1995
1996 // gpio settings
1997 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event
1998 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event
1999 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event
2000 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event
2001
2002 // gfxclk pll spread spectrum
2003 uint8_t pllgfxclkspreadenabled; // on or off
2004 uint8_t pllgfxclkspreadpercent; // q4.4
2005 uint16_t pllgfxclkspreadfreq; // khz
2006
2007 // uclk spread spectrum
2008 uint8_t uclkspreadenabled; // on or off
2009 uint8_t uclkspreadpercent; // q4.4
2010 uint16_t uclkspreadfreq; // khz
2011
2012 // fclk spread spectrum
2013 uint8_t fclkspreadenabled; // on or off
2014 uint8_t fclkspreadpercent; // q4.4
2015 uint16_t fclkspreadfreq; // khz
2016
2017
2018 // gfxclk fll spread spectrum
2019 uint8_t fllgfxclkspreadenabled; // on or off
2020 uint8_t fllgfxclkspreadpercent; // q4.4
2021 uint16_t fllgfxclkspreadfreq; // khz
2022
2023 // i2c controller structure
2024 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8];
2025
2026 // memory section
2027 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask.
2028
2029 uint8_t drambitwidth; // for dram use only. see dram bit width type defines
2030 uint8_t paddingmem[3];
2031
2032 // total board power
2033 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power
2034 uint16_t boardpadding;
2035
2036 // section: xgmi training
2037 uint8_t xgmilinkspeed[4];
2038 uint8_t xgmilinkwidth[4];
2039
2040 uint16_t xgmifclkfreq[4];
2041 uint16_t xgmisocvoltage[4];
2042
2043 // reserved
2044 uint32_t boardreserved[10];
2045};
2046
2047struct atom_smc_dpm_info_v4_7
2048{
2049 struct atom_common_table_header table_header;
2050 // SECTION: BOARD PARAMETERS
2051 // I2C Control
2052 struct smudpm_i2c_controller_config_v2 I2cControllers[8];
2053
2054 // SVI2 Board Parameters
2055 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2056 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2057
2058 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2059 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2060 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2061 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2062
2063 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2064 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2065 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2066 uint8_t Padding8_V;
2067
2068 // Telemetry Settings
2069 uint16_t GfxMaxCurrent; // in Amps
2070 uint8_t GfxOffset; // in Amps
2071 uint8_t Padding_TelemetryGfx;
2072 uint16_t SocMaxCurrent; // in Amps
2073 uint8_t SocOffset; // in Amps
2074 uint8_t Padding_TelemetrySoc;
2075
2076 uint16_t Mem0MaxCurrent; // in Amps
2077 uint8_t Mem0Offset; // in Amps
2078 uint8_t Padding_TelemetryMem0;
2079
2080 uint16_t Mem1MaxCurrent; // in Amps
2081 uint8_t Mem1Offset; // in Amps
2082 uint8_t Padding_TelemetryMem1;
2083
2084 // GPIO Settings
2085 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2086 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2087 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2088 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2089
2090 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2091 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2092 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2093 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2094
2095 // LED Display Settings
2096 uint8_t LedPin0; // GPIO number for LedPin[0]
2097 uint8_t LedPin1; // GPIO number for LedPin[1]
2098 uint8_t LedPin2; // GPIO number for LedPin[2]
2099 uint8_t padding8_4;
2100
2101 // GFXCLK PLL Spread Spectrum
2102 uint8_t PllGfxclkSpreadEnabled; // on or off
2103 uint8_t PllGfxclkSpreadPercent; // Q4.4
2104 uint16_t PllGfxclkSpreadFreq; // kHz
2105
2106 // GFXCLK DFLL Spread Spectrum
2107 uint8_t DfllGfxclkSpreadEnabled; // on or off
2108 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2109 uint16_t DfllGfxclkSpreadFreq; // kHz
2110
2111 // UCLK Spread Spectrum
2112 uint8_t UclkSpreadEnabled; // on or off
2113 uint8_t UclkSpreadPercent; // Q4.4
2114 uint16_t UclkSpreadFreq; // kHz
2115
2116 // SOCCLK Spread Spectrum
2117 uint8_t SoclkSpreadEnabled; // on or off
2118 uint8_t SocclkSpreadPercent; // Q4.4
2119 uint16_t SocclkSpreadFreq; // kHz
2120
2121 // Total board power
2122 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2123 uint16_t BoardPadding;
2124
2125 // Mvdd Svi2 Div Ratio Setting
2126 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
2127
2128 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
2129 uint8_t GpioI2cScl; // Serial Clock
2130 uint8_t GpioI2cSda; // Serial Data
2131 uint16_t GpioPadding;
2132
2133 // Additional LED Display Settings
2134 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed
2135 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status
2136 uint16_t LedEnableMask;
2137
2138 // Power Limit Scalars
2139 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT]
2140
2141 uint8_t MvddUlvPhaseSheddingMask;
2142 uint8_t VddciUlvPhaseSheddingMask;
2143 uint8_t Padding8_Psi1;
2144 uint8_t Padding8_Psi2;
2145
2146 uint32_t BoardReserved[5];
2147};
2148
2149struct smudpm_i2c_controller_config_v3
2150{
2151 uint8_t Enabled;
2152 uint8_t Speed;
2153 uint8_t SlaveAddress;
2154 uint8_t ControllerPort;
2155 uint8_t ControllerName;
2156 uint8_t ThermalThrotter;
2157 uint8_t I2cProtocol;
2158 uint8_t PaddingConfig;
2159};
2160
2161struct atom_smc_dpm_info_v4_9
2162{
2163 struct atom_common_table_header table_header;
2164
2165 //SECTION: Gaming Clocks
2166 //uint32_t GamingClk[6];
2167
2168 // SECTION: I2C Control
2169 struct smudpm_i2c_controller_config_v3 I2cControllers[16];
2170
2171 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1
2172 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1
2173 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off
2174 uint8_t I2cSpare;
2175
2176 // SECTION: SVI2 Board Parameters
2177 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2178 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2179 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2180 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2181
2182 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2183 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2184 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2185 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2186
2187 // SECTION: Telemetry Settings
2188 uint16_t GfxMaxCurrent; // in Amps
2189 uint8_t GfxOffset; // in Amps
2190 uint8_t Padding_TelemetryGfx;
2191
2192 uint16_t SocMaxCurrent; // in Amps
2193 uint8_t SocOffset; // in Amps
2194 uint8_t Padding_TelemetrySoc;
2195
2196 uint16_t Mem0MaxCurrent; // in Amps
2197 uint8_t Mem0Offset; // in Amps
2198 uint8_t Padding_TelemetryMem0;
2199
2200 uint16_t Mem1MaxCurrent; // in Amps
2201 uint8_t Mem1Offset; // in Amps
2202 uint8_t Padding_TelemetryMem1;
2203
2204 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
2205
2206 // SECTION: GPIO Settings
2207 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2208 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2209 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2210 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2211
2212 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2213 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2214 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2215 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2216
2217 // LED Display Settings
2218 uint8_t LedPin0; // GPIO number for LedPin[0]
2219 uint8_t LedPin1; // GPIO number for LedPin[1]
2220 uint8_t LedPin2; // GPIO number for LedPin[2]
2221 uint8_t LedEnableMask;
2222
2223 uint8_t LedPcie; // GPIO number for PCIE results
2224 uint8_t LedError; // GPIO number for Error Cases
2225 uint8_t LedSpare1[2];
2226
2227 // SECTION: Clock Spread Spectrum
2228
2229 // GFXCLK PLL Spread Spectrum
2230 uint8_t PllGfxclkSpreadEnabled; // on or off
2231 uint8_t PllGfxclkSpreadPercent; // Q4.4
2232 uint16_t PllGfxclkSpreadFreq; // kHz
2233
2234 // GFXCLK DFLL Spread Spectrum
2235 uint8_t DfllGfxclkSpreadEnabled; // on or off
2236 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2237 uint16_t DfllGfxclkSpreadFreq; // kHz
2238
2239 // UCLK Spread Spectrum
2240 uint8_t UclkSpreadEnabled; // on or off
2241 uint8_t UclkSpreadPercent; // Q4.4
2242 uint16_t UclkSpreadFreq; // kHz
2243
2244 // FCLK Spread Spectrum
2245 uint8_t FclkSpreadEnabled; // on or off
2246 uint8_t FclkSpreadPercent; // Q4.4
2247 uint16_t FclkSpreadFreq; // kHz
2248
2249 // Section: Memory Config
2250 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
2251
2252 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines
2253 uint8_t PaddingMem1[3];
2254
2255 // Section: Total Board Power
2256 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2257 uint16_t BoardPowerPadding;
2258
2259 // SECTION: XGMI Training
2260 uint8_t XgmiLinkSpeed [4];
2261 uint8_t XgmiLinkWidth [4];
2262
2263 uint16_t XgmiFclkFreq [4];
2264 uint16_t XgmiSocVoltage [4];
2265
2266 // SECTION: Board Reserved
2267
2268 uint32_t BoardReserved[16];
2269
2270};
2271
2272/*
2273 ***************************************************************************
2274 Data Table asic_profiling_info structure
2275 ***************************************************************************
2276*/
2277struct atom_asic_profiling_info_v4_1
2278{
2279 struct atom_common_table_header table_header;
2280 uint32_t maxvddc;
2281 uint32_t minvddc;
2282 uint32_t avfs_meannsigma_acontant0;
2283 uint32_t avfs_meannsigma_acontant1;
2284 uint32_t avfs_meannsigma_acontant2;
2285 uint16_t avfs_meannsigma_dc_tol_sigma;
2286 uint16_t avfs_meannsigma_platform_mean;
2287 uint16_t avfs_meannsigma_platform_sigma;
2288 uint32_t gb_vdroop_table_cksoff_a0;
2289 uint32_t gb_vdroop_table_cksoff_a1;
2290 uint32_t gb_vdroop_table_cksoff_a2;
2291 uint32_t gb_vdroop_table_ckson_a0;
2292 uint32_t gb_vdroop_table_ckson_a1;
2293 uint32_t gb_vdroop_table_ckson_a2;
2294 uint32_t avfsgb_fuse_table_cksoff_m1;
2295 uint32_t avfsgb_fuse_table_cksoff_m2;
2296 uint32_t avfsgb_fuse_table_cksoff_b;
2297 uint32_t avfsgb_fuse_table_ckson_m1;
2298 uint32_t avfsgb_fuse_table_ckson_m2;
2299 uint32_t avfsgb_fuse_table_ckson_b;
2300 uint16_t max_voltage_0_25mv;
2301 uint8_t enable_gb_vdroop_table_cksoff;
2302 uint8_t enable_gb_vdroop_table_ckson;
2303 uint8_t enable_gb_fuse_table_cksoff;
2304 uint8_t enable_gb_fuse_table_ckson;
2305 uint16_t psm_age_comfactor;
2306 uint8_t enable_apply_avfs_cksoff_voltage;
2307 uint8_t reserved;
2308 uint32_t dispclk2gfxclk_a;
2309 uint32_t dispclk2gfxclk_b;
2310 uint32_t dispclk2gfxclk_c;
2311 uint32_t pixclk2gfxclk_a;
2312 uint32_t pixclk2gfxclk_b;
2313 uint32_t pixclk2gfxclk_c;
2314 uint32_t dcefclk2gfxclk_a;
2315 uint32_t dcefclk2gfxclk_b;
2316 uint32_t dcefclk2gfxclk_c;
2317 uint32_t phyclk2gfxclk_a;
2318 uint32_t phyclk2gfxclk_b;
2319 uint32_t phyclk2gfxclk_c;
2320};
2321
2322struct atom_asic_profiling_info_v4_2 {
2323 struct atom_common_table_header table_header;
2324 uint32_t maxvddc;
2325 uint32_t minvddc;
2326 uint32_t avfs_meannsigma_acontant0;
2327 uint32_t avfs_meannsigma_acontant1;
2328 uint32_t avfs_meannsigma_acontant2;
2329 uint16_t avfs_meannsigma_dc_tol_sigma;
2330 uint16_t avfs_meannsigma_platform_mean;
2331 uint16_t avfs_meannsigma_platform_sigma;
2332 uint32_t gb_vdroop_table_cksoff_a0;
2333 uint32_t gb_vdroop_table_cksoff_a1;
2334 uint32_t gb_vdroop_table_cksoff_a2;
2335 uint32_t gb_vdroop_table_ckson_a0;
2336 uint32_t gb_vdroop_table_ckson_a1;
2337 uint32_t gb_vdroop_table_ckson_a2;
2338 uint32_t avfsgb_fuse_table_cksoff_m1;
2339 uint32_t avfsgb_fuse_table_cksoff_m2;
2340 uint32_t avfsgb_fuse_table_cksoff_b;
2341 uint32_t avfsgb_fuse_table_ckson_m1;
2342 uint32_t avfsgb_fuse_table_ckson_m2;
2343 uint32_t avfsgb_fuse_table_ckson_b;
2344 uint16_t max_voltage_0_25mv;
2345 uint8_t enable_gb_vdroop_table_cksoff;
2346 uint8_t enable_gb_vdroop_table_ckson;
2347 uint8_t enable_gb_fuse_table_cksoff;
2348 uint8_t enable_gb_fuse_table_ckson;
2349 uint16_t psm_age_comfactor;
2350 uint8_t enable_apply_avfs_cksoff_voltage;
2351 uint8_t reserved;
2352 uint32_t dispclk2gfxclk_a;
2353 uint32_t dispclk2gfxclk_b;
2354 uint32_t dispclk2gfxclk_c;
2355 uint32_t pixclk2gfxclk_a;
2356 uint32_t pixclk2gfxclk_b;
2357 uint32_t pixclk2gfxclk_c;
2358 uint32_t dcefclk2gfxclk_a;
2359 uint32_t dcefclk2gfxclk_b;
2360 uint32_t dcefclk2gfxclk_c;
2361 uint32_t phyclk2gfxclk_a;
2362 uint32_t phyclk2gfxclk_b;
2363 uint32_t phyclk2gfxclk_c;
2364 uint32_t acg_gb_vdroop_table_a0;
2365 uint32_t acg_gb_vdroop_table_a1;
2366 uint32_t acg_gb_vdroop_table_a2;
2367 uint32_t acg_avfsgb_fuse_table_m1;
2368 uint32_t acg_avfsgb_fuse_table_m2;
2369 uint32_t acg_avfsgb_fuse_table_b;
2370 uint8_t enable_acg_gb_vdroop_table;
2371 uint8_t enable_acg_gb_fuse_table;
2372 uint32_t acg_dispclk2gfxclk_a;
2373 uint32_t acg_dispclk2gfxclk_b;
2374 uint32_t acg_dispclk2gfxclk_c;
2375 uint32_t acg_pixclk2gfxclk_a;
2376 uint32_t acg_pixclk2gfxclk_b;
2377 uint32_t acg_pixclk2gfxclk_c;
2378 uint32_t acg_dcefclk2gfxclk_a;
2379 uint32_t acg_dcefclk2gfxclk_b;
2380 uint32_t acg_dcefclk2gfxclk_c;
2381 uint32_t acg_phyclk2gfxclk_a;
2382 uint32_t acg_phyclk2gfxclk_b;
2383 uint32_t acg_phyclk2gfxclk_c;
2384};
2385
2386/*
2387 ***************************************************************************
2388 Data Table multimedia_info structure
2389 ***************************************************************************
2390*/
2391struct atom_multimedia_info_v2_1
2392{
2393 struct atom_common_table_header table_header;
2394 uint8_t uvdip_min_ver;
2395 uint8_t uvdip_max_ver;
2396 uint8_t vceip_min_ver;
2397 uint8_t vceip_max_ver;
2398 uint16_t uvd_enc_max_input_width_pixels;
2399 uint16_t uvd_enc_max_input_height_pixels;
2400 uint16_t vce_enc_max_input_width_pixels;
2401 uint16_t vce_enc_max_input_height_pixels;
2402 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
2403 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
2404};
2405
2406
2407/*
2408 ***************************************************************************
2409 Data Table umc_info structure
2410 ***************************************************************************
2411*/
2412struct atom_umc_info_v3_1
2413{
2414 struct atom_common_table_header table_header;
2415 uint32_t ucode_version;
2416 uint32_t ucode_rom_startaddr;
2417 uint32_t ucode_length;
2418 uint16_t umc_reg_init_offset;
2419 uint16_t customer_ucode_name_offset;
2420 uint16_t mclk_ss_percentage;
2421 uint16_t mclk_ss_rate_10hz;
2422 uint8_t umcip_min_ver;
2423 uint8_t umcip_max_ver;
2424 uint8_t vram_type; //enum of atom_dgpu_vram_type
2425 uint8_t umc_config;
2426 uint32_t mem_refclk_10khz;
2427};
2428
2429// umc_info.umc_config
2430enum atom_umc_config_def {
2431 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001,
2432 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002,
2433 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004,
2434 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008,
2435 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010,
2436 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020,
2437};
2438
2439struct atom_umc_info_v3_2
2440{
2441 struct atom_common_table_header table_header;
2442 uint32_t ucode_version;
2443 uint32_t ucode_rom_startaddr;
2444 uint32_t ucode_length;
2445 uint16_t umc_reg_init_offset;
2446 uint16_t customer_ucode_name_offset;
2447 uint16_t mclk_ss_percentage;
2448 uint16_t mclk_ss_rate_10hz;
2449 uint8_t umcip_min_ver;
2450 uint8_t umcip_max_ver;
2451 uint8_t vram_type; //enum of atom_dgpu_vram_type
2452 uint8_t umc_config;
2453 uint32_t mem_refclk_10khz;
2454 uint32_t pstate_uclk_10khz[4];
2455 uint16_t umcgoldenoffset;
2456 uint16_t densitygoldenoffset;
2457};
2458
2459struct atom_umc_info_v3_3
2460{
2461 struct atom_common_table_header table_header;
2462 uint32_t ucode_reserved;
2463 uint32_t ucode_rom_startaddr;
2464 uint32_t ucode_length;
2465 uint16_t umc_reg_init_offset;
2466 uint16_t customer_ucode_name_offset;
2467 uint16_t mclk_ss_percentage;
2468 uint16_t mclk_ss_rate_10hz;
2469 uint8_t umcip_min_ver;
2470 uint8_t umcip_max_ver;
2471 uint8_t vram_type; //enum of atom_dgpu_vram_type
2472 uint8_t umc_config;
2473 uint32_t mem_refclk_10khz;
2474 uint32_t pstate_uclk_10khz[4];
2475 uint16_t umcgoldenoffset;
2476 uint16_t densitygoldenoffset;
2477 uint32_t reserved[4];
2478};
2479
2480/*
2481 ***************************************************************************
2482 Data Table vram_info structure
2483 ***************************************************************************
2484*/
2485struct atom_vram_module_v9 {
2486 // Design Specific Values
2487 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2488 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
2489 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
2490 uint16_t reserved[3];
2491 uint16_t mem_voltage; // mem_voltage
2492 uint16_t vram_module_size; // Size of atom_vram_module_v9
2493 uint8_t ext_memory_id; // Current memory module ID
2494 uint8_t memory_type; // enum of atom_dgpu_vram_type
2495 uint8_t channel_num; // Number of mem. channels supported in this module
2496 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2497 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2498 uint8_t tunningset_id; // MC phy registers set per.
2499 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2500 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2501 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id
2502 uint8_t vram_rsd2; // reserved
2503 char dram_pnstring[20]; // part number end with '0'.
2504};
2505
2506struct atom_vram_info_header_v2_3 {
2507 struct atom_common_table_header table_header;
2508 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
2509 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
2510 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2511 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
2512 uint16_t dram_data_remap_tbloffset; // reserved for now
2513 uint16_t tmrs_seq_offset; // offset of HBM tmrs
2514 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2515 uint16_t vram_rsd2;
2516 uint8_t vram_module_num; // indicate number of VRAM module
2517 uint8_t umcip_min_ver;
2518 uint8_t umcip_max_ver;
2519 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2520 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2521};
2522
2523struct atom_umc_register_addr_info{
2524 uint32_t umc_register_addr:24;
2525 uint32_t umc_reg_type_ind:1;
2526 uint32_t umc_reg_rsvd:7;
2527};
2528
2529//atom_umc_register_addr_info.
2530enum atom_umc_register_addr_info_flag{
2531 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01,
2532};
2533
2534union atom_umc_register_addr_info_access
2535{
2536 struct atom_umc_register_addr_info umc_reg_addr;
2537 uint32_t u32umc_reg_addr;
2538};
2539
2540struct atom_umc_reg_setting_id_config{
2541 uint32_t memclockrange:24;
2542 uint32_t mem_blk_id:8;
2543};
2544
2545union atom_umc_reg_setting_id_config_access
2546{
2547 struct atom_umc_reg_setting_id_config umc_id_access;
2548 uint32_t u32umc_id_access;
2549};
2550
2551struct atom_umc_reg_setting_data_block{
2552 union atom_umc_reg_setting_id_config_access block_id;
2553 uint32_t u32umc_reg_data[1];
2554};
2555
2556struct atom_umc_init_reg_block{
2557 uint16_t umc_reg_num;
2558 uint16_t reserved;
2559 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num;
2560 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
2561};
2562
2563struct atom_vram_module_v10 {
2564 // Design Specific Values
2565 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2566 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
2567 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
2568 uint16_t reserved[3];
2569 uint16_t mem_voltage; // mem_voltage
2570 uint16_t vram_module_size; // Size of atom_vram_module_v9
2571 uint8_t ext_memory_id; // Current memory module ID
2572 uint8_t memory_type; // enum of atom_dgpu_vram_type
2573 uint8_t channel_num; // Number of mem. channels supported in this module
2574 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2575 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2576 uint8_t tunningset_id; // MC phy registers set per
2577 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2578 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2579 uint8_t vram_flags; // bit0= bankgroup enable
2580 uint8_t vram_rsd2; // reserved
2581 uint16_t gddr6_mr10; // gddr6 mode register10 value
2582 uint16_t gddr6_mr1; // gddr6 mode register1 value
2583 uint16_t gddr6_mr2; // gddr6 mode register2 value
2584 uint16_t gddr6_mr7; // gddr6 mode register7 value
2585 char dram_pnstring[20]; // part number end with '0'
2586};
2587
2588struct atom_vram_info_header_v2_4 {
2589 struct atom_common_table_header table_header;
2590 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
2591 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
2592 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2593 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
2594 uint16_t dram_data_remap_tbloffset; // reserved for now
2595 uint16_t reserved; // offset of reserved
2596 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2597 uint16_t vram_rsd2;
2598 uint8_t vram_module_num; // indicate number of VRAM module
2599 uint8_t umcip_min_ver;
2600 uint8_t umcip_max_ver;
2601 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2602 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2603};
2604
2605struct atom_vram_module_v11 {
2606 // Design Specific Values
2607 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
2608 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
2609 uint16_t mem_voltage; // mem_voltage
2610 uint16_t vram_module_size; // Size of atom_vram_module_v9
2611 uint8_t ext_memory_id; // Current memory module ID
2612 uint8_t memory_type; // enum of atom_dgpu_vram_type
2613 uint8_t channel_num; // Number of mem. channels supported in this module
2614 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2615 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2616 uint8_t tunningset_id; // MC phy registers set per.
2617 uint16_t reserved[4]; // reserved
2618 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2619 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2620 uint8_t vram_flags; // bit0= bankgroup enable
2621 uint8_t vram_rsd2; // reserved
2622 uint16_t gddr6_mr10; // gddr6 mode register10 value
2623 uint16_t gddr6_mr0; // gddr6 mode register0 value
2624 uint16_t gddr6_mr1; // gddr6 mode register1 value
2625 uint16_t gddr6_mr2; // gddr6 mode register2 value
2626 uint16_t gddr6_mr4; // gddr6 mode register4 value
2627 uint16_t gddr6_mr7; // gddr6 mode register7 value
2628 uint16_t gddr6_mr8; // gddr6 mode register8 value
2629 char dram_pnstring[40]; // part number end with '0'.
2630};
2631
2632struct atom_gddr6_ac_timing_v2_5 {
2633 uint32_t u32umc_id_access;
2634 uint8_t RL;
2635 uint8_t WL;
2636 uint8_t tRAS;
2637 uint8_t tRC;
2638
2639 uint16_t tREFI;
2640 uint8_t tRFC;
2641 uint8_t tRFCpb;
2642
2643 uint8_t tRREFD;
2644 uint8_t tRCDRD;
2645 uint8_t tRCDWR;
2646 uint8_t tRP;
2647
2648 uint8_t tRRDS;
2649 uint8_t tRRDL;
2650 uint8_t tWR;
2651 uint8_t tWTRS;
2652
2653 uint8_t tWTRL;
2654 uint8_t tFAW;
2655 uint8_t tCCDS;
2656 uint8_t tCCDL;
2657
2658 uint8_t tCRCRL;
2659 uint8_t tCRCWL;
2660 uint8_t tCKE;
2661 uint8_t tCKSRE;
2662
2663 uint8_t tCKSRX;
2664 uint8_t tRTPS;
2665 uint8_t tRTPL;
2666 uint8_t tMRD;
2667
2668 uint8_t tMOD;
2669 uint8_t tXS;
2670 uint8_t tXHP;
2671 uint8_t tXSMRS;
2672
2673 uint32_t tXSH;
2674
2675 uint8_t tPD;
2676 uint8_t tXP;
2677 uint8_t tCPDED;
2678 uint8_t tACTPDE;
2679
2680 uint8_t tPREPDE;
2681 uint8_t tREFPDE;
2682 uint8_t tMRSPDEN;
2683 uint8_t tRDSRE;
2684
2685 uint8_t tWRSRE;
2686 uint8_t tPPD;
2687 uint8_t tCCDMW;
2688 uint8_t tWTRTR;
2689
2690 uint8_t tLTLTR;
2691 uint8_t tREFTR;
2692 uint8_t VNDR;
2693 uint8_t reserved[9];
2694};
2695
2696struct atom_gddr6_bit_byte_remap {
2697 uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap
2698 uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0
2699 uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1
2700 uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2
2701 uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0
2702 uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1
2703 uint32_t phy_dram; //mmUMC_PHY_DRAM
2704};
2705
2706struct atom_gddr6_dram_data_remap {
2707 uint32_t table_size;
2708 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK
2709 struct atom_gddr6_bit_byte_remap bit_byte_remap[16];
2710};
2711
2712struct atom_vram_info_header_v2_5 {
2713 struct atom_common_table_header table_header;
2714 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings
2715 uint16_t gddr6_ac_timing_offset; // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings
2716 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
2717 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
2718 uint16_t dram_data_remap_tbloffset; // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping
2719 uint16_t reserved; // offset of reserved
2720 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
2721 uint16_t strobe_mode_patch_tbloffset; // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings
2722 uint8_t vram_module_num; // indicate number of VRAM module
2723 uint8_t umcip_min_ver;
2724 uint8_t umcip_max_ver;
2725 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
2726 struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
2727};
2728
2729/*
2730 ***************************************************************************
2731 Data Table voltageobject_info structure
2732 ***************************************************************************
2733*/
2734struct atom_i2c_data_entry
2735{
2736 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit
2737 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit
2738};
2739
2740struct atom_voltage_object_header_v4{
2741 uint8_t voltage_type; //enum atom_voltage_type
2742 uint8_t voltage_mode; //enum atom_voltage_object_mode
2743 uint16_t object_size; //Size of Object
2744};
2745
2746// atom_voltage_object_header_v4.voltage_mode
2747enum atom_voltage_object_mode
2748{
2749 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4
2750 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4
2751 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4
2752 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4
2753 VOLTAGE_OBJ_EVV = 8,
2754 VOLTAGE_OBJ_MERGED_POWER = 9,
2755};
2756
2757struct atom_i2c_voltage_object_v4
2758{
2759 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
2760 uint8_t regulator_id; //Indicate Voltage Regulator Id
2761 uint8_t i2c_id;
2762 uint8_t i2c_slave_addr;
2763 uint8_t i2c_control_offset;
2764 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
2765 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz.
2766 uint8_t reserved[2];
2767 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff
2768};
2769
2770// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
2771enum atom_i2c_voltage_control_flag
2772{
2773 VOLTAGE_DATA_ONE_BYTE = 0,
2774 VOLTAGE_DATA_TWO_BYTE = 1,
2775};
2776
2777
2778struct atom_voltage_gpio_map_lut
2779{
2780 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register
2781 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV
2782};
2783
2784struct atom_gpio_voltage_object_v4
2785{
2786 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
2787 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode
2788 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table
2789 uint8_t phase_delay_us; // phase delay in unit of micro second
2790 uint8_t reserved;
2791 uint32_t gpio_mask_val; // GPIO Mask value
2792 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1];
2793};
2794
2795struct atom_svid2_voltage_object_v4
2796{
2797 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2
2798 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
2799 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
2800 uint8_t psi0_enable; //
2801 uint8_t maxvstep;
2802 uint8_t telemetry_offset;
2803 uint8_t telemetry_gain;
2804 uint16_t reserved1;
2805};
2806
2807struct atom_merged_voltage_object_v4
2808{
2809 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER
2810 uint8_t merged_powerrail_type; //enum atom_voltage_type
2811 uint8_t reserved[3];
2812};
2813
2814union atom_voltage_object_v4{
2815 struct atom_gpio_voltage_object_v4 gpio_voltage_obj;
2816 struct atom_i2c_voltage_object_v4 i2c_voltage_obj;
2817 struct atom_svid2_voltage_object_v4 svid2_voltage_obj;
2818 struct atom_merged_voltage_object_v4 merged_voltage_obj;
2819};
2820
2821struct atom_voltage_objects_info_v4_1
2822{
2823 struct atom_common_table_header table_header;
2824 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control
2825};
2826
2827
2828/*
2829 ***************************************************************************
2830 All Command Function structure definition
2831 ***************************************************************************
2832*/
2833
2834/*
2835 ***************************************************************************
2836 Structures used by asic_init
2837 ***************************************************************************
2838*/
2839
2840struct asic_init_engine_parameters
2841{
2842 uint32_t sclkfreqin10khz:24;
2843 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */
2844};
2845
2846struct asic_init_mem_parameters
2847{
2848 uint32_t mclkfreqin10khz:24;
2849 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */
2850};
2851
2852struct asic_init_parameters_v2_1
2853{
2854 struct asic_init_engine_parameters engineparam;
2855 struct asic_init_mem_parameters memparam;
2856};
2857
2858struct asic_init_ps_allocation_v2_1
2859{
2860 struct asic_init_parameters_v2_1 param;
2861 uint32_t reserved[16];
2862};
2863
2864
2865enum atom_asic_init_engine_flag
2866{
2867 b3NORMAL_ENGINE_INIT = 0,
2868 b3SRIOV_SKIP_ASIC_INIT = 0x02,
2869 b3SRIOV_LOAD_UCODE = 0x40,
2870};
2871
2872enum atom_asic_init_mem_flag
2873{
2874 b3NORMAL_MEM_INIT = 0,
2875 b3DRAM_SELF_REFRESH_EXIT =0x20,
2876};
2877
2878/*
2879 ***************************************************************************
2880 Structures used by setengineclock
2881 ***************************************************************************
2882*/
2883
2884struct set_engine_clock_parameters_v2_1
2885{
2886 uint32_t sclkfreqin10khz:24;
2887 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
2888 uint32_t reserved[10];
2889};
2890
2891struct set_engine_clock_ps_allocation_v2_1
2892{
2893 struct set_engine_clock_parameters_v2_1 clockinfo;
2894 uint32_t reserved[10];
2895};
2896
2897
2898enum atom_set_engine_mem_clock_flag
2899{
2900 b3NORMAL_CHANGE_CLOCK = 0,
2901 b3FIRST_TIME_CHANGE_CLOCK = 0x08,
2902 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result
2903};
2904
2905/*
2906 ***************************************************************************
2907 Structures used by getengineclock
2908 ***************************************************************************
2909*/
2910struct get_engine_clock_parameter
2911{
2912 uint32_t sclk_10khz; // current engine speed in 10KHz unit
2913 uint32_t reserved;
2914};
2915
2916/*
2917 ***************************************************************************
2918 Structures used by setmemoryclock
2919 ***************************************************************************
2920*/
2921struct set_memory_clock_parameters_v2_1
2922{
2923 uint32_t mclkfreqin10khz:24;
2924 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
2925 uint32_t reserved[10];
2926};
2927
2928struct set_memory_clock_ps_allocation_v2_1
2929{
2930 struct set_memory_clock_parameters_v2_1 clockinfo;
2931 uint32_t reserved[10];
2932};
2933
2934
2935/*
2936 ***************************************************************************
2937 Structures used by getmemoryclock
2938 ***************************************************************************
2939*/
2940struct get_memory_clock_parameter
2941{
2942 uint32_t mclk_10khz; // current engine speed in 10KHz unit
2943 uint32_t reserved;
2944};
2945
2946
2947
2948/*
2949 ***************************************************************************
2950 Structures used by setvoltage
2951 ***************************************************************************
2952*/
2953
2954struct set_voltage_parameters_v1_4
2955{
2956 uint8_t voltagetype; /* enum atom_voltage_type */
2957 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */
2958 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */
2959};
2960
2961//set_voltage_parameters_v2_1.voltagemode
2962enum atom_set_voltage_command{
2963 ATOM_SET_VOLTAGE = 0,
2964 ATOM_INIT_VOLTAGE_REGULATOR = 3,
2965 ATOM_SET_VOLTAGE_PHASE = 4,
2966 ATOM_GET_LEAKAGE_ID = 8,
2967};
2968
2969struct set_voltage_ps_allocation_v1_4
2970{
2971 struct set_voltage_parameters_v1_4 setvoltageparam;
2972 uint32_t reserved[10];
2973};
2974
2975
2976/*
2977 ***************************************************************************
2978 Structures used by computegpuclockparam
2979 ***************************************************************************
2980*/
2981
2982//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
2983enum atom_gpu_clock_type
2984{
2985 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
2986 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
2987 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
2988};
2989
2990struct compute_gpu_clock_input_parameter_v1_8
2991{
2992 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
2993 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type
2994 uint32_t reserved[5];
2995};
2996
2997
2998struct compute_gpu_clock_output_parameter_v1_8
2999{
3000 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
3001 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly
3002 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
3003 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac
3004 uint16_t pll_ss_slew_frac;
3005 uint8_t pll_ss_enable;
3006 uint8_t reserved;
3007 uint32_t reserved1[2];
3008};
3009
3010
3011
3012/*
3013 ***************************************************************************
3014 Structures used by ReadEfuseValue
3015 ***************************************************************************
3016*/
3017
3018struct read_efuse_input_parameters_v3_1
3019{
3020 uint16_t efuse_start_index;
3021 uint8_t reserved;
3022 uint8_t bitslen;
3023};
3024
3025// ReadEfuseValue input/output parameter
3026union read_efuse_value_parameters_v3_1
3027{
3028 struct read_efuse_input_parameters_v3_1 efuse_info;
3029 uint32_t efusevalue;
3030};
3031
3032
3033/*
3034 ***************************************************************************
3035 Structures used by getsmuclockinfo
3036 ***************************************************************************
3037*/
3038struct atom_get_smu_clock_info_parameters_v3_1
3039{
3040 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
3041 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3042 uint8_t command; // enum of atom_get_smu_clock_info_command
3043 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3044};
3045
3046enum atom_get_smu_clock_info_command
3047{
3048 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0,
3049 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1,
3050 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2,
3051};
3052
3053enum atom_smu9_syspll0_clock_id
3054{
3055 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK
3056 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK)
3057 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
3058 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK
3059 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK
3060 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK
3061 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK
3062 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK
3063 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK
3064 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK
3065 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
3066};
3067
3068enum atom_smu11_syspll_id {
3069 SMU11_SYSPLL0_ID = 0,
3070 SMU11_SYSPLL1_0_ID = 1,
3071 SMU11_SYSPLL1_1_ID = 2,
3072 SMU11_SYSPLL1_2_ID = 3,
3073 SMU11_SYSPLL2_ID = 4,
3074 SMU11_SYSPLL3_0_ID = 5,
3075 SMU11_SYSPLL3_1_ID = 6,
3076};
3077
3078enum atom_smu11_syspll0_clock_id {
3079 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK
3080 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK
3081 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
3082 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK
3083 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK
3084 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
3085};
3086
3087enum atom_smu11_syspll1_0_clock_id {
3088 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
3089};
3090
3091enum atom_smu11_syspll1_1_clock_id {
3092 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
3093};
3094
3095enum atom_smu11_syspll1_2_clock_id {
3096 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
3097};
3098
3099enum atom_smu11_syspll2_clock_id {
3100 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
3101};
3102
3103enum atom_smu11_syspll3_0_clock_id {
3104 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
3105 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
3106 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
3107};
3108
3109enum atom_smu11_syspll3_1_clock_id {
3110 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
3111 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
3112 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
3113};
3114
3115struct atom_get_smu_clock_info_output_parameters_v3_1
3116{
3117 union {
3118 uint32_t smu_clock_freq_hz;
3119 uint32_t syspllvcofreq_10khz;
3120 uint32_t sysspllrefclk_10khz;
3121 }atom_smu_outputclkfreq;
3122};
3123
3124
3125
3126/*
3127 ***************************************************************************
3128 Structures used by dynamicmemorysettings
3129 ***************************************************************************
3130*/
3131
3132enum atom_dynamic_memory_setting_command
3133{
3134 COMPUTE_MEMORY_PLL_PARAM = 1,
3135 COMPUTE_ENGINE_PLL_PARAM = 2,
3136 ADJUST_MC_SETTING_PARAM = 3,
3137};
3138
3139/* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */
3140struct dynamic_mclk_settings_parameters_v2_1
3141{
3142 uint32_t mclk_10khz:24; //Input= target mclk
3143 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
3144 uint32_t reserved;
3145};
3146
3147/* when command = COMPUTE_ENGINE_PLL_PARAM */
3148struct dynamic_sclk_settings_parameters_v2_1
3149{
3150 uint32_t sclk_10khz:24; //Input= target mclk
3151 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
3152 uint32_t mclk_10khz;
3153 uint32_t reserved;
3154};
3155
3156union dynamic_memory_settings_parameters_v2_1
3157{
3158 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting;
3159 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting;
3160};
3161
3162
3163
3164/*
3165 ***************************************************************************
3166 Structures used by memorytraining
3167 ***************************************************************************
3168*/
3169
3170enum atom_umc6_0_ucode_function_call_enum_id
3171{
3172 UMC60_UCODE_FUNC_ID_REINIT = 0,
3173 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1,
3174 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2,
3175};
3176
3177
3178struct memory_training_parameters_v2_1
3179{
3180 uint8_t ucode_func_id;
3181 uint8_t ucode_reserved[3];
3182 uint32_t reserved[5];
3183};
3184
3185
3186/*
3187 ***************************************************************************
3188 Structures used by setpixelclock
3189 ***************************************************************************
3190*/
3191
3192struct set_pixel_clock_parameter_v1_7
3193{
3194 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
3195
3196 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
3197 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
3198 // indicate which graphic encoder will be used.
3199 uint8_t encoder_mode; // Encoder mode:
3200 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
3201 uint8_t crtc_id; // enum of atom_crtc_def
3202 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
3203 uint8_t reserved1[2];
3204 uint32_t reserved2;
3205};
3206
3207//ucMiscInfo
3208enum atom_set_pixel_clock_v1_7_misc_info
3209{
3210 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01,
3211 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02,
3212 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04,
3213 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08,
3214 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30,
3215 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00,
3216 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10,
3217 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20,
3218 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30,
3219 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40,
3220 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80,
3221};
3222
3223/* deep_color_ratio */
3224enum atom_set_pixel_clock_v1_7_deepcolor_ratio
3225{
3226 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
3227 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
3228 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
3229 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
3230};
3231
3232/*
3233 ***************************************************************************
3234 Structures used by setdceclock
3235 ***************************************************************************
3236*/
3237
3238// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above
3239struct set_dce_clock_parameters_v2_1
3240{
3241 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
3242 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
3243 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
3244 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
3245 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
3246};
3247
3248//ucDCEClkType
3249enum atom_set_dce_clock_clock_type
3250{
3251 DCE_CLOCK_TYPE_DISPCLK = 0,
3252 DCE_CLOCK_TYPE_DPREFCLK = 1,
3253 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock
3254};
3255
3256//ucDCEClkFlag when ucDCEClkType == DPREFCLK
3257enum atom_set_dce_clock_dprefclk_flag
3258{
3259 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03,
3260 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00,
3261 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01,
3262 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02,
3263 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03,
3264};
3265
3266//ucDCEClkFlag when ucDCEClkType == PIXCLK
3267enum atom_set_dce_clock_pixclk_flag
3268{
3269 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03,
3270 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
3271 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
3272 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
3273 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
3274 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04,
3275};
3276
3277struct set_dce_clock_ps_allocation_v2_1
3278{
3279 struct set_dce_clock_parameters_v2_1 param;
3280 uint32_t ulReserved[2];
3281};
3282
3283
3284/****************************************************************************/
3285// Structures used by BlankCRTC
3286/****************************************************************************/
3287struct blank_crtc_parameters
3288{
3289 uint8_t crtc_id; // enum atom_crtc_def
3290 uint8_t blanking; // enum atom_blank_crtc_command
3291 uint16_t reserved;
3292 uint32_t reserved1;
3293};
3294
3295enum atom_blank_crtc_command
3296{
3297 ATOM_BLANKING = 1,
3298 ATOM_BLANKING_OFF = 0,
3299};
3300
3301/****************************************************************************/
3302// Structures used by enablecrtc
3303/****************************************************************************/
3304struct enable_crtc_parameters
3305{
3306 uint8_t crtc_id; // enum atom_crtc_def
3307 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
3308 uint8_t padding[2];
3309};
3310
3311
3312/****************************************************************************/
3313// Structure used by EnableDispPowerGating
3314/****************************************************************************/
3315struct enable_disp_power_gating_parameters_v2_1
3316{
3317 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
3318 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
3319 uint8_t padding[2];
3320};
3321
3322struct enable_disp_power_gating_ps_allocation
3323{
3324 struct enable_disp_power_gating_parameters_v2_1 param;
3325 uint32_t ulReserved[4];
3326};
3327
3328/****************************************************************************/
3329// Structure used in setcrtc_usingdtdtiming
3330/****************************************************************************/
3331struct set_crtc_using_dtd_timing_parameters
3332{
3333 uint16_t h_size;
3334 uint16_t h_blanking_time;
3335 uint16_t v_size;
3336 uint16_t v_blanking_time;
3337 uint16_t h_syncoffset;
3338 uint16_t h_syncwidth;
3339 uint16_t v_syncoffset;
3340 uint16_t v_syncwidth;
3341 uint16_t modemiscinfo;
3342 uint8_t h_border;
3343 uint8_t v_border;
3344 uint8_t crtc_id; // enum atom_crtc_def
3345 uint8_t encoder_mode; // atom_encode_mode_def
3346 uint8_t padding[2];
3347};
3348
3349
3350/****************************************************************************/
3351// Structures used by processi2cchanneltransaction
3352/****************************************************************************/
3353struct process_i2c_channel_transaction_parameters
3354{
3355 uint8_t i2cspeed_khz;
3356 union {
3357 uint8_t regindex;
3358 uint8_t status; /* enum atom_process_i2c_flag */
3359 } regind_status;
3360 uint16_t i2c_data_out;
3361 uint8_t flag; /* enum atom_process_i2c_status */
3362 uint8_t trans_bytes;
3363 uint8_t slave_addr;
3364 uint8_t i2c_id;
3365};
3366
3367//ucFlag
3368enum atom_process_i2c_flag
3369{
3370 HW_I2C_WRITE = 1,
3371 HW_I2C_READ = 0,
3372 I2C_2BYTE_ADDR = 0x02,
3373 HW_I2C_SMBUS_BYTE_WR = 0x04,
3374};
3375
3376//status
3377enum atom_process_i2c_status
3378{
3379 HW_ASSISTED_I2C_STATUS_FAILURE =2,
3380 HW_ASSISTED_I2C_STATUS_SUCCESS =1,
3381};
3382
3383
3384/****************************************************************************/
3385// Structures used by processauxchanneltransaction
3386/****************************************************************************/
3387
3388struct process_aux_channel_transaction_parameters_v1_2
3389{
3390 uint16_t aux_request;
3391 uint16_t dataout;
3392 uint8_t channelid;
3393 union {
3394 uint8_t reply_status;
3395 uint8_t aux_delay;
3396 } aux_status_delay;
3397 uint8_t dataout_len;
3398 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
3399};
3400
3401
3402/****************************************************************************/
3403// Structures used by selectcrtc_source
3404/****************************************************************************/
3405
3406struct select_crtc_source_parameters_v2_3
3407{
3408 uint8_t crtc_id; // enum atom_crtc_def
3409 uint8_t encoder_id; // enum atom_dig_def
3410 uint8_t encode_mode; // enum atom_encode_mode_def
3411 uint8_t dst_bpc; // enum atom_panel_bit_per_color
3412};
3413
3414
3415/****************************************************************************/
3416// Structures used by digxencodercontrol
3417/****************************************************************************/
3418
3419// ucAction:
3420enum atom_dig_encoder_control_action
3421{
3422 ATOM_ENCODER_CMD_DISABLE_DIG = 0,
3423 ATOM_ENCODER_CMD_ENABLE_DIG = 1,
3424 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08,
3425 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09,
3426 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a,
3427 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13,
3428 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b,
3429 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c,
3430 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d,
3431 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10,
3432 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14,
3433 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F,
3434 ATOM_ENCODER_CMD_LINK_SETUP = 0x11,
3435 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12,
3436};
3437
3438//define ucPanelMode
3439enum atom_dig_encoder_control_panelmode
3440{
3441 DP_PANEL_MODE_DISABLE = 0x00,
3442 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01,
3443 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11,
3444};
3445
3446//ucDigId
3447enum atom_dig_encoder_control_v5_digid
3448{
3449 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00,
3450 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01,
3451 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02,
3452 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03,
3453 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04,
3454 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05,
3455 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06,
3456 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07,
3457};
3458
3459struct dig_encoder_stream_setup_parameters_v1_5
3460{
3461 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3462 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
3463 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
3464 uint8_t lanenum; // Lane number
3465 uint32_t pclk_10khz; // Pixel Clock in 10Khz
3466 uint8_t bitpercolor;
3467 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
3468 uint8_t reserved[2];
3469};
3470
3471struct dig_encoder_link_setup_parameters_v1_5
3472{
3473 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3474 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
3475 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
3476 uint8_t lanenum; // Lane number
3477 uint8_t symclk_10khz; // Symbol Clock in 10Khz
3478 uint8_t hpd_sel;
3479 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
3480 uint8_t reserved[2];
3481};
3482
3483struct dp_panel_mode_set_parameters_v1_5
3484{
3485 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3486 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
3487 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
3488 uint8_t reserved1;
3489 uint32_t reserved2[2];
3490};
3491
3492struct dig_encoder_generic_cmd_parameters_v1_5
3493{
3494 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3495 uint8_t action; // = rest of generic encoder command which does not carry any parameters
3496 uint8_t reserved1[2];
3497 uint32_t reserved2[2];
3498};
3499
3500union dig_encoder_control_parameters_v1_5
3501{
3502 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param;
3503 struct dig_encoder_stream_setup_parameters_v1_5 stream_param;
3504 struct dig_encoder_link_setup_parameters_v1_5 link_param;
3505 struct dp_panel_mode_set_parameters_v1_5 dppanel_param;
3506};
3507
3508/*
3509 ***************************************************************************
3510 Structures used by dig1transmittercontrol
3511 ***************************************************************************
3512*/
3513struct dig_transmitter_control_parameters_v1_6
3514{
3515 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
3516 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
3517 union {
3518 uint8_t digmode; // enum atom_encode_mode_def
3519 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
3520 } mode_laneset;
3521 uint8_t lanenum; // Lane number 1, 2, 4, 8
3522 uint32_t symclk_10khz; // Symbol Clock in 10Khz
3523 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
3524 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
3525 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
3526 uint8_t reserved;
3527 uint32_t reserved1;
3528};
3529
3530struct dig_transmitter_control_ps_allocation_v1_6
3531{
3532 struct dig_transmitter_control_parameters_v1_6 param;
3533 uint32_t reserved[4];
3534};
3535
3536//ucAction
3537enum atom_dig_transmitter_control_action
3538{
3539 ATOM_TRANSMITTER_ACTION_DISABLE = 0,
3540 ATOM_TRANSMITTER_ACTION_ENABLE = 1,
3541 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2,
3542 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3,
3543 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4,
3544 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5,
3545 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6,
3546 ATOM_TRANSMITTER_ACTION_INIT = 7,
3547 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8,
3548 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9,
3549 ATOM_TRANSMITTER_ACTION_SETUP = 10,
3550 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11,
3551 ATOM_TRANSMITTER_ACTION_POWER_ON = 12,
3552 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13,
3553};
3554
3555// digfe_sel
3556enum atom_dig_transmitter_control_digfe_sel
3557{
3558 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01,
3559 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02,
3560 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04,
3561 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08,
3562 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10,
3563 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20,
3564 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40,
3565};
3566
3567
3568//ucHPDSel
3569enum atom_dig_transmitter_control_hpd_sel
3570{
3571 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00,
3572 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01,
3573 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02,
3574 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03,
3575 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04,
3576 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05,
3577 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06,
3578};
3579
3580// ucDPLaneSet
3581enum atom_dig_transmitter_control_dplaneset
3582{
3583 DP_LANE_SET__0DB_0_4V = 0x00,
3584 DP_LANE_SET__0DB_0_6V = 0x01,
3585 DP_LANE_SET__0DB_0_8V = 0x02,
3586 DP_LANE_SET__0DB_1_2V = 0x03,
3587 DP_LANE_SET__3_5DB_0_4V = 0x08,
3588 DP_LANE_SET__3_5DB_0_6V = 0x09,
3589 DP_LANE_SET__3_5DB_0_8V = 0x0a,
3590 DP_LANE_SET__6DB_0_4V = 0x10,
3591 DP_LANE_SET__6DB_0_6V = 0x11,
3592 DP_LANE_SET__9_5DB_0_4V = 0x18,
3593};
3594
3595
3596
3597/****************************************************************************/
3598// Structures used by ExternalEncoderControl V2.4
3599/****************************************************************************/
3600
3601struct external_encoder_control_parameters_v2_4
3602{
3603 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
3604 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
3605 uint8_t action; //
3606 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
3607 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
3608 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
3609 uint8_t hpd_id;
3610};
3611
3612
3613// ucAction
3614enum external_encoder_control_action_def
3615{
3616 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00,
3617 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01,
3618 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07,
3619 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f,
3620 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10,
3621 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11,
3622 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12,
3623 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14,
3624};
3625
3626// ucConfig
3627enum external_encoder_control_v2_4_config_def
3628{
3629 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03,
3630 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00,
3631 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01,
3632 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02,
3633 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03,
3634 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70,
3635 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00,
3636 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10,
3637 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20,
3638};
3639
3640struct external_encoder_control_ps_allocation_v2_4
3641{
3642 struct external_encoder_control_parameters_v2_4 sExtEncoder;
3643 uint32_t reserved[2];
3644};
3645
3646
3647/*
3648 ***************************************************************************
3649 AMD ACPI Table
3650
3651 ***************************************************************************
3652*/
3653
3654struct amd_acpi_description_header{
3655 uint32_t signature;
3656 uint32_t tableLength; //Length
3657 uint8_t revision;
3658 uint8_t checksum;
3659 uint8_t oemId[6];
3660 uint8_t oemTableId[8]; //UINT64 OemTableId;
3661 uint32_t oemRevision;
3662 uint32_t creatorId;
3663 uint32_t creatorRevision;
3664};
3665
3666struct uefi_acpi_vfct{
3667 struct amd_acpi_description_header sheader;
3668 uint8_t tableUUID[16]; //0x24
3669 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
3670 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
3671 uint32_t reserved[4]; //0x3C
3672};
3673
3674struct vfct_image_header{
3675 uint32_t pcibus; //0x4C
3676 uint32_t pcidevice; //0x50
3677 uint32_t pcifunction; //0x54
3678 uint16_t vendorid; //0x58
3679 uint16_t deviceid; //0x5A
3680 uint16_t ssvid; //0x5C
3681 uint16_t ssid; //0x5E
3682 uint32_t revision; //0x60
3683 uint32_t imagelength; //0x64
3684};
3685
3686
3687struct gop_vbios_content {
3688 struct vfct_image_header vbiosheader;
3689 uint8_t vbioscontent[1];
3690};
3691
3692struct gop_lib1_content {
3693 struct vfct_image_header lib1header;
3694 uint8_t lib1content[1];
3695};
3696
3697
3698
3699/*
3700 ***************************************************************************
3701 Scratch Register definitions
3702 Each number below indicates which scratch regiser request, Active and
3703 Connect all share the same definitions as display_device_tag defines
3704 ***************************************************************************
3705*/
3706
3707enum scratch_register_def{
3708 ATOM_DEVICE_CONNECT_INFO_DEF = 0,
3709 ATOM_BL_BRI_LEVEL_INFO_DEF = 2,
3710 ATOM_ACTIVE_INFO_DEF = 3,
3711 ATOM_LCD_INFO_DEF = 4,
3712 ATOM_DEVICE_REQ_INFO_DEF = 5,
3713 ATOM_ACC_CHANGE_INFO_DEF = 6,
3714 ATOM_PRE_OS_MODE_INFO_DEF = 7,
3715 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers.
3716 ATOM_INTERNAL_TIMER_INFO_DEF = 10,
3717};
3718
3719enum scratch_device_connect_info_bit_def{
3720 ATOM_DISPLAY_LCD1_CONNECT =0x0002,
3721 ATOM_DISPLAY_DFP1_CONNECT =0x0008,
3722 ATOM_DISPLAY_DFP2_CONNECT =0x0080,
3723 ATOM_DISPLAY_DFP3_CONNECT =0x0200,
3724 ATOM_DISPLAY_DFP4_CONNECT =0x0400,
3725 ATOM_DISPLAY_DFP5_CONNECT =0x0800,
3726 ATOM_DISPLAY_DFP6_CONNECT =0x0040,
3727 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8,
3728 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff,
3729};
3730
3731enum scratch_bl_bri_level_info_bit_def{
3732 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8,
3733#ifndef _H2INC
3734 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00,
3735 ATOM_DEVICE_DPMS_STATE =0x00010000,
3736#endif
3737};
3738
3739enum scratch_active_info_bits_def{
3740 ATOM_DISPLAY_LCD1_ACTIVE =0x0002,
3741 ATOM_DISPLAY_DFP1_ACTIVE =0x0008,
3742 ATOM_DISPLAY_DFP2_ACTIVE =0x0080,
3743 ATOM_DISPLAY_DFP3_ACTIVE =0x0200,
3744 ATOM_DISPLAY_DFP4_ACTIVE =0x0400,
3745 ATOM_DISPLAY_DFP5_ACTIVE =0x0800,
3746 ATOM_DISPLAY_DFP6_ACTIVE =0x0040,
3747 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff,
3748};
3749
3750enum scratch_device_req_info_bits_def{
3751 ATOM_DISPLAY_LCD1_REQ =0x0002,
3752 ATOM_DISPLAY_DFP1_REQ =0x0008,
3753 ATOM_DISPLAY_DFP2_REQ =0x0080,
3754 ATOM_DISPLAY_DFP3_REQ =0x0200,
3755 ATOM_DISPLAY_DFP4_REQ =0x0400,
3756 ATOM_DISPLAY_DFP5_REQ =0x0800,
3757 ATOM_DISPLAY_DFP6_REQ =0x0040,
3758 ATOM_REQ_INFO_DEVICE_MASK =0x0fff,
3759};
3760
3761enum scratch_acc_change_info_bitshift_def{
3762 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4,
3763 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6,
3764};
3765
3766enum scratch_acc_change_info_bits_def{
3767 ATOM_ACC_CHANGE_ACC_MODE =0x00000010,
3768 ATOM_ACC_CHANGE_LID_STATUS =0x00000040,
3769};
3770
3771enum scratch_pre_os_mode_info_bits_def{
3772 ATOM_PRE_OS_MODE_MASK =0x00000003,
3773 ATOM_PRE_OS_MODE_VGA =0x00000000,
3774 ATOM_PRE_OS_MODE_VESA =0x00000001,
3775 ATOM_PRE_OS_MODE_GOP =0x00000002,
3776 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C,
3777 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
3778 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100,
3779 ATOM_ASIC_INIT_COMPLETE =0x00000200,
3780#ifndef _H2INC
3781 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000,
3782#endif
3783};
3784
3785
3786
3787/*
3788 ***************************************************************************
3789 ATOM firmware ID header file
3790 !! Please keep it at end of the atomfirmware.h !!
3791 ***************************************************************************
3792*/
3793#include "atomfirmwareid.h"
3794#pragma pack()
3795
3796#endif
3797
1/****************************************************************************\
2*
3* File Name atomfirmware.h
4* Project This is an interface header file between atombios and OS GPU drivers for SoC15 products
5*
6* Description header file of general definitions for OS and pre-OS video drivers
7*
8* Copyright 2014 Advanced Micro Devices, Inc.
9*
10* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
11* and associated documentation files (the "Software"), to deal in the Software without restriction,
12* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
13* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
14* subject to the following conditions:
15*
16* The above copyright notice and this permission notice shall be included in all copies or substantial
17* portions of the Software.
18*
19* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25* OTHER DEALINGS IN THE SOFTWARE.
26*
27\****************************************************************************/
28
29/*IMPORTANT NOTES
30* If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file.
31* If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file.
32* If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h.
33*/
34
35#ifndef _ATOMFIRMWARE_H_
36#define _ATOMFIRMWARE_H_
37
38enum atom_bios_header_version_def{
39 ATOM_MAJOR_VERSION =0x0003,
40 ATOM_MINOR_VERSION =0x0003,
41};
42
43#ifdef _H2INC
44 #ifndef uint32_t
45 typedef unsigned long uint32_t;
46 #endif
47
48 #ifndef uint16_t
49 typedef unsigned short uint16_t;
50 #endif
51
52 #ifndef uint8_t
53 typedef unsigned char uint8_t;
54 #endif
55#endif
56
57enum atom_crtc_def{
58 ATOM_CRTC1 =0,
59 ATOM_CRTC2 =1,
60 ATOM_CRTC3 =2,
61 ATOM_CRTC4 =3,
62 ATOM_CRTC5 =4,
63 ATOM_CRTC6 =5,
64 ATOM_CRTC_INVALID =0xff,
65};
66
67enum atom_ppll_def{
68 ATOM_PPLL0 =2,
69 ATOM_GCK_DFS =8,
70 ATOM_FCH_CLK =9,
71 ATOM_DP_DTO =11,
72 ATOM_COMBOPHY_PLL0 =20,
73 ATOM_COMBOPHY_PLL1 =21,
74 ATOM_COMBOPHY_PLL2 =22,
75 ATOM_COMBOPHY_PLL3 =23,
76 ATOM_COMBOPHY_PLL4 =24,
77 ATOM_COMBOPHY_PLL5 =25,
78 ATOM_PPLL_INVALID =0xff,
79};
80
81// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
82enum atom_dig_def{
83 ASIC_INT_DIG1_ENCODER_ID =0x03,
84 ASIC_INT_DIG2_ENCODER_ID =0x09,
85 ASIC_INT_DIG3_ENCODER_ID =0x0a,
86 ASIC_INT_DIG4_ENCODER_ID =0x0b,
87 ASIC_INT_DIG5_ENCODER_ID =0x0c,
88 ASIC_INT_DIG6_ENCODER_ID =0x0d,
89 ASIC_INT_DIG7_ENCODER_ID =0x0e,
90};
91
92//ucEncoderMode
93enum atom_encode_mode_def
94{
95 ATOM_ENCODER_MODE_DP =0,
96 ATOM_ENCODER_MODE_DP_SST =0,
97 ATOM_ENCODER_MODE_LVDS =1,
98 ATOM_ENCODER_MODE_DVI =2,
99 ATOM_ENCODER_MODE_HDMI =3,
100 ATOM_ENCODER_MODE_DP_AUDIO =5,
101 ATOM_ENCODER_MODE_DP_MST =5,
102 ATOM_ENCODER_MODE_CRT =15,
103 ATOM_ENCODER_MODE_DVO =16,
104};
105
106enum atom_encoder_refclk_src_def{
107 ENCODER_REFCLK_SRC_P1PLL =0,
108 ENCODER_REFCLK_SRC_P2PLL =1,
109 ENCODER_REFCLK_SRC_P3PLL =2,
110 ENCODER_REFCLK_SRC_EXTCLK =3,
111 ENCODER_REFCLK_SRC_INVALID =0xff,
112};
113
114enum atom_scaler_def{
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/
118};
119
120enum atom_operation_def{
121 ATOM_DISABLE = 0,
122 ATOM_ENABLE = 1,
123 ATOM_INIT = 7,
124 ATOM_GET_STATUS = 8,
125};
126
127enum atom_embedded_display_op_def{
128 ATOM_LCD_BL_OFF = 2,
129 ATOM_LCD_BL_OM = 3,
130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4,
131 ATOM_LCD_SELFTEST_START = 5,
132 ATOM_LCD_SELFTEST_STOP = 6,
133};
134
135enum atom_spread_spectrum_mode{
136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01,
137 ATOM_SS_DOWN_SPREAD_MODE = 0x00,
138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01,
139 ATOM_INT_OR_EXT_SS_MASK = 0x02,
140 ATOM_INTERNAL_SS_MASK = 0x00,
141 ATOM_EXTERNAL_SS_MASK = 0x02,
142};
143
144/* define panel bit per color */
145enum atom_panel_bit_per_color{
146 PANEL_BPC_UNDEFINE =0x00,
147 PANEL_6BIT_PER_COLOR =0x01,
148 PANEL_8BIT_PER_COLOR =0x02,
149 PANEL_10BIT_PER_COLOR =0x03,
150 PANEL_12BIT_PER_COLOR =0x04,
151 PANEL_16BIT_PER_COLOR =0x05,
152};
153
154//ucVoltageType
155enum atom_voltage_type
156{
157 VOLTAGE_TYPE_VDDC = 1,
158 VOLTAGE_TYPE_MVDDC = 2,
159 VOLTAGE_TYPE_MVDDQ = 3,
160 VOLTAGE_TYPE_VDDCI = 4,
161 VOLTAGE_TYPE_VDDGFX = 5,
162 VOLTAGE_TYPE_PCC = 6,
163 VOLTAGE_TYPE_MVPP = 7,
164 VOLTAGE_TYPE_LEDDPM = 8,
165 VOLTAGE_TYPE_PCC_MVDD = 9,
166 VOLTAGE_TYPE_PCIE_VDDC = 10,
167 VOLTAGE_TYPE_PCIE_VDDR = 11,
168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
178};
179
180enum atom_dgpu_vram_type {
181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60,
183 ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61,
184 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70,
185 ATOM_DGPU_VRAM_TYPE_HBM3 = 0x80,
186};
187
188enum atom_dp_vs_preemph_def{
189 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
190 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
191 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
192 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
193 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
194 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
195 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
196 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
197 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
198 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
199};
200
201#define BIOS_ATOM_PREFIX "ATOMBIOS"
202#define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
203#define BIOS_STRING_LENGTH 43
204
205/*
206enum atom_string_def{
207asic_bus_type_pcie_string = "PCI_EXPRESS",
208atom_fire_gl_string = "FGL",
209atom_bios_string = "ATOM"
210};
211*/
212
213#pragma pack(1) /* BIOS data must use byte aligment*/
214
215enum atombios_image_offset{
216 OFFSET_TO_ATOM_ROM_HEADER_POINTER = 0x00000048,
217 OFFSET_TO_ATOM_ROM_IMAGE_SIZE = 0x00000002,
218 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE = 0x94,
219 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE = 20, /*including the terminator 0x0!*/
220 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS = 0x2f,
221 OFFSET_TO_GET_ATOMBIOS_STRING_START = 0x6e,
222 OFFSET_TO_VBIOS_PART_NUMBER = 0x80,
223 OFFSET_TO_VBIOS_DATE = 0x50,
224};
225
226/****************************************************************************
227* Common header for all tables (Data table, Command function).
228* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.
229* And the pointer actually points to this header.
230****************************************************************************/
231
232struct atom_common_table_header
233{
234 uint16_t structuresize;
235 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible
236 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change
237};
238
239/****************************************************************************
240* Structure stores the ROM header.
241****************************************************************************/
242struct atom_rom_header_v2_2
243{
244 struct atom_common_table_header table_header;
245 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
246 uint16_t bios_segment_address;
247 uint16_t protectedmodeoffset;
248 uint16_t configfilenameoffset;
249 uint16_t crc_block_offset;
250 uint16_t vbios_bootupmessageoffset;
251 uint16_t int10_offset;
252 uint16_t pcibusdevinitcode;
253 uint16_t iobaseaddress;
254 uint16_t subsystem_vendor_id;
255 uint16_t subsystem_id;
256 uint16_t pci_info_offset;
257 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position
258 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position
259 uint16_t reserved;
260 uint32_t pspdirtableoffset;
261};
262
263/*==============================hw function portion======================================================================*/
264
265
266/****************************************************************************
267* Structures used in Command.mtb, each function name is not given here since those function could change from time to time
268* The real functionality of each function is associated with the parameter structure version when defined
269* For all internal cmd function definitions, please reference to atomstruct.h
270****************************************************************************/
271struct atom_master_list_of_command_functions_v2_1{
272 uint16_t asic_init; //Function
273 uint16_t cmd_function1; //used as an internal one
274 uint16_t cmd_function2; //used as an internal one
275 uint16_t cmd_function3; //used as an internal one
276 uint16_t digxencodercontrol; //Function
277 uint16_t cmd_function5; //used as an internal one
278 uint16_t cmd_function6; //used as an internal one
279 uint16_t cmd_function7; //used as an internal one
280 uint16_t cmd_function8; //used as an internal one
281 uint16_t cmd_function9; //used as an internal one
282 uint16_t setengineclock; //Function
283 uint16_t setmemoryclock; //Function
284 uint16_t setpixelclock; //Function
285 uint16_t enabledisppowergating; //Function
286 uint16_t cmd_function14; //used as an internal one
287 uint16_t cmd_function15; //used as an internal one
288 uint16_t cmd_function16; //used as an internal one
289 uint16_t cmd_function17; //used as an internal one
290 uint16_t cmd_function18; //used as an internal one
291 uint16_t cmd_function19; //used as an internal one
292 uint16_t cmd_function20; //used as an internal one
293 uint16_t cmd_function21; //used as an internal one
294 uint16_t cmd_function22; //used as an internal one
295 uint16_t cmd_function23; //used as an internal one
296 uint16_t cmd_function24; //used as an internal one
297 uint16_t cmd_function25; //used as an internal one
298 uint16_t cmd_function26; //used as an internal one
299 uint16_t cmd_function27; //used as an internal one
300 uint16_t cmd_function28; //used as an internal one
301 uint16_t cmd_function29; //used as an internal one
302 uint16_t cmd_function30; //used as an internal one
303 uint16_t cmd_function31; //used as an internal one
304 uint16_t cmd_function32; //used as an internal one
305 uint16_t cmd_function33; //used as an internal one
306 uint16_t blankcrtc; //Function
307 uint16_t enablecrtc; //Function
308 uint16_t cmd_function36; //used as an internal one
309 uint16_t cmd_function37; //used as an internal one
310 uint16_t cmd_function38; //used as an internal one
311 uint16_t cmd_function39; //used as an internal one
312 uint16_t cmd_function40; //used as an internal one
313 uint16_t getsmuclockinfo; //Function
314 uint16_t selectcrtc_source; //Function
315 uint16_t cmd_function43; //used as an internal one
316 uint16_t cmd_function44; //used as an internal one
317 uint16_t cmd_function45; //used as an internal one
318 uint16_t setdceclock; //Function
319 uint16_t getmemoryclock; //Function
320 uint16_t getengineclock; //Function
321 uint16_t setcrtc_usingdtdtiming; //Function
322 uint16_t externalencodercontrol; //Function
323 uint16_t cmd_function51; //used as an internal one
324 uint16_t cmd_function52; //used as an internal one
325 uint16_t cmd_function53; //used as an internal one
326 uint16_t processi2cchanneltransaction;//Function
327 uint16_t cmd_function55; //used as an internal one
328 uint16_t cmd_function56; //used as an internal one
329 uint16_t cmd_function57; //used as an internal one
330 uint16_t cmd_function58; //used as an internal one
331 uint16_t cmd_function59; //used as an internal one
332 uint16_t computegpuclockparam; //Function
333 uint16_t cmd_function61; //used as an internal one
334 uint16_t cmd_function62; //used as an internal one
335 uint16_t dynamicmemorysettings; //Function function
336 uint16_t memorytraining; //Function function
337 uint16_t cmd_function65; //used as an internal one
338 uint16_t cmd_function66; //used as an internal one
339 uint16_t setvoltage; //Function
340 uint16_t cmd_function68; //used as an internal one
341 uint16_t readefusevalue; //Function
342 uint16_t cmd_function70; //used as an internal one
343 uint16_t cmd_function71; //used as an internal one
344 uint16_t cmd_function72; //used as an internal one
345 uint16_t cmd_function73; //used as an internal one
346 uint16_t cmd_function74; //used as an internal one
347 uint16_t cmd_function75; //used as an internal one
348 uint16_t dig1transmittercontrol; //Function
349 uint16_t cmd_function77; //used as an internal one
350 uint16_t processauxchanneltransaction;//Function
351 uint16_t cmd_function79; //used as an internal one
352 uint16_t getvoltageinfo; //Function
353};
354
355struct atom_master_command_function_v2_1
356{
357 struct atom_common_table_header table_header;
358 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions;
359};
360
361/****************************************************************************
362* Structures used in every command function
363****************************************************************************/
364struct atom_function_attribute
365{
366 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
367 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
368 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util
369};
370
371
372/****************************************************************************
373* Common header for all hw functions.
374* Every function pointed by _master_list_of_hw_function has this common header.
375* And the pointer actually points to this header.
376****************************************************************************/
377struct atom_rom_hw_function_header
378{
379 struct atom_common_table_header func_header;
380 struct atom_function_attribute func_attrib;
381};
382
383
384/*==============================sw data table portion======================================================================*/
385/****************************************************************************
386* Structures used in data.mtb, each data table name is not given here since those data table could change from time to time
387* The real name of each table is given when its data structure version is defined
388****************************************************************************/
389struct atom_master_list_of_data_tables_v2_1{
390 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/
391 uint16_t multimedia_info;
392 uint16_t smc_dpm_info;
393 uint16_t sw_datatable3;
394 uint16_t firmwareinfo; /* Shared by various SW components */
395 uint16_t sw_datatable5;
396 uint16_t lcd_info; /* Shared by various SW components */
397 uint16_t sw_datatable7;
398 uint16_t smu_info;
399 uint16_t sw_datatable9;
400 uint16_t sw_datatable10;
401 uint16_t vram_usagebyfirmware; /* Shared by various SW components */
402 uint16_t gpio_pin_lut; /* Shared by various SW components */
403 uint16_t sw_datatable13;
404 uint16_t gfx_info;
405 uint16_t powerplayinfo; /* Shared by various SW components */
406 uint16_t sw_datatable16;
407 uint16_t sw_datatable17;
408 uint16_t sw_datatable18;
409 uint16_t sw_datatable19;
410 uint16_t sw_datatable20;
411 uint16_t sw_datatable21;
412 uint16_t displayobjectinfo; /* Shared by various SW components */
413 uint16_t indirectioaccess; /* used as an internal one */
414 uint16_t umc_info; /* Shared by various SW components */
415 uint16_t sw_datatable25;
416 uint16_t sw_datatable26;
417 uint16_t dce_info; /* Shared by various SW components */
418 uint16_t vram_info; /* Shared by various SW components */
419 uint16_t sw_datatable29;
420 uint16_t integratedsysteminfo; /* Shared by various SW components */
421 uint16_t asic_profiling_info; /* Shared by various SW components */
422 uint16_t voltageobject_info; /* shared by various SW components */
423 uint16_t sw_datatable33;
424 uint16_t sw_datatable34;
425};
426
427
428struct atom_master_data_table_v2_1
429{
430 struct atom_common_table_header table_header;
431 struct atom_master_list_of_data_tables_v2_1 listOfdatatables;
432};
433
434
435struct atom_dtd_format
436{
437 uint16_t pixclk;
438 uint16_t h_active;
439 uint16_t h_blanking_time;
440 uint16_t v_active;
441 uint16_t v_blanking_time;
442 uint16_t h_sync_offset;
443 uint16_t h_sync_width;
444 uint16_t v_sync_offset;
445 uint16_t v_syncwidth;
446 uint16_t reserved;
447 uint16_t reserved0;
448 uint8_t h_border;
449 uint8_t v_border;
450 uint16_t miscinfo;
451 uint8_t atom_mode_id;
452 uint8_t refreshrate;
453};
454
455/* atom_dtd_format.modemiscinfo defintion */
456enum atom_dtd_format_modemiscinfo{
457 ATOM_HSYNC_POLARITY = 0x0002,
458 ATOM_VSYNC_POLARITY = 0x0004,
459 ATOM_H_REPLICATIONBY2 = 0x0010,
460 ATOM_V_REPLICATIONBY2 = 0x0020,
461 ATOM_INTERLACE = 0x0080,
462 ATOM_COMPOSITESYNC = 0x0040,
463};
464
465
466/* utilitypipeline
467 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
468 * the location of it can't change
469*/
470
471
472/*
473 ***************************************************************************
474 Data Table firmwareinfo structure
475 ***************************************************************************
476*/
477
478struct atom_firmware_info_v3_1
479{
480 struct atom_common_table_header table_header;
481 uint32_t firmware_revision;
482 uint32_t bootup_sclk_in10khz;
483 uint32_t bootup_mclk_in10khz;
484 uint32_t firmware_capability; // enum atombios_firmware_capability
485 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
486 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
487 uint16_t bootup_vddc_mv;
488 uint16_t bootup_vddci_mv;
489 uint16_t bootup_mvddc_mv;
490 uint16_t bootup_vddgfx_mv;
491 uint8_t mem_module_id;
492 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
493 uint8_t reserved1[2];
494 uint32_t mc_baseaddr_high;
495 uint32_t mc_baseaddr_low;
496 uint32_t reserved2[6];
497};
498
499/* Total 32bit cap indication */
500enum atombios_firmware_capability
501{
502 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
503 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002,
504 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040,
505 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080,
506 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100,
507 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200,
508 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400,
509 ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000,
510 ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000,
511};
512
513enum atom_cooling_solution_id{
514 AIR_COOLING = 0x00,
515 LIQUID_COOLING = 0x01
516};
517
518struct atom_firmware_info_v3_2 {
519 struct atom_common_table_header table_header;
520 uint32_t firmware_revision;
521 uint32_t bootup_sclk_in10khz;
522 uint32_t bootup_mclk_in10khz;
523 uint32_t firmware_capability; // enum atombios_firmware_capability
524 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
525 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
526 uint16_t bootup_vddc_mv;
527 uint16_t bootup_vddci_mv;
528 uint16_t bootup_mvddc_mv;
529 uint16_t bootup_vddgfx_mv;
530 uint8_t mem_module_id;
531 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
532 uint8_t reserved1[2];
533 uint32_t mc_baseaddr_high;
534 uint32_t mc_baseaddr_low;
535 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
536 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
537 uint8_t board_i2c_feature_slave_addr;
538 uint8_t reserved3;
539 uint16_t bootup_mvddq_mv;
540 uint16_t bootup_mvpp_mv;
541 uint32_t zfbstartaddrin16mb;
542 uint32_t reserved2[3];
543};
544
545struct atom_firmware_info_v3_3
546{
547 struct atom_common_table_header table_header;
548 uint32_t firmware_revision;
549 uint32_t bootup_sclk_in10khz;
550 uint32_t bootup_mclk_in10khz;
551 uint32_t firmware_capability; // enum atombios_firmware_capability
552 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
553 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
554 uint16_t bootup_vddc_mv;
555 uint16_t bootup_vddci_mv;
556 uint16_t bootup_mvddc_mv;
557 uint16_t bootup_vddgfx_mv;
558 uint8_t mem_module_id;
559 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
560 uint8_t reserved1[2];
561 uint32_t mc_baseaddr_high;
562 uint32_t mc_baseaddr_low;
563 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
564 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
565 uint8_t board_i2c_feature_slave_addr;
566 uint8_t reserved3;
567 uint16_t bootup_mvddq_mv;
568 uint16_t bootup_mvpp_mv;
569 uint32_t zfbstartaddrin16mb;
570 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
571 uint32_t reserved2[2];
572};
573
574struct atom_firmware_info_v3_4 {
575 struct atom_common_table_header table_header;
576 uint32_t firmware_revision;
577 uint32_t bootup_sclk_in10khz;
578 uint32_t bootup_mclk_in10khz;
579 uint32_t firmware_capability; // enum atombios_firmware_capability
580 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
581 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
582 uint16_t bootup_vddc_mv;
583 uint16_t bootup_vddci_mv;
584 uint16_t bootup_mvddc_mv;
585 uint16_t bootup_vddgfx_mv;
586 uint8_t mem_module_id;
587 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
588 uint8_t reserved1[2];
589 uint32_t mc_baseaddr_high;
590 uint32_t mc_baseaddr_low;
591 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
592 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
593 uint8_t board_i2c_feature_slave_addr;
594 uint8_t ras_rom_i2c_slave_addr;
595 uint16_t bootup_mvddq_mv;
596 uint16_t bootup_mvpp_mv;
597 uint32_t zfbstartaddrin16mb;
598 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
599 uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2)
600 uint16_t hw_bootup_vddgfx_mv; // hw default vddgfx voltage level decide by board strap
601 uint16_t hw_bootup_vddc_mv; // hw default vddc voltage level decide by board strap
602 uint16_t hw_bootup_mvddc_mv; // hw default mvddc voltage level decide by board strap
603 uint16_t hw_bootup_vddci_mv; // hw default vddci voltage level decide by board strap
604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
606 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb.
607 uint32_t pspbl_init_done_reg_addr;
608 uint32_t pspbl_init_done_value;
609 uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init done
610 uint32_t reserved[2];
611};
612
613struct atom_firmware_info_v3_5 {
614 struct atom_common_table_header table_header;
615 uint32_t firmware_revision;
616 uint32_t bootup_clk_reserved[2];
617 uint32_t firmware_capability; // enum atombios_firmware_capability
618 uint32_t fw_protect_region_size_in_kb; /* FW allocate a write protect region at top of FB. */
619 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
620 uint32_t bootup_voltage_reserved[2];
621 uint8_t mem_module_id;
622 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
623 uint8_t hw_blt_mode; //0:HW_BLT_DMA_PIO_MODE; 1:HW_BLT_LITE_SDMA_MODE; 2:HW_BLT_PCI_IO_MODE
624 uint8_t reserved1;
625 uint32_t mc_baseaddr_high;
626 uint32_t mc_baseaddr_low;
627 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
628 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
629 uint8_t board_i2c_feature_slave_addr;
630 uint8_t ras_rom_i2c_slave_addr;
631 uint32_t bootup_voltage_reserved1;
632 uint32_t zfb_reserved;
633 // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS
634 uint32_t pplib_pptable_id;
635 uint32_t hw_voltage_reserved[3];
636 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
637 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
638 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb.
639 uint32_t pspbl_init_reserved[3];
640 uint32_t spi_rom_size; // GPU spi rom size
641 uint16_t support_dev_in_objinfo;
642 uint16_t disp_phy_tunning_size;
643 uint32_t reserved[16];
644};
645/*
646 ***************************************************************************
647 Data Table lcd_info structure
648 ***************************************************************************
649*/
650
651struct lcd_info_v2_1
652{
653 struct atom_common_table_header table_header;
654 struct atom_dtd_format lcd_timing;
655 uint16_t backlight_pwm;
656 uint16_t special_handle_cap;
657 uint16_t panel_misc;
658 uint16_t lvds_max_slink_pclk;
659 uint16_t lvds_ss_percentage;
660 uint16_t lvds_ss_rate_10hz;
661 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
662 uint8_t pwr_on_de_to_vary_bl;
663 uint8_t pwr_down_vary_bloff_to_de;
664 uint8_t pwr_down_de_to_digoff;
665 uint8_t pwr_off_delay;
666 uint8_t pwr_on_vary_bl_to_blon;
667 uint8_t pwr_down_bloff_to_vary_bloff;
668 uint8_t panel_bpc;
669 uint8_t dpcd_edp_config_cap;
670 uint8_t dpcd_max_link_rate;
671 uint8_t dpcd_max_lane_count;
672 uint8_t dpcd_max_downspread;
673 uint8_t min_allowed_bl_level;
674 uint8_t max_allowed_bl_level;
675 uint8_t bootup_bl_level;
676 uint8_t dplvdsrxid;
677 uint32_t reserved1[8];
678};
679
680/* lcd_info_v2_1.panel_misc defintion */
681enum atom_lcd_info_panel_misc{
682 ATOM_PANEL_MISC_FPDI =0x0002,
683};
684
685//uceDPToLVDSRxId
686enum atom_lcd_info_dptolvds_rx_id
687{
688 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
689 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init
690 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init
691};
692
693
694/*
695 ***************************************************************************
696 Data Table gpio_pin_lut structure
697 ***************************************************************************
698*/
699
700struct atom_gpio_pin_assignment
701{
702 uint32_t data_a_reg_index;
703 uint8_t gpio_bitshift;
704 uint8_t gpio_mask_bitshift;
705 uint8_t gpio_id;
706 uint8_t reserved;
707};
708
709/* atom_gpio_pin_assignment.gpio_id definition */
710enum atom_gpio_pin_assignment_gpio_id {
711 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */
712 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */
713 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */
714
715 /* gpio_id pre-define id for multiple usage */
716 /* GPIO use to control PCIE_VDDC in certain SLT board */
717 PCIE_VDDC_CONTROL_GPIO_PINID = 56,
718 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */
719 PP_AC_DC_SWITCH_GPIO_PINID = 60,
720 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */
721 VDDC_VRHOT_GPIO_PINID = 61,
722 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */
723 VDDC_PCC_GPIO_PINID = 62,
724 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */
725 EFUSE_CUT_ENABLE_GPIO_PINID = 63,
726 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */
727 DRAM_SELF_REFRESH_GPIO_PINID = 64,
728 /* Thermal interrupt output->system thermal chip GPIO pin */
729 THERMAL_INT_OUTPUT_GPIO_PINID =65,
730};
731
732
733struct atom_gpio_pin_lut_v2_1
734{
735 struct atom_common_table_header table_header;
736 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */
737 struct atom_gpio_pin_assignment gpio_pin[];
738};
739
740
741/*
742 * VBIOS/PRE-OS always reserve a FB region at the top of frame buffer. driver should not write
743 * access that region. driver can allocate their own reservation region as long as it does not
744 * overlap firwmare's reservation region.
745 * if (pre-NV1X) atom data table firmwareInfoTable version < 3.3:
746 * in this case, atom data table vram_usagebyfirmwareTable version always <= 2.1
747 * if VBIOS/UEFI GOP is posted:
748 * VBIOS/UEFIGOP update used_by_firmware_in_kb = total reserved size by VBIOS
749 * update start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb;
750 * ( total_mem_size_in_kb = reg(CONFIG_MEMSIZE)<<10)
751 * driver can allocate driver reservation region under firmware reservation,
752 * used_by_driver_in_kb = driver reservation size
753 * driver reservation start address = (start_address_in_kb - used_by_driver_in_kb)
754 * Comment1[hchan]: There is only one reservation at the beginning of the FB reserved by
755 * host driver. Host driver would overwrite the table with the following
756 * used_by_firmware_in_kb = total reserved size for pf-vf info exchange and
757 * set SRIOV_MSG_SHARE_RESERVATION mask start_address_in_kb = 0
758 * else there is no VBIOS reservation region:
759 * driver must allocate driver reservation region at top of FB.
760 * driver set used_by_driver_in_kb = driver reservation size
761 * driver reservation start address = (total_mem_size_in_kb - used_by_driver_in_kb)
762 * same as Comment1
763 * else (NV1X and after):
764 * if VBIOS/UEFI GOP is posted:
765 * VBIOS/UEFIGOP update:
766 * used_by_firmware_in_kb = atom_firmware_Info_v3_3.fw_reserved_size_in_kb;
767 * start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb;
768 * (total_mem_size_in_kb = reg(CONFIG_MEMSIZE)<<10)
769 * if vram_usagebyfirmwareTable version <= 2.1:
770 * driver can allocate driver reservation region under firmware reservation,
771 * driver set used_by_driver_in_kb = driver reservation size
772 * driver reservation start address = start_address_in_kb - used_by_driver_in_kb
773 * same as Comment1
774 * else driver can:
775 * allocate it reservation any place as long as it does overlap pre-OS FW reservation area
776 * set used_by_driver_region0_in_kb = driver reservation size
777 * set driver_region0_start_address_in_kb = driver reservation region start address
778 * Comment2[hchan]: Host driver can set used_by_firmware_in_kb and start_address_in_kb to
779 * zero as the reservation for VF as it doesn’t exist. And Host driver should also
780 * update atom_firmware_Info table to remove the same VBIOS reservation as well.
781 */
782
783struct vram_usagebyfirmware_v2_1
784{
785 struct atom_common_table_header table_header;
786 uint32_t start_address_in_kb;
787 uint16_t used_by_firmware_in_kb;
788 uint16_t used_by_driver_in_kb;
789};
790
791struct vram_usagebyfirmware_v2_2 {
792 struct atom_common_table_header table_header;
793 uint32_t fw_region_start_address_in_kb;
794 uint16_t used_by_firmware_in_kb;
795 uint16_t reserved;
796 uint32_t driver_region0_start_address_in_kb;
797 uint32_t used_by_driver_region0_in_kb;
798 uint32_t reserved32[7];
799};
800
801/*
802 ***************************************************************************
803 Data Table displayobjectinfo structure
804 ***************************************************************************
805*/
806
807enum atom_object_record_type_id {
808 ATOM_I2C_RECORD_TYPE = 1,
809 ATOM_HPD_INT_RECORD_TYPE = 2,
810 ATOM_CONNECTOR_CAP_RECORD_TYPE = 3,
811 ATOM_CONNECTOR_SPEED_UPTO = 4,
812 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE = 9,
813 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE = 16,
814 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE = 17,
815 ATOM_ENCODER_CAP_RECORD_TYPE = 20,
816 ATOM_BRACKET_LAYOUT_RECORD_TYPE = 21,
817 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE = 22,
818 ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE = 23,
819 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE = 25,
820 ATOM_RECORD_END_TYPE = 0xFF,
821};
822
823struct atom_common_record_header
824{
825 uint8_t record_type; //An emun to indicate the record type
826 uint8_t record_size; //The size of the whole record in byte
827};
828
829struct atom_i2c_record
830{
831 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE
832 uint8_t i2c_id;
833 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC
834};
835
836struct atom_hpd_int_record
837{
838 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE
839 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info
840 uint8_t plugin_pin_state;
841};
842
843struct atom_connector_caps_record {
844 struct atom_common_record_header
845 record_header; //record_type = ATOM_CONN_CAP_RECORD_TYPE
846 uint16_t connector_caps; //01b if internal display is checked; 10b if internal BL is checked; 0 of Not
847};
848
849struct atom_connector_speed_record {
850 struct atom_common_record_header
851 record_header; //record_type = ATOM_CONN_SPEED_UPTO
852 uint32_t connector_max_speed; // connector Max speed attribute, it sets 8100 in Mhz when DP connector @8.1Ghz.
853 uint16_t reserved;
854};
855
856// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
857enum atom_encoder_caps_def
858{
859 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
860 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not.
861 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
862 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not.
863 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board.
864 ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board.
865 ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported by board
866 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is supported by board
867 ATOM_ENCODER_CAP_RECORD_UHBR20_EN =0x80, // DP2.0 UHBR20 settings is supported by board
868 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type.
869};
870
871struct atom_encoder_caps_record
872{
873 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE
874 uint32_t encodercaps;
875};
876
877enum atom_connector_caps_def
878{
879 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display
880 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq
881};
882
883struct atom_disp_connector_caps_record
884{
885 struct atom_common_record_header record_header;
886 uint32_t connectcaps;
887};
888
889//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
890struct atom_gpio_pin_control_pair
891{
892 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
893 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
894};
895
896struct atom_object_gpio_cntl_record
897{
898 struct atom_common_record_header record_header;
899 uint8_t flag; // Future expnadibility
900 uint8_t number_of_pins; // Number of GPIO pins used to control the object
901 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
902};
903
904//Definitions for GPIO pin state
905enum atom_gpio_pin_control_pinstate_def
906{
907 GPIO_PIN_TYPE_INPUT = 0x00,
908 GPIO_PIN_TYPE_OUTPUT = 0x10,
909 GPIO_PIN_TYPE_HW_CONTROL = 0x20,
910
911//For GPIO_PIN_TYPE_OUTPUT the following is defined
912 GPIO_PIN_OUTPUT_STATE_MASK = 0x01,
913 GPIO_PIN_OUTPUT_STATE_SHIFT = 0,
914 GPIO_PIN_STATE_ACTIVE_LOW = 0x0,
915 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1,
916};
917
918// Indexes to GPIO array in GLSync record
919// GLSync record is for Frame Lock/Gen Lock feature.
920enum atom_glsync_record_gpio_index_def
921{
922 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0,
923 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1,
924 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2,
925 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3,
926 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4,
927 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5,
928 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6,
929 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7,
930 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8,
931 ATOM_GPIO_INDEX_GLSYNC_MAX = 9,
932};
933
934
935struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
936{
937 struct atom_common_record_header record_header;
938 uint8_t hpd_pin_map[8];
939};
940
941struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
942{
943 struct atom_common_record_header record_header;
944 uint8_t aux_ddc_map[8];
945};
946
947struct atom_connector_forced_tmds_cap_record
948{
949 struct atom_common_record_header record_header;
950 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
951 uint8_t maxtmdsclkrate_in2_5mhz;
952 uint8_t reserved;
953};
954
955struct atom_connector_layout_info
956{
957 uint16_t connectorobjid;
958 uint8_t connector_type;
959 uint8_t position;
960};
961
962// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
963enum atom_connector_layout_info_connector_type_def
964{
965 CONNECTOR_TYPE_DVI_D = 1,
966
967 CONNECTOR_TYPE_HDMI = 4,
968 CONNECTOR_TYPE_DISPLAY_PORT = 5,
969 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6,
970};
971
972struct atom_bracket_layout_record
973{
974 struct atom_common_record_header record_header;
975 uint8_t bracketlen;
976 uint8_t bracketwidth;
977 uint8_t conn_num;
978 uint8_t reserved;
979 struct atom_connector_layout_info conn_info[1];
980};
981struct atom_bracket_layout_record_v2 {
982 struct atom_common_record_header
983 record_header; //record_type = ATOM_BRACKET_LAYOUT_RECORD_TYPE
984 uint8_t bracketlen; //Bracket Length in mm
985 uint8_t bracketwidth; //Bracket Width in mm
986 uint8_t conn_num; //Connector numbering
987 uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini)
988 uint8_t reserved1;
989 uint8_t reserved2;
990};
991
992enum atom_connector_layout_info_mini_type_def {
993 MINI_TYPE_NORMAL = 0,
994 MINI_TYPE_MINI = 1,
995};
996
997enum atom_display_device_tag_def{
998 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
999 ATOM_DISPLAY_LCD2_SUPPORT = 0x0020, //second edp device tag 0x0020 for backward compability
1000 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008,
1001 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080,
1002 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200,
1003 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400,
1004 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800,
1005 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040,
1006 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8,
1007};
1008
1009struct atom_display_object_path_v2
1010{
1011 uint16_t display_objid; //Connector Object ID or Misc Object ID
1012 uint16_t disp_recordoffset;
1013 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder
1014 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view;
1015 uint16_t encoder_recordoffset;
1016 uint16_t extencoder_recordoffset;
1017 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first
1018 uint8_t priority_id;
1019 uint8_t reserved;
1020};
1021
1022struct atom_display_object_path_v3 {
1023 uint16_t display_objid; //Connector Object ID or Misc Object ID
1024 uint16_t disp_recordoffset;
1025 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder
1026 uint16_t reserved1; //only on USBC case, otherwise always = 0
1027 uint16_t reserved2; //reserved and always = 0
1028 uint16_t reserved3; //reserved and always = 0
1029 //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority,
1030 //a path appears first
1031 uint16_t device_tag;
1032 uint16_t reserved4; //reserved and always = 0
1033};
1034
1035struct display_object_info_table_v1_4
1036{
1037 struct atom_common_table_header table_header;
1038 uint16_t supporteddevices;
1039 uint8_t number_of_path;
1040 uint8_t reserved;
1041 struct atom_display_object_path_v2 display_path[]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
1042};
1043
1044struct display_object_info_table_v1_5 {
1045 struct atom_common_table_header table_header;
1046 uint16_t supporteddevices;
1047 uint8_t number_of_path;
1048 uint8_t reserved;
1049 // the real number of this included in the structure is calculated by using the
1050 // (whole structure size - the header size- number_of_path)/size of atom_display_object_path
1051 struct atom_display_object_path_v3 display_path[];
1052};
1053
1054/*
1055 ***************************************************************************
1056 Data Table dce_info structure
1057 ***************************************************************************
1058*/
1059struct atom_display_controller_info_v4_1
1060{
1061 struct atom_common_table_header table_header;
1062 uint32_t display_caps;
1063 uint32_t bootup_dispclk_10khz;
1064 uint16_t dce_refclk_10khz;
1065 uint16_t i2c_engine_refclk_10khz;
1066 uint16_t dvi_ss_percentage; // in unit of 0.001%
1067 uint16_t dvi_ss_rate_10hz;
1068 uint16_t hdmi_ss_percentage; // in unit of 0.001%
1069 uint16_t hdmi_ss_rate_10hz;
1070 uint16_t dp_ss_percentage; // in unit of 0.001%
1071 uint16_t dp_ss_rate_10hz;
1072 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1073 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1074 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1075 uint8_t ss_reserved;
1076 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
1077 uint8_t reserved1[3];
1078 uint16_t dpphy_refclk_10khz;
1079 uint16_t reserved2;
1080 uint8_t dceip_min_ver;
1081 uint8_t dceip_max_ver;
1082 uint8_t max_disp_pipe_num;
1083 uint8_t max_vbios_active_disp_pipe_num;
1084 uint8_t max_ppll_num;
1085 uint8_t max_disp_phy_num;
1086 uint8_t max_aux_pairs;
1087 uint8_t remotedisplayconfig;
1088 uint8_t reserved3[8];
1089};
1090
1091struct atom_display_controller_info_v4_2
1092{
1093 struct atom_common_table_header table_header;
1094 uint32_t display_caps;
1095 uint32_t bootup_dispclk_10khz;
1096 uint16_t dce_refclk_10khz;
1097 uint16_t i2c_engine_refclk_10khz;
1098 uint16_t dvi_ss_percentage; // in unit of 0.001%
1099 uint16_t dvi_ss_rate_10hz;
1100 uint16_t hdmi_ss_percentage; // in unit of 0.001%
1101 uint16_t hdmi_ss_rate_10hz;
1102 uint16_t dp_ss_percentage; // in unit of 0.001%
1103 uint16_t dp_ss_rate_10hz;
1104 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1105 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1106 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1107 uint8_t ss_reserved;
1108 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1109 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1110 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1111 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1112 uint16_t dpphy_refclk_10khz;
1113 uint16_t reserved2;
1114 uint8_t dcnip_min_ver;
1115 uint8_t dcnip_max_ver;
1116 uint8_t max_disp_pipe_num;
1117 uint8_t max_vbios_active_disp_pipe_num;
1118 uint8_t max_ppll_num;
1119 uint8_t max_disp_phy_num;
1120 uint8_t max_aux_pairs;
1121 uint8_t remotedisplayconfig;
1122 uint8_t reserved3[8];
1123};
1124
1125struct atom_display_controller_info_v4_3
1126{
1127 struct atom_common_table_header table_header;
1128 uint32_t display_caps;
1129 uint32_t bootup_dispclk_10khz;
1130 uint16_t dce_refclk_10khz;
1131 uint16_t i2c_engine_refclk_10khz;
1132 uint16_t dvi_ss_percentage; // in unit of 0.001%
1133 uint16_t dvi_ss_rate_10hz;
1134 uint16_t hdmi_ss_percentage; // in unit of 0.001%
1135 uint16_t hdmi_ss_rate_10hz;
1136 uint16_t dp_ss_percentage; // in unit of 0.001%
1137 uint16_t dp_ss_rate_10hz;
1138 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1139 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1140 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1141 uint8_t ss_reserved;
1142 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1143 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1144 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1145 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1146 uint16_t dpphy_refclk_10khz;
1147 uint16_t reserved2;
1148 uint8_t dcnip_min_ver;
1149 uint8_t dcnip_max_ver;
1150 uint8_t max_disp_pipe_num;
1151 uint8_t max_vbios_active_disp_pipe_num;
1152 uint8_t max_ppll_num;
1153 uint8_t max_disp_phy_num;
1154 uint8_t max_aux_pairs;
1155 uint8_t remotedisplayconfig;
1156 uint8_t reserved3[8];
1157};
1158
1159struct atom_display_controller_info_v4_4 {
1160 struct atom_common_table_header table_header;
1161 uint32_t display_caps;
1162 uint32_t bootup_dispclk_10khz;
1163 uint16_t dce_refclk_10khz;
1164 uint16_t i2c_engine_refclk_10khz;
1165 uint16_t dvi_ss_percentage; // in unit of 0.001%
1166 uint16_t dvi_ss_rate_10hz;
1167 uint16_t hdmi_ss_percentage; // in unit of 0.001%
1168 uint16_t hdmi_ss_rate_10hz;
1169 uint16_t dp_ss_percentage; // in unit of 0.001%
1170 uint16_t dp_ss_rate_10hz;
1171 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1172 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1173 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1174 uint8_t ss_reserved;
1175 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1176 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1177 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1178 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1179 uint16_t dpphy_refclk_10khz;
1180 uint16_t hw_chip_id;
1181 uint8_t dcnip_min_ver;
1182 uint8_t dcnip_max_ver;
1183 uint8_t max_disp_pipe_num;
1184 uint8_t max_vbios_active_disp_pipum;
1185 uint8_t max_ppll_num;
1186 uint8_t max_disp_phy_num;
1187 uint8_t max_aux_pairs;
1188 uint8_t remotedisplayconfig;
1189 uint32_t dispclk_pll_vco_freq;
1190 uint32_t dp_ref_clk_freq;
1191 uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us)
1192 uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us)
1193 uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us)
1194 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx
1195 uint16_t dc_golden_table_ver;
1196 uint32_t reserved3[3];
1197};
1198
1199struct atom_dc_golden_table_v1
1200{
1201 uint32_t aux_dphy_rx_control0_val;
1202 uint32_t aux_dphy_tx_control_val;
1203 uint32_t aux_dphy_rx_control1_val;
1204 uint32_t dc_gpio_aux_ctrl_0_val;
1205 uint32_t dc_gpio_aux_ctrl_1_val;
1206 uint32_t dc_gpio_aux_ctrl_2_val;
1207 uint32_t dc_gpio_aux_ctrl_3_val;
1208 uint32_t dc_gpio_aux_ctrl_4_val;
1209 uint32_t dc_gpio_aux_ctrl_5_val;
1210 uint32_t reserved[23];
1211};
1212
1213enum dce_info_caps_def {
1214 // only for VBIOS
1215 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED = 0x02,
1216 // only for VBIOS
1217 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 = 0x04,
1218 // only for VBIOS
1219 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING = 0x08,
1220 // only for VBIOS
1221 DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE = 0x20,
1222 DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40,
1223};
1224
1225struct atom_display_controller_info_v4_5
1226{
1227 struct atom_common_table_header table_header;
1228 uint32_t display_caps;
1229 uint32_t bootup_dispclk_10khz;
1230 uint16_t dce_refclk_10khz;
1231 uint16_t i2c_engine_refclk_10khz;
1232 uint16_t dvi_ss_percentage; // in unit of 0.001%
1233 uint16_t dvi_ss_rate_10hz;
1234 uint16_t hdmi_ss_percentage; // in unit of 0.001%
1235 uint16_t hdmi_ss_rate_10hz;
1236 uint16_t dp_ss_percentage; // in unit of 0.001%
1237 uint16_t dp_ss_rate_10hz;
1238 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1239 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1240 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1241 uint8_t ss_reserved;
1242 // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1243 uint8_t dfp_hardcode_mode_num;
1244 // DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1245 uint8_t dfp_hardcode_refreshrate;
1246 // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1247 uint8_t vga_hardcode_mode_num;
1248 // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1249 uint8_t vga_hardcode_refreshrate;
1250 uint16_t dpphy_refclk_10khz;
1251 uint16_t hw_chip_id;
1252 uint8_t dcnip_min_ver;
1253 uint8_t dcnip_max_ver;
1254 uint8_t max_disp_pipe_num;
1255 uint8_t max_vbios_active_disp_pipe_num;
1256 uint8_t max_ppll_num;
1257 uint8_t max_disp_phy_num;
1258 uint8_t max_aux_pairs;
1259 uint8_t remotedisplayconfig;
1260 uint32_t dispclk_pll_vco_freq;
1261 uint32_t dp_ref_clk_freq;
1262 // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us)
1263 uint32_t max_mclk_chg_lat;
1264 // Worst case memory self refresh exit time, units of 100ns of ns (0.1us)
1265 uint32_t max_sr_exit_lat;
1266 // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us)
1267 uint32_t max_sr_enter_exit_lat;
1268 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx
1269 uint16_t dc_golden_table_ver;
1270 uint32_t aux_dphy_rx_control0_val;
1271 uint32_t aux_dphy_tx_control_val;
1272 uint32_t aux_dphy_rx_control1_val;
1273 uint32_t dc_gpio_aux_ctrl_0_val;
1274 uint32_t dc_gpio_aux_ctrl_1_val;
1275 uint32_t dc_gpio_aux_ctrl_2_val;
1276 uint32_t dc_gpio_aux_ctrl_3_val;
1277 uint32_t dc_gpio_aux_ctrl_4_val;
1278 uint32_t dc_gpio_aux_ctrl_5_val;
1279 uint32_t reserved[26];
1280};
1281
1282/*
1283 ***************************************************************************
1284 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure
1285 ***************************************************************************
1286*/
1287struct atom_ext_display_path
1288{
1289 uint16_t device_tag; //A bit vector to show what devices are supported
1290 uint16_t device_acpi_enum; //16bit device ACPI id.
1291 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions
1292 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
1293 uint8_t hpdlut_index; //An index into external HPD pin LUT
1294 uint16_t ext_encoder_objid; //external encoder object id
1295 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping
1296 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
1297 uint16_t caps;
1298 uint16_t reserved;
1299};
1300
1301//usCaps
1302enum ext_display_path_cap_def {
1303 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE = 0x0001,
1304 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = 0x0002,
1305 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007C,
1306 EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x01 << 2), //PI redriver chip
1307 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip
1308 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip
1309};
1310
1311struct atom_external_display_connection_info
1312{
1313 struct atom_common_table_header table_header;
1314 uint8_t guid[16]; // a GUID is a 16 byte long string
1315 struct atom_ext_display_path path[7]; // total of fixed 7 entries.
1316 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0.
1317 uint8_t stereopinid; // use for eDP panel
1318 uint8_t remotedisplayconfig;
1319 uint8_t edptolvdsrxid;
1320 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value
1321 uint8_t reserved[3]; // for potential expansion
1322};
1323
1324/*
1325 ***************************************************************************
1326 Data Table integratedsysteminfo structure
1327 ***************************************************************************
1328*/
1329
1330struct atom_camera_dphy_timing_param
1331{
1332 uint8_t profile_id; // SENSOR_PROFILES
1333 uint32_t param;
1334};
1335
1336struct atom_camera_dphy_elec_param
1337{
1338 uint16_t param[3];
1339};
1340
1341struct atom_camera_module_info
1342{
1343 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
1344 uint8_t module_name[8];
1345 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor
1346};
1347
1348struct atom_camera_flashlight_info
1349{
1350 uint8_t flashlight_id; // 0: Rear, 1: Front
1351 uint8_t name[8];
1352};
1353
1354struct atom_camera_data
1355{
1356 uint32_t versionCode;
1357 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max
1358 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max
1359 struct atom_camera_dphy_elec_param dphy_param;
1360 uint32_t crc_val; // CRC
1361};
1362
1363
1364struct atom_14nm_dpphy_dvihdmi_tuningset
1365{
1366 uint32_t max_symclk_in10khz;
1367 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1368 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1369 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1370 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1371 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1372 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1373 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1374};
1375
1376struct atom_14nm_dpphy_dp_setting{
1377 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1378 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1379 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1380 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1381};
1382
1383struct atom_14nm_dpphy_dp_tuningset{
1384 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1385 uint8_t version;
1386 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset
1387 uint16_t reserved;
1388 struct atom_14nm_dpphy_dp_setting dptuning[10];
1389};
1390
1391struct atom_14nm_dig_transmitter_info_header_v4_0{
1392 struct atom_common_table_header table_header;
1393 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl
1394 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl
1395 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl
1396};
1397
1398struct atom_14nm_combphy_tmds_vs_set
1399{
1400 uint8_t sym_clk;
1401 uint8_t dig_mode;
1402 uint8_t phy_sel;
1403 uint16_t common_mar_deemph_nom__margin_deemph_val;
1404 uint8_t common_seldeemph60__deemph_6db_4_val;
1405 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1406 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1407 uint8_t margin_deemph_lane0__deemph_sel_val;
1408};
1409
1410struct atom_DCN_dpphy_dvihdmi_tuningset
1411{
1412 uint32_t max_symclk_in10khz;
1413 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1414 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1415 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1416 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1417 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1418 uint8_t reserved1;
1419 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1420 uint8_t reserved2;
1421};
1422
1423struct atom_DCN_dpphy_dp_setting{
1424 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1425 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1426 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1427 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1428 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1429};
1430
1431struct atom_DCN_dpphy_dp_tuningset{
1432 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1433 uint8_t version;
1434 uint16_t table_size; // size of atom_14nm_dpphy_dp_setting
1435 uint16_t reserved;
1436 struct atom_DCN_dpphy_dp_setting dptunings[10];
1437};
1438
1439struct atom_i2c_reg_info {
1440 uint8_t ucI2cRegIndex;
1441 uint8_t ucI2cRegVal;
1442};
1443
1444struct atom_hdmi_retimer_redriver_set {
1445 uint8_t HdmiSlvAddr;
1446 uint8_t HdmiRegNum;
1447 uint8_t Hdmi6GRegNum;
1448 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use
1449 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use.
1450};
1451
1452struct atom_integrated_system_info_v1_11
1453{
1454 struct atom_common_table_header table_header;
1455 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1456 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1457 uint32_t system_config;
1458 uint32_t cpucapinfo;
1459 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1460 uint16_t gpuclk_ss_type;
1461 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1%
1462 uint16_t lvds_ss_rate_10hz;
1463 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1464 uint16_t hdmi_ss_rate_10hz;
1465 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1466 uint16_t dvi_ss_rate_10hz;
1467 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1468 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def
1469 uint16_t backlight_pwm_hz; // pwm frequency in hz
1470 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1471 uint8_t umachannelnumber; // number of memory channels
1472 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1473 uint8_t pwr_on_de_to_vary_bl;
1474 uint8_t pwr_down_vary_bloff_to_de;
1475 uint8_t pwr_down_de_to_digoff;
1476 uint8_t pwr_off_delay;
1477 uint8_t pwr_on_vary_bl_to_blon;
1478 uint8_t pwr_down_bloff_to_vary_bloff;
1479 uint8_t min_allowed_bl_level;
1480 uint8_t htc_hyst_limit;
1481 uint8_t htc_tmp_limit;
1482 uint8_t reserved1;
1483 uint8_t reserved2;
1484 struct atom_external_display_connection_info extdispconninfo;
1485 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset;
1486 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset;
1487 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset;
1488 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set
1489 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set
1490 struct atom_camera_data camera_info;
1491 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
1492 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
1493 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1494 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
1495 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set
1496 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set
1497 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set
1498 uint32_t reserved[66];
1499};
1500
1501struct atom_integrated_system_info_v1_12
1502{
1503 struct atom_common_table_header table_header;
1504 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1505 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1506 uint32_t system_config;
1507 uint32_t cpucapinfo;
1508 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1509 uint16_t gpuclk_ss_type;
1510 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1%
1511 uint16_t lvds_ss_rate_10hz;
1512 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1513 uint16_t hdmi_ss_rate_10hz;
1514 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1515 uint16_t dvi_ss_rate_10hz;
1516 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1517 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def
1518 uint16_t backlight_pwm_hz; // pwm frequency in hz
1519 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1520 uint8_t umachannelnumber; // number of memory channels
1521 uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms //
1522 uint8_t pwr_on_de_to_vary_bl;
1523 uint8_t pwr_down_vary_bloff_to_de;
1524 uint8_t pwr_down_de_to_digoff;
1525 uint8_t pwr_off_delay;
1526 uint8_t pwr_on_vary_bl_to_blon;
1527 uint8_t pwr_down_bloff_to_vary_bloff;
1528 uint8_t min_allowed_bl_level;
1529 uint8_t htc_hyst_limit;
1530 uint8_t htc_tmp_limit;
1531 uint8_t reserved1;
1532 uint8_t reserved2;
1533 struct atom_external_display_connection_info extdispconninfo;
1534 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset;
1535 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset;
1536 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset;
1537 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set
1538 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set
1539 struct atom_camera_data camera_info;
1540 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
1541 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
1542 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1543 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
1544 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set
1545 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set
1546 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set
1547 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset;
1548 uint32_t reserved[63];
1549};
1550
1551struct edp_info_table
1552{
1553 uint16_t edp_backlight_pwm_hz;
1554 uint16_t edp_ss_percentage;
1555 uint16_t edp_ss_rate_10hz;
1556 uint16_t reserved1;
1557 uint32_t reserved2;
1558 uint8_t edp_pwr_on_off_delay;
1559 uint8_t edp_pwr_on_vary_bl_to_blon;
1560 uint8_t edp_pwr_down_bloff_to_vary_bloff;
1561 uint8_t edp_panel_bpc;
1562 uint8_t edp_bootup_bl_level;
1563 uint8_t reserved3[3];
1564 uint32_t reserved4[3];
1565};
1566
1567struct atom_integrated_system_info_v2_1
1568{
1569 struct atom_common_table_header table_header;
1570 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1571 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1572 uint32_t system_config;
1573 uint32_t cpucapinfo;
1574 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1575 uint16_t gpuclk_ss_type;
1576 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1577 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1578 uint8_t umachannelnumber; // number of memory channels
1579 uint8_t htc_hyst_limit;
1580 uint8_t htc_tmp_limit;
1581 uint8_t reserved1;
1582 uint8_t reserved2;
1583 struct edp_info_table edp1_info;
1584 struct edp_info_table edp2_info;
1585 uint32_t reserved3[8];
1586 struct atom_external_display_connection_info extdispconninfo;
1587 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset;
1588 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; //add clk6
1589 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset;
1590 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset;
1591 uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset)
1592 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set
1593 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set
1594 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set
1595 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set
1596 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set
1597 uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset)
1598 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
1599 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
1600 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1601 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
1602 uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info
1603 uint32_t reserved7[32];
1604
1605};
1606
1607struct atom_n6_display_phy_tuning_set {
1608 uint8_t display_signal_type;
1609 uint8_t phy_sel;
1610 uint8_t preset_level;
1611 uint8_t reserved1;
1612 uint32_t reserved2;
1613 uint32_t speed_upto;
1614 uint8_t tx_vboost_level;
1615 uint8_t tx_vreg_v2i;
1616 uint8_t tx_vregdrv_byp;
1617 uint8_t tx_term_cntl;
1618 uint8_t tx_peak_level;
1619 uint8_t tx_slew_en;
1620 uint8_t tx_eq_pre;
1621 uint8_t tx_eq_main;
1622 uint8_t tx_eq_post;
1623 uint8_t tx_en_inv_pre;
1624 uint8_t tx_en_inv_post;
1625 uint8_t reserved3;
1626 uint32_t reserved4;
1627 uint32_t reserved5;
1628 uint32_t reserved6;
1629};
1630
1631struct atom_display_phy_tuning_info {
1632 struct atom_common_table_header table_header;
1633 struct atom_n6_display_phy_tuning_set disp_phy_tuning[1];
1634};
1635
1636struct atom_integrated_system_info_v2_2
1637{
1638 struct atom_common_table_header table_header;
1639 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1640 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1641 uint32_t system_config;
1642 uint32_t cpucapinfo;
1643 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1644 uint16_t gpuclk_ss_type;
1645 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1646 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1647 uint8_t umachannelnumber; // number of memory channels
1648 uint8_t htc_hyst_limit;
1649 uint8_t htc_tmp_limit;
1650 uint8_t reserved1;
1651 uint8_t reserved2;
1652 struct edp_info_table edp1_info;
1653 struct edp_info_table edp2_info;
1654 uint32_t reserved3[8];
1655 struct atom_external_display_connection_info extdispconninfo;
1656
1657 uint32_t reserved4[189];
1658};
1659
1660struct uma_carveout_option {
1661 char optionName[29]; //max length of string is 28chars + '\0'. Current design is for "minimum", "Medium", "High". This makes entire struct size 64bits
1662 uint8_t memoryCarvedGb; //memory carved out with setting
1663 uint8_t memoryRemainingGb; //memory remaining on system
1664 union {
1665 struct _flags {
1666 uint8_t Auto : 1;
1667 uint8_t Custom : 1;
1668 uint8_t Reserved : 6;
1669 } flags;
1670 uint8_t all8;
1671 } uma_carveout_option_flags;
1672};
1673
1674struct atom_integrated_system_info_v2_3 {
1675 struct atom_common_table_header table_header;
1676 uint32_t vbios_misc; // enum of atom_system_vbiosmisc_def
1677 uint32_t gpucapinfo; // enum of atom_system_gpucapinf_def
1678 uint32_t system_config;
1679 uint32_t cpucapinfo;
1680 uint16_t gpuclk_ss_percentage; // unit of 0.001%, 1000 mean 1%
1681 uint16_t gpuclk_ss_type;
1682 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1683 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1684 uint8_t umachannelnumber; // number of memory channels
1685 uint8_t htc_hyst_limit;
1686 uint8_t htc_tmp_limit;
1687 uint8_t reserved1; // dp_ss_control
1688 uint8_t gpu_package_id;
1689 struct edp_info_table edp1_info;
1690 struct edp_info_table edp2_info;
1691 uint32_t reserved2[8];
1692 struct atom_external_display_connection_info extdispconninfo;
1693 uint8_t UMACarveoutVersion;
1694 uint8_t UMACarveoutIndexMax;
1695 uint8_t UMACarveoutTypeDefault;
1696 uint8_t UMACarveoutIndexDefault;
1697 uint8_t UMACarveoutType; //Auto or Custom
1698 uint8_t UMACarveoutIndex;
1699 struct uma_carveout_option UMASizeControlOption[20];
1700 uint8_t reserved3[110];
1701};
1702
1703// system_config
1704enum atom_system_vbiosmisc_def{
1705 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1706};
1707
1708
1709// gpucapinfo
1710enum atom_system_gpucapinf_def{
1711 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10,
1712};
1713
1714//dpphy_override
1715enum atom_sysinfo_dpphy_override_def{
1716 ATOM_ENABLE_DVI_TUNINGSET = 0x01,
1717 ATOM_ENABLE_HDMI_TUNINGSET = 0x02,
1718 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04,
1719 ATOM_ENABLE_DP_TUNINGSET = 0x08,
1720 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10,
1721};
1722
1723//lvds_misc
1724enum atom_sys_info_lvds_misc_def
1725{
1726 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01,
1727 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04,
1728 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08,
1729};
1730
1731
1732//memorytype DMI Type 17 offset 12h - Memory Type
1733enum atom_dmi_t17_mem_type_def{
1734 OtherMemType = 0x01, ///< Assign 01 to Other
1735 UnknownMemType, ///< Assign 02 to Unknown
1736 DramMemType, ///< Assign 03 to DRAM
1737 EdramMemType, ///< Assign 04 to EDRAM
1738 VramMemType, ///< Assign 05 to VRAM
1739 SramMemType, ///< Assign 06 to SRAM
1740 RamMemType, ///< Assign 07 to RAM
1741 RomMemType, ///< Assign 08 to ROM
1742 FlashMemType, ///< Assign 09 to Flash
1743 EepromMemType, ///< Assign 10 to EEPROM
1744 FepromMemType, ///< Assign 11 to FEPROM
1745 EpromMemType, ///< Assign 12 to EPROM
1746 CdramMemType, ///< Assign 13 to CDRAM
1747 ThreeDramMemType, ///< Assign 14 to 3DRAM
1748 SdramMemType, ///< Assign 15 to SDRAM
1749 SgramMemType, ///< Assign 16 to SGRAM
1750 RdramMemType, ///< Assign 17 to RDRAM
1751 DdrMemType, ///< Assign 18 to DDR
1752 Ddr2MemType, ///< Assign 19 to DDR2
1753 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
1754 Ddr3MemType = 0x18, ///< Assign 24 to DDR3
1755 Fbd2MemType, ///< Assign 25 to FBD2
1756 Ddr4MemType, ///< Assign 26 to DDR4
1757 LpDdrMemType, ///< Assign 27 to LPDDR
1758 LpDdr2MemType, ///< Assign 28 to LPDDR2
1759 LpDdr3MemType, ///< Assign 29 to LPDDR3
1760 LpDdr4MemType, ///< Assign 30 to LPDDR4
1761 GDdr6MemType, ///< Assign 31 to GDDR6
1762 HbmMemType, ///< Assign 32 to HBM
1763 Hbm2MemType, ///< Assign 33 to HBM2
1764 Ddr5MemType, ///< Assign 34 to DDR5
1765 LpDdr5MemType, ///< Assign 35 to LPDDR5
1766};
1767
1768
1769// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable
1770struct atom_fusion_system_info_v4
1771{
1772 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
1773 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable
1774};
1775
1776
1777/*
1778 ***************************************************************************
1779 Data Table gfx_info structure
1780 ***************************************************************************
1781*/
1782
1783struct atom_gfx_info_v2_2
1784{
1785 struct atom_common_table_header table_header;
1786 uint8_t gfxip_min_ver;
1787 uint8_t gfxip_max_ver;
1788 uint8_t max_shader_engines;
1789 uint8_t max_tile_pipes;
1790 uint8_t max_cu_per_sh;
1791 uint8_t max_sh_per_se;
1792 uint8_t max_backends_per_se;
1793 uint8_t max_texture_channel_caches;
1794 uint32_t regaddr_cp_dma_src_addr;
1795 uint32_t regaddr_cp_dma_src_addr_hi;
1796 uint32_t regaddr_cp_dma_dst_addr;
1797 uint32_t regaddr_cp_dma_dst_addr_hi;
1798 uint32_t regaddr_cp_dma_command;
1799 uint32_t regaddr_cp_status;
1800 uint32_t regaddr_rlc_gpu_clock_32;
1801 uint32_t rlc_gpu_timer_refclk;
1802};
1803
1804struct atom_gfx_info_v2_3 {
1805 struct atom_common_table_header table_header;
1806 uint8_t gfxip_min_ver;
1807 uint8_t gfxip_max_ver;
1808 uint8_t max_shader_engines;
1809 uint8_t max_tile_pipes;
1810 uint8_t max_cu_per_sh;
1811 uint8_t max_sh_per_se;
1812 uint8_t max_backends_per_se;
1813 uint8_t max_texture_channel_caches;
1814 uint32_t regaddr_cp_dma_src_addr;
1815 uint32_t regaddr_cp_dma_src_addr_hi;
1816 uint32_t regaddr_cp_dma_dst_addr;
1817 uint32_t regaddr_cp_dma_dst_addr_hi;
1818 uint32_t regaddr_cp_dma_command;
1819 uint32_t regaddr_cp_status;
1820 uint32_t regaddr_rlc_gpu_clock_32;
1821 uint32_t rlc_gpu_timer_refclk;
1822 uint8_t active_cu_per_sh;
1823 uint8_t active_rb_per_se;
1824 uint16_t gcgoldenoffset;
1825 uint32_t rm21_sram_vmin_value;
1826};
1827
1828struct atom_gfx_info_v2_4
1829{
1830 struct atom_common_table_header table_header;
1831 uint8_t gfxip_min_ver;
1832 uint8_t gfxip_max_ver;
1833 uint8_t max_shader_engines;
1834 uint8_t reserved;
1835 uint8_t max_cu_per_sh;
1836 uint8_t max_sh_per_se;
1837 uint8_t max_backends_per_se;
1838 uint8_t max_texture_channel_caches;
1839 uint32_t regaddr_cp_dma_src_addr;
1840 uint32_t regaddr_cp_dma_src_addr_hi;
1841 uint32_t regaddr_cp_dma_dst_addr;
1842 uint32_t regaddr_cp_dma_dst_addr_hi;
1843 uint32_t regaddr_cp_dma_command;
1844 uint32_t regaddr_cp_status;
1845 uint32_t regaddr_rlc_gpu_clock_32;
1846 uint32_t rlc_gpu_timer_refclk;
1847 uint8_t active_cu_per_sh;
1848 uint8_t active_rb_per_se;
1849 uint16_t gcgoldenoffset;
1850 uint16_t gc_num_gprs;
1851 uint16_t gc_gsprim_buff_depth;
1852 uint16_t gc_parameter_cache_depth;
1853 uint16_t gc_wave_size;
1854 uint16_t gc_max_waves_per_simd;
1855 uint16_t gc_lds_size;
1856 uint8_t gc_num_max_gs_thds;
1857 uint8_t gc_gs_table_depth;
1858 uint8_t gc_double_offchip_lds_buffer;
1859 uint8_t gc_max_scratch_slots_per_cu;
1860 uint32_t sram_rm_fuses_val;
1861 uint32_t sram_custom_rm_fuses_val;
1862};
1863
1864struct atom_gfx_info_v2_7 {
1865 struct atom_common_table_header table_header;
1866 uint8_t gfxip_min_ver;
1867 uint8_t gfxip_max_ver;
1868 uint8_t max_shader_engines;
1869 uint8_t reserved;
1870 uint8_t max_cu_per_sh;
1871 uint8_t max_sh_per_se;
1872 uint8_t max_backends_per_se;
1873 uint8_t max_texture_channel_caches;
1874 uint32_t regaddr_cp_dma_src_addr;
1875 uint32_t regaddr_cp_dma_src_addr_hi;
1876 uint32_t regaddr_cp_dma_dst_addr;
1877 uint32_t regaddr_cp_dma_dst_addr_hi;
1878 uint32_t regaddr_cp_dma_command;
1879 uint32_t regaddr_cp_status;
1880 uint32_t regaddr_rlc_gpu_clock_32;
1881 uint32_t rlc_gpu_timer_refclk;
1882 uint8_t active_cu_per_sh;
1883 uint8_t active_rb_per_se;
1884 uint16_t gcgoldenoffset;
1885 uint16_t gc_num_gprs;
1886 uint16_t gc_gsprim_buff_depth;
1887 uint16_t gc_parameter_cache_depth;
1888 uint16_t gc_wave_size;
1889 uint16_t gc_max_waves_per_simd;
1890 uint16_t gc_lds_size;
1891 uint8_t gc_num_max_gs_thds;
1892 uint8_t gc_gs_table_depth;
1893 uint8_t gc_double_offchip_lds_buffer;
1894 uint8_t gc_max_scratch_slots_per_cu;
1895 uint32_t sram_rm_fuses_val;
1896 uint32_t sram_custom_rm_fuses_val;
1897 uint8_t cut_cu;
1898 uint8_t active_cu_total;
1899 uint8_t cu_reserved[2];
1900 uint32_t gc_config;
1901 uint8_t inactive_cu_per_se[8];
1902 uint32_t reserved2[6];
1903};
1904
1905struct atom_gfx_info_v3_0 {
1906 struct atom_common_table_header table_header;
1907 uint8_t gfxip_min_ver;
1908 uint8_t gfxip_max_ver;
1909 uint8_t max_shader_engines;
1910 uint8_t max_tile_pipes;
1911 uint8_t max_cu_per_sh;
1912 uint8_t max_sh_per_se;
1913 uint8_t max_backends_per_se;
1914 uint8_t max_texture_channel_caches;
1915 uint32_t regaddr_lsdma_queue0_rb_rptr;
1916 uint32_t regaddr_lsdma_queue0_rb_rptr_hi;
1917 uint32_t regaddr_lsdma_queue0_rb_wptr;
1918 uint32_t regaddr_lsdma_queue0_rb_wptr_hi;
1919 uint32_t regaddr_lsdma_command;
1920 uint32_t regaddr_lsdma_status;
1921 uint32_t regaddr_golden_tsc_count_lower;
1922 uint32_t golden_tsc_count_lower_refclk;
1923 uint8_t active_wgp_per_se;
1924 uint8_t active_rb_per_se;
1925 uint8_t active_se;
1926 uint8_t reserved1;
1927 uint32_t sram_rm_fuses_val;
1928 uint32_t sram_custom_rm_fuses_val;
1929 uint32_t inactive_sa_mask;
1930 uint32_t gc_config;
1931 uint8_t inactive_wgp[16];
1932 uint8_t inactive_rb[16];
1933 uint32_t gdfll_as_wait_ctrl_val;
1934 uint32_t gdfll_as_step_ctrl_val;
1935 uint32_t reserved[8];
1936};
1937
1938/*
1939 ***************************************************************************
1940 Data Table smu_info structure
1941 ***************************************************************************
1942*/
1943struct atom_smu_info_v3_1
1944{
1945 struct atom_common_table_header table_header;
1946 uint8_t smuip_min_ver;
1947 uint8_t smuip_max_ver;
1948 uint8_t smu_rsd1;
1949 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1950 uint16_t sclk_ss_percentage;
1951 uint16_t sclk_ss_rate_10hz;
1952 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1953 uint16_t gpuclk_ss_rate_10hz;
1954 uint32_t core_refclk_10khz;
1955 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1956 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1957 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1958 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1959 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1960 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1961 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1962 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1963};
1964
1965struct atom_smu_info_v3_2 {
1966 struct atom_common_table_header table_header;
1967 uint8_t smuip_min_ver;
1968 uint8_t smuip_max_ver;
1969 uint8_t smu_rsd1;
1970 uint8_t gpuclk_ss_mode;
1971 uint16_t sclk_ss_percentage;
1972 uint16_t sclk_ss_rate_10hz;
1973 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1974 uint16_t gpuclk_ss_rate_10hz;
1975 uint32_t core_refclk_10khz;
1976 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1977 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1978 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1979 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1980 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1981 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1982 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1983 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1984 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1985 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1986 uint16_t smugoldenoffset;
1987 uint32_t gpupll_vco_freq_10khz;
1988 uint32_t bootup_smnclk_10khz;
1989 uint32_t bootup_socclk_10khz;
1990 uint32_t bootup_mp0clk_10khz;
1991 uint32_t bootup_mp1clk_10khz;
1992 uint32_t bootup_lclk_10khz;
1993 uint32_t bootup_dcefclk_10khz;
1994 uint32_t ctf_threshold_override_value;
1995 uint32_t reserved[5];
1996};
1997
1998struct atom_smu_info_v3_3 {
1999 struct atom_common_table_header table_header;
2000 uint8_t smuip_min_ver;
2001 uint8_t smuip_max_ver;
2002 uint8_t waflclk_ss_mode;
2003 uint8_t gpuclk_ss_mode;
2004 uint16_t sclk_ss_percentage;
2005 uint16_t sclk_ss_rate_10hz;
2006 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
2007 uint16_t gpuclk_ss_rate_10hz;
2008 uint32_t core_refclk_10khz;
2009 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
2010 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
2011 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
2012 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
2013 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
2014 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
2015 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
2016 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
2017 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
2018 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
2019 uint16_t smugoldenoffset;
2020 uint32_t gpupll_vco_freq_10khz;
2021 uint32_t bootup_smnclk_10khz;
2022 uint32_t bootup_socclk_10khz;
2023 uint32_t bootup_mp0clk_10khz;
2024 uint32_t bootup_mp1clk_10khz;
2025 uint32_t bootup_lclk_10khz;
2026 uint32_t bootup_dcefclk_10khz;
2027 uint32_t ctf_threshold_override_value;
2028 uint32_t syspll3_0_vco_freq_10khz;
2029 uint32_t syspll3_1_vco_freq_10khz;
2030 uint32_t bootup_fclk_10khz;
2031 uint32_t bootup_waflclk_10khz;
2032 uint32_t smu_info_caps;
2033 uint16_t waflclk_ss_percentage; // in unit of 0.001%
2034 uint16_t smuinitoffset;
2035 uint32_t reserved;
2036};
2037
2038struct atom_smu_info_v3_5
2039{
2040 struct atom_common_table_header table_header;
2041 uint8_t smuip_min_ver;
2042 uint8_t smuip_max_ver;
2043 uint8_t waflclk_ss_mode;
2044 uint8_t gpuclk_ss_mode;
2045 uint16_t sclk_ss_percentage;
2046 uint16_t sclk_ss_rate_10hz;
2047 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
2048 uint16_t gpuclk_ss_rate_10hz;
2049 uint32_t core_refclk_10khz;
2050 uint32_t syspll0_1_vco_freq_10khz;
2051 uint32_t syspll0_2_vco_freq_10khz;
2052 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
2053 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
2054 uint16_t smugoldenoffset;
2055 uint32_t syspll0_0_vco_freq_10khz;
2056 uint32_t bootup_smnclk_10khz;
2057 uint32_t bootup_socclk_10khz;
2058 uint32_t bootup_mp0clk_10khz;
2059 uint32_t bootup_mp1clk_10khz;
2060 uint32_t bootup_lclk_10khz;
2061 uint32_t bootup_dcefclk_10khz;
2062 uint32_t ctf_threshold_override_value;
2063 uint32_t syspll3_0_vco_freq_10khz;
2064 uint32_t syspll3_1_vco_freq_10khz;
2065 uint32_t bootup_fclk_10khz;
2066 uint32_t bootup_waflclk_10khz;
2067 uint32_t smu_info_caps;
2068 uint16_t waflclk_ss_percentage; // in unit of 0.001%
2069 uint16_t smuinitoffset;
2070 uint32_t bootup_dprefclk_10khz;
2071 uint32_t bootup_usbclk_10khz;
2072 uint32_t smb_slave_address;
2073 uint32_t cg_fdo_ctrl0_val;
2074 uint32_t cg_fdo_ctrl1_val;
2075 uint32_t cg_fdo_ctrl2_val;
2076 uint32_t gdfll_as_wait_ctrl_val;
2077 uint32_t gdfll_as_step_ctrl_val;
2078 uint32_t bootup_dtbclk_10khz;
2079 uint32_t fclk_syspll_refclk_10khz;
2080 uint32_t smusvi_svc0_val;
2081 uint32_t smusvi_svc1_val;
2082 uint32_t smusvi_svd0_val;
2083 uint32_t smusvi_svd1_val;
2084 uint32_t smusvi_svt0_val;
2085 uint32_t smusvi_svt1_val;
2086 uint32_t cg_tach_ctrl_val;
2087 uint32_t cg_pump_ctrl1_val;
2088 uint32_t cg_pump_tach_ctrl_val;
2089 uint32_t thm_ctf_delay_val;
2090 uint32_t thm_thermal_int_ctrl_val;
2091 uint32_t thm_tmon_config_val;
2092 uint32_t reserved[16];
2093};
2094
2095struct atom_smu_info_v3_6
2096{
2097 struct atom_common_table_header table_header;
2098 uint8_t smuip_min_ver;
2099 uint8_t smuip_max_ver;
2100 uint8_t waflclk_ss_mode;
2101 uint8_t gpuclk_ss_mode;
2102 uint16_t sclk_ss_percentage;
2103 uint16_t sclk_ss_rate_10hz;
2104 uint16_t gpuclk_ss_percentage;
2105 uint16_t gpuclk_ss_rate_10hz;
2106 uint32_t core_refclk_10khz;
2107 uint32_t syspll0_1_vco_freq_10khz;
2108 uint32_t syspll0_2_vco_freq_10khz;
2109 uint8_t pcc_gpio_bit;
2110 uint8_t pcc_gpio_polarity;
2111 uint16_t smugoldenoffset;
2112 uint32_t syspll0_0_vco_freq_10khz;
2113 uint32_t bootup_smnclk_10khz;
2114 uint32_t bootup_socclk_10khz;
2115 uint32_t bootup_mp0clk_10khz;
2116 uint32_t bootup_mp1clk_10khz;
2117 uint32_t bootup_lclk_10khz;
2118 uint32_t bootup_dxioclk_10khz;
2119 uint32_t ctf_threshold_override_value;
2120 uint32_t syspll3_0_vco_freq_10khz;
2121 uint32_t syspll3_1_vco_freq_10khz;
2122 uint32_t bootup_fclk_10khz;
2123 uint32_t bootup_waflclk_10khz;
2124 uint32_t smu_info_caps;
2125 uint16_t waflclk_ss_percentage;
2126 uint16_t smuinitoffset;
2127 uint32_t bootup_gfxavsclk_10khz;
2128 uint32_t bootup_mpioclk_10khz;
2129 uint32_t smb_slave_address;
2130 uint32_t cg_fdo_ctrl0_val;
2131 uint32_t cg_fdo_ctrl1_val;
2132 uint32_t cg_fdo_ctrl2_val;
2133 uint32_t gdfll_as_wait_ctrl_val;
2134 uint32_t gdfll_as_step_ctrl_val;
2135 uint32_t reserved_clk;
2136 uint32_t fclk_syspll_refclk_10khz;
2137 uint32_t smusvi_svc0_val;
2138 uint32_t smusvi_svc1_val;
2139 uint32_t smusvi_svd0_val;
2140 uint32_t smusvi_svd1_val;
2141 uint32_t smusvi_svt0_val;
2142 uint32_t smusvi_svt1_val;
2143 uint32_t cg_tach_ctrl_val;
2144 uint32_t cg_pump_ctrl1_val;
2145 uint32_t cg_pump_tach_ctrl_val;
2146 uint32_t thm_ctf_delay_val;
2147 uint32_t thm_thermal_int_ctrl_val;
2148 uint32_t thm_tmon_config_val;
2149 uint32_t bootup_vclk_10khz;
2150 uint32_t bootup_dclk_10khz;
2151 uint32_t smu_gpiopad_pu_en_val;
2152 uint32_t smu_gpiopad_pd_en_val;
2153 uint32_t reserved[12];
2154};
2155
2156struct atom_smu_info_v4_0 {
2157 struct atom_common_table_header table_header;
2158 uint32_t bootup_gfxclk_bypass_10khz;
2159 uint32_t bootup_usrclk_10khz;
2160 uint32_t bootup_csrclk_10khz;
2161 uint32_t core_refclk_10khz;
2162 uint32_t syspll1_vco_freq_10khz;
2163 uint32_t syspll2_vco_freq_10khz;
2164 uint8_t pcc_gpio_bit;
2165 uint8_t pcc_gpio_polarity;
2166 uint16_t bootup_vddusr_mv;
2167 uint32_t syspll0_vco_freq_10khz;
2168 uint32_t bootup_smnclk_10khz;
2169 uint32_t bootup_socclk_10khz;
2170 uint32_t bootup_mp0clk_10khz;
2171 uint32_t bootup_mp1clk_10khz;
2172 uint32_t bootup_lclk_10khz;
2173 uint32_t bootup_dcefclk_10khz;
2174 uint32_t ctf_threshold_override_value;
2175 uint32_t syspll3_vco_freq_10khz;
2176 uint32_t mm_syspll_vco_freq_10khz;
2177 uint32_t bootup_fclk_10khz;
2178 uint32_t bootup_waflclk_10khz;
2179 uint32_t smu_info_caps;
2180 uint16_t waflclk_ss_percentage;
2181 uint16_t smuinitoffset;
2182 uint32_t bootup_dprefclk_10khz;
2183 uint32_t bootup_usbclk_10khz;
2184 uint32_t smb_slave_address;
2185 uint32_t cg_fdo_ctrl0_val;
2186 uint32_t cg_fdo_ctrl1_val;
2187 uint32_t cg_fdo_ctrl2_val;
2188 uint32_t gdfll_as_wait_ctrl_val;
2189 uint32_t gdfll_as_step_ctrl_val;
2190 uint32_t bootup_dtbclk_10khz;
2191 uint32_t fclk_syspll_refclk_10khz;
2192 uint32_t smusvi_svc0_val;
2193 uint32_t smusvi_svc1_val;
2194 uint32_t smusvi_svd0_val;
2195 uint32_t smusvi_svd1_val;
2196 uint32_t smusvi_svt0_val;
2197 uint32_t smusvi_svt1_val;
2198 uint32_t cg_tach_ctrl_val;
2199 uint32_t cg_pump_ctrl1_val;
2200 uint32_t cg_pump_tach_ctrl_val;
2201 uint32_t thm_ctf_delay_val;
2202 uint32_t thm_thermal_int_ctrl_val;
2203 uint32_t thm_tmon_config_val;
2204 uint32_t smbus_timing_cntrl0_val;
2205 uint32_t smbus_timing_cntrl1_val;
2206 uint32_t smbus_timing_cntrl2_val;
2207 uint32_t pwr_disp_timer_global_control_val;
2208 uint32_t bootup_mpioclk_10khz;
2209 uint32_t bootup_dclk0_10khz;
2210 uint32_t bootup_vclk0_10khz;
2211 uint32_t bootup_dclk1_10khz;
2212 uint32_t bootup_vclk1_10khz;
2213 uint32_t bootup_baco400clk_10khz;
2214 uint32_t bootup_baco1200clk_bypass_10khz;
2215 uint32_t bootup_baco700clk_bypass_10khz;
2216 uint32_t reserved[16];
2217};
2218
2219/*
2220 ***************************************************************************
2221 Data Table smc_dpm_info structure
2222 ***************************************************************************
2223 */
2224struct atom_smc_dpm_info_v4_1
2225{
2226 struct atom_common_table_header table_header;
2227 uint8_t liquid1_i2c_address;
2228 uint8_t liquid2_i2c_address;
2229 uint8_t vr_i2c_address;
2230 uint8_t plx_i2c_address;
2231
2232 uint8_t liquid_i2c_linescl;
2233 uint8_t liquid_i2c_linesda;
2234 uint8_t vr_i2c_linescl;
2235 uint8_t vr_i2c_linesda;
2236
2237 uint8_t plx_i2c_linescl;
2238 uint8_t plx_i2c_linesda;
2239 uint8_t vrsensorpresent;
2240 uint8_t liquidsensorpresent;
2241
2242 uint16_t maxvoltagestepgfx;
2243 uint16_t maxvoltagestepsoc;
2244
2245 uint8_t vddgfxvrmapping;
2246 uint8_t vddsocvrmapping;
2247 uint8_t vddmem0vrmapping;
2248 uint8_t vddmem1vrmapping;
2249
2250 uint8_t gfxulvphasesheddingmask;
2251 uint8_t soculvphasesheddingmask;
2252 uint8_t padding8_v[2];
2253
2254 uint16_t gfxmaxcurrent;
2255 uint8_t gfxoffset;
2256 uint8_t padding_telemetrygfx;
2257
2258 uint16_t socmaxcurrent;
2259 uint8_t socoffset;
2260 uint8_t padding_telemetrysoc;
2261
2262 uint16_t mem0maxcurrent;
2263 uint8_t mem0offset;
2264 uint8_t padding_telemetrymem0;
2265
2266 uint16_t mem1maxcurrent;
2267 uint8_t mem1offset;
2268 uint8_t padding_telemetrymem1;
2269
2270 uint8_t acdcgpio;
2271 uint8_t acdcpolarity;
2272 uint8_t vr0hotgpio;
2273 uint8_t vr0hotpolarity;
2274
2275 uint8_t vr1hotgpio;
2276 uint8_t vr1hotpolarity;
2277 uint8_t padding1;
2278 uint8_t padding2;
2279
2280 uint8_t ledpin0;
2281 uint8_t ledpin1;
2282 uint8_t ledpin2;
2283 uint8_t padding8_4;
2284
2285 uint8_t pllgfxclkspreadenabled;
2286 uint8_t pllgfxclkspreadpercent;
2287 uint16_t pllgfxclkspreadfreq;
2288
2289 uint8_t uclkspreadenabled;
2290 uint8_t uclkspreadpercent;
2291 uint16_t uclkspreadfreq;
2292
2293 uint8_t socclkspreadenabled;
2294 uint8_t socclkspreadpercent;
2295 uint16_t socclkspreadfreq;
2296
2297 uint8_t acggfxclkspreadenabled;
2298 uint8_t acggfxclkspreadpercent;
2299 uint16_t acggfxclkspreadfreq;
2300
2301 uint8_t Vr2_I2C_address;
2302 uint8_t padding_vr2[3];
2303
2304 uint32_t boardreserved[9];
2305};
2306
2307/*
2308 ***************************************************************************
2309 Data Table smc_dpm_info structure
2310 ***************************************************************************
2311 */
2312struct atom_smc_dpm_info_v4_3
2313{
2314 struct atom_common_table_header table_header;
2315 uint8_t liquid1_i2c_address;
2316 uint8_t liquid2_i2c_address;
2317 uint8_t vr_i2c_address;
2318 uint8_t plx_i2c_address;
2319
2320 uint8_t liquid_i2c_linescl;
2321 uint8_t liquid_i2c_linesda;
2322 uint8_t vr_i2c_linescl;
2323 uint8_t vr_i2c_linesda;
2324
2325 uint8_t plx_i2c_linescl;
2326 uint8_t plx_i2c_linesda;
2327 uint8_t vrsensorpresent;
2328 uint8_t liquidsensorpresent;
2329
2330 uint16_t maxvoltagestepgfx;
2331 uint16_t maxvoltagestepsoc;
2332
2333 uint8_t vddgfxvrmapping;
2334 uint8_t vddsocvrmapping;
2335 uint8_t vddmem0vrmapping;
2336 uint8_t vddmem1vrmapping;
2337
2338 uint8_t gfxulvphasesheddingmask;
2339 uint8_t soculvphasesheddingmask;
2340 uint8_t externalsensorpresent;
2341 uint8_t padding8_v;
2342
2343 uint16_t gfxmaxcurrent;
2344 uint8_t gfxoffset;
2345 uint8_t padding_telemetrygfx;
2346
2347 uint16_t socmaxcurrent;
2348 uint8_t socoffset;
2349 uint8_t padding_telemetrysoc;
2350
2351 uint16_t mem0maxcurrent;
2352 uint8_t mem0offset;
2353 uint8_t padding_telemetrymem0;
2354
2355 uint16_t mem1maxcurrent;
2356 uint8_t mem1offset;
2357 uint8_t padding_telemetrymem1;
2358
2359 uint8_t acdcgpio;
2360 uint8_t acdcpolarity;
2361 uint8_t vr0hotgpio;
2362 uint8_t vr0hotpolarity;
2363
2364 uint8_t vr1hotgpio;
2365 uint8_t vr1hotpolarity;
2366 uint8_t padding1;
2367 uint8_t padding2;
2368
2369 uint8_t ledpin0;
2370 uint8_t ledpin1;
2371 uint8_t ledpin2;
2372 uint8_t padding8_4;
2373
2374 uint8_t pllgfxclkspreadenabled;
2375 uint8_t pllgfxclkspreadpercent;
2376 uint16_t pllgfxclkspreadfreq;
2377
2378 uint8_t uclkspreadenabled;
2379 uint8_t uclkspreadpercent;
2380 uint16_t uclkspreadfreq;
2381
2382 uint8_t fclkspreadenabled;
2383 uint8_t fclkspreadpercent;
2384 uint16_t fclkspreadfreq;
2385
2386 uint8_t fllgfxclkspreadenabled;
2387 uint8_t fllgfxclkspreadpercent;
2388 uint16_t fllgfxclkspreadfreq;
2389
2390 uint32_t boardreserved[10];
2391};
2392
2393struct smudpm_i2ccontrollerconfig_t {
2394 uint32_t enabled;
2395 uint32_t slaveaddress;
2396 uint32_t controllerport;
2397 uint32_t controllername;
2398 uint32_t thermalthrottler;
2399 uint32_t i2cprotocol;
2400 uint32_t i2cspeed;
2401};
2402
2403struct atom_smc_dpm_info_v4_4
2404{
2405 struct atom_common_table_header table_header;
2406 uint32_t i2c_padding[3];
2407
2408 uint16_t maxvoltagestepgfx;
2409 uint16_t maxvoltagestepsoc;
2410
2411 uint8_t vddgfxvrmapping;
2412 uint8_t vddsocvrmapping;
2413 uint8_t vddmem0vrmapping;
2414 uint8_t vddmem1vrmapping;
2415
2416 uint8_t gfxulvphasesheddingmask;
2417 uint8_t soculvphasesheddingmask;
2418 uint8_t externalsensorpresent;
2419 uint8_t padding8_v;
2420
2421 uint16_t gfxmaxcurrent;
2422 uint8_t gfxoffset;
2423 uint8_t padding_telemetrygfx;
2424
2425 uint16_t socmaxcurrent;
2426 uint8_t socoffset;
2427 uint8_t padding_telemetrysoc;
2428
2429 uint16_t mem0maxcurrent;
2430 uint8_t mem0offset;
2431 uint8_t padding_telemetrymem0;
2432
2433 uint16_t mem1maxcurrent;
2434 uint8_t mem1offset;
2435 uint8_t padding_telemetrymem1;
2436
2437
2438 uint8_t acdcgpio;
2439 uint8_t acdcpolarity;
2440 uint8_t vr0hotgpio;
2441 uint8_t vr0hotpolarity;
2442
2443 uint8_t vr1hotgpio;
2444 uint8_t vr1hotpolarity;
2445 uint8_t padding1;
2446 uint8_t padding2;
2447
2448
2449 uint8_t ledpin0;
2450 uint8_t ledpin1;
2451 uint8_t ledpin2;
2452 uint8_t padding8_4;
2453
2454
2455 uint8_t pllgfxclkspreadenabled;
2456 uint8_t pllgfxclkspreadpercent;
2457 uint16_t pllgfxclkspreadfreq;
2458
2459
2460 uint8_t uclkspreadenabled;
2461 uint8_t uclkspreadpercent;
2462 uint16_t uclkspreadfreq;
2463
2464
2465 uint8_t fclkspreadenabled;
2466 uint8_t fclkspreadpercent;
2467 uint16_t fclkspreadfreq;
2468
2469
2470 uint8_t fllgfxclkspreadenabled;
2471 uint8_t fllgfxclkspreadpercent;
2472 uint16_t fllgfxclkspreadfreq;
2473
2474
2475 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7];
2476
2477
2478 uint32_t boardreserved[10];
2479};
2480
2481enum smudpm_v4_5_i2ccontrollername_e{
2482 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0,
2483 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC,
2484 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI,
2485 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD,
2486 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0,
2487 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1,
2488 SMC_V4_5_I2C_CONTROLLER_NAME_PLX,
2489 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE,
2490 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT,
2491};
2492
2493enum smudpm_v4_5_i2ccontrollerthrottler_e{
2494 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
2495 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX,
2496 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC,
2497 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI,
2498 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD,
2499 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0,
2500 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1,
2501 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX,
2502 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT,
2503};
2504
2505enum smudpm_v4_5_i2ccontrollerprotocol_e{
2506 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0,
2507 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1,
2508 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0,
2509 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1,
2510 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0,
2511 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1,
2512 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT,
2513};
2514
2515struct smudpm_i2c_controller_config_v2
2516{
2517 uint8_t Enabled;
2518 uint8_t Speed;
2519 uint8_t Padding[2];
2520 uint32_t SlaveAddress;
2521 uint8_t ControllerPort;
2522 uint8_t ControllerName;
2523 uint8_t ThermalThrotter;
2524 uint8_t I2cProtocol;
2525};
2526
2527struct atom_smc_dpm_info_v4_5
2528{
2529 struct atom_common_table_header table_header;
2530 // SECTION: BOARD PARAMETERS
2531 // I2C Control
2532 struct smudpm_i2c_controller_config_v2 I2cControllers[8];
2533
2534 // SVI2 Board Parameters
2535 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2536 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2537
2538 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2539 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2540 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2541 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2542
2543 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2544 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2545 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2546 uint8_t Padding8_V;
2547
2548 // Telemetry Settings
2549 uint16_t GfxMaxCurrent; // in Amps
2550 uint8_t GfxOffset; // in Amps
2551 uint8_t Padding_TelemetryGfx;
2552 uint16_t SocMaxCurrent; // in Amps
2553 uint8_t SocOffset; // in Amps
2554 uint8_t Padding_TelemetrySoc;
2555
2556 uint16_t Mem0MaxCurrent; // in Amps
2557 uint8_t Mem0Offset; // in Amps
2558 uint8_t Padding_TelemetryMem0;
2559
2560 uint16_t Mem1MaxCurrent; // in Amps
2561 uint8_t Mem1Offset; // in Amps
2562 uint8_t Padding_TelemetryMem1;
2563
2564 // GPIO Settings
2565 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2566 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2567 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2568 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2569
2570 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2571 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2572 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2573 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2574
2575 // LED Display Settings
2576 uint8_t LedPin0; // GPIO number for LedPin[0]
2577 uint8_t LedPin1; // GPIO number for LedPin[1]
2578 uint8_t LedPin2; // GPIO number for LedPin[2]
2579 uint8_t padding8_4;
2580
2581 // GFXCLK PLL Spread Spectrum
2582 uint8_t PllGfxclkSpreadEnabled; // on or off
2583 uint8_t PllGfxclkSpreadPercent; // Q4.4
2584 uint16_t PllGfxclkSpreadFreq; // kHz
2585
2586 // GFXCLK DFLL Spread Spectrum
2587 uint8_t DfllGfxclkSpreadEnabled; // on or off
2588 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2589 uint16_t DfllGfxclkSpreadFreq; // kHz
2590
2591 // UCLK Spread Spectrum
2592 uint8_t UclkSpreadEnabled; // on or off
2593 uint8_t UclkSpreadPercent; // Q4.4
2594 uint16_t UclkSpreadFreq; // kHz
2595
2596 // SOCCLK Spread Spectrum
2597 uint8_t SoclkSpreadEnabled; // on or off
2598 uint8_t SocclkSpreadPercent; // Q4.4
2599 uint16_t SocclkSpreadFreq; // kHz
2600
2601 // Total board power
2602 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2603 uint16_t BoardPadding;
2604
2605 // Mvdd Svi2 Div Ratio Setting
2606 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
2607
2608 uint32_t BoardReserved[9];
2609
2610};
2611
2612struct atom_smc_dpm_info_v4_6
2613{
2614 struct atom_common_table_header table_header;
2615 // section: board parameters
2616 uint32_t i2c_padding[3]; // old i2c control are moved to new area
2617
2618 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
2619 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
2620
2621 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields
2622 uint8_t vddsocvrmapping; // use vr_mapping* bitfields
2623 uint8_t vddmemvrmapping; // use vr_mapping* bitfields
2624 uint8_t boardvrmapping; // use vr_mapping* bitfields
2625
2626 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
2627 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in)
2628 uint8_t padding8_v[2];
2629
2630 // telemetry settings
2631 uint16_t gfxmaxcurrent; // in amps
2632 uint8_t gfxoffset; // in amps
2633 uint8_t padding_telemetrygfx;
2634
2635 uint16_t socmaxcurrent; // in amps
2636 uint8_t socoffset; // in amps
2637 uint8_t padding_telemetrysoc;
2638
2639 uint16_t memmaxcurrent; // in amps
2640 uint8_t memoffset; // in amps
2641 uint8_t padding_telemetrymem;
2642
2643 uint16_t boardmaxcurrent; // in amps
2644 uint8_t boardoffset; // in amps
2645 uint8_t padding_telemetryboardinput;
2646
2647 // gpio settings
2648 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event
2649 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event
2650 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event
2651 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event
2652
2653 // gfxclk pll spread spectrum
2654 uint8_t pllgfxclkspreadenabled; // on or off
2655 uint8_t pllgfxclkspreadpercent; // q4.4
2656 uint16_t pllgfxclkspreadfreq; // khz
2657
2658 // uclk spread spectrum
2659 uint8_t uclkspreadenabled; // on or off
2660 uint8_t uclkspreadpercent; // q4.4
2661 uint16_t uclkspreadfreq; // khz
2662
2663 // fclk spread spectrum
2664 uint8_t fclkspreadenabled; // on or off
2665 uint8_t fclkspreadpercent; // q4.4
2666 uint16_t fclkspreadfreq; // khz
2667
2668
2669 // gfxclk fll spread spectrum
2670 uint8_t fllgfxclkspreadenabled; // on or off
2671 uint8_t fllgfxclkspreadpercent; // q4.4
2672 uint16_t fllgfxclkspreadfreq; // khz
2673
2674 // i2c controller structure
2675 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8];
2676
2677 // memory section
2678 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask.
2679
2680 uint8_t drambitwidth; // for dram use only. see dram bit width type defines
2681 uint8_t paddingmem[3];
2682
2683 // total board power
2684 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power
2685 uint16_t boardpadding;
2686
2687 // section: xgmi training
2688 uint8_t xgmilinkspeed[4];
2689 uint8_t xgmilinkwidth[4];
2690
2691 uint16_t xgmifclkfreq[4];
2692 uint16_t xgmisocvoltage[4];
2693
2694 // reserved
2695 uint32_t boardreserved[10];
2696};
2697
2698struct atom_smc_dpm_info_v4_7
2699{
2700 struct atom_common_table_header table_header;
2701 // SECTION: BOARD PARAMETERS
2702 // I2C Control
2703 struct smudpm_i2c_controller_config_v2 I2cControllers[8];
2704
2705 // SVI2 Board Parameters
2706 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2707 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
2708
2709 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2710 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2711 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2712 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2713
2714 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2715 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2716 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2717 uint8_t Padding8_V;
2718
2719 // Telemetry Settings
2720 uint16_t GfxMaxCurrent; // in Amps
2721 uint8_t GfxOffset; // in Amps
2722 uint8_t Padding_TelemetryGfx;
2723 uint16_t SocMaxCurrent; // in Amps
2724 uint8_t SocOffset; // in Amps
2725 uint8_t Padding_TelemetrySoc;
2726
2727 uint16_t Mem0MaxCurrent; // in Amps
2728 uint8_t Mem0Offset; // in Amps
2729 uint8_t Padding_TelemetryMem0;
2730
2731 uint16_t Mem1MaxCurrent; // in Amps
2732 uint8_t Mem1Offset; // in Amps
2733 uint8_t Padding_TelemetryMem1;
2734
2735 // GPIO Settings
2736 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2737 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2738 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2739 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2740
2741 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2742 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2743 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2744 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2745
2746 // LED Display Settings
2747 uint8_t LedPin0; // GPIO number for LedPin[0]
2748 uint8_t LedPin1; // GPIO number for LedPin[1]
2749 uint8_t LedPin2; // GPIO number for LedPin[2]
2750 uint8_t padding8_4;
2751
2752 // GFXCLK PLL Spread Spectrum
2753 uint8_t PllGfxclkSpreadEnabled; // on or off
2754 uint8_t PllGfxclkSpreadPercent; // Q4.4
2755 uint16_t PllGfxclkSpreadFreq; // kHz
2756
2757 // GFXCLK DFLL Spread Spectrum
2758 uint8_t DfllGfxclkSpreadEnabled; // on or off
2759 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2760 uint16_t DfllGfxclkSpreadFreq; // kHz
2761
2762 // UCLK Spread Spectrum
2763 uint8_t UclkSpreadEnabled; // on or off
2764 uint8_t UclkSpreadPercent; // Q4.4
2765 uint16_t UclkSpreadFreq; // kHz
2766
2767 // SOCCLK Spread Spectrum
2768 uint8_t SoclkSpreadEnabled; // on or off
2769 uint8_t SocclkSpreadPercent; // Q4.4
2770 uint16_t SocclkSpreadFreq; // kHz
2771
2772 // Total board power
2773 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2774 uint16_t BoardPadding;
2775
2776 // Mvdd Svi2 Div Ratio Setting
2777 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
2778
2779 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
2780 uint8_t GpioI2cScl; // Serial Clock
2781 uint8_t GpioI2cSda; // Serial Data
2782 uint16_t GpioPadding;
2783
2784 // Additional LED Display Settings
2785 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed
2786 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status
2787 uint16_t LedEnableMask;
2788
2789 // Power Limit Scalars
2790 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT]
2791
2792 uint8_t MvddUlvPhaseSheddingMask;
2793 uint8_t VddciUlvPhaseSheddingMask;
2794 uint8_t Padding8_Psi1;
2795 uint8_t Padding8_Psi2;
2796
2797 uint32_t BoardReserved[5];
2798};
2799
2800struct smudpm_i2c_controller_config_v3
2801{
2802 uint8_t Enabled;
2803 uint8_t Speed;
2804 uint8_t SlaveAddress;
2805 uint8_t ControllerPort;
2806 uint8_t ControllerName;
2807 uint8_t ThermalThrotter;
2808 uint8_t I2cProtocol;
2809 uint8_t PaddingConfig;
2810};
2811
2812struct atom_smc_dpm_info_v4_9
2813{
2814 struct atom_common_table_header table_header;
2815
2816 //SECTION: Gaming Clocks
2817 //uint32_t GamingClk[6];
2818
2819 // SECTION: I2C Control
2820 struct smudpm_i2c_controller_config_v3 I2cControllers[16];
2821
2822 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1
2823 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1
2824 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off
2825 uint8_t I2cSpare;
2826
2827 // SECTION: SVI2 Board Parameters
2828 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2829 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2830 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2831 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2832
2833 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2834 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2835 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2836 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2837
2838 // SECTION: Telemetry Settings
2839 uint16_t GfxMaxCurrent; // in Amps
2840 uint8_t GfxOffset; // in Amps
2841 uint8_t Padding_TelemetryGfx;
2842
2843 uint16_t SocMaxCurrent; // in Amps
2844 uint8_t SocOffset; // in Amps
2845 uint8_t Padding_TelemetrySoc;
2846
2847 uint16_t Mem0MaxCurrent; // in Amps
2848 uint8_t Mem0Offset; // in Amps
2849 uint8_t Padding_TelemetryMem0;
2850
2851 uint16_t Mem1MaxCurrent; // in Amps
2852 uint8_t Mem1Offset; // in Amps
2853 uint8_t Padding_TelemetryMem1;
2854
2855 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
2856
2857 // SECTION: GPIO Settings
2858 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2859 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2860 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2861 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2862
2863 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2864 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2865 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2866 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2867
2868 // LED Display Settings
2869 uint8_t LedPin0; // GPIO number for LedPin[0]
2870 uint8_t LedPin1; // GPIO number for LedPin[1]
2871 uint8_t LedPin2; // GPIO number for LedPin[2]
2872 uint8_t LedEnableMask;
2873
2874 uint8_t LedPcie; // GPIO number for PCIE results
2875 uint8_t LedError; // GPIO number for Error Cases
2876 uint8_t LedSpare1[2];
2877
2878 // SECTION: Clock Spread Spectrum
2879
2880 // GFXCLK PLL Spread Spectrum
2881 uint8_t PllGfxclkSpreadEnabled; // on or off
2882 uint8_t PllGfxclkSpreadPercent; // Q4.4
2883 uint16_t PllGfxclkSpreadFreq; // kHz
2884
2885 // GFXCLK DFLL Spread Spectrum
2886 uint8_t DfllGfxclkSpreadEnabled; // on or off
2887 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2888 uint16_t DfllGfxclkSpreadFreq; // kHz
2889
2890 // UCLK Spread Spectrum
2891 uint8_t UclkSpreadEnabled; // on or off
2892 uint8_t UclkSpreadPercent; // Q4.4
2893 uint16_t UclkSpreadFreq; // kHz
2894
2895 // FCLK Spread Spectrum
2896 uint8_t FclkSpreadEnabled; // on or off
2897 uint8_t FclkSpreadPercent; // Q4.4
2898 uint16_t FclkSpreadFreq; // kHz
2899
2900 // Section: Memory Config
2901 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
2902
2903 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines
2904 uint8_t PaddingMem1[3];
2905
2906 // Section: Total Board Power
2907 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
2908 uint16_t BoardPowerPadding;
2909
2910 // SECTION: XGMI Training
2911 uint8_t XgmiLinkSpeed [4];
2912 uint8_t XgmiLinkWidth [4];
2913
2914 uint16_t XgmiFclkFreq [4];
2915 uint16_t XgmiSocVoltage [4];
2916
2917 // SECTION: Board Reserved
2918
2919 uint32_t BoardReserved[16];
2920
2921};
2922
2923struct atom_smc_dpm_info_v4_10
2924{
2925 struct atom_common_table_header table_header;
2926
2927 // SECTION: BOARD PARAMETERS
2928 // Telemetry Settings
2929 uint16_t GfxMaxCurrent; // in Amps
2930 uint8_t GfxOffset; // in Amps
2931 uint8_t Padding_TelemetryGfx;
2932
2933 uint16_t SocMaxCurrent; // in Amps
2934 uint8_t SocOffset; // in Amps
2935 uint8_t Padding_TelemetrySoc;
2936
2937 uint16_t MemMaxCurrent; // in Amps
2938 uint8_t MemOffset; // in Amps
2939 uint8_t Padding_TelemetryMem;
2940
2941 uint16_t BoardMaxCurrent; // in Amps
2942 uint8_t BoardOffset; // in Amps
2943 uint8_t Padding_TelemetryBoardInput;
2944
2945 // Platform input telemetry voltage coefficient
2946 uint32_t BoardVoltageCoeffA; // decode by /1000
2947 uint32_t BoardVoltageCoeffB; // decode by /1000
2948
2949 // GPIO Settings
2950 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2951 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2952 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2953 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2954
2955 // UCLK Spread Spectrum
2956 uint8_t UclkSpreadEnabled; // on or off
2957 uint8_t UclkSpreadPercent; // Q4.4
2958 uint16_t UclkSpreadFreq; // kHz
2959
2960 // FCLK Spread Spectrum
2961 uint8_t FclkSpreadEnabled; // on or off
2962 uint8_t FclkSpreadPercent; // Q4.4
2963 uint16_t FclkSpreadFreq; // kHz
2964
2965 // I2C Controller Structure
2966 struct smudpm_i2c_controller_config_v3 I2cControllers[8];
2967
2968 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
2969 uint8_t GpioI2cScl; // Serial Clock
2970 uint8_t GpioI2cSda; // Serial Data
2971 uint16_t spare5;
2972
2973 uint32_t reserved[16];
2974};
2975
2976/*
2977 ***************************************************************************
2978 Data Table asic_profiling_info structure
2979 ***************************************************************************
2980*/
2981struct atom_asic_profiling_info_v4_1
2982{
2983 struct atom_common_table_header table_header;
2984 uint32_t maxvddc;
2985 uint32_t minvddc;
2986 uint32_t avfs_meannsigma_acontant0;
2987 uint32_t avfs_meannsigma_acontant1;
2988 uint32_t avfs_meannsigma_acontant2;
2989 uint16_t avfs_meannsigma_dc_tol_sigma;
2990 uint16_t avfs_meannsigma_platform_mean;
2991 uint16_t avfs_meannsigma_platform_sigma;
2992 uint32_t gb_vdroop_table_cksoff_a0;
2993 uint32_t gb_vdroop_table_cksoff_a1;
2994 uint32_t gb_vdroop_table_cksoff_a2;
2995 uint32_t gb_vdroop_table_ckson_a0;
2996 uint32_t gb_vdroop_table_ckson_a1;
2997 uint32_t gb_vdroop_table_ckson_a2;
2998 uint32_t avfsgb_fuse_table_cksoff_m1;
2999 uint32_t avfsgb_fuse_table_cksoff_m2;
3000 uint32_t avfsgb_fuse_table_cksoff_b;
3001 uint32_t avfsgb_fuse_table_ckson_m1;
3002 uint32_t avfsgb_fuse_table_ckson_m2;
3003 uint32_t avfsgb_fuse_table_ckson_b;
3004 uint16_t max_voltage_0_25mv;
3005 uint8_t enable_gb_vdroop_table_cksoff;
3006 uint8_t enable_gb_vdroop_table_ckson;
3007 uint8_t enable_gb_fuse_table_cksoff;
3008 uint8_t enable_gb_fuse_table_ckson;
3009 uint16_t psm_age_comfactor;
3010 uint8_t enable_apply_avfs_cksoff_voltage;
3011 uint8_t reserved;
3012 uint32_t dispclk2gfxclk_a;
3013 uint32_t dispclk2gfxclk_b;
3014 uint32_t dispclk2gfxclk_c;
3015 uint32_t pixclk2gfxclk_a;
3016 uint32_t pixclk2gfxclk_b;
3017 uint32_t pixclk2gfxclk_c;
3018 uint32_t dcefclk2gfxclk_a;
3019 uint32_t dcefclk2gfxclk_b;
3020 uint32_t dcefclk2gfxclk_c;
3021 uint32_t phyclk2gfxclk_a;
3022 uint32_t phyclk2gfxclk_b;
3023 uint32_t phyclk2gfxclk_c;
3024};
3025
3026struct atom_asic_profiling_info_v4_2 {
3027 struct atom_common_table_header table_header;
3028 uint32_t maxvddc;
3029 uint32_t minvddc;
3030 uint32_t avfs_meannsigma_acontant0;
3031 uint32_t avfs_meannsigma_acontant1;
3032 uint32_t avfs_meannsigma_acontant2;
3033 uint16_t avfs_meannsigma_dc_tol_sigma;
3034 uint16_t avfs_meannsigma_platform_mean;
3035 uint16_t avfs_meannsigma_platform_sigma;
3036 uint32_t gb_vdroop_table_cksoff_a0;
3037 uint32_t gb_vdroop_table_cksoff_a1;
3038 uint32_t gb_vdroop_table_cksoff_a2;
3039 uint32_t gb_vdroop_table_ckson_a0;
3040 uint32_t gb_vdroop_table_ckson_a1;
3041 uint32_t gb_vdroop_table_ckson_a2;
3042 uint32_t avfsgb_fuse_table_cksoff_m1;
3043 uint32_t avfsgb_fuse_table_cksoff_m2;
3044 uint32_t avfsgb_fuse_table_cksoff_b;
3045 uint32_t avfsgb_fuse_table_ckson_m1;
3046 uint32_t avfsgb_fuse_table_ckson_m2;
3047 uint32_t avfsgb_fuse_table_ckson_b;
3048 uint16_t max_voltage_0_25mv;
3049 uint8_t enable_gb_vdroop_table_cksoff;
3050 uint8_t enable_gb_vdroop_table_ckson;
3051 uint8_t enable_gb_fuse_table_cksoff;
3052 uint8_t enable_gb_fuse_table_ckson;
3053 uint16_t psm_age_comfactor;
3054 uint8_t enable_apply_avfs_cksoff_voltage;
3055 uint8_t reserved;
3056 uint32_t dispclk2gfxclk_a;
3057 uint32_t dispclk2gfxclk_b;
3058 uint32_t dispclk2gfxclk_c;
3059 uint32_t pixclk2gfxclk_a;
3060 uint32_t pixclk2gfxclk_b;
3061 uint32_t pixclk2gfxclk_c;
3062 uint32_t dcefclk2gfxclk_a;
3063 uint32_t dcefclk2gfxclk_b;
3064 uint32_t dcefclk2gfxclk_c;
3065 uint32_t phyclk2gfxclk_a;
3066 uint32_t phyclk2gfxclk_b;
3067 uint32_t phyclk2gfxclk_c;
3068 uint32_t acg_gb_vdroop_table_a0;
3069 uint32_t acg_gb_vdroop_table_a1;
3070 uint32_t acg_gb_vdroop_table_a2;
3071 uint32_t acg_avfsgb_fuse_table_m1;
3072 uint32_t acg_avfsgb_fuse_table_m2;
3073 uint32_t acg_avfsgb_fuse_table_b;
3074 uint8_t enable_acg_gb_vdroop_table;
3075 uint8_t enable_acg_gb_fuse_table;
3076 uint32_t acg_dispclk2gfxclk_a;
3077 uint32_t acg_dispclk2gfxclk_b;
3078 uint32_t acg_dispclk2gfxclk_c;
3079 uint32_t acg_pixclk2gfxclk_a;
3080 uint32_t acg_pixclk2gfxclk_b;
3081 uint32_t acg_pixclk2gfxclk_c;
3082 uint32_t acg_dcefclk2gfxclk_a;
3083 uint32_t acg_dcefclk2gfxclk_b;
3084 uint32_t acg_dcefclk2gfxclk_c;
3085 uint32_t acg_phyclk2gfxclk_a;
3086 uint32_t acg_phyclk2gfxclk_b;
3087 uint32_t acg_phyclk2gfxclk_c;
3088};
3089
3090/*
3091 ***************************************************************************
3092 Data Table multimedia_info structure
3093 ***************************************************************************
3094*/
3095struct atom_multimedia_info_v2_1
3096{
3097 struct atom_common_table_header table_header;
3098 uint8_t uvdip_min_ver;
3099 uint8_t uvdip_max_ver;
3100 uint8_t vceip_min_ver;
3101 uint8_t vceip_max_ver;
3102 uint16_t uvd_enc_max_input_width_pixels;
3103 uint16_t uvd_enc_max_input_height_pixels;
3104 uint16_t vce_enc_max_input_width_pixels;
3105 uint16_t vce_enc_max_input_height_pixels;
3106 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
3107 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
3108};
3109
3110
3111/*
3112 ***************************************************************************
3113 Data Table umc_info structure
3114 ***************************************************************************
3115*/
3116struct atom_umc_info_v3_1
3117{
3118 struct atom_common_table_header table_header;
3119 uint32_t ucode_version;
3120 uint32_t ucode_rom_startaddr;
3121 uint32_t ucode_length;
3122 uint16_t umc_reg_init_offset;
3123 uint16_t customer_ucode_name_offset;
3124 uint16_t mclk_ss_percentage;
3125 uint16_t mclk_ss_rate_10hz;
3126 uint8_t umcip_min_ver;
3127 uint8_t umcip_max_ver;
3128 uint8_t vram_type; //enum of atom_dgpu_vram_type
3129 uint8_t umc_config;
3130 uint32_t mem_refclk_10khz;
3131};
3132
3133// umc_info.umc_config
3134enum atom_umc_config_def {
3135 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001,
3136 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002,
3137 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004,
3138 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008,
3139 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010,
3140 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020,
3141};
3142
3143struct atom_umc_info_v3_2
3144{
3145 struct atom_common_table_header table_header;
3146 uint32_t ucode_version;
3147 uint32_t ucode_rom_startaddr;
3148 uint32_t ucode_length;
3149 uint16_t umc_reg_init_offset;
3150 uint16_t customer_ucode_name_offset;
3151 uint16_t mclk_ss_percentage;
3152 uint16_t mclk_ss_rate_10hz;
3153 uint8_t umcip_min_ver;
3154 uint8_t umcip_max_ver;
3155 uint8_t vram_type; //enum of atom_dgpu_vram_type
3156 uint8_t umc_config;
3157 uint32_t mem_refclk_10khz;
3158 uint32_t pstate_uclk_10khz[4];
3159 uint16_t umcgoldenoffset;
3160 uint16_t densitygoldenoffset;
3161};
3162
3163struct atom_umc_info_v3_3
3164{
3165 struct atom_common_table_header table_header;
3166 uint32_t ucode_reserved;
3167 uint32_t ucode_rom_startaddr;
3168 uint32_t ucode_length;
3169 uint16_t umc_reg_init_offset;
3170 uint16_t customer_ucode_name_offset;
3171 uint16_t mclk_ss_percentage;
3172 uint16_t mclk_ss_rate_10hz;
3173 uint8_t umcip_min_ver;
3174 uint8_t umcip_max_ver;
3175 uint8_t vram_type; //enum of atom_dgpu_vram_type
3176 uint8_t umc_config;
3177 uint32_t mem_refclk_10khz;
3178 uint32_t pstate_uclk_10khz[4];
3179 uint16_t umcgoldenoffset;
3180 uint16_t densitygoldenoffset;
3181 uint32_t umc_config1;
3182 uint32_t bist_data_startaddr;
3183 uint32_t reserved[2];
3184};
3185
3186enum atom_umc_config1_def {
3187 UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001,
3188 UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002,
3189 UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004,
3190 UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008,
3191 UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010,
3192 UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000,
3193};
3194
3195struct atom_umc_info_v4_0 {
3196 struct atom_common_table_header table_header;
3197 uint32_t ucode_reserved[5];
3198 uint8_t umcip_min_ver;
3199 uint8_t umcip_max_ver;
3200 uint8_t vram_type;
3201 uint8_t umc_config;
3202 uint32_t mem_refclk_10khz;
3203 uint32_t clk_reserved[4];
3204 uint32_t golden_reserved;
3205 uint32_t umc_config1;
3206 uint32_t reserved[2];
3207 uint8_t channel_num;
3208 uint8_t channel_width;
3209 uint8_t channel_reserve[2];
3210 uint8_t umc_info_reserved[16];
3211};
3212
3213/*
3214 ***************************************************************************
3215 Data Table vram_info structure
3216 ***************************************************************************
3217*/
3218struct atom_vram_module_v9 {
3219 // Design Specific Values
3220 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
3221 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
3222 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
3223 uint16_t reserved[3];
3224 uint16_t mem_voltage; // mem_voltage
3225 uint16_t vram_module_size; // Size of atom_vram_module_v9
3226 uint8_t ext_memory_id; // Current memory module ID
3227 uint8_t memory_type; // enum of atom_dgpu_vram_type
3228 uint8_t channel_num; // Number of mem. channels supported in this module
3229 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3230 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3231 uint8_t tunningset_id; // MC phy registers set per.
3232 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3233 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3234 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id
3235 uint8_t vram_rsd2; // reserved
3236 char dram_pnstring[20]; // part number end with '0'.
3237};
3238
3239struct atom_vram_info_header_v2_3 {
3240 struct atom_common_table_header table_header;
3241 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
3242 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
3243 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
3244 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
3245 uint16_t dram_data_remap_tbloffset; // reserved for now
3246 uint16_t tmrs_seq_offset; // offset of HBM tmrs
3247 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
3248 uint16_t vram_rsd2;
3249 uint8_t vram_module_num; // indicate number of VRAM module
3250 uint8_t umcip_min_ver;
3251 uint8_t umcip_max_ver;
3252 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3253 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
3254};
3255
3256/*
3257 ***************************************************************************
3258 Data Table vram_info v3.0 structure
3259 ***************************************************************************
3260*/
3261struct atom_vram_module_v3_0 {
3262 uint8_t density;
3263 uint8_t tunningset_id;
3264 uint8_t ext_memory_id;
3265 uint8_t dram_vendor_id;
3266 uint16_t dram_info_offset;
3267 uint16_t mem_tuning_offset;
3268 uint16_t tmrs_seq_offset;
3269 uint16_t reserved1;
3270 uint32_t dram_size_per_ch;
3271 uint32_t reserved[3];
3272 char dram_pnstring[40];
3273};
3274
3275struct atom_vram_info_header_v3_0 {
3276 struct atom_common_table_header table_header;
3277 uint16_t mem_tuning_table_offset;
3278 uint16_t dram_info_table_offset;
3279 uint16_t tmrs_table_offset;
3280 uint16_t mc_init_table_offset;
3281 uint16_t dram_data_remap_table_offset;
3282 uint16_t umc_emuinittable_offset;
3283 uint16_t reserved_sub_table_offset[2];
3284 uint8_t vram_module_num;
3285 uint8_t umcip_min_ver;
3286 uint8_t umcip_max_ver;
3287 uint8_t mc_phy_tile_num;
3288 uint8_t memory_type;
3289 uint8_t channel_num;
3290 uint8_t channel_width;
3291 uint8_t reserved1;
3292 uint32_t channel_enable;
3293 uint32_t channel1_enable;
3294 uint32_t feature_enable;
3295 uint32_t feature1_enable;
3296 uint32_t hardcode_mem_size;
3297 uint32_t reserved4[4];
3298 struct atom_vram_module_v3_0 vram_module[8];
3299};
3300
3301struct atom_umc_register_addr_info{
3302 uint32_t umc_register_addr:24;
3303 uint32_t umc_reg_type_ind:1;
3304 uint32_t umc_reg_rsvd:7;
3305};
3306
3307//atom_umc_register_addr_info.
3308enum atom_umc_register_addr_info_flag{
3309 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01,
3310};
3311
3312union atom_umc_register_addr_info_access
3313{
3314 struct atom_umc_register_addr_info umc_reg_addr;
3315 uint32_t u32umc_reg_addr;
3316};
3317
3318struct atom_umc_reg_setting_id_config{
3319 uint32_t memclockrange:24;
3320 uint32_t mem_blk_id:8;
3321};
3322
3323union atom_umc_reg_setting_id_config_access
3324{
3325 struct atom_umc_reg_setting_id_config umc_id_access;
3326 uint32_t u32umc_id_access;
3327};
3328
3329struct atom_umc_reg_setting_data_block{
3330 union atom_umc_reg_setting_id_config_access block_id;
3331 uint32_t u32umc_reg_data[1];
3332};
3333
3334struct atom_umc_init_reg_block{
3335 uint16_t umc_reg_num;
3336 uint16_t reserved;
3337 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num;
3338 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
3339};
3340
3341struct atom_vram_module_v10 {
3342 // Design Specific Values
3343 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
3344 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
3345 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
3346 uint16_t reserved[3];
3347 uint16_t mem_voltage; // mem_voltage
3348 uint16_t vram_module_size; // Size of atom_vram_module_v9
3349 uint8_t ext_memory_id; // Current memory module ID
3350 uint8_t memory_type; // enum of atom_dgpu_vram_type
3351 uint8_t channel_num; // Number of mem. channels supported in this module
3352 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3353 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3354 uint8_t tunningset_id; // MC phy registers set per
3355 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3356 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3357 uint8_t vram_flags; // bit0= bankgroup enable
3358 uint8_t vram_rsd2; // reserved
3359 uint16_t gddr6_mr10; // gddr6 mode register10 value
3360 uint16_t gddr6_mr1; // gddr6 mode register1 value
3361 uint16_t gddr6_mr2; // gddr6 mode register2 value
3362 uint16_t gddr6_mr7; // gddr6 mode register7 value
3363 char dram_pnstring[20]; // part number end with '0'
3364};
3365
3366struct atom_vram_info_header_v2_4 {
3367 struct atom_common_table_header table_header;
3368 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
3369 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
3370 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
3371 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
3372 uint16_t dram_data_remap_tbloffset; // reserved for now
3373 uint16_t reserved; // offset of reserved
3374 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
3375 uint16_t vram_rsd2;
3376 uint8_t vram_module_num; // indicate number of VRAM module
3377 uint8_t umcip_min_ver;
3378 uint8_t umcip_max_ver;
3379 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3380 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
3381};
3382
3383struct atom_vram_module_v11 {
3384 // Design Specific Values
3385 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
3386 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
3387 uint16_t mem_voltage; // mem_voltage
3388 uint16_t vram_module_size; // Size of atom_vram_module_v9
3389 uint8_t ext_memory_id; // Current memory module ID
3390 uint8_t memory_type; // enum of atom_dgpu_vram_type
3391 uint8_t channel_num; // Number of mem. channels supported in this module
3392 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3393 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3394 uint8_t tunningset_id; // MC phy registers set per.
3395 uint16_t reserved[4]; // reserved
3396 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3397 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3398 uint8_t vram_flags; // bit0= bankgroup enable
3399 uint8_t vram_rsd2; // reserved
3400 uint16_t gddr6_mr10; // gddr6 mode register10 value
3401 uint16_t gddr6_mr0; // gddr6 mode register0 value
3402 uint16_t gddr6_mr1; // gddr6 mode register1 value
3403 uint16_t gddr6_mr2; // gddr6 mode register2 value
3404 uint16_t gddr6_mr4; // gddr6 mode register4 value
3405 uint16_t gddr6_mr7; // gddr6 mode register7 value
3406 uint16_t gddr6_mr8; // gddr6 mode register8 value
3407 char dram_pnstring[40]; // part number end with '0'.
3408};
3409
3410struct atom_gddr6_ac_timing_v2_5 {
3411 uint32_t u32umc_id_access;
3412 uint8_t RL;
3413 uint8_t WL;
3414 uint8_t tRAS;
3415 uint8_t tRC;
3416
3417 uint16_t tREFI;
3418 uint8_t tRFC;
3419 uint8_t tRFCpb;
3420
3421 uint8_t tRREFD;
3422 uint8_t tRCDRD;
3423 uint8_t tRCDWR;
3424 uint8_t tRP;
3425
3426 uint8_t tRRDS;
3427 uint8_t tRRDL;
3428 uint8_t tWR;
3429 uint8_t tWTRS;
3430
3431 uint8_t tWTRL;
3432 uint8_t tFAW;
3433 uint8_t tCCDS;
3434 uint8_t tCCDL;
3435
3436 uint8_t tCRCRL;
3437 uint8_t tCRCWL;
3438 uint8_t tCKE;
3439 uint8_t tCKSRE;
3440
3441 uint8_t tCKSRX;
3442 uint8_t tRTPS;
3443 uint8_t tRTPL;
3444 uint8_t tMRD;
3445
3446 uint8_t tMOD;
3447 uint8_t tXS;
3448 uint8_t tXHP;
3449 uint8_t tXSMRS;
3450
3451 uint32_t tXSH;
3452
3453 uint8_t tPD;
3454 uint8_t tXP;
3455 uint8_t tCPDED;
3456 uint8_t tACTPDE;
3457
3458 uint8_t tPREPDE;
3459 uint8_t tREFPDE;
3460 uint8_t tMRSPDEN;
3461 uint8_t tRDSRE;
3462
3463 uint8_t tWRSRE;
3464 uint8_t tPPD;
3465 uint8_t tCCDMW;
3466 uint8_t tWTRTR;
3467
3468 uint8_t tLTLTR;
3469 uint8_t tREFTR;
3470 uint8_t VNDR;
3471 uint8_t reserved[9];
3472};
3473
3474struct atom_gddr6_bit_byte_remap {
3475 uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap
3476 uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0
3477 uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1
3478 uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2
3479 uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0
3480 uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1
3481 uint32_t phy_dram; //mmUMC_PHY_DRAM
3482};
3483
3484struct atom_gddr6_dram_data_remap {
3485 uint32_t table_size;
3486 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK
3487 struct atom_gddr6_bit_byte_remap bit_byte_remap[16];
3488};
3489
3490struct atom_vram_info_header_v2_5 {
3491 struct atom_common_table_header table_header;
3492 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings
3493 uint16_t gddr6_ac_timing_offset; // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings
3494 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
3495 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
3496 uint16_t dram_data_remap_tbloffset; // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping
3497 uint16_t reserved; // offset of reserved
3498 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
3499 uint16_t strobe_mode_patch_tbloffset; // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings
3500 uint8_t vram_module_num; // indicate number of VRAM module
3501 uint8_t umcip_min_ver;
3502 uint8_t umcip_max_ver;
3503 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3504 struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
3505};
3506
3507struct atom_vram_info_header_v2_6 {
3508 struct atom_common_table_header table_header;
3509 uint16_t mem_adjust_tbloffset;
3510 uint16_t mem_clk_patch_tbloffset;
3511 uint16_t mc_adjust_pertile_tbloffset;
3512 uint16_t mc_phyinit_tbloffset;
3513 uint16_t dram_data_remap_tbloffset;
3514 uint16_t tmrs_seq_offset;
3515 uint16_t post_ucode_init_offset;
3516 uint16_t vram_rsd2;
3517 uint8_t vram_module_num;
3518 uint8_t umcip_min_ver;
3519 uint8_t umcip_max_ver;
3520 uint8_t mc_phy_tile_num;
3521 struct atom_vram_module_v9 vram_module[16];
3522};
3523/*
3524 ***************************************************************************
3525 Data Table voltageobject_info structure
3526 ***************************************************************************
3527*/
3528struct atom_i2c_data_entry
3529{
3530 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit
3531 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit
3532};
3533
3534struct atom_voltage_object_header_v4{
3535 uint8_t voltage_type; //enum atom_voltage_type
3536 uint8_t voltage_mode; //enum atom_voltage_object_mode
3537 uint16_t object_size; //Size of Object
3538};
3539
3540// atom_voltage_object_header_v4.voltage_mode
3541enum atom_voltage_object_mode
3542{
3543 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4
3544 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4
3545 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4
3546 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4
3547 VOLTAGE_OBJ_EVV = 8,
3548 VOLTAGE_OBJ_MERGED_POWER = 9,
3549};
3550
3551struct atom_i2c_voltage_object_v4
3552{
3553 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
3554 uint8_t regulator_id; //Indicate Voltage Regulator Id
3555 uint8_t i2c_id;
3556 uint8_t i2c_slave_addr;
3557 uint8_t i2c_control_offset;
3558 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
3559 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz.
3560 uint8_t reserved[2];
3561 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff
3562};
3563
3564// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
3565enum atom_i2c_voltage_control_flag
3566{
3567 VOLTAGE_DATA_ONE_BYTE = 0,
3568 VOLTAGE_DATA_TWO_BYTE = 1,
3569};
3570
3571
3572struct atom_voltage_gpio_map_lut
3573{
3574 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register
3575 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV
3576};
3577
3578struct atom_gpio_voltage_object_v4
3579{
3580 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
3581 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode
3582 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table
3583 uint8_t phase_delay_us; // phase delay in unit of micro second
3584 uint8_t reserved;
3585 uint32_t gpio_mask_val; // GPIO Mask value
3586 struct atom_voltage_gpio_map_lut voltage_gpio_lut[] __counted_by(gpio_entry_num);
3587};
3588
3589struct atom_svid2_voltage_object_v4
3590{
3591 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2
3592 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
3593 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
3594 uint8_t psi0_enable; //
3595 uint8_t maxvstep;
3596 uint8_t telemetry_offset;
3597 uint8_t telemetry_gain;
3598 uint16_t reserved1;
3599};
3600
3601struct atom_merged_voltage_object_v4
3602{
3603 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER
3604 uint8_t merged_powerrail_type; //enum atom_voltage_type
3605 uint8_t reserved[3];
3606};
3607
3608union atom_voltage_object_v4{
3609 struct atom_gpio_voltage_object_v4 gpio_voltage_obj;
3610 struct atom_i2c_voltage_object_v4 i2c_voltage_obj;
3611 struct atom_svid2_voltage_object_v4 svid2_voltage_obj;
3612 struct atom_merged_voltage_object_v4 merged_voltage_obj;
3613};
3614
3615struct atom_voltage_objects_info_v4_1
3616{
3617 struct atom_common_table_header table_header;
3618 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control
3619};
3620
3621
3622/*
3623 ***************************************************************************
3624 All Command Function structure definition
3625 ***************************************************************************
3626*/
3627
3628/*
3629 ***************************************************************************
3630 Structures used by asic_init
3631 ***************************************************************************
3632*/
3633
3634struct asic_init_engine_parameters
3635{
3636 uint32_t sclkfreqin10khz:24;
3637 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */
3638};
3639
3640struct asic_init_mem_parameters
3641{
3642 uint32_t mclkfreqin10khz:24;
3643 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */
3644};
3645
3646struct asic_init_parameters_v2_1
3647{
3648 struct asic_init_engine_parameters engineparam;
3649 struct asic_init_mem_parameters memparam;
3650};
3651
3652struct asic_init_ps_allocation_v2_1
3653{
3654 struct asic_init_parameters_v2_1 param;
3655 uint32_t reserved[16];
3656};
3657
3658
3659enum atom_asic_init_engine_flag
3660{
3661 b3NORMAL_ENGINE_INIT = 0,
3662 b3SRIOV_SKIP_ASIC_INIT = 0x02,
3663 b3SRIOV_LOAD_UCODE = 0x40,
3664};
3665
3666enum atom_asic_init_mem_flag
3667{
3668 b3NORMAL_MEM_INIT = 0,
3669 b3DRAM_SELF_REFRESH_EXIT =0x20,
3670};
3671
3672/*
3673 ***************************************************************************
3674 Structures used by setengineclock
3675 ***************************************************************************
3676*/
3677
3678struct set_engine_clock_parameters_v2_1
3679{
3680 uint32_t sclkfreqin10khz:24;
3681 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
3682 uint32_t reserved[10];
3683};
3684
3685struct set_engine_clock_ps_allocation_v2_1
3686{
3687 struct set_engine_clock_parameters_v2_1 clockinfo;
3688 uint32_t reserved[10];
3689};
3690
3691
3692enum atom_set_engine_mem_clock_flag
3693{
3694 b3NORMAL_CHANGE_CLOCK = 0,
3695 b3FIRST_TIME_CHANGE_CLOCK = 0x08,
3696 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result
3697};
3698
3699/*
3700 ***************************************************************************
3701 Structures used by getengineclock
3702 ***************************************************************************
3703*/
3704struct get_engine_clock_parameter
3705{
3706 uint32_t sclk_10khz; // current engine speed in 10KHz unit
3707 uint32_t reserved;
3708};
3709
3710/*
3711 ***************************************************************************
3712 Structures used by setmemoryclock
3713 ***************************************************************************
3714*/
3715struct set_memory_clock_parameters_v2_1
3716{
3717 uint32_t mclkfreqin10khz:24;
3718 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
3719 uint32_t reserved[10];
3720};
3721
3722struct set_memory_clock_ps_allocation_v2_1
3723{
3724 struct set_memory_clock_parameters_v2_1 clockinfo;
3725 uint32_t reserved[10];
3726};
3727
3728
3729/*
3730 ***************************************************************************
3731 Structures used by getmemoryclock
3732 ***************************************************************************
3733*/
3734struct get_memory_clock_parameter
3735{
3736 uint32_t mclk_10khz; // current engine speed in 10KHz unit
3737 uint32_t reserved;
3738};
3739
3740
3741
3742/*
3743 ***************************************************************************
3744 Structures used by setvoltage
3745 ***************************************************************************
3746*/
3747
3748struct set_voltage_parameters_v1_4
3749{
3750 uint8_t voltagetype; /* enum atom_voltage_type */
3751 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */
3752 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */
3753};
3754
3755//set_voltage_parameters_v2_1.voltagemode
3756enum atom_set_voltage_command{
3757 ATOM_SET_VOLTAGE = 0,
3758 ATOM_INIT_VOLTAGE_REGULATOR = 3,
3759 ATOM_SET_VOLTAGE_PHASE = 4,
3760 ATOM_GET_LEAKAGE_ID = 8,
3761};
3762
3763struct set_voltage_ps_allocation_v1_4
3764{
3765 struct set_voltage_parameters_v1_4 setvoltageparam;
3766 uint32_t reserved[10];
3767};
3768
3769
3770/*
3771 ***************************************************************************
3772 Structures used by computegpuclockparam
3773 ***************************************************************************
3774*/
3775
3776//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
3777enum atom_gpu_clock_type
3778{
3779 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
3780 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
3781 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
3782};
3783
3784struct compute_gpu_clock_input_parameter_v1_8
3785{
3786 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
3787 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type
3788 uint32_t reserved[5];
3789};
3790
3791
3792struct compute_gpu_clock_output_parameter_v1_8
3793{
3794 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
3795 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly
3796 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
3797 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac
3798 uint16_t pll_ss_slew_frac;
3799 uint8_t pll_ss_enable;
3800 uint8_t reserved;
3801 uint32_t reserved1[2];
3802};
3803
3804
3805
3806/*
3807 ***************************************************************************
3808 Structures used by ReadEfuseValue
3809 ***************************************************************************
3810*/
3811
3812struct read_efuse_input_parameters_v3_1
3813{
3814 uint16_t efuse_start_index;
3815 uint8_t reserved;
3816 uint8_t bitslen;
3817};
3818
3819// ReadEfuseValue input/output parameter
3820union read_efuse_value_parameters_v3_1
3821{
3822 struct read_efuse_input_parameters_v3_1 efuse_info;
3823 uint32_t efusevalue;
3824};
3825
3826
3827/*
3828 ***************************************************************************
3829 Structures used by getsmuclockinfo
3830 ***************************************************************************
3831*/
3832struct atom_get_smu_clock_info_parameters_v3_1
3833{
3834 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
3835 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3836 uint8_t command; // enum of atom_get_smu_clock_info_command
3837 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3838};
3839
3840enum atom_get_smu_clock_info_command
3841{
3842 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0,
3843 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1,
3844 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2,
3845};
3846
3847enum atom_smu9_syspll0_clock_id
3848{
3849 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK
3850 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK)
3851 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
3852 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK
3853 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK
3854 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK
3855 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK
3856 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK
3857 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK
3858 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK
3859 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
3860};
3861
3862enum atom_smu11_syspll_id {
3863 SMU11_SYSPLL0_ID = 0,
3864 SMU11_SYSPLL1_0_ID = 1,
3865 SMU11_SYSPLL1_1_ID = 2,
3866 SMU11_SYSPLL1_2_ID = 3,
3867 SMU11_SYSPLL2_ID = 4,
3868 SMU11_SYSPLL3_0_ID = 5,
3869 SMU11_SYSPLL3_1_ID = 6,
3870};
3871
3872enum atom_smu11_syspll0_clock_id {
3873 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK
3874 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK
3875 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
3876 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK
3877 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK
3878 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
3879};
3880
3881enum atom_smu11_syspll1_0_clock_id {
3882 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
3883};
3884
3885enum atom_smu11_syspll1_1_clock_id {
3886 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
3887};
3888
3889enum atom_smu11_syspll1_2_clock_id {
3890 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
3891};
3892
3893enum atom_smu11_syspll2_clock_id {
3894 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
3895};
3896
3897enum atom_smu11_syspll3_0_clock_id {
3898 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
3899 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
3900 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
3901};
3902
3903enum atom_smu11_syspll3_1_clock_id {
3904 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
3905 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
3906 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
3907};
3908
3909enum atom_smu12_syspll_id {
3910 SMU12_SYSPLL0_ID = 0,
3911 SMU12_SYSPLL1_ID = 1,
3912 SMU12_SYSPLL2_ID = 2,
3913 SMU12_SYSPLL3_0_ID = 3,
3914 SMU12_SYSPLL3_1_ID = 4,
3915};
3916
3917enum atom_smu12_syspll0_clock_id {
3918 SMU12_SYSPLL0_SMNCLK_ID = 0, // SOCCLK
3919 SMU12_SYSPLL0_SOCCLK_ID = 1, // SOCCLK
3920 SMU12_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
3921 SMU12_SYSPLL0_MP1CLK_ID = 3, // MP1CLK
3922 SMU12_SYSPLL0_MP2CLK_ID = 4, // MP2CLK
3923 SMU12_SYSPLL0_VCLK_ID = 5, // VCLK
3924 SMU12_SYSPLL0_LCLK_ID = 6, // LCLK
3925 SMU12_SYSPLL0_DCLK_ID = 7, // DCLK
3926 SMU12_SYSPLL0_ACLK_ID = 8, // ACLK
3927 SMU12_SYSPLL0_ISPCLK_ID = 9, // ISPCLK
3928 SMU12_SYSPLL0_SHUBCLK_ID = 10, // SHUBCLK
3929};
3930
3931enum atom_smu12_syspll1_clock_id {
3932 SMU12_SYSPLL1_DISPCLK_ID = 0, // DISPCLK
3933 SMU12_SYSPLL1_DPPCLK_ID = 1, // DPPCLK
3934 SMU12_SYSPLL1_DPREFCLK_ID = 2, // DPREFCLK
3935 SMU12_SYSPLL1_DCFCLK_ID = 3, // DCFCLK
3936};
3937
3938enum atom_smu12_syspll2_clock_id {
3939 SMU12_SYSPLL2_Pre_GFXCLK_ID = 0, // Pre_GFXCLK
3940};
3941
3942enum atom_smu12_syspll3_0_clock_id {
3943 SMU12_SYSPLL3_0_FCLK_ID = 0, // FCLK
3944};
3945
3946enum atom_smu12_syspll3_1_clock_id {
3947 SMU12_SYSPLL3_1_UMCCLK_ID = 0, // UMCCLK
3948};
3949
3950struct atom_get_smu_clock_info_output_parameters_v3_1
3951{
3952 union {
3953 uint32_t smu_clock_freq_hz;
3954 uint32_t syspllvcofreq_10khz;
3955 uint32_t sysspllrefclk_10khz;
3956 }atom_smu_outputclkfreq;
3957};
3958
3959
3960
3961/*
3962 ***************************************************************************
3963 Structures used by dynamicmemorysettings
3964 ***************************************************************************
3965*/
3966
3967enum atom_dynamic_memory_setting_command
3968{
3969 COMPUTE_MEMORY_PLL_PARAM = 1,
3970 COMPUTE_ENGINE_PLL_PARAM = 2,
3971 ADJUST_MC_SETTING_PARAM = 3,
3972};
3973
3974/* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */
3975struct dynamic_mclk_settings_parameters_v2_1
3976{
3977 uint32_t mclk_10khz:24; //Input= target mclk
3978 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
3979 uint32_t reserved;
3980};
3981
3982/* when command = COMPUTE_ENGINE_PLL_PARAM */
3983struct dynamic_sclk_settings_parameters_v2_1
3984{
3985 uint32_t sclk_10khz:24; //Input= target mclk
3986 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
3987 uint32_t mclk_10khz;
3988 uint32_t reserved;
3989};
3990
3991union dynamic_memory_settings_parameters_v2_1
3992{
3993 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting;
3994 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting;
3995};
3996
3997
3998
3999/*
4000 ***************************************************************************
4001 Structures used by memorytraining
4002 ***************************************************************************
4003*/
4004
4005enum atom_umc6_0_ucode_function_call_enum_id
4006{
4007 UMC60_UCODE_FUNC_ID_REINIT = 0,
4008 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1,
4009 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2,
4010};
4011
4012
4013struct memory_training_parameters_v2_1
4014{
4015 uint8_t ucode_func_id;
4016 uint8_t ucode_reserved[3];
4017 uint32_t reserved[5];
4018};
4019
4020
4021/*
4022 ***************************************************************************
4023 Structures used by setpixelclock
4024 ***************************************************************************
4025*/
4026
4027struct set_pixel_clock_parameter_v1_7
4028{
4029 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
4030
4031 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
4032 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
4033 // indicate which graphic encoder will be used.
4034 uint8_t encoder_mode; // Encoder mode:
4035 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
4036 uint8_t crtc_id; // enum of atom_crtc_def
4037 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
4038 uint8_t reserved1[2];
4039 uint32_t reserved2;
4040};
4041
4042//ucMiscInfo
4043enum atom_set_pixel_clock_v1_7_misc_info
4044{
4045 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01,
4046 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02,
4047 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04,
4048 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08,
4049 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30,
4050 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00,
4051 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10,
4052 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20,
4053 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30,
4054 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40,
4055 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80,
4056};
4057
4058/* deep_color_ratio */
4059enum atom_set_pixel_clock_v1_7_deepcolor_ratio
4060{
4061 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
4062 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
4063 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
4064 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
4065};
4066
4067/*
4068 ***************************************************************************
4069 Structures used by setdceclock
4070 ***************************************************************************
4071*/
4072
4073// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above
4074struct set_dce_clock_parameters_v2_1
4075{
4076 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
4077 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
4078 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
4079 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
4080 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
4081};
4082
4083//ucDCEClkType
4084enum atom_set_dce_clock_clock_type
4085{
4086 DCE_CLOCK_TYPE_DISPCLK = 0,
4087 DCE_CLOCK_TYPE_DPREFCLK = 1,
4088 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock
4089};
4090
4091//ucDCEClkFlag when ucDCEClkType == DPREFCLK
4092enum atom_set_dce_clock_dprefclk_flag
4093{
4094 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03,
4095 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00,
4096 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01,
4097 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02,
4098 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03,
4099};
4100
4101//ucDCEClkFlag when ucDCEClkType == PIXCLK
4102enum atom_set_dce_clock_pixclk_flag
4103{
4104 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03,
4105 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
4106 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
4107 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
4108 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
4109 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04,
4110};
4111
4112struct set_dce_clock_ps_allocation_v2_1
4113{
4114 struct set_dce_clock_parameters_v2_1 param;
4115 uint32_t ulReserved[2];
4116};
4117
4118
4119/****************************************************************************/
4120// Structures used by BlankCRTC
4121/****************************************************************************/
4122struct blank_crtc_parameters
4123{
4124 uint8_t crtc_id; // enum atom_crtc_def
4125 uint8_t blanking; // enum atom_blank_crtc_command
4126 uint16_t reserved;
4127 uint32_t reserved1;
4128};
4129
4130enum atom_blank_crtc_command
4131{
4132 ATOM_BLANKING = 1,
4133 ATOM_BLANKING_OFF = 0,
4134};
4135
4136/****************************************************************************/
4137// Structures used by enablecrtc
4138/****************************************************************************/
4139struct enable_crtc_parameters
4140{
4141 uint8_t crtc_id; // enum atom_crtc_def
4142 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
4143 uint8_t padding[2];
4144};
4145
4146
4147/****************************************************************************/
4148// Structure used by EnableDispPowerGating
4149/****************************************************************************/
4150struct enable_disp_power_gating_parameters_v2_1
4151{
4152 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
4153 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
4154 uint8_t padding[2];
4155};
4156
4157struct enable_disp_power_gating_ps_allocation
4158{
4159 struct enable_disp_power_gating_parameters_v2_1 param;
4160 uint32_t ulReserved[4];
4161};
4162
4163/****************************************************************************/
4164// Structure used in setcrtc_usingdtdtiming
4165/****************************************************************************/
4166struct set_crtc_using_dtd_timing_parameters
4167{
4168 uint16_t h_size;
4169 uint16_t h_blanking_time;
4170 uint16_t v_size;
4171 uint16_t v_blanking_time;
4172 uint16_t h_syncoffset;
4173 uint16_t h_syncwidth;
4174 uint16_t v_syncoffset;
4175 uint16_t v_syncwidth;
4176 uint16_t modemiscinfo;
4177 uint8_t h_border;
4178 uint8_t v_border;
4179 uint8_t crtc_id; // enum atom_crtc_def
4180 uint8_t encoder_mode; // atom_encode_mode_def
4181 uint8_t padding[2];
4182};
4183
4184
4185/****************************************************************************/
4186// Structures used by processi2cchanneltransaction
4187/****************************************************************************/
4188struct process_i2c_channel_transaction_parameters
4189{
4190 uint8_t i2cspeed_khz;
4191 union {
4192 uint8_t regindex;
4193 uint8_t status; /* enum atom_process_i2c_flag */
4194 } regind_status;
4195 uint16_t i2c_data_out;
4196 uint8_t flag; /* enum atom_process_i2c_status */
4197 uint8_t trans_bytes;
4198 uint8_t slave_addr;
4199 uint8_t i2c_id;
4200};
4201
4202//ucFlag
4203enum atom_process_i2c_flag
4204{
4205 HW_I2C_WRITE = 1,
4206 HW_I2C_READ = 0,
4207 I2C_2BYTE_ADDR = 0x02,
4208 HW_I2C_SMBUS_BYTE_WR = 0x04,
4209};
4210
4211//status
4212enum atom_process_i2c_status
4213{
4214 HW_ASSISTED_I2C_STATUS_FAILURE =2,
4215 HW_ASSISTED_I2C_STATUS_SUCCESS =1,
4216};
4217
4218
4219/****************************************************************************/
4220// Structures used by processauxchanneltransaction
4221/****************************************************************************/
4222
4223struct process_aux_channel_transaction_parameters_v1_2
4224{
4225 uint16_t aux_request;
4226 uint16_t dataout;
4227 uint8_t channelid;
4228 union {
4229 uint8_t reply_status;
4230 uint8_t aux_delay;
4231 } aux_status_delay;
4232 uint8_t dataout_len;
4233 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
4234};
4235
4236
4237/****************************************************************************/
4238// Structures used by selectcrtc_source
4239/****************************************************************************/
4240
4241struct select_crtc_source_parameters_v2_3
4242{
4243 uint8_t crtc_id; // enum atom_crtc_def
4244 uint8_t encoder_id; // enum atom_dig_def
4245 uint8_t encode_mode; // enum atom_encode_mode_def
4246 uint8_t dst_bpc; // enum atom_panel_bit_per_color
4247};
4248
4249
4250/****************************************************************************/
4251// Structures used by digxencodercontrol
4252/****************************************************************************/
4253
4254// ucAction:
4255enum atom_dig_encoder_control_action
4256{
4257 ATOM_ENCODER_CMD_DISABLE_DIG = 0,
4258 ATOM_ENCODER_CMD_ENABLE_DIG = 1,
4259 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08,
4260 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09,
4261 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a,
4262 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13,
4263 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b,
4264 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c,
4265 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d,
4266 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10,
4267 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14,
4268 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F,
4269 ATOM_ENCODER_CMD_LINK_SETUP = 0x11,
4270 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12,
4271};
4272
4273//define ucPanelMode
4274enum atom_dig_encoder_control_panelmode
4275{
4276 DP_PANEL_MODE_DISABLE = 0x00,
4277 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01,
4278 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11,
4279};
4280
4281//ucDigId
4282enum atom_dig_encoder_control_v5_digid
4283{
4284 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00,
4285 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01,
4286 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02,
4287 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03,
4288 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04,
4289 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05,
4290 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06,
4291 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07,
4292};
4293
4294struct dig_encoder_stream_setup_parameters_v1_5
4295{
4296 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4297 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
4298 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
4299 uint8_t lanenum; // Lane number
4300 uint32_t pclk_10khz; // Pixel Clock in 10Khz
4301 uint8_t bitpercolor;
4302 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
4303 uint8_t reserved[2];
4304};
4305
4306struct dig_encoder_link_setup_parameters_v1_5
4307{
4308 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4309 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
4310 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
4311 uint8_t lanenum; // Lane number
4312 uint8_t symclk_10khz; // Symbol Clock in 10Khz
4313 uint8_t hpd_sel;
4314 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
4315 uint8_t reserved[2];
4316};
4317
4318struct dp_panel_mode_set_parameters_v1_5
4319{
4320 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4321 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
4322 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
4323 uint8_t reserved1;
4324 uint32_t reserved2[2];
4325};
4326
4327struct dig_encoder_generic_cmd_parameters_v1_5
4328{
4329 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4330 uint8_t action; // = rest of generic encoder command which does not carry any parameters
4331 uint8_t reserved1[2];
4332 uint32_t reserved2[2];
4333};
4334
4335union dig_encoder_control_parameters_v1_5
4336{
4337 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param;
4338 struct dig_encoder_stream_setup_parameters_v1_5 stream_param;
4339 struct dig_encoder_link_setup_parameters_v1_5 link_param;
4340 struct dp_panel_mode_set_parameters_v1_5 dppanel_param;
4341};
4342
4343/*
4344 ***************************************************************************
4345 Structures used by dig1transmittercontrol
4346 ***************************************************************************
4347*/
4348struct dig_transmitter_control_parameters_v1_6
4349{
4350 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
4351 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
4352 union {
4353 uint8_t digmode; // enum atom_encode_mode_def
4354 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
4355 } mode_laneset;
4356 uint8_t lanenum; // Lane number 1, 2, 4, 8
4357 uint32_t symclk_10khz; // Symbol Clock in 10Khz
4358 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
4359 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
4360 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
4361 uint8_t reserved;
4362 uint32_t reserved1;
4363};
4364
4365struct dig_transmitter_control_ps_allocation_v1_6
4366{
4367 struct dig_transmitter_control_parameters_v1_6 param;
4368 uint32_t reserved[4];
4369};
4370
4371//ucAction
4372enum atom_dig_transmitter_control_action
4373{
4374 ATOM_TRANSMITTER_ACTION_DISABLE = 0,
4375 ATOM_TRANSMITTER_ACTION_ENABLE = 1,
4376 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2,
4377 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3,
4378 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4,
4379 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5,
4380 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6,
4381 ATOM_TRANSMITTER_ACTION_INIT = 7,
4382 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8,
4383 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9,
4384 ATOM_TRANSMITTER_ACTION_SETUP = 10,
4385 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11,
4386 ATOM_TRANSMITTER_ACTION_POWER_ON = 12,
4387 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13,
4388};
4389
4390// digfe_sel
4391enum atom_dig_transmitter_control_digfe_sel
4392{
4393 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01,
4394 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02,
4395 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04,
4396 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08,
4397 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10,
4398 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20,
4399 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40,
4400};
4401
4402
4403//ucHPDSel
4404enum atom_dig_transmitter_control_hpd_sel
4405{
4406 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00,
4407 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01,
4408 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02,
4409 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03,
4410 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04,
4411 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05,
4412 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06,
4413};
4414
4415// ucDPLaneSet
4416enum atom_dig_transmitter_control_dplaneset
4417{
4418 DP_LANE_SET__0DB_0_4V = 0x00,
4419 DP_LANE_SET__0DB_0_6V = 0x01,
4420 DP_LANE_SET__0DB_0_8V = 0x02,
4421 DP_LANE_SET__0DB_1_2V = 0x03,
4422 DP_LANE_SET__3_5DB_0_4V = 0x08,
4423 DP_LANE_SET__3_5DB_0_6V = 0x09,
4424 DP_LANE_SET__3_5DB_0_8V = 0x0a,
4425 DP_LANE_SET__6DB_0_4V = 0x10,
4426 DP_LANE_SET__6DB_0_6V = 0x11,
4427 DP_LANE_SET__9_5DB_0_4V = 0x18,
4428};
4429
4430
4431
4432/****************************************************************************/
4433// Structures used by ExternalEncoderControl V2.4
4434/****************************************************************************/
4435
4436struct external_encoder_control_parameters_v2_4
4437{
4438 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
4439 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
4440 uint8_t action; //
4441 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
4442 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
4443 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
4444 uint8_t hpd_id;
4445};
4446
4447
4448// ucAction
4449enum external_encoder_control_action_def
4450{
4451 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00,
4452 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01,
4453 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07,
4454 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f,
4455 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10,
4456 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11,
4457 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12,
4458 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14,
4459};
4460
4461// ucConfig
4462enum external_encoder_control_v2_4_config_def
4463{
4464 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03,
4465 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00,
4466 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01,
4467 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02,
4468 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03,
4469 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70,
4470 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00,
4471 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10,
4472 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20,
4473};
4474
4475struct external_encoder_control_ps_allocation_v2_4
4476{
4477 struct external_encoder_control_parameters_v2_4 sExtEncoder;
4478 uint32_t reserved[2];
4479};
4480
4481
4482/*
4483 ***************************************************************************
4484 AMD ACPI Table
4485
4486 ***************************************************************************
4487*/
4488
4489struct amd_acpi_description_header{
4490 uint32_t signature;
4491 uint32_t tableLength; //Length
4492 uint8_t revision;
4493 uint8_t checksum;
4494 uint8_t oemId[6];
4495 uint8_t oemTableId[8]; //UINT64 OemTableId;
4496 uint32_t oemRevision;
4497 uint32_t creatorId;
4498 uint32_t creatorRevision;
4499};
4500
4501struct uefi_acpi_vfct{
4502 struct amd_acpi_description_header sheader;
4503 uint8_t tableUUID[16]; //0x24
4504 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
4505 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
4506 uint32_t reserved[4]; //0x3C
4507};
4508
4509struct vfct_image_header{
4510 uint32_t pcibus; //0x4C
4511 uint32_t pcidevice; //0x50
4512 uint32_t pcifunction; //0x54
4513 uint16_t vendorid; //0x58
4514 uint16_t deviceid; //0x5A
4515 uint16_t ssvid; //0x5C
4516 uint16_t ssid; //0x5E
4517 uint32_t revision; //0x60
4518 uint32_t imagelength; //0x64
4519};
4520
4521
4522struct gop_vbios_content {
4523 struct vfct_image_header vbiosheader;
4524 uint8_t vbioscontent[1];
4525};
4526
4527struct gop_lib1_content {
4528 struct vfct_image_header lib1header;
4529 uint8_t lib1content[1];
4530};
4531
4532
4533
4534/*
4535 ***************************************************************************
4536 Scratch Register definitions
4537 Each number below indicates which scratch regiser request, Active and
4538 Connect all share the same definitions as display_device_tag defines
4539 ***************************************************************************
4540*/
4541
4542enum scratch_register_def{
4543 ATOM_DEVICE_CONNECT_INFO_DEF = 0,
4544 ATOM_BL_BRI_LEVEL_INFO_DEF = 2,
4545 ATOM_ACTIVE_INFO_DEF = 3,
4546 ATOM_LCD_INFO_DEF = 4,
4547 ATOM_DEVICE_REQ_INFO_DEF = 5,
4548 ATOM_ACC_CHANGE_INFO_DEF = 6,
4549 ATOM_PRE_OS_MODE_INFO_DEF = 7,
4550 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers.
4551 ATOM_INTERNAL_TIMER_INFO_DEF = 10,
4552};
4553
4554enum scratch_device_connect_info_bit_def{
4555 ATOM_DISPLAY_LCD1_CONNECT =0x0002,
4556 ATOM_DISPLAY_DFP1_CONNECT =0x0008,
4557 ATOM_DISPLAY_DFP2_CONNECT =0x0080,
4558 ATOM_DISPLAY_DFP3_CONNECT =0x0200,
4559 ATOM_DISPLAY_DFP4_CONNECT =0x0400,
4560 ATOM_DISPLAY_DFP5_CONNECT =0x0800,
4561 ATOM_DISPLAY_DFP6_CONNECT =0x0040,
4562 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8,
4563 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff,
4564};
4565
4566enum scratch_bl_bri_level_info_bit_def{
4567 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8,
4568#ifndef _H2INC
4569 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00,
4570 ATOM_DEVICE_DPMS_STATE =0x00010000,
4571#endif
4572};
4573
4574enum scratch_active_info_bits_def{
4575 ATOM_DISPLAY_LCD1_ACTIVE =0x0002,
4576 ATOM_DISPLAY_DFP1_ACTIVE =0x0008,
4577 ATOM_DISPLAY_DFP2_ACTIVE =0x0080,
4578 ATOM_DISPLAY_DFP3_ACTIVE =0x0200,
4579 ATOM_DISPLAY_DFP4_ACTIVE =0x0400,
4580 ATOM_DISPLAY_DFP5_ACTIVE =0x0800,
4581 ATOM_DISPLAY_DFP6_ACTIVE =0x0040,
4582 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff,
4583};
4584
4585enum scratch_device_req_info_bits_def{
4586 ATOM_DISPLAY_LCD1_REQ =0x0002,
4587 ATOM_DISPLAY_DFP1_REQ =0x0008,
4588 ATOM_DISPLAY_DFP2_REQ =0x0080,
4589 ATOM_DISPLAY_DFP3_REQ =0x0200,
4590 ATOM_DISPLAY_DFP4_REQ =0x0400,
4591 ATOM_DISPLAY_DFP5_REQ =0x0800,
4592 ATOM_DISPLAY_DFP6_REQ =0x0040,
4593 ATOM_REQ_INFO_DEVICE_MASK =0x0fff,
4594};
4595
4596enum scratch_acc_change_info_bitshift_def{
4597 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4,
4598 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6,
4599};
4600
4601enum scratch_acc_change_info_bits_def{
4602 ATOM_ACC_CHANGE_ACC_MODE =0x00000010,
4603 ATOM_ACC_CHANGE_LID_STATUS =0x00000040,
4604};
4605
4606enum scratch_pre_os_mode_info_bits_def{
4607 ATOM_PRE_OS_MODE_MASK =0x00000003,
4608 ATOM_PRE_OS_MODE_VGA =0x00000000,
4609 ATOM_PRE_OS_MODE_VESA =0x00000001,
4610 ATOM_PRE_OS_MODE_GOP =0x00000002,
4611 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C,
4612 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
4613 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100,
4614 ATOM_ASIC_INIT_COMPLETE =0x00000200,
4615#ifndef _H2INC
4616 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000,
4617#endif
4618};
4619
4620
4621
4622/*
4623 ***************************************************************************
4624 ATOM firmware ID header file
4625 !! Please keep it at end of the atomfirmware.h !!
4626 ***************************************************************************
4627*/
4628#include "atomfirmwareid.h"
4629#pragma pack()
4630
4631#endif
4632