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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __KFD_TOPOLOGY_H__
24#define __KFD_TOPOLOGY_H__
25
26#include <linux/types.h>
27#include <linux/list.h>
28#include "kfd_crat.h"
29
30#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 32
31
32#define HSA_CAP_HOT_PLUGGABLE 0x00000001
33#define HSA_CAP_ATS_PRESENT 0x00000002
34#define HSA_CAP_SHARED_WITH_GRAPHICS 0x00000004
35#define HSA_CAP_QUEUE_SIZE_POW2 0x00000008
36#define HSA_CAP_QUEUE_SIZE_32BIT 0x00000010
37#define HSA_CAP_QUEUE_IDLE_EVENT 0x00000020
38#define HSA_CAP_VA_LIMIT 0x00000040
39#define HSA_CAP_WATCH_POINTS_SUPPORTED 0x00000080
40#define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK 0x00000f00
41#define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT 8
42#define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK 0x00003000
43#define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT 12
44
45#define HSA_CAP_DOORBELL_TYPE_PRE_1_0 0x0
46#define HSA_CAP_DOORBELL_TYPE_1_0 0x1
47#define HSA_CAP_DOORBELL_TYPE_2_0 0x2
48#define HSA_CAP_AQL_QUEUE_DOUBLE_MAP 0x00004000
49
50#define HSA_CAP_SRAM_EDCSUPPORTED 0x00080000
51#define HSA_CAP_MEM_EDCSUPPORTED 0x00100000
52#define HSA_CAP_RASEVENTNOTIFY 0x00200000
53#define HSA_CAP_ASIC_REVISION_MASK 0x03c00000
54#define HSA_CAP_ASIC_REVISION_SHIFT 22
55
56#define HSA_CAP_RESERVED 0xfc078000
57
58struct kfd_node_properties {
59 uint64_t hive_id;
60 uint64_t unique_id;
61 uint32_t cpu_cores_count;
62 uint32_t simd_count;
63 uint32_t mem_banks_count;
64 uint32_t caches_count;
65 uint32_t io_links_count;
66 uint32_t cpu_core_id_base;
67 uint32_t simd_id_base;
68 uint32_t capability;
69 uint32_t max_waves_per_simd;
70 uint32_t lds_size_in_kb;
71 uint32_t gds_size_in_kb;
72 uint32_t num_gws;
73 uint32_t wave_front_size;
74 uint32_t array_count;
75 uint32_t simd_arrays_per_engine;
76 uint32_t cu_per_simd_array;
77 uint32_t simd_per_cu;
78 uint32_t max_slots_scratch_cu;
79 uint32_t engine_id;
80 uint32_t vendor_id;
81 uint32_t device_id;
82 uint32_t location_id;
83 uint32_t domain;
84 uint32_t max_engine_clk_fcompute;
85 uint32_t max_engine_clk_ccompute;
86 int32_t drm_render_minor;
87 uint32_t num_sdma_engines;
88 uint32_t num_sdma_xgmi_engines;
89 uint32_t num_sdma_queues_per_engine;
90 uint32_t num_cp_queues;
91 char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
92};
93
94#define HSA_MEM_HEAP_TYPE_SYSTEM 0
95#define HSA_MEM_HEAP_TYPE_FB_PUBLIC 1
96#define HSA_MEM_HEAP_TYPE_FB_PRIVATE 2
97#define HSA_MEM_HEAP_TYPE_GPU_GDS 3
98#define HSA_MEM_HEAP_TYPE_GPU_LDS 4
99#define HSA_MEM_HEAP_TYPE_GPU_SCRATCH 5
100
101#define HSA_MEM_FLAGS_HOT_PLUGGABLE 0x00000001
102#define HSA_MEM_FLAGS_NON_VOLATILE 0x00000002
103#define HSA_MEM_FLAGS_RESERVED 0xfffffffc
104
105struct kfd_mem_properties {
106 struct list_head list;
107 uint32_t heap_type;
108 uint64_t size_in_bytes;
109 uint32_t flags;
110 uint32_t width;
111 uint32_t mem_clk_max;
112 struct kfd_dev *gpu;
113 struct kobject *kobj;
114 struct attribute attr;
115};
116
117#define HSA_CACHE_TYPE_DATA 0x00000001
118#define HSA_CACHE_TYPE_INSTRUCTION 0x00000002
119#define HSA_CACHE_TYPE_CPU 0x00000004
120#define HSA_CACHE_TYPE_HSACU 0x00000008
121#define HSA_CACHE_TYPE_RESERVED 0xfffffff0
122
123struct kfd_cache_properties {
124 struct list_head list;
125 uint32_t processor_id_low;
126 uint32_t cache_level;
127 uint32_t cache_size;
128 uint32_t cacheline_size;
129 uint32_t cachelines_per_tag;
130 uint32_t cache_assoc;
131 uint32_t cache_latency;
132 uint32_t cache_type;
133 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
134 struct kfd_dev *gpu;
135 struct kobject *kobj;
136 struct attribute attr;
137};
138
139struct kfd_iolink_properties {
140 struct list_head list;
141 uint32_t iolink_type;
142 uint32_t ver_maj;
143 uint32_t ver_min;
144 uint32_t node_from;
145 uint32_t node_to;
146 uint32_t weight;
147 uint32_t min_latency;
148 uint32_t max_latency;
149 uint32_t min_bandwidth;
150 uint32_t max_bandwidth;
151 uint32_t rec_transfer_size;
152 uint32_t flags;
153 struct kfd_dev *gpu;
154 struct kobject *kobj;
155 struct attribute attr;
156};
157
158struct kfd_perf_properties {
159 struct list_head list;
160 char block_name[16];
161 uint32_t max_concurrent;
162 struct attribute_group *attr_group;
163};
164
165struct kfd_topology_device {
166 struct list_head list;
167 uint32_t gpu_id;
168 uint32_t proximity_domain;
169 struct kfd_node_properties node_props;
170 struct list_head mem_props;
171 uint32_t cache_count;
172 struct list_head cache_props;
173 uint32_t io_link_count;
174 struct list_head io_link_props;
175 struct list_head perf_props;
176 struct kfd_dev *gpu;
177 struct kobject *kobj_node;
178 struct kobject *kobj_mem;
179 struct kobject *kobj_cache;
180 struct kobject *kobj_iolink;
181 struct kobject *kobj_perf;
182 struct attribute attr_gpuid;
183 struct attribute attr_name;
184 struct attribute attr_props;
185 uint8_t oem_id[CRAT_OEMID_LENGTH];
186 uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH];
187 uint32_t oem_revision;
188};
189
190struct kfd_system_properties {
191 uint32_t num_devices; /* Number of H-NUMA nodes */
192 uint32_t generation_count;
193 uint64_t platform_oem;
194 uint64_t platform_id;
195 uint64_t platform_rev;
196 struct kobject *kobj_topology;
197 struct kobject *kobj_nodes;
198 struct attribute attr_genid;
199 struct attribute attr_props;
200};
201
202struct kfd_topology_device *kfd_create_topology_device(
203 struct list_head *device_list);
204void kfd_release_topology_device_list(struct list_head *device_list);
205
206#endif /* __KFD_TOPOLOGY_H__ */
1/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2/*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef __KFD_TOPOLOGY_H__
25#define __KFD_TOPOLOGY_H__
26
27#include <linux/types.h>
28#include <linux/list.h>
29#include <linux/kfd_sysfs.h>
30#include "kfd_crat.h"
31
32#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 32
33
34#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9 6
35#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9_4_3 7
36#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 7
37#define HSA_DBG_WATCH_ADDR_MASK_HI_BIT \
38 (29 << HSA_DBG_WATCH_ADDR_MASK_HI_BIT_SHIFT)
39#define HSA_DBG_WATCH_ADDR_MASK_HI_BIT_GFX9_4_3 \
40 (30 << HSA_DBG_WATCH_ADDR_MASK_HI_BIT_SHIFT)
41
42struct kfd_node_properties {
43 uint64_t hive_id;
44 uint32_t cpu_cores_count;
45 uint32_t simd_count;
46 uint32_t mem_banks_count;
47 uint32_t caches_count;
48 uint32_t io_links_count;
49 uint32_t p2p_links_count;
50 uint32_t cpu_core_id_base;
51 uint32_t simd_id_base;
52 uint32_t capability;
53 uint64_t debug_prop;
54 uint32_t max_waves_per_simd;
55 uint32_t lds_size_in_kb;
56 uint32_t gds_size_in_kb;
57 uint32_t num_gws;
58 uint32_t wave_front_size;
59 uint32_t array_count;
60 uint32_t simd_arrays_per_engine;
61 uint32_t cu_per_simd_array;
62 uint32_t simd_per_cu;
63 uint32_t max_slots_scratch_cu;
64 uint32_t engine_id;
65 uint32_t gfx_target_version;
66 uint32_t vendor_id;
67 uint32_t device_id;
68 uint32_t location_id;
69 uint32_t domain;
70 uint32_t max_engine_clk_fcompute;
71 uint32_t max_engine_clk_ccompute;
72 int32_t drm_render_minor;
73 uint32_t num_sdma_engines;
74 uint32_t num_sdma_xgmi_engines;
75 uint32_t num_sdma_queues_per_engine;
76 uint32_t num_cp_queues;
77 uint32_t cwsr_size;
78 uint32_t ctl_stack_size;
79 uint32_t eop_buffer_size;
80 uint32_t debug_memory_size;
81 char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
82};
83
84struct kfd_mem_properties {
85 struct list_head list;
86 uint32_t heap_type;
87 uint64_t size_in_bytes;
88 uint32_t flags;
89 uint32_t width;
90 uint32_t mem_clk_max;
91 struct kfd_node *gpu;
92 struct kobject *kobj;
93 struct attribute attr;
94};
95
96#define CACHE_SIBLINGMAP_SIZE 128
97
98struct kfd_cache_properties {
99 struct list_head list;
100 uint32_t processor_id_low;
101 uint32_t cache_level;
102 uint32_t cache_size;
103 uint32_t cacheline_size;
104 uint32_t cachelines_per_tag;
105 uint32_t cache_assoc;
106 uint32_t cache_latency;
107 uint32_t cache_type;
108 uint8_t sibling_map[CACHE_SIBLINGMAP_SIZE];
109 struct kfd_node *gpu;
110 struct kobject *kobj;
111 struct attribute attr;
112 uint32_t sibling_map_size;
113};
114
115struct kfd_iolink_properties {
116 struct list_head list;
117 uint32_t iolink_type;
118 uint32_t ver_maj;
119 uint32_t ver_min;
120 uint32_t node_from;
121 uint32_t node_to;
122 uint32_t weight;
123 uint32_t min_latency;
124 uint32_t max_latency;
125 uint32_t min_bandwidth;
126 uint32_t max_bandwidth;
127 uint32_t rec_transfer_size;
128 uint32_t rec_sdma_eng_id_mask;
129 uint32_t flags;
130 struct kfd_node *gpu;
131 struct kobject *kobj;
132 struct attribute attr;
133};
134
135struct kfd_perf_properties {
136 struct list_head list;
137 char block_name[16];
138 uint32_t max_concurrent;
139 struct attribute_group *attr_group;
140};
141
142struct kfd_topology_device {
143 struct list_head list;
144 uint32_t gpu_id;
145 uint32_t proximity_domain;
146 struct kfd_node_properties node_props;
147 struct list_head mem_props;
148 struct list_head cache_props;
149 struct list_head io_link_props;
150 struct list_head p2p_link_props;
151 struct list_head perf_props;
152 struct kfd_node *gpu;
153 struct kobject *kobj_node;
154 struct kobject *kobj_mem;
155 struct kobject *kobj_cache;
156 struct kobject *kobj_iolink;
157 struct kobject *kobj_p2plink;
158 struct kobject *kobj_perf;
159 struct attribute attr_gpuid;
160 struct attribute attr_name;
161 struct attribute attr_props;
162 union {
163 uint8_t oem_id[CRAT_OEMID_LENGTH];
164 uint64_t oem_id64;
165 };
166 uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH];
167 uint32_t oem_revision;
168};
169
170struct kfd_system_properties {
171 uint32_t num_devices; /* Number of H-NUMA nodes */
172 uint32_t generation_count;
173 uint64_t platform_oem;
174 uint64_t platform_id;
175 uint64_t platform_rev;
176 struct kobject *kobj_topology;
177 struct kobject *kobj_nodes;
178 struct attribute attr_genid;
179 struct attribute attr_props;
180};
181
182struct kfd_topology_device *kfd_create_topology_device(
183 struct list_head *device_list);
184void kfd_release_topology_device_list(struct list_head *device_list);
185
186#endif /* __KFD_TOPOLOGY_H__ */