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1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <drm/drm_drv.h>
26
27#include "amdgpu.h"
28#include "amdgpu_vcn.h"
29#include "amdgpu_pm.h"
30#include "soc15.h"
31#include "soc15d.h"
32#include "soc15_hw_ip.h"
33#include "vcn_v2_0.h"
34#include "mmsch_v4_0_3.h"
35
36#include "vcn/vcn_4_0_3_offset.h"
37#include "vcn/vcn_4_0_3_sh_mask.h"
38#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
39
40#define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL
41#define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX
42#define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA
43#define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX
44
45#define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
46#define VCN1_VID_SOC_ADDRESS_3_0 0x48300
47
48static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
49 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
50 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),
53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG),
77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS),
78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)
82};
83
84#define NORMALIZE_VCN_REG_OFFSET(offset) \
85 (offset & 0x1FFFF)
86
87static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
88static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
89static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
90static int vcn_v4_0_3_set_powergating_state(void *handle,
91 enum amd_powergating_state state);
92static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,
93 int inst_idx, struct dpg_pause_state *new_state);
94static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring);
95static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
96static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev,
97 int inst_idx, bool indirect);
98
99static inline bool vcn_v4_0_3_normalizn_reqd(struct amdgpu_device *adev)
100{
101 return (amdgpu_sriov_vf(adev) ||
102 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)));
103}
104
105/**
106 * vcn_v4_0_3_early_init - set function pointers
107 *
108 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
109 *
110 * Set ring and irq function pointers
111 */
112static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block)
113{
114 struct amdgpu_device *adev = ip_block->adev;
115
116 /* re-use enc ring as unified ring */
117 adev->vcn.num_enc_rings = 1;
118
119 vcn_v4_0_3_set_unified_ring_funcs(adev);
120 vcn_v4_0_3_set_irq_funcs(adev);
121 vcn_v4_0_3_set_ras_funcs(adev);
122
123 return amdgpu_vcn_early_init(adev);
124}
125
126static int vcn_v4_0_3_fw_shared_init(struct amdgpu_device *adev, int inst_idx)
127{
128 struct amdgpu_vcn4_fw_shared *fw_shared;
129
130 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
131 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
132 fw_shared->sq.is_enabled = 1;
133
134 if (amdgpu_vcnfw_log)
135 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]);
136
137 return 0;
138}
139
140/**
141 * vcn_v4_0_3_sw_init - sw init for VCN block
142 *
143 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
144 *
145 * Load firmware and sw initialization
146 */
147static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block)
148{
149 struct amdgpu_device *adev = ip_block->adev;
150 struct amdgpu_ring *ring;
151 int i, r, vcn_inst;
152 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
153 uint32_t *ptr;
154
155 r = amdgpu_vcn_sw_init(adev);
156 if (r)
157 return r;
158
159 amdgpu_vcn_setup_ucode(adev);
160
161 r = amdgpu_vcn_resume(adev);
162 if (r)
163 return r;
164
165 /* VCN DEC TRAP */
166 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
167 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq);
168 if (r)
169 return r;
170
171 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
172 vcn_inst = GET_INST(VCN, i);
173
174 ring = &adev->vcn.inst[i].ring_enc[0];
175 ring->use_doorbell = true;
176
177 if (!amdgpu_sriov_vf(adev))
178 ring->doorbell_index =
179 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
180 9 * vcn_inst;
181 else
182 ring->doorbell_index =
183 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
184 32 * vcn_inst;
185
186 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id);
187 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id);
188 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
189 AMDGPU_RING_PRIO_DEFAULT,
190 &adev->vcn.inst[i].sched_score);
191 if (r)
192 return r;
193
194 vcn_v4_0_3_fw_shared_init(adev, i);
195 }
196
197 /* TODO: Add queue reset mask when FW fully supports it */
198 adev->vcn.supported_reset =
199 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
200
201 if (amdgpu_sriov_vf(adev)) {
202 r = amdgpu_virt_alloc_mm_table(adev);
203 if (r)
204 return r;
205 }
206
207 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
208 adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;
209
210 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) {
211 r = amdgpu_vcn_ras_sw_init(adev);
212 if (r) {
213 dev_err(adev->dev, "Failed to initialize vcn ras block!\n");
214 return r;
215 }
216 }
217
218 /* Allocate memory for VCN IP Dump buffer */
219 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
220 if (!ptr) {
221 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
222 adev->vcn.ip_dump = NULL;
223 } else {
224 adev->vcn.ip_dump = ptr;
225 }
226
227 r = amdgpu_vcn_sysfs_reset_mask_init(adev);
228 if (r)
229 return r;
230
231 return 0;
232}
233
234/**
235 * vcn_v4_0_3_sw_fini - sw fini for VCN block
236 *
237 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
238 *
239 * VCN suspend and free up sw allocation
240 */
241static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block)
242{
243 struct amdgpu_device *adev = ip_block->adev;
244 int i, r, idx;
245
246 if (drm_dev_enter(&adev->ddev, &idx)) {
247 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
248 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
249
250 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
251 fw_shared->present_flag_0 = 0;
252 fw_shared->sq.is_enabled = cpu_to_le32(false);
253 }
254 drm_dev_exit(idx);
255 }
256
257 if (amdgpu_sriov_vf(adev))
258 amdgpu_virt_free_mm_table(adev);
259
260 r = amdgpu_vcn_suspend(adev);
261 if (r)
262 return r;
263
264 amdgpu_vcn_sysfs_reset_mask_fini(adev);
265 r = amdgpu_vcn_sw_fini(adev);
266
267 kfree(adev->vcn.ip_dump);
268
269 return r;
270}
271
272/**
273 * vcn_v4_0_3_hw_init - start and test VCN block
274 *
275 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
276 *
277 * Initialize the hardware, boot up the VCPU and do some testing
278 */
279static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block)
280{
281 struct amdgpu_device *adev = ip_block->adev;
282 struct amdgpu_ring *ring;
283 int i, r, vcn_inst;
284
285 if (amdgpu_sriov_vf(adev)) {
286 r = vcn_v4_0_3_start_sriov(adev);
287 if (r)
288 return r;
289
290 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
291 ring = &adev->vcn.inst[i].ring_enc[0];
292 ring->wptr = 0;
293 ring->wptr_old = 0;
294 vcn_v4_0_3_unified_ring_set_wptr(ring);
295 ring->sched.ready = true;
296 }
297 } else {
298 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
299 struct amdgpu_vcn4_fw_shared *fw_shared;
300
301 vcn_inst = GET_INST(VCN, i);
302 ring = &adev->vcn.inst[i].ring_enc[0];
303
304 if (ring->use_doorbell) {
305 adev->nbio.funcs->vcn_doorbell_range(
306 adev, ring->use_doorbell,
307 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
308 9 * vcn_inst,
309 adev->vcn.inst[i].aid_id);
310
311 WREG32_SOC15(
312 VCN, GET_INST(VCN, ring->me),
313 regVCN_RB1_DB_CTRL,
314 ring->doorbell_index
315 << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
316 VCN_RB1_DB_CTRL__EN_MASK);
317
318 /* Read DB_CTRL to flush the write DB_CTRL command. */
319 RREG32_SOC15(
320 VCN, GET_INST(VCN, ring->me),
321 regVCN_RB1_DB_CTRL);
322 }
323
324 /* Re-init fw_shared when RAS fatal error occurred */
325 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
326 if (!fw_shared->sq.is_enabled)
327 vcn_v4_0_3_fw_shared_init(adev, i);
328
329 r = amdgpu_ring_test_helper(ring);
330 if (r)
331 return r;
332 }
333 }
334
335 return r;
336}
337
338/**
339 * vcn_v4_0_3_hw_fini - stop the hardware block
340 *
341 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
342 *
343 * Stop the VCN block, mark ring as not ready any more
344 */
345static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block)
346{
347 struct amdgpu_device *adev = ip_block->adev;
348
349 cancel_delayed_work_sync(&adev->vcn.idle_work);
350
351 if (adev->vcn.cur_state != AMD_PG_STATE_GATE)
352 vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
353
354 return 0;
355}
356
357/**
358 * vcn_v4_0_3_suspend - suspend VCN block
359 *
360 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
361 *
362 * HW fini and suspend VCN block
363 */
364static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block)
365{
366 int r;
367
368 r = vcn_v4_0_3_hw_fini(ip_block);
369 if (r)
370 return r;
371
372 r = amdgpu_vcn_suspend(ip_block->adev);
373
374 return r;
375}
376
377/**
378 * vcn_v4_0_3_resume - resume VCN block
379 *
380 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
381 *
382 * Resume firmware and hw init VCN block
383 */
384static int vcn_v4_0_3_resume(struct amdgpu_ip_block *ip_block)
385{
386 int r;
387
388 r = amdgpu_vcn_resume(ip_block->adev);
389 if (r)
390 return r;
391
392 r = vcn_v4_0_3_hw_init(ip_block);
393
394 return r;
395}
396
397/**
398 * vcn_v4_0_3_mc_resume - memory controller programming
399 *
400 * @adev: amdgpu_device pointer
401 * @inst_idx: instance number
402 *
403 * Let the VCN memory controller know it's offsets
404 */
405static void vcn_v4_0_3_mc_resume(struct amdgpu_device *adev, int inst_idx)
406{
407 uint32_t offset, size, vcn_inst;
408 const struct common_firmware_header *hdr;
409
410 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
411 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
412
413 vcn_inst = GET_INST(VCN, inst_idx);
414 /* cache window 0: fw */
415 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
416 WREG32_SOC15(
417 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
418 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx]
419 .tmr_mc_addr_lo));
420 WREG32_SOC15(
421 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
422 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx]
423 .tmr_mc_addr_hi));
424 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0);
425 offset = 0;
426 } else {
427 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
428 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr));
429 WREG32_SOC15(VCN, vcn_inst,
430 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
431 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr));
432 offset = size;
433 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0,
434 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
435 }
436 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size);
437
438 /* cache window 1: stack */
439 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
440 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset));
441 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
442 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset));
443 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0);
444 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1,
445 AMDGPU_VCN_STACK_SIZE);
446
447 /* cache window 2: context */
448 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
449 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
450 AMDGPU_VCN_STACK_SIZE));
451 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
452 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
453 AMDGPU_VCN_STACK_SIZE));
454 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0);
455 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2,
456 AMDGPU_VCN_CONTEXT_SIZE);
457
458 /* non-cache window */
459 WREG32_SOC15(
460 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
461 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));
462 WREG32_SOC15(
463 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
464 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));
465 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
466 WREG32_SOC15(
467 VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0,
468 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
469}
470
471/**
472 * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode
473 *
474 * @adev: amdgpu_device pointer
475 * @inst_idx: instance number index
476 * @indirect: indirectly write sram
477 *
478 * Let the VCN memory controller know it's offsets with dpg mode
479 */
480static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
481{
482 uint32_t offset, size;
483 const struct common_firmware_header *hdr;
484
485 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
486 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
487
488 /* cache window 0: fw */
489 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
490 if (!indirect) {
491 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
492 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
493 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
494 inst_idx].tmr_mc_addr_lo), 0, indirect);
495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
496 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
497 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
498 inst_idx].tmr_mc_addr_hi), 0, indirect);
499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
500 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
501 } else {
502 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
503 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
504 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
505 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
507 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
508 }
509 offset = 0;
510 } else {
511 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
512 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
513 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
514 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
515 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
516 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
517 offset = size;
518 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
519 VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
520 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
521 }
522
523 if (!indirect)
524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
525 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
526 else
527 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
528 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
529
530 /* cache window 1: stack */
531 if (!indirect) {
532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
533 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
534 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
535 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
536 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
537 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
539 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
540 } else {
541 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
542 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
543 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
544 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
545 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
546 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
547 }
548 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
549 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
550
551 /* cache window 2: context */
552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
553 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
554 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
555 AMDGPU_VCN_STACK_SIZE), 0, indirect);
556 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
557 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
558 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
559 AMDGPU_VCN_STACK_SIZE), 0, indirect);
560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
561 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
562 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
563 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
564
565 /* non-cache window */
566 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
567 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
568 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
569 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
570 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
571 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
572 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
573 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
574 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
575 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0),
576 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
577
578 /* VCN global tiling registers */
579 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
580 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
581 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
582 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
583}
584
585/**
586 * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating
587 *
588 * @adev: amdgpu_device pointer
589 * @inst_idx: instance number
590 *
591 * Disable clock gating for VCN block
592 */
593static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx)
594{
595 uint32_t data;
596 int vcn_inst;
597
598 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
599 return;
600
601 vcn_inst = GET_INST(VCN, inst_idx);
602
603 /* VCN disable CGC */
604 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);
605 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
606 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
607 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
608 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data);
609
610 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE);
611 data &= ~(UVD_CGC_GATE__SYS_MASK
612 | UVD_CGC_GATE__MPEG2_MASK
613 | UVD_CGC_GATE__REGS_MASK
614 | UVD_CGC_GATE__RBC_MASK
615 | UVD_CGC_GATE__LMI_MC_MASK
616 | UVD_CGC_GATE__LMI_UMC_MASK
617 | UVD_CGC_GATE__MPC_MASK
618 | UVD_CGC_GATE__LBSI_MASK
619 | UVD_CGC_GATE__LRBBM_MASK
620 | UVD_CGC_GATE__WCB_MASK
621 | UVD_CGC_GATE__VCPU_MASK
622 | UVD_CGC_GATE__MMSCH_MASK);
623
624 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data);
625 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF);
626
627 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);
628 data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK
629 | UVD_CGC_CTRL__MPEG2_MODE_MASK
630 | UVD_CGC_CTRL__REGS_MODE_MASK
631 | UVD_CGC_CTRL__RBC_MODE_MASK
632 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
633 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
634 | UVD_CGC_CTRL__MPC_MODE_MASK
635 | UVD_CGC_CTRL__LBSI_MODE_MASK
636 | UVD_CGC_CTRL__LRBBM_MODE_MASK
637 | UVD_CGC_CTRL__WCB_MODE_MASK
638 | UVD_CGC_CTRL__VCPU_MODE_MASK
639 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
640 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data);
641
642 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE);
643 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
644 | UVD_SUVD_CGC_GATE__SIT_MASK
645 | UVD_SUVD_CGC_GATE__SMP_MASK
646 | UVD_SUVD_CGC_GATE__SCM_MASK
647 | UVD_SUVD_CGC_GATE__SDB_MASK
648 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
649 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
650 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
651 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
652 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
653 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
654 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
655 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
656 | UVD_SUVD_CGC_GATE__ENT_MASK
657 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
658 | UVD_SUVD_CGC_GATE__SITE_MASK
659 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
660 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
661 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
662 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
663 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
664 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE, data);
665
666 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL);
667 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
668 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
669 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
670 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
671 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
672 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
673 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
674 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
675 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data);
676}
677
678/**
679 * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
680 *
681 * @adev: amdgpu_device pointer
682 * @sram_sel: sram select
683 * @inst_idx: instance number index
684 * @indirect: indirectly write sram
685 *
686 * Disable clock gating for VCN block with dpg mode
687 */
688static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,
689 int inst_idx, uint8_t indirect)
690{
691 uint32_t reg_data = 0;
692
693 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
694 return;
695
696 /* enable sw clock gating control */
697 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
698 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
699 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
700 reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK |
701 UVD_CGC_CTRL__MPEG2_MODE_MASK |
702 UVD_CGC_CTRL__REGS_MODE_MASK |
703 UVD_CGC_CTRL__RBC_MODE_MASK |
704 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
705 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
706 UVD_CGC_CTRL__IDCT_MODE_MASK |
707 UVD_CGC_CTRL__MPRD_MODE_MASK |
708 UVD_CGC_CTRL__MPC_MODE_MASK |
709 UVD_CGC_CTRL__LBSI_MODE_MASK |
710 UVD_CGC_CTRL__LRBBM_MODE_MASK |
711 UVD_CGC_CTRL__WCB_MODE_MASK |
712 UVD_CGC_CTRL__VCPU_MODE_MASK);
713 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
714 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
715
716 /* turn off clock gating */
717 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
718 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect);
719
720 /* turn on SUVD clock gating */
721 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
722 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
723
724 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
725 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
726 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
727}
728
729/**
730 * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating
731 *
732 * @adev: amdgpu_device pointer
733 * @inst_idx: instance number
734 *
735 * Enable clock gating for VCN block
736 */
737static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx)
738{
739 uint32_t data;
740 int vcn_inst;
741
742 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
743 return;
744
745 vcn_inst = GET_INST(VCN, inst_idx);
746
747 /* enable VCN CGC */
748 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);
749 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
750 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
751 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
752 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data);
753
754 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);
755 data |= (UVD_CGC_CTRL__SYS_MODE_MASK
756 | UVD_CGC_CTRL__MPEG2_MODE_MASK
757 | UVD_CGC_CTRL__REGS_MODE_MASK
758 | UVD_CGC_CTRL__RBC_MODE_MASK
759 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
760 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
761 | UVD_CGC_CTRL__MPC_MODE_MASK
762 | UVD_CGC_CTRL__LBSI_MODE_MASK
763 | UVD_CGC_CTRL__LRBBM_MODE_MASK
764 | UVD_CGC_CTRL__WCB_MODE_MASK
765 | UVD_CGC_CTRL__VCPU_MODE_MASK);
766 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data);
767
768 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL);
769 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
770 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
771 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
772 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
773 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
774 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
775 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
776 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
777 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data);
778}
779
780/**
781 * vcn_v4_0_3_start_dpg_mode - VCN start with dpg mode
782 *
783 * @adev: amdgpu_device pointer
784 * @inst_idx: instance number index
785 * @indirect: indirectly write sram
786 *
787 * Start VCN block with dpg mode
788 */
789static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
790{
791 volatile struct amdgpu_vcn4_fw_shared *fw_shared =
792 adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
793 struct amdgpu_ring *ring;
794 int vcn_inst;
795 uint32_t tmp;
796
797 vcn_inst = GET_INST(VCN, inst_idx);
798 /* disable register anti-hang mechanism */
799 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1,
800 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
801 /* enable dynamic power gating mode */
802 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS);
803 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
804 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
805 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp);
806
807 if (indirect) {
808 DRM_DEV_DEBUG(adev->dev, "VCN %d start: on AID %d",
809 inst_idx, adev->vcn.inst[inst_idx].aid_id);
810 adev->vcn.inst[inst_idx].dpg_sram_curr_addr =
811 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
812 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */
813 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF,
814 adev->vcn.inst[inst_idx].aid_id, 0, true);
815 }
816
817 /* enable clock gating */
818 vcn_v4_0_3_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
819
820 /* enable VCPU clock */
821 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
822 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
823 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
824
825 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
826 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
827
828 /* disable master interrupt */
829 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
830 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect);
831
832 /* setup regUVD_LMI_CTRL */
833 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
834 UVD_LMI_CTRL__REQ_MODE_MASK |
835 UVD_LMI_CTRL__CRC_RESET_MASK |
836 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
837 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
838 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
839 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
840 0x00100000L);
841 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
842 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect);
843
844 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
845 VCN, 0, regUVD_MPC_CNTL),
846 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
847
848 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
849 VCN, 0, regUVD_MPC_SET_MUXA0),
850 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
851 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
852 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
853 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
854
855 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
856 VCN, 0, regUVD_MPC_SET_MUXB0),
857 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
858 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
859 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
860 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
861
862 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
863 VCN, 0, regUVD_MPC_SET_MUX),
864 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
865 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
866 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
867
868 vcn_v4_0_3_mc_resume_dpg_mode(adev, inst_idx, indirect);
869
870 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
871 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
872 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
873 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
874
875 /* enable LMI MC and UMC channels */
876 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
877 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
878 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect);
879
880 vcn_v4_0_3_enable_ras(adev, inst_idx, indirect);
881
882 /* enable master interrupt */
883 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
884 VCN, 0, regUVD_MASTINT_EN),
885 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
886
887 if (indirect)
888 amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);
889
890 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
891
892 /* program the RB_BASE for ring buffer */
893 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,
894 lower_32_bits(ring->gpu_addr));
895 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,
896 upper_32_bits(ring->gpu_addr));
897
898 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE,
899 ring->ring_size / sizeof(uint32_t));
900
901 /* resetting ring, fw should not check RB ring */
902 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
903 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
904 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
905 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
906
907 /* Initialize the ring buffer's read and write pointers */
908 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
909 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
910 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
911
912 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
913 tmp |= VCN_RB_ENABLE__RB_EN_MASK;
914 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
915 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
916
917 /*resetting done, fw can check RB ring */
918 fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
919
920 return 0;
921}
922
923static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev)
924{
925 int i, vcn_inst;
926 struct amdgpu_ring *ring_enc;
927 uint64_t cache_addr;
928 uint64_t rb_enc_addr;
929 uint64_t ctx_addr;
930 uint32_t param, resp, expected;
931 uint32_t offset, cache_size;
932 uint32_t tmp, timeout;
933
934 struct amdgpu_mm_table *table = &adev->virt.mm_table;
935 uint32_t *table_loc;
936 uint32_t table_size;
937 uint32_t size, size_dw;
938 uint32_t init_status;
939 uint32_t enabled_vcn;
940
941 struct mmsch_v4_0_cmd_direct_write
942 direct_wt = { {0} };
943 struct mmsch_v4_0_cmd_direct_read_modify_write
944 direct_rd_mod_wt = { {0} };
945 struct mmsch_v4_0_cmd_end end = { {0} };
946 struct mmsch_v4_0_3_init_header header;
947
948 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
949 volatile struct amdgpu_fw_shared_rb_setup *rb_setup;
950
951 direct_wt.cmd_header.command_type =
952 MMSCH_COMMAND__DIRECT_REG_WRITE;
953 direct_rd_mod_wt.cmd_header.command_type =
954 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
955 end.cmd_header.command_type = MMSCH_COMMAND__END;
956
957 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
958 vcn_inst = GET_INST(VCN, i);
959
960 vcn_v4_0_3_fw_shared_init(adev, vcn_inst);
961
962 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header));
963 header.version = MMSCH_VERSION;
964 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2;
965
966 table_loc = (uint32_t *)table->cpu_addr;
967 table_loc += header.total_size;
968
969 table_size = 0;
970
971 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS),
972 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
973
974 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
975
976 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
977 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
978 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
979 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
980
981 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
982 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
983 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
984
985 offset = 0;
986 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
987 regUVD_VCPU_CACHE_OFFSET0), 0);
988 } else {
989 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
990 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
991 lower_32_bits(adev->vcn.inst[i].gpu_addr));
992 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
993 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
994 upper_32_bits(adev->vcn.inst[i].gpu_addr));
995 offset = cache_size;
996 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
997 regUVD_VCPU_CACHE_OFFSET0),
998 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
999 }
1000
1001 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1002 regUVD_VCPU_CACHE_SIZE0),
1003 cache_size);
1004
1005 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset;
1006 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1007 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr));
1008 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1009 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr));
1010 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1011 regUVD_VCPU_CACHE_OFFSET1), 0);
1012 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1013 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE);
1014
1015 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset +
1016 AMDGPU_VCN_STACK_SIZE;
1017
1018 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1019 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr));
1020
1021 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1022 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr));
1023
1024 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1025 regUVD_VCPU_CACHE_OFFSET2), 0);
1026
1027 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1028 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE);
1029
1030 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr;
1031 rb_setup = &fw_shared->rb_setup;
1032
1033 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0];
1034 ring_enc->wptr = 0;
1035 rb_enc_addr = ring_enc->gpu_addr;
1036
1037 rb_setup->is_rb_enabled_flags |= RB_ENABLED;
1038 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
1039 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);
1040 rb_setup->rb_size = ring_enc->ring_size / 4;
1041 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
1042
1043 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1044 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
1045 lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
1046 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1047 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
1048 upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
1049 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1050 regUVD_VCPU_NONCACHE_SIZE0),
1051 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
1052 MMSCH_V4_0_INSERT_END();
1053
1054 header.vcn0.init_status = 0;
1055 header.vcn0.table_offset = header.total_size;
1056 header.vcn0.table_size = table_size;
1057 header.total_size += table_size;
1058
1059 /* Send init table to mmsch */
1060 size = sizeof(struct mmsch_v4_0_3_init_header);
1061 table_loc = (uint32_t *)table->cpu_addr;
1062 memcpy((void *)table_loc, &header, size);
1063
1064 ctx_addr = table->gpu_addr;
1065 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1066 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1067
1068 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID);
1069 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1070 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1071 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp);
1072
1073 size = header.total_size;
1074 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size);
1075
1076 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0);
1077
1078 param = 0x00000001;
1079 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param);
1080 tmp = 0;
1081 timeout = 1000;
1082 resp = 0;
1083 expected = MMSCH_VF_MAILBOX_RESP__OK;
1084 while (resp != expected) {
1085 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP);
1086 if (resp != 0)
1087 break;
1088
1089 udelay(10);
1090 tmp = tmp + 10;
1091 if (tmp >= timeout) {
1092 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1093 " waiting for regMMSCH_VF_MAILBOX_RESP "\
1094 "(expected=0x%08x, readback=0x%08x)\n",
1095 tmp, expected, resp);
1096 return -EBUSY;
1097 }
1098 }
1099
1100 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0;
1101 init_status = ((struct mmsch_v4_0_3_init_header *)(table_loc))->vcn0.init_status;
1102 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
1103 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) {
1104 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\
1105 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status);
1106 }
1107 }
1108
1109 return 0;
1110}
1111
1112/**
1113 * vcn_v4_0_3_start - VCN start
1114 *
1115 * @adev: amdgpu_device pointer
1116 *
1117 * Start VCN block
1118 */
1119static int vcn_v4_0_3_start(struct amdgpu_device *adev)
1120{
1121 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1122 struct amdgpu_ring *ring;
1123 int i, j, k, r, vcn_inst;
1124 uint32_t tmp;
1125
1126 if (adev->pm.dpm_enabled)
1127 amdgpu_dpm_enable_uvd(adev, true);
1128
1129 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1130 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1131 r = vcn_v4_0_3_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1132 continue;
1133 }
1134
1135 vcn_inst = GET_INST(VCN, i);
1136 /* set VCN status busy */
1137 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |
1138 UVD_STATUS__UVD_BUSY;
1139 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);
1140
1141 /*SW clock gating */
1142 vcn_v4_0_3_disable_clock_gating(adev, i);
1143
1144 /* enable VCPU clock */
1145 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
1146 UVD_VCPU_CNTL__CLK_EN_MASK,
1147 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1148
1149 /* disable master interrupt */
1150 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,
1151 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1152
1153 /* enable LMI MC and UMC channels */
1154 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,
1155 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1156
1157 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
1158 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1159 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1160 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
1161
1162 /* setup regUVD_LMI_CTRL */
1163 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);
1164 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL,
1165 tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1166 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1167 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1168 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1169
1170 /* setup regUVD_MPC_CNTL */
1171 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL);
1172 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1173 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1174 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp);
1175
1176 /* setup UVD_MPC_SET_MUXA0 */
1177 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0,
1178 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1179 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1180 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1181 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1182
1183 /* setup UVD_MPC_SET_MUXB0 */
1184 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0,
1185 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1186 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1187 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1188 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1189
1190 /* setup UVD_MPC_SET_MUX */
1191 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX,
1192 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1193 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1194 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1195
1196 vcn_v4_0_3_mc_resume(adev, i);
1197
1198 /* VCN global tiling registers */
1199 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG,
1200 adev->gfx.config.gb_addr_config);
1201 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG,
1202 adev->gfx.config.gb_addr_config);
1203
1204 /* unblock VCPU register access */
1205 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,
1206 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1207
1208 /* release VCPU reset to boot */
1209 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
1210 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1211
1212 for (j = 0; j < 10; ++j) {
1213 uint32_t status;
1214
1215 for (k = 0; k < 100; ++k) {
1216 status = RREG32_SOC15(VCN, vcn_inst,
1217 regUVD_STATUS);
1218 if (status & 2)
1219 break;
1220 mdelay(10);
1221 }
1222 r = 0;
1223 if (status & 2)
1224 break;
1225
1226 DRM_DEV_ERROR(adev->dev,
1227 "VCN decode not responding, trying to reset the VCPU!!!\n");
1228 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
1229 regUVD_VCPU_CNTL),
1230 UVD_VCPU_CNTL__BLK_RST_MASK,
1231 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1232 mdelay(10);
1233 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
1234 regUVD_VCPU_CNTL),
1235 0, ~UVD_VCPU_CNTL__BLK_RST_MASK);
1236
1237 mdelay(10);
1238 r = -1;
1239 }
1240
1241 if (r) {
1242 DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n");
1243 return r;
1244 }
1245
1246 /* enable master interrupt */
1247 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),
1248 UVD_MASTINT_EN__VCPU_EN_MASK,
1249 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1250
1251 /* clear the busy bit of VCN_STATUS */
1252 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,
1253 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1254
1255 ring = &adev->vcn.inst[i].ring_enc[0];
1256 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1257
1258 /* program the RB_BASE for ring buffer */
1259 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,
1260 lower_32_bits(ring->gpu_addr));
1261 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,
1262 upper_32_bits(ring->gpu_addr));
1263
1264 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE,
1265 ring->ring_size / sizeof(uint32_t));
1266
1267 /* resetting ring, fw should not check RB ring */
1268 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
1269 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
1270 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
1271
1272 /* Initialize the ring buffer's read and write pointers */
1273 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
1274 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
1275
1276 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
1277 tmp |= VCN_RB_ENABLE__RB_EN_MASK;
1278 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
1279
1280 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
1281 fw_shared->sq.queue_mode &=
1282 cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF));
1283
1284 }
1285 return 0;
1286}
1287
1288/**
1289 * vcn_v4_0_3_stop_dpg_mode - VCN stop with dpg mode
1290 *
1291 * @adev: amdgpu_device pointer
1292 * @inst_idx: instance number index
1293 *
1294 * Stop VCN block with dpg mode
1295 */
1296static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1297{
1298 uint32_t tmp;
1299 int vcn_inst;
1300
1301 vcn_inst = GET_INST(VCN, inst_idx);
1302
1303 /* Wait for power status to be 1 */
1304 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1,
1305 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1306
1307 /* wait for read ptr to be equal to write ptr */
1308 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
1309 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1310
1311 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1,
1312 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1313
1314 /* disable dynamic power gating mode */
1315 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0,
1316 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1317 return 0;
1318}
1319
1320/**
1321 * vcn_v4_0_3_stop - VCN stop
1322 *
1323 * @adev: amdgpu_device pointer
1324 *
1325 * Stop VCN block
1326 */
1327static int vcn_v4_0_3_stop(struct amdgpu_device *adev)
1328{
1329 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1330 int i, r = 0, vcn_inst;
1331 uint32_t tmp;
1332
1333 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1334 vcn_inst = GET_INST(VCN, i);
1335
1336 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1337 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
1338
1339 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1340 vcn_v4_0_3_stop_dpg_mode(adev, i);
1341 continue;
1342 }
1343
1344 /* wait for vcn idle */
1345 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS,
1346 UVD_STATUS__IDLE, 0x7);
1347 if (r)
1348 goto Done;
1349
1350 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1351 UVD_LMI_STATUS__READ_CLEAN_MASK |
1352 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1353 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1354 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
1355 tmp);
1356 if (r)
1357 goto Done;
1358
1359 /* stall UMC channel */
1360 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);
1361 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1362 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);
1363 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1364 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1365 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
1366 tmp);
1367 if (r)
1368 goto Done;
1369
1370 /* Unblock VCPU Register access */
1371 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),
1372 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1373 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1374
1375 /* release VCPU reset to boot */
1376 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
1377 UVD_VCPU_CNTL__BLK_RST_MASK,
1378 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1379
1380 /* disable VCPU clock */
1381 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
1382 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1383
1384 /* reset LMI UMC/LMI/VCPU */
1385 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
1386 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1387 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
1388
1389 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
1390 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1391 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
1392
1393 /* clear VCN status */
1394 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);
1395
1396 /* apply HW clock gating */
1397 vcn_v4_0_3_enable_clock_gating(adev, i);
1398 }
1399Done:
1400 if (adev->pm.dpm_enabled)
1401 amdgpu_dpm_enable_uvd(adev, false);
1402
1403 return 0;
1404}
1405
1406/**
1407 * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode
1408 *
1409 * @adev: amdgpu_device pointer
1410 * @inst_idx: instance number index
1411 * @new_state: pause state
1412 *
1413 * Pause dpg mode for VCN block
1414 */
1415static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
1416 struct dpg_pause_state *new_state)
1417{
1418
1419 return 0;
1420}
1421
1422/**
1423 * vcn_v4_0_3_unified_ring_get_rptr - get unified read pointer
1424 *
1425 * @ring: amdgpu_ring pointer
1426 *
1427 * Returns the current hardware unified read pointer
1428 */
1429static uint64_t vcn_v4_0_3_unified_ring_get_rptr(struct amdgpu_ring *ring)
1430{
1431 struct amdgpu_device *adev = ring->adev;
1432
1433 if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1434 DRM_ERROR("wrong ring id is identified in %s", __func__);
1435
1436 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);
1437}
1438
1439/**
1440 * vcn_v4_0_3_unified_ring_get_wptr - get unified write pointer
1441 *
1442 * @ring: amdgpu_ring pointer
1443 *
1444 * Returns the current hardware unified write pointer
1445 */
1446static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring)
1447{
1448 struct amdgpu_device *adev = ring->adev;
1449
1450 if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1451 DRM_ERROR("wrong ring id is identified in %s", __func__);
1452
1453 if (ring->use_doorbell)
1454 return *ring->wptr_cpu_addr;
1455 else
1456 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me),
1457 regUVD_RB_WPTR);
1458}
1459
1460static void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1461 uint32_t val, uint32_t mask)
1462{
1463 /* Use normalized offsets when required */
1464 if (vcn_v4_0_3_normalizn_reqd(ring->adev))
1465 reg = NORMALIZE_VCN_REG_OFFSET(reg);
1466
1467 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1468 amdgpu_ring_write(ring, reg << 2);
1469 amdgpu_ring_write(ring, mask);
1470 amdgpu_ring_write(ring, val);
1471}
1472
1473static void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1474{
1475 /* Use normalized offsets when required */
1476 if (vcn_v4_0_3_normalizn_reqd(ring->adev))
1477 reg = NORMALIZE_VCN_REG_OFFSET(reg);
1478
1479 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1480 amdgpu_ring_write(ring, reg << 2);
1481 amdgpu_ring_write(ring, val);
1482}
1483
1484static void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1485 unsigned int vmid, uint64_t pd_addr)
1486{
1487 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1488
1489 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1490
1491 /* wait for reg writes */
1492 vcn_v4_0_3_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1493 vmid * hub->ctx_addr_distance,
1494 lower_32_bits(pd_addr), 0xffffffff);
1495}
1496
1497static void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1498{
1499 /* VCN engine access for HDP flush doesn't work when RRMT is enabled.
1500 * This is a workaround to avoid any HDP flush through VCN ring.
1501 */
1502}
1503
1504/**
1505 * vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer
1506 *
1507 * @ring: amdgpu_ring pointer
1508 *
1509 * Commits the enc write pointer to the hardware
1510 */
1511static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring)
1512{
1513 struct amdgpu_device *adev = ring->adev;
1514
1515 if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1516 DRM_ERROR("wrong ring id is identified in %s", __func__);
1517
1518 if (ring->use_doorbell) {
1519 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1520 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1521 } else {
1522 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR,
1523 lower_32_bits(ring->wptr));
1524 }
1525}
1526
1527static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = {
1528 .type = AMDGPU_RING_TYPE_VCN_ENC,
1529 .align_mask = 0x3f,
1530 .nop = VCN_ENC_CMD_NO_OP,
1531 .get_rptr = vcn_v4_0_3_unified_ring_get_rptr,
1532 .get_wptr = vcn_v4_0_3_unified_ring_get_wptr,
1533 .set_wptr = vcn_v4_0_3_unified_ring_set_wptr,
1534 .emit_frame_size =
1535 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1536 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1537 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1538 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1539 1, /* vcn_v2_0_enc_ring_insert_end */
1540 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1541 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1542 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1543 .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush,
1544 .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush,
1545 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1546 .test_ib = amdgpu_vcn_unified_ring_test_ib,
1547 .insert_nop = amdgpu_ring_insert_nop,
1548 .insert_end = vcn_v2_0_enc_ring_insert_end,
1549 .pad_ib = amdgpu_ring_generic_pad_ib,
1550 .begin_use = amdgpu_vcn_ring_begin_use,
1551 .end_use = amdgpu_vcn_ring_end_use,
1552 .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg,
1553 .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait,
1554 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1555};
1556
1557/**
1558 * vcn_v4_0_3_set_unified_ring_funcs - set unified ring functions
1559 *
1560 * @adev: amdgpu_device pointer
1561 *
1562 * Set unified ring functions
1563 */
1564static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev)
1565{
1566 int i, vcn_inst;
1567
1568 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1569 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs;
1570 adev->vcn.inst[i].ring_enc[0].me = i;
1571 vcn_inst = GET_INST(VCN, i);
1572 adev->vcn.inst[i].aid_id =
1573 vcn_inst / adev->vcn.num_inst_per_aid;
1574 }
1575}
1576
1577/**
1578 * vcn_v4_0_3_is_idle - check VCN block is idle
1579 *
1580 * @handle: amdgpu_device pointer
1581 *
1582 * Check whether VCN block is idle
1583 */
1584static bool vcn_v4_0_3_is_idle(void *handle)
1585{
1586 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1587 int i, ret = 1;
1588
1589 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1590 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) ==
1591 UVD_STATUS__IDLE);
1592 }
1593
1594 return ret;
1595}
1596
1597/**
1598 * vcn_v4_0_3_wait_for_idle - wait for VCN block idle
1599 *
1600 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
1601 *
1602 * Wait for VCN block idle
1603 */
1604static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block)
1605{
1606 struct amdgpu_device *adev = ip_block->adev;
1607 int i, ret = 0;
1608
1609 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1610 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS,
1611 UVD_STATUS__IDLE, UVD_STATUS__IDLE);
1612 if (ret)
1613 return ret;
1614 }
1615
1616 return ret;
1617}
1618
1619/* vcn_v4_0_3_set_clockgating_state - set VCN block clockgating state
1620 *
1621 * @handle: amdgpu_device pointer
1622 * @state: clock gating state
1623 *
1624 * Set VCN block clockgating state
1625 */
1626static int vcn_v4_0_3_set_clockgating_state(void *handle,
1627 enum amd_clockgating_state state)
1628{
1629 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1630 bool enable = state == AMD_CG_STATE_GATE;
1631 int i;
1632
1633 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1634 if (enable) {
1635 if (RREG32_SOC15(VCN, GET_INST(VCN, i),
1636 regUVD_STATUS) != UVD_STATUS__IDLE)
1637 return -EBUSY;
1638 vcn_v4_0_3_enable_clock_gating(adev, i);
1639 } else {
1640 vcn_v4_0_3_disable_clock_gating(adev, i);
1641 }
1642 }
1643 return 0;
1644}
1645
1646/**
1647 * vcn_v4_0_3_set_powergating_state - set VCN block powergating state
1648 *
1649 * @handle: amdgpu_device pointer
1650 * @state: power gating state
1651 *
1652 * Set VCN block powergating state
1653 */
1654static int vcn_v4_0_3_set_powergating_state(void *handle,
1655 enum amd_powergating_state state)
1656{
1657 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1658 int ret;
1659
1660 /* for SRIOV, guest should not control VCN Power-gating
1661 * MMSCH FW should control Power-gating and clock-gating
1662 * guest should avoid touching CGC and PG
1663 */
1664 if (amdgpu_sriov_vf(adev)) {
1665 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
1666 return 0;
1667 }
1668
1669 if (state == adev->vcn.cur_state)
1670 return 0;
1671
1672 if (state == AMD_PG_STATE_GATE)
1673 ret = vcn_v4_0_3_stop(adev);
1674 else
1675 ret = vcn_v4_0_3_start(adev);
1676
1677 if (!ret)
1678 adev->vcn.cur_state = state;
1679
1680 return ret;
1681}
1682
1683/**
1684 * vcn_v4_0_3_set_interrupt_state - set VCN block interrupt state
1685 *
1686 * @adev: amdgpu_device pointer
1687 * @source: interrupt sources
1688 * @type: interrupt types
1689 * @state: interrupt states
1690 *
1691 * Set VCN block interrupt state
1692 */
1693static int vcn_v4_0_3_set_interrupt_state(struct amdgpu_device *adev,
1694 struct amdgpu_irq_src *source,
1695 unsigned int type,
1696 enum amdgpu_interrupt_state state)
1697{
1698 return 0;
1699}
1700
1701/**
1702 * vcn_v4_0_3_process_interrupt - process VCN block interrupt
1703 *
1704 * @adev: amdgpu_device pointer
1705 * @source: interrupt sources
1706 * @entry: interrupt entry from clients and sources
1707 *
1708 * Process VCN block interrupt
1709 */
1710static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev,
1711 struct amdgpu_irq_src *source,
1712 struct amdgpu_iv_entry *entry)
1713{
1714 uint32_t i, inst;
1715
1716 i = node_id_to_phys_map[entry->node_id];
1717
1718 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n");
1719
1720 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst)
1721 if (adev->vcn.inst[inst].aid_id == i)
1722 break;
1723
1724 if (inst >= adev->vcn.num_vcn_inst) {
1725 dev_WARN_ONCE(adev->dev, 1,
1726 "Interrupt received for unknown VCN instance %d",
1727 entry->node_id);
1728 return 0;
1729 }
1730
1731 switch (entry->src_id) {
1732 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1733 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]);
1734 break;
1735 default:
1736 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
1737 entry->src_id, entry->src_data[0]);
1738 break;
1739 }
1740
1741 return 0;
1742}
1743
1744static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = {
1745 .set = vcn_v4_0_3_set_interrupt_state,
1746 .process = vcn_v4_0_3_process_interrupt,
1747};
1748
1749/**
1750 * vcn_v4_0_3_set_irq_funcs - set VCN block interrupt irq functions
1751 *
1752 * @adev: amdgpu_device pointer
1753 *
1754 * Set VCN block interrupt irq functions
1755 */
1756static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
1757{
1758 int i;
1759
1760 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1761 adev->vcn.inst->irq.num_types++;
1762 }
1763 adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
1764}
1765
1766static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
1767{
1768 struct amdgpu_device *adev = ip_block->adev;
1769 int i, j;
1770 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
1771 uint32_t inst_off, is_powered;
1772
1773 if (!adev->vcn.ip_dump)
1774 return;
1775
1776 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
1777 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1778 if (adev->vcn.harvest_config & (1 << i)) {
1779 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
1780 continue;
1781 }
1782
1783 inst_off = i * reg_count;
1784 is_powered = (adev->vcn.ip_dump[inst_off] &
1785 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
1786
1787 if (is_powered) {
1788 drm_printf(p, "\nActive Instance:VCN%d\n", i);
1789 for (j = 0; j < reg_count; j++)
1790 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name,
1791 adev->vcn.ip_dump[inst_off + j]);
1792 } else {
1793 drm_printf(p, "\nInactive Instance:VCN%d\n", i);
1794 }
1795 }
1796}
1797
1798static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block)
1799{
1800 struct amdgpu_device *adev = ip_block->adev;
1801 int i, j;
1802 bool is_powered;
1803 uint32_t inst_off, inst_id;
1804 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
1805
1806 if (!adev->vcn.ip_dump)
1807 return;
1808
1809 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1810 if (adev->vcn.harvest_config & (1 << i))
1811 continue;
1812
1813 inst_id = GET_INST(VCN, i);
1814 inst_off = i * reg_count;
1815 /* mmUVD_POWER_STATUS is always readable and is first element of the array */
1816 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);
1817 is_powered = (adev->vcn.ip_dump[inst_off] &
1818 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
1819
1820 if (is_powered)
1821 for (j = 1; j < reg_count; j++)
1822 adev->vcn.ip_dump[inst_off + j] =
1823 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],
1824 inst_id));
1825 }
1826}
1827
1828static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
1829 .name = "vcn_v4_0_3",
1830 .early_init = vcn_v4_0_3_early_init,
1831 .sw_init = vcn_v4_0_3_sw_init,
1832 .sw_fini = vcn_v4_0_3_sw_fini,
1833 .hw_init = vcn_v4_0_3_hw_init,
1834 .hw_fini = vcn_v4_0_3_hw_fini,
1835 .suspend = vcn_v4_0_3_suspend,
1836 .resume = vcn_v4_0_3_resume,
1837 .is_idle = vcn_v4_0_3_is_idle,
1838 .wait_for_idle = vcn_v4_0_3_wait_for_idle,
1839 .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
1840 .set_powergating_state = vcn_v4_0_3_set_powergating_state,
1841 .dump_ip_state = vcn_v4_0_3_dump_ip_state,
1842 .print_ip_state = vcn_v4_0_3_print_ip_state,
1843};
1844
1845const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = {
1846 .type = AMD_IP_BLOCK_TYPE_VCN,
1847 .major = 4,
1848 .minor = 0,
1849 .rev = 3,
1850 .funcs = &vcn_v4_0_3_ip_funcs,
1851};
1852
1853static const struct amdgpu_ras_err_status_reg_entry vcn_v4_0_3_ue_reg_list[] = {
1854 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDD, regVCN_UE_ERR_STATUS_HI_VIDD),
1855 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDD"},
1856 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDV, regVCN_UE_ERR_STATUS_HI_VIDV),
1857 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDV"},
1858};
1859
1860static void vcn_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev,
1861 uint32_t vcn_inst,
1862 void *ras_err_status)
1863{
1864 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
1865
1866 /* vcn v4_0_3 only support query uncorrectable errors */
1867 amdgpu_ras_inst_query_ras_error_count(adev,
1868 vcn_v4_0_3_ue_reg_list,
1869 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list),
1870 NULL, 0, GET_INST(VCN, vcn_inst),
1871 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
1872 &err_data->ue_count);
1873}
1874
1875static void vcn_v4_0_3_query_ras_error_count(struct amdgpu_device *adev,
1876 void *ras_err_status)
1877{
1878 uint32_t i;
1879
1880 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) {
1881 dev_warn(adev->dev, "VCN RAS is not supported\n");
1882 return;
1883 }
1884
1885 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
1886 vcn_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status);
1887}
1888
1889static void vcn_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev,
1890 uint32_t vcn_inst)
1891{
1892 amdgpu_ras_inst_reset_ras_error_count(adev,
1893 vcn_v4_0_3_ue_reg_list,
1894 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list),
1895 GET_INST(VCN, vcn_inst));
1896}
1897
1898static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev)
1899{
1900 uint32_t i;
1901
1902 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) {
1903 dev_warn(adev->dev, "VCN RAS is not supported\n");
1904 return;
1905 }
1906
1907 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
1908 vcn_v4_0_3_inst_reset_ras_error_count(adev, i);
1909}
1910
1911static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = {
1912 .query_ras_error_count = vcn_v4_0_3_query_ras_error_count,
1913 .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count,
1914};
1915
1916static struct amdgpu_vcn_ras vcn_v4_0_3_ras = {
1917 .ras_block = {
1918 .hw_ops = &vcn_v4_0_3_ras_hw_ops,
1919 },
1920};
1921
1922static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev)
1923{
1924 adev->vcn.ras = &vcn_v4_0_3_ras;
1925}
1926
1927static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev,
1928 int inst_idx, bool indirect)
1929{
1930 uint32_t tmp;
1931
1932 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
1933 return;
1934
1935 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
1936 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
1937 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
1938 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
1939 WREG32_SOC15_DPG_MODE(inst_idx,
1940 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL),
1941 tmp, 0, indirect);
1942
1943 tmp = UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK;
1944 WREG32_SOC15_DPG_MODE(inst_idx,
1945 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_VCPU_INT_EN2),
1946 tmp, 0, indirect);
1947
1948 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
1949 WREG32_SOC15_DPG_MODE(inst_idx,
1950 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN),
1951 tmp, 0, indirect);
1952}