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1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28
29#include "amdgpu.h"
30#include "amdgpu_ucode.h"
31#include "amdgpu_trace.h"
32
33#include "gc/gc_12_0_0_offset.h"
34#include "gc/gc_12_0_0_sh_mask.h"
35#include "hdp/hdp_6_0_0_offset.h"
36#include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
37
38#include "soc15_common.h"
39#include "soc15.h"
40#include "sdma_v6_0_0_pkt_open.h"
41#include "nbio_v4_3.h"
42#include "sdma_common.h"
43#include "sdma_v7_0.h"
44#include "v12_structs.h"
45
46MODULE_FIRMWARE("amdgpu/sdma_7_0_0.bin");
47MODULE_FIRMWARE("amdgpu/sdma_7_0_1.bin");
48
49#define SDMA1_REG_OFFSET 0x600
50#define SDMA0_HYP_DEC_REG_START 0x5880
51#define SDMA0_HYP_DEC_REG_END 0x589a
52#define SDMA1_HYP_DEC_REG_OFFSET 0x20
53
54/*define for compression field for sdma7*/
55#define SDMA_PKT_CONSTANT_FILL_HEADER_compress_offset 0
56#define SDMA_PKT_CONSTANT_FILL_HEADER_compress_mask 0x00000001
57#define SDMA_PKT_CONSTANT_FILL_HEADER_compress_shift 16
58#define SDMA_PKT_CONSTANT_FILL_HEADER_COMPRESS(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_compress_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_compress_shift)
59
60static const struct amdgpu_hwip_reg_entry sdma_reg_list_7_0[] = {
61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),
62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),
63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),
64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG),
68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_REV),
69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI),
70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH),
71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS),
72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS),
73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0),
74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1),
75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0),
76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1),
77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL),
78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR),
79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI),
80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR),
81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI),
82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET),
83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO),
84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI),
85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL),
86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR),
87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN),
88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG),
89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0),
90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL),
91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR),
92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI),
93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR),
94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI),
95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET),
96 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO),
97 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI),
98 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR),
99 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN),
100 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG),
101 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL),
102 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR),
103 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI),
104 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR),
105 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI),
106 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET),
107 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO),
108 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI),
109 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR),
110 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN),
111 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG),
112 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS),
113 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_VM_CNTL),
114 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
115 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS),
116};
117
118static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev);
119static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev);
120static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev);
121static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev);
122static int sdma_v7_0_start(struct amdgpu_device *adev);
123
124static u32 sdma_v7_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
125{
126 u32 base;
127
128 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
129 internal_offset <= SDMA0_HYP_DEC_REG_END) {
130 base = adev->reg_offset[GC_HWIP][0][1];
131 if (instance != 0)
132 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
133 } else {
134 base = adev->reg_offset[GC_HWIP][0][0];
135 if (instance == 1)
136 internal_offset += SDMA1_REG_OFFSET;
137 }
138
139 return base + internal_offset;
140}
141
142static unsigned sdma_v7_0_ring_init_cond_exec(struct amdgpu_ring *ring,
143 uint64_t addr)
144{
145 unsigned ret;
146
147 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));
148 amdgpu_ring_write(ring, lower_32_bits(addr));
149 amdgpu_ring_write(ring, upper_32_bits(addr));
150 amdgpu_ring_write(ring, 1);
151 /* this is the offset we need patch later */
152 ret = ring->wptr & ring->buf_mask;
153 /* insert dummy here and patch it later */
154 amdgpu_ring_write(ring, 0);
155
156 return ret;
157}
158
159/**
160 * sdma_v7_0_ring_get_rptr - get the current read pointer
161 *
162 * @ring: amdgpu ring pointer
163 *
164 * Get the current rptr from the hardware.
165 */
166static uint64_t sdma_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
167{
168 u64 *rptr;
169
170 /* XXX check if swapping is necessary on BE */
171 rptr = (u64 *)ring->rptr_cpu_addr;
172
173 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
174 return ((*rptr) >> 2);
175}
176
177/**
178 * sdma_v7_0_ring_get_wptr - get the current write pointer
179 *
180 * @ring: amdgpu ring pointer
181 *
182 * Get the current wptr from the hardware.
183 */
184static uint64_t sdma_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
185{
186 u64 wptr = 0;
187
188 if (ring->use_doorbell) {
189 /* XXX check if swapping is necessary on BE */
190 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
191 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
192 }
193
194 return wptr >> 2;
195}
196
197/**
198 * sdma_v7_0_ring_set_wptr - commit the write pointer
199 *
200 * @ring: amdgpu ring pointer
201 *
202 * Write the wptr back to the hardware.
203 */
204static void sdma_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
205{
206 struct amdgpu_device *adev = ring->adev;
207 uint32_t *wptr_saved;
208 uint32_t *is_queue_unmap;
209 uint64_t aggregated_db_index;
210 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
211
212 DRM_DEBUG("Setting write pointer\n");
213
214 if (ring->is_mes_queue) {
215 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
216 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
217 sizeof(uint32_t));
218 aggregated_db_index =
219 amdgpu_mes_get_aggregated_doorbell_index(adev,
220 ring->hw_prio);
221
222 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
223 ring->wptr << 2);
224 *wptr_saved = ring->wptr << 2;
225 if (*is_queue_unmap) {
226 WDOORBELL64(aggregated_db_index, ring->wptr << 2);
227 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
228 ring->doorbell_index, ring->wptr << 2);
229 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
230 } else {
231 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
232 ring->doorbell_index, ring->wptr << 2);
233 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
234 }
235 } else {
236 if (ring->use_doorbell) {
237 DRM_DEBUG("Using doorbell -- "
238 "wptr_offs == 0x%08x "
239 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
240 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
241 ring->wptr_offs,
242 lower_32_bits(ring->wptr << 2),
243 upper_32_bits(ring->wptr << 2));
244 /* XXX check if swapping is necessary on BE */
245 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
246 ring->wptr << 2);
247 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
248 ring->doorbell_index, ring->wptr << 2);
249 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
250 } else {
251 DRM_DEBUG("Not using doorbell -- "
252 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
253 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
254 ring->me,
255 lower_32_bits(ring->wptr << 2),
256 ring->me,
257 upper_32_bits(ring->wptr << 2));
258 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev,
259 ring->me,
260 regSDMA0_QUEUE0_RB_WPTR),
261 lower_32_bits(ring->wptr << 2));
262 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev,
263 ring->me,
264 regSDMA0_QUEUE0_RB_WPTR_HI),
265 upper_32_bits(ring->wptr << 2));
266 }
267 }
268}
269
270static void sdma_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
271{
272 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
273 int i;
274
275 for (i = 0; i < count; i++)
276 if (sdma && sdma->burst_nop && (i == 0))
277 amdgpu_ring_write(ring, ring->funcs->nop |
278 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
279 else
280 amdgpu_ring_write(ring, ring->funcs->nop);
281}
282
283/**
284 * sdma_v7_0_ring_emit_ib - Schedule an IB on the DMA engine
285 *
286 * @ring: amdgpu ring pointer
287 * @job: job to retrieve vmid from
288 * @ib: IB object to schedule
289 * @flags: unused
290 *
291 * Schedule an IB in the DMA ring.
292 */
293static void sdma_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
294 struct amdgpu_job *job,
295 struct amdgpu_ib *ib,
296 uint32_t flags)
297{
298 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
299 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
300
301 /* An IB packet must end on a 8 DW boundary--the next dword
302 * must be on a 8-dword boundary. Our IB packet below is 6
303 * dwords long, thus add x number of NOPs, such that, in
304 * modular arithmetic,
305 * wptr + 6 + x = 8k, k >= 0, which in C is,
306 * (wptr + 6 + x) % 8 = 0.
307 * The expression below, is a solution of x.
308 */
309 sdma_v7_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
310
311 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) |
312 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
313 /* base must be 32 byte aligned */
314 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
315 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
316 amdgpu_ring_write(ring, ib->length_dw);
317 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
318 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
319}
320
321/**
322 * sdma_v7_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
323 *
324 * @ring: amdgpu ring pointer
325 *
326 * flush the IB by graphics cache rinse.
327 */
328static void sdma_v7_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
329{
330 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
331 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
332 SDMA_GCR_GLI_INV(1);
333
334 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
335 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ));
336 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
337 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
338 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
339 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
340 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
341 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
342 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
343}
344
345
346/**
347 * sdma_v7_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
348 *
349 * @ring: amdgpu ring pointer
350 *
351 * Emit an hdp flush packet on the requested DMA ring.
352 */
353static void sdma_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
354{
355 struct amdgpu_device *adev = ring->adev;
356 u32 ref_and_mask = 0;
357 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
358
359 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
360
361 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
362 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
363 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
364 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
365 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
366 amdgpu_ring_write(ring, ref_and_mask); /* reference */
367 amdgpu_ring_write(ring, ref_and_mask); /* mask */
368 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
369 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
370}
371
372/**
373 * sdma_v7_0_ring_emit_fence - emit a fence on the DMA ring
374 *
375 * @ring: amdgpu ring pointer
376 * @addr: address
377 * @seq: fence seq number
378 * @flags: fence flags
379 *
380 * Add a DMA fence packet to the ring to write
381 * the fence seq number and DMA trap packet to generate
382 * an interrupt if needed.
383 */
384static void sdma_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
385 unsigned flags)
386{
387 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
388 /* write the fence */
389 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
390 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
391 /* zero in first two bits */
392 BUG_ON(addr & 0x3);
393 amdgpu_ring_write(ring, lower_32_bits(addr));
394 amdgpu_ring_write(ring, upper_32_bits(addr));
395 amdgpu_ring_write(ring, lower_32_bits(seq));
396
397 /* optionally write high bits as well */
398 if (write64bit) {
399 addr += 4;
400 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
401 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
402 /* zero in first two bits */
403 BUG_ON(addr & 0x3);
404 amdgpu_ring_write(ring, lower_32_bits(addr));
405 amdgpu_ring_write(ring, upper_32_bits(addr));
406 amdgpu_ring_write(ring, upper_32_bits(seq));
407 }
408
409 if (flags & AMDGPU_FENCE_FLAG_INT) {
410 uint32_t ctx = ring->is_mes_queue ?
411 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
412 /* generate an interrupt */
413 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP));
414 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
415 }
416}
417
418/**
419 * sdma_v7_0_gfx_stop - stop the gfx async dma engines
420 *
421 * @adev: amdgpu_device pointer
422 *
423 * Stop the gfx async dma ring buffers.
424 */
425static void sdma_v7_0_gfx_stop(struct amdgpu_device *adev)
426{
427 u32 rb_cntl, ib_cntl;
428 int i;
429
430 for (i = 0; i < adev->sdma.num_instances; i++) {
431 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
432 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);
433 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
434 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
435 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);
436 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
437 }
438}
439
440/**
441 * sdma_v7_0_rlc_stop - stop the compute async dma engines
442 *
443 * @adev: amdgpu_device pointer
444 *
445 * Stop the compute async dma queues.
446 */
447static void sdma_v7_0_rlc_stop(struct amdgpu_device *adev)
448{
449 /* XXX todo */
450}
451
452/**
453 * sdma_v7_0_ctx_switch_enable - stop the async dma engines context switch
454 *
455 * @adev: amdgpu_device pointer
456 * @enable: enable/disable the DMA MEs context switch.
457 *
458 * Halt or unhalt the async dma engines context switch.
459 */
460static void sdma_v7_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
461{
462}
463
464/**
465 * sdma_v7_0_enable - stop the async dma engines
466 *
467 * @adev: amdgpu_device pointer
468 * @enable: enable/disable the DMA MEs.
469 *
470 * Halt or unhalt the async dma engines.
471 */
472static void sdma_v7_0_enable(struct amdgpu_device *adev, bool enable)
473{
474 u32 mcu_cntl;
475 int i;
476
477 if (!enable) {
478 sdma_v7_0_gfx_stop(adev);
479 sdma_v7_0_rlc_stop(adev);
480 }
481
482 if (amdgpu_sriov_vf(adev))
483 return;
484
485 for (i = 0; i < adev->sdma.num_instances; i++) {
486 mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));
487 mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_MCU_CNTL, HALT, enable ? 0 : 1);
488 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), mcu_cntl);
489 }
490}
491
492/**
493 * sdma_v7_0_gfx_resume - setup and start the async dma engines
494 *
495 * @adev: amdgpu_device pointer
496 *
497 * Set up the gfx DMA ring buffers and enable them.
498 * Returns 0 for success, error for failure.
499 */
500static int sdma_v7_0_gfx_resume(struct amdgpu_device *adev)
501{
502 struct amdgpu_ring *ring;
503 u32 rb_cntl, ib_cntl;
504 u32 rb_bufsz;
505 u32 doorbell;
506 u32 doorbell_offset;
507 u32 tmp;
508 u64 wptr_gpu_addr;
509 int i, r;
510
511 for (i = 0; i < adev->sdma.num_instances; i++) {
512 ring = &adev->sdma.instance[i].ring;
513
514 //if (!amdgpu_sriov_vf(adev))
515 // WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
516
517 /* Set ring buffer size in dwords */
518 rb_bufsz = order_base_2(ring->ring_size / 4);
519 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
520 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);
521#ifdef __BIG_ENDIAN
522 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);
523 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,
524 RPTR_WRITEBACK_SWAP_ENABLE, 1);
525#endif
526 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
527 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
528
529 /* Initialize the ring buffer's read and write pointers */
530 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
531 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
532 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
533 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
534
535 /* setup the wptr shadow polling */
536 wptr_gpu_addr = ring->wptr_gpu_addr;
537 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
538 lower_32_bits(wptr_gpu_addr));
539 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),
540 upper_32_bits(wptr_gpu_addr));
541
542 /* set the wb address whether it's enabled or not */
543 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),
544 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
545 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),
546 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
547
548 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
549 if (amdgpu_sriov_vf(adev))
550 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1);
551 else
552 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
553 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, MCU_WPTR_POLL_ENABLE, 1);
554
555 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
556 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
557
558 ring->wptr = 0;
559
560 /* before programing wptr to a less value, need set minor_ptr_update first */
561 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
562
563 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
564 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
565 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
566 }
567
568 doorbell = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));
569 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));
570
571 if (ring->use_doorbell) {
572 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
573 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,
574 OFFSET, ring->doorbell_index);
575 } else {
576 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);
577 }
578 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);
579 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
580
581 if (i == 0)
582 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
583 ring->doorbell_index,
584 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);
585
586 if (amdgpu_sriov_vf(adev))
587 sdma_v7_0_ring_set_wptr(ring);
588
589 /* set minor_ptr_update to 0 after wptr programed */
590 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);
591
592 /* Set up sdma hang watchdog */
593 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));
594 /* 100ms per unit */
595 tmp = REG_SET_FIELD(tmp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT,
596 max(adev->usec_timeout/100000, 1));
597 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), tmp);
598
599 /* Set up RESP_MODE to non-copy addresses */
600 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
601 tmp = REG_SET_FIELD(tmp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
602 tmp = REG_SET_FIELD(tmp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
603 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), tmp);
604
605 /* program default cache read and write policy */
606 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
607 /* clean read policy and write policy bits */
608 tmp &= 0xFF0FFF;
609 tmp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
610 (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
611 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), tmp);
612
613 if (!amdgpu_sriov_vf(adev)) {
614 /* unhalt engine */
615 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));
616 tmp = REG_SET_FIELD(tmp, SDMA0_MCU_CNTL, HALT, 0);
617 tmp = REG_SET_FIELD(tmp, SDMA0_MCU_CNTL, RESET, 0);
618 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), tmp);
619 }
620
621 /* enable DMA RB */
622 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);
623 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
624
625 ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
626 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);
627#ifdef __BIG_ENDIAN
628 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);
629#endif
630 /* enable DMA IBs */
631 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
632
633 ring->sched.ready = true;
634
635 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
636 sdma_v7_0_ctx_switch_enable(adev, true);
637 sdma_v7_0_enable(adev, true);
638 }
639
640 r = amdgpu_ring_test_helper(ring);
641 if (r) {
642 ring->sched.ready = false;
643 return r;
644 }
645
646 }
647
648 return 0;
649}
650
651/**
652 * sdma_v7_0_rlc_resume - setup and start the async dma engines
653 *
654 * @adev: amdgpu_device pointer
655 *
656 * Set up the compute DMA queues and enable them.
657 * Returns 0 for success, error for failure.
658 */
659static int sdma_v7_0_rlc_resume(struct amdgpu_device *adev)
660{
661 return 0;
662}
663
664static void sdma_v12_0_free_ucode_buffer(struct amdgpu_device *adev)
665{
666 int i;
667
668 for (i = 0; i < adev->sdma.num_instances; i++) {
669 amdgpu_bo_free_kernel(&adev->sdma.instance[i].sdma_fw_obj,
670 &adev->sdma.instance[i].sdma_fw_gpu_addr,
671 (void **)&adev->sdma.instance[i].sdma_fw_ptr);
672 }
673}
674
675/**
676 * sdma_v7_0_load_microcode - load the sDMA ME ucode
677 *
678 * @adev: amdgpu_device pointer
679 *
680 * Loads the sDMA0/1 ucode.
681 * Returns 0 for success, -EINVAL if the ucode is not available.
682 */
683static int sdma_v7_0_load_microcode(struct amdgpu_device *adev)
684{
685 const struct sdma_firmware_header_v3_0 *hdr;
686 const __le32 *fw_data;
687 u32 fw_size;
688 uint32_t tmp, sdma_status, ic_op_cntl;
689 int i, r, j;
690
691 /* halt the MEs */
692 sdma_v7_0_enable(adev, false);
693
694 if (!adev->sdma.instance[0].fw)
695 return -EINVAL;
696
697 hdr = (const struct sdma_firmware_header_v3_0 *)
698 adev->sdma.instance[0].fw->data;
699 amdgpu_ucode_print_sdma_hdr(&hdr->header);
700
701 fw_data = (const __le32 *)(adev->sdma.instance[0].fw->data +
702 le32_to_cpu(hdr->ucode_offset_bytes));
703 fw_size = le32_to_cpu(hdr->ucode_size_bytes);
704
705 for (i = 0; i < adev->sdma.num_instances; i++) {
706 r = amdgpu_bo_create_reserved(adev, fw_size,
707 PAGE_SIZE,
708 AMDGPU_GEM_DOMAIN_VRAM,
709 &adev->sdma.instance[i].sdma_fw_obj,
710 &adev->sdma.instance[i].sdma_fw_gpu_addr,
711 (void **)&adev->sdma.instance[i].sdma_fw_ptr);
712 if (r) {
713 dev_err(adev->dev, "(%d) failed to create sdma ucode bo\n", r);
714 return r;
715 }
716
717 memcpy(adev->sdma.instance[i].sdma_fw_ptr, fw_data, fw_size);
718
719 amdgpu_bo_kunmap(adev->sdma.instance[i].sdma_fw_obj);
720 amdgpu_bo_unreserve(adev->sdma.instance[i].sdma_fw_obj);
721
722 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL));
723 tmp = REG_SET_FIELD(tmp, SDMA0_IC_CNTL, GPA, 0);
724 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_CNTL), tmp);
725
726 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_LO),
727 lower_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr));
728 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_BASE_HI),
729 upper_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr));
730
731 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL));
732 tmp = REG_SET_FIELD(tmp, SDMA0_IC_OP_CNTL, PRIME_ICACHE, 1);
733 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL), tmp);
734
735 /* Wait for sdma ucode init complete */
736 for (j = 0; j < adev->usec_timeout; j++) {
737 ic_op_cntl = RREG32_SOC15_IP(GC,
738 sdma_v7_0_get_reg_offset(adev, i, regSDMA0_IC_OP_CNTL));
739 sdma_status = RREG32_SOC15_IP(GC,
740 sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
741 if ((REG_GET_FIELD(ic_op_cntl, SDMA0_IC_OP_CNTL, ICACHE_PRIMED) == 1) &&
742 (REG_GET_FIELD(sdma_status, SDMA0_STATUS_REG, UCODE_INIT_DONE) == 1))
743 break;
744 udelay(1);
745 }
746
747 if (j >= adev->usec_timeout) {
748 dev_err(adev->dev, "failed to init sdma ucode\n");
749 return -EINVAL;
750 }
751 }
752
753 return 0;
754}
755
756static int sdma_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)
757{
758 struct amdgpu_device *adev = ip_block->adev;
759 u32 tmp;
760 int i;
761
762 sdma_v7_0_gfx_stop(adev);
763
764 for (i = 0; i < adev->sdma.num_instances; i++) {
765 //tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_FREEZE));
766 //tmp |= SDMA0_FREEZE__FREEZE_MASK;
767 //WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);
768 tmp = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL));
769 tmp |= SDMA0_MCU_CNTL__HALT_MASK;
770 tmp |= SDMA0_MCU_CNTL__RESET_MASK;
771 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_MCU_CNTL), tmp);
772
773 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);
774
775 udelay(100);
776
777 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i;
778 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
779 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
780
781 udelay(100);
782
783 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);
784 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
785
786 udelay(100);
787 }
788
789 return sdma_v7_0_start(adev);
790}
791
792static bool sdma_v7_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
793{
794 struct amdgpu_device *adev = ip_block->adev;
795 struct amdgpu_ring *ring;
796 int i, r;
797 long tmo = msecs_to_jiffies(1000);
798
799 for (i = 0; i < adev->sdma.num_instances; i++) {
800 ring = &adev->sdma.instance[i].ring;
801 r = amdgpu_ring_test_ib(ring, tmo);
802 if (r)
803 return true;
804 }
805
806 return false;
807}
808
809/**
810 * sdma_v7_0_start - setup and start the async dma engines
811 *
812 * @adev: amdgpu_device pointer
813 *
814 * Set up the DMA engines and enable them.
815 * Returns 0 for success, error for failure.
816 */
817static int sdma_v7_0_start(struct amdgpu_device *adev)
818{
819 int r = 0;
820
821 if (amdgpu_sriov_vf(adev)) {
822 sdma_v7_0_ctx_switch_enable(adev, false);
823 sdma_v7_0_enable(adev, false);
824
825 /* set RB registers */
826 r = sdma_v7_0_gfx_resume(adev);
827 return r;
828 }
829
830 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
831 r = sdma_v7_0_load_microcode(adev);
832 if (r) {
833 sdma_v12_0_free_ucode_buffer(adev);
834 return r;
835 }
836
837 if (amdgpu_emu_mode == 1)
838 msleep(1000);
839 }
840
841 /* unhalt the MEs */
842 sdma_v7_0_enable(adev, true);
843 /* enable sdma ring preemption */
844 sdma_v7_0_ctx_switch_enable(adev, true);
845
846 /* start the gfx rings and rlc compute queues */
847 r = sdma_v7_0_gfx_resume(adev);
848 if (r)
849 return r;
850 r = sdma_v7_0_rlc_resume(adev);
851
852 return r;
853}
854
855static int sdma_v7_0_mqd_init(struct amdgpu_device *adev, void *mqd,
856 struct amdgpu_mqd_prop *prop)
857{
858 struct v12_sdma_mqd *m = mqd;
859 uint64_t wb_gpu_addr;
860
861 m->sdmax_rlcx_rb_cntl =
862 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
863 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
864 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
865 1 << SDMA0_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT;
866
867 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
868 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
869
870 wb_gpu_addr = prop->wptr_gpu_addr;
871 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
872 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
873
874 wb_gpu_addr = prop->rptr_gpu_addr;
875 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
876 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
877
878 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, 0,
879 regSDMA0_QUEUE0_IB_CNTL));
880
881 m->sdmax_rlcx_doorbell_offset =
882 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
883
884 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
885
886 m->sdmax_rlcx_doorbell_log = 0;
887 m->sdmax_rlcx_rb_aql_cntl = 0x4000; //regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;
888 m->sdmax_rlcx_dummy_reg = 0xf; //regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;
889
890 return 0;
891}
892
893static void sdma_v7_0_set_mqd_funcs(struct amdgpu_device *adev)
894{
895 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v12_sdma_mqd);
896 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v7_0_mqd_init;
897}
898
899/**
900 * sdma_v7_0_ring_test_ring - simple async dma engine test
901 *
902 * @ring: amdgpu_ring structure holding ring information
903 *
904 * Test the DMA engine by writing using it to write an
905 * value to memory.
906 * Returns 0 for success, error for failure.
907 */
908static int sdma_v7_0_ring_test_ring(struct amdgpu_ring *ring)
909{
910 struct amdgpu_device *adev = ring->adev;
911 unsigned i;
912 unsigned index;
913 int r;
914 u32 tmp;
915 u64 gpu_addr;
916 volatile uint32_t *cpu_ptr = NULL;
917
918 tmp = 0xCAFEDEAD;
919
920 if (ring->is_mes_queue) {
921 uint32_t offset = 0;
922 offset = amdgpu_mes_ctx_get_offs(ring,
923 AMDGPU_MES_CTX_PADDING_OFFS);
924 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
925 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
926 *cpu_ptr = tmp;
927 } else {
928 r = amdgpu_device_wb_get(adev, &index);
929 if (r) {
930 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
931 return r;
932 }
933
934 gpu_addr = adev->wb.gpu_addr + (index * 4);
935 adev->wb.wb[index] = cpu_to_le32(tmp);
936 }
937
938 r = amdgpu_ring_alloc(ring, 5);
939 if (r) {
940 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
941 if (!ring->is_mes_queue)
942 amdgpu_device_wb_free(adev, index);
943 return r;
944 }
945
946 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
947 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
948 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
949 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
950 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
951 amdgpu_ring_write(ring, 0xDEADBEEF);
952 amdgpu_ring_commit(ring);
953
954 for (i = 0; i < adev->usec_timeout; i++) {
955 if (ring->is_mes_queue)
956 tmp = le32_to_cpu(*cpu_ptr);
957 else
958 tmp = le32_to_cpu(adev->wb.wb[index]);
959 if (tmp == 0xDEADBEEF)
960 break;
961 if (amdgpu_emu_mode == 1)
962 msleep(1);
963 else
964 udelay(1);
965 }
966
967 if (i >= adev->usec_timeout)
968 r = -ETIMEDOUT;
969
970 if (!ring->is_mes_queue)
971 amdgpu_device_wb_free(adev, index);
972
973 return r;
974}
975
976/**
977 * sdma_v7_0_ring_test_ib - test an IB on the DMA engine
978 *
979 * @ring: amdgpu_ring structure holding ring information
980 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
981 *
982 * Test a simple IB in the DMA ring.
983 * Returns 0 on success, error on failure.
984 */
985static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
986{
987 struct amdgpu_device *adev = ring->adev;
988 struct amdgpu_ib ib;
989 struct dma_fence *f = NULL;
990 unsigned index;
991 long r;
992 u32 tmp = 0;
993 u64 gpu_addr;
994 volatile uint32_t *cpu_ptr = NULL;
995
996 tmp = 0xCAFEDEAD;
997 memset(&ib, 0, sizeof(ib));
998
999 if (ring->is_mes_queue) {
1000 uint32_t offset = 0;
1001 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
1002 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1003 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1004
1005 offset = amdgpu_mes_ctx_get_offs(ring,
1006 AMDGPU_MES_CTX_PADDING_OFFS);
1007 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1008 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1009 *cpu_ptr = tmp;
1010 } else {
1011 r = amdgpu_device_wb_get(adev, &index);
1012 if (r) {
1013 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1014 return r;
1015 }
1016
1017 gpu_addr = adev->wb.gpu_addr + (index * 4);
1018 adev->wb.wb[index] = cpu_to_le32(tmp);
1019
1020 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
1021 if (r) {
1022 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1023 goto err0;
1024 }
1025 }
1026
1027 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1028 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1029 ib.ptr[1] = lower_32_bits(gpu_addr);
1030 ib.ptr[2] = upper_32_bits(gpu_addr);
1031 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1032 ib.ptr[4] = 0xDEADBEEF;
1033 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1034 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1035 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1036 ib.length_dw = 8;
1037
1038 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1039 if (r)
1040 goto err1;
1041
1042 r = dma_fence_wait_timeout(f, false, timeout);
1043 if (r == 0) {
1044 DRM_ERROR("amdgpu: IB test timed out\n");
1045 r = -ETIMEDOUT;
1046 goto err1;
1047 } else if (r < 0) {
1048 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1049 goto err1;
1050 }
1051
1052 if (ring->is_mes_queue)
1053 tmp = le32_to_cpu(*cpu_ptr);
1054 else
1055 tmp = le32_to_cpu(adev->wb.wb[index]);
1056
1057 if (tmp == 0xDEADBEEF)
1058 r = 0;
1059 else
1060 r = -EINVAL;
1061
1062err1:
1063 amdgpu_ib_free(adev, &ib, NULL);
1064 dma_fence_put(f);
1065err0:
1066 if (!ring->is_mes_queue)
1067 amdgpu_device_wb_free(adev, index);
1068 return r;
1069}
1070
1071
1072/**
1073 * sdma_v7_0_vm_copy_pte - update PTEs by copying them from the GART
1074 *
1075 * @ib: indirect buffer to fill with commands
1076 * @pe: addr of the page entry
1077 * @src: src addr to copy from
1078 * @count: number of page entries to update
1079 *
1080 * Update PTEs by copying them from the GART using sDMA.
1081 */
1082static void sdma_v7_0_vm_copy_pte(struct amdgpu_ib *ib,
1083 uint64_t pe, uint64_t src,
1084 unsigned count)
1085{
1086 unsigned bytes = count * 8;
1087
1088 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1089 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1090 SDMA_PKT_COPY_LINEAR_HEADER_CPV(1);
1091
1092 ib->ptr[ib->length_dw++] = bytes - 1;
1093 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1094 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1095 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1096 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1097 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1098 ib->ptr[ib->length_dw++] = 0;
1099
1100}
1101
1102/**
1103 * sdma_v7_0_vm_write_pte - update PTEs by writing them manually
1104 *
1105 * @ib: indirect buffer to fill with commands
1106 * @pe: addr of the page entry
1107 * @value: dst addr to write into pe
1108 * @count: number of page entries to update
1109 * @incr: increase next addr by incr bytes
1110 *
1111 * Update PTEs by writing them manually using sDMA.
1112 */
1113static void sdma_v7_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1114 uint64_t value, unsigned count,
1115 uint32_t incr)
1116{
1117 unsigned ndw = count * 2;
1118
1119 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1120 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1121 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1122 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1123 ib->ptr[ib->length_dw++] = ndw - 1;
1124 for (; ndw > 0; ndw -= 2) {
1125 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1126 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1127 value += incr;
1128 }
1129}
1130
1131/**
1132 * sdma_v7_0_vm_set_pte_pde - update the page tables using sDMA
1133 *
1134 * @ib: indirect buffer to fill with commands
1135 * @pe: addr of the page entry
1136 * @addr: dst addr to write into pe
1137 * @count: number of page entries to update
1138 * @incr: increase next addr by incr bytes
1139 * @flags: access flags
1140 *
1141 * Update the page tables using sDMA.
1142 */
1143static void sdma_v7_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1144 uint64_t pe,
1145 uint64_t addr, unsigned count,
1146 uint32_t incr, uint64_t flags)
1147{
1148 /* for physically contiguous pages (vram) */
1149 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);
1150 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1151 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1152 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1153 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1154 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1155 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1156 ib->ptr[ib->length_dw++] = incr; /* increment size */
1157 ib->ptr[ib->length_dw++] = 0;
1158 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1159}
1160
1161/**
1162 * sdma_v7_0_ring_pad_ib - pad the IB
1163 *
1164 * @ring: amdgpu ring pointer
1165 * @ib: indirect buffer to fill with padding
1166 *
1167 * Pad the IB with NOPs to a boundary multiple of 8.
1168 */
1169static void sdma_v7_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1170{
1171 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1172 u32 pad_count;
1173 int i;
1174
1175 pad_count = (-ib->length_dw) & 0x7;
1176 for (i = 0; i < pad_count; i++)
1177 if (sdma && sdma->burst_nop && (i == 0))
1178 ib->ptr[ib->length_dw++] =
1179 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) |
1180 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1181 else
1182 ib->ptr[ib->length_dw++] =
1183 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP);
1184}
1185
1186/**
1187 * sdma_v7_0_ring_emit_pipeline_sync - sync the pipeline
1188 *
1189 * @ring: amdgpu_ring pointer
1190 *
1191 * Make sure all previous operations are completed (CIK).
1192 */
1193static void sdma_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1194{
1195 uint32_t seq = ring->fence_drv.sync_seq;
1196 uint64_t addr = ring->fence_drv.gpu_addr;
1197
1198 /* wait for idle */
1199 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1200 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1201 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1202 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1203 amdgpu_ring_write(ring, addr & 0xfffffffc);
1204 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1205 amdgpu_ring_write(ring, seq); /* reference */
1206 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1207 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1208 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1209}
1210
1211/**
1212 * sdma_v7_0_ring_emit_vm_flush - vm flush using sDMA
1213 *
1214 * @ring: amdgpu_ring pointer
1215 * @vmid: vmid number to use
1216 * @pd_addr: address
1217 *
1218 * Update the page table base and flush the VM TLB
1219 * using sDMA.
1220 */
1221static void sdma_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1222 unsigned vmid, uint64_t pd_addr)
1223{
1224 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1225}
1226
1227static void sdma_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
1228 uint32_t reg, uint32_t val)
1229{
1230 /* SRBM WRITE command will not support on sdma v7.
1231 * Use Register WRITE command instead, which OPCODE is same as SRBM WRITE
1232 */
1233 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE));
1234 amdgpu_ring_write(ring, reg << 2);
1235 amdgpu_ring_write(ring, val);
1236}
1237
1238static void sdma_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1239 uint32_t val, uint32_t mask)
1240{
1241 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1242 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1243 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1244 amdgpu_ring_write(ring, reg << 2);
1245 amdgpu_ring_write(ring, 0);
1246 amdgpu_ring_write(ring, val); /* reference */
1247 amdgpu_ring_write(ring, mask); /* mask */
1248 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1249 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1250}
1251
1252static void sdma_v7_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1253 uint32_t reg0, uint32_t reg1,
1254 uint32_t ref, uint32_t mask)
1255{
1256 amdgpu_ring_emit_wreg(ring, reg0, ref);
1257 /* wait for a cycle to reset vm_inv_eng*_ack */
1258 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1259 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1260}
1261
1262static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block)
1263{
1264 struct amdgpu_device *adev = ip_block->adev;
1265 int r;
1266
1267 r = amdgpu_sdma_init_microcode(adev, 0, true);
1268 if (r) {
1269 DRM_ERROR("Failed to init sdma firmware!\n");
1270 return r;
1271 }
1272
1273 sdma_v7_0_set_ring_funcs(adev);
1274 sdma_v7_0_set_buffer_funcs(adev);
1275 sdma_v7_0_set_vm_pte_funcs(adev);
1276 sdma_v7_0_set_irq_funcs(adev);
1277 sdma_v7_0_set_mqd_funcs(adev);
1278
1279 return 0;
1280}
1281
1282static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block)
1283{
1284 struct amdgpu_ring *ring;
1285 int r, i;
1286 struct amdgpu_device *adev = ip_block->adev;
1287 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0);
1288 uint32_t *ptr;
1289
1290 /* SDMA trap event */
1291 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1292 GFX_11_0_0__SRCID__SDMA_TRAP,
1293 &adev->sdma.trap_irq);
1294 if (r)
1295 return r;
1296
1297 for (i = 0; i < adev->sdma.num_instances; i++) {
1298 ring = &adev->sdma.instance[i].ring;
1299 ring->ring_obj = NULL;
1300 ring->use_doorbell = true;
1301 ring->me = i;
1302
1303 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1304 ring->use_doorbell?"true":"false");
1305
1306 ring->doorbell_index =
1307 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset
1308
1309 ring->vm_hub = AMDGPU_GFXHUB(0);
1310 sprintf(ring->name, "sdma%d", i);
1311 r = amdgpu_ring_init(adev, ring, 1024,
1312 &adev->sdma.trap_irq,
1313 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1314 AMDGPU_RING_PRIO_DEFAULT, NULL);
1315 if (r)
1316 return r;
1317 }
1318
1319 /* Allocate memory for SDMA IP Dump buffer */
1320 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);
1321 if (ptr)
1322 adev->sdma.ip_dump = ptr;
1323 else
1324 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
1325
1326 return r;
1327}
1328
1329static int sdma_v7_0_sw_fini(struct amdgpu_ip_block *ip_block)
1330{
1331 struct amdgpu_device *adev = ip_block->adev;
1332 int i;
1333
1334 for (i = 0; i < adev->sdma.num_instances; i++)
1335 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1336
1337 amdgpu_sdma_destroy_inst_ctx(adev, true);
1338
1339 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)
1340 sdma_v12_0_free_ucode_buffer(adev);
1341
1342 kfree(adev->sdma.ip_dump);
1343
1344 return 0;
1345}
1346
1347static int sdma_v7_0_hw_init(struct amdgpu_ip_block *ip_block)
1348{
1349 struct amdgpu_device *adev = ip_block->adev;
1350
1351 return sdma_v7_0_start(adev);
1352}
1353
1354static int sdma_v7_0_hw_fini(struct amdgpu_ip_block *ip_block)
1355{
1356 struct amdgpu_device *adev = ip_block->adev;
1357
1358 if (amdgpu_sriov_vf(adev))
1359 return 0;
1360
1361 sdma_v7_0_ctx_switch_enable(adev, false);
1362 sdma_v7_0_enable(adev, false);
1363
1364 return 0;
1365}
1366
1367static int sdma_v7_0_suspend(struct amdgpu_ip_block *ip_block)
1368{
1369 return sdma_v7_0_hw_fini(ip_block);
1370}
1371
1372static int sdma_v7_0_resume(struct amdgpu_ip_block *ip_block)
1373{
1374 return sdma_v7_0_hw_init(ip_block);
1375}
1376
1377static bool sdma_v7_0_is_idle(void *handle)
1378{
1379 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1380 u32 i;
1381
1382 for (i = 0; i < adev->sdma.num_instances; i++) {
1383 u32 tmp = RREG32(sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
1384
1385 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1386 return false;
1387 }
1388
1389 return true;
1390}
1391
1392static int sdma_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
1393{
1394 unsigned i;
1395 u32 sdma0, sdma1;
1396 struct amdgpu_device *adev = ip_block->adev;
1397
1398 for (i = 0; i < adev->usec_timeout; i++) {
1399 sdma0 = RREG32(sdma_v7_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
1400 sdma1 = RREG32(sdma_v7_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));
1401
1402 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1403 return 0;
1404 udelay(1);
1405 }
1406 return -ETIMEDOUT;
1407}
1408
1409static int sdma_v7_0_ring_preempt_ib(struct amdgpu_ring *ring)
1410{
1411 int i, r = 0;
1412 struct amdgpu_device *adev = ring->adev;
1413 u32 index = 0;
1414 u64 sdma_gfx_preempt;
1415
1416 amdgpu_sdma_get_index_from_ring(ring, &index);
1417 sdma_gfx_preempt =
1418 sdma_v7_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);
1419
1420 /* assert preemption condition */
1421 amdgpu_ring_set_preempt_cond_exec(ring, false);
1422
1423 /* emit the trailing fence */
1424 ring->trail_seq += 1;
1425 r = amdgpu_ring_alloc(ring, 10);
1426 if (r) {
1427 DRM_ERROR("ring %d failed to be allocated \n", ring->idx);
1428 return r;
1429 }
1430 sdma_v7_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1431 ring->trail_seq, 0);
1432 amdgpu_ring_commit(ring);
1433
1434 /* assert IB preemption */
1435 WREG32(sdma_gfx_preempt, 1);
1436
1437 /* poll the trailing fence */
1438 for (i = 0; i < adev->usec_timeout; i++) {
1439 if (ring->trail_seq ==
1440 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1441 break;
1442 udelay(1);
1443 }
1444
1445 if (i >= adev->usec_timeout) {
1446 r = -EINVAL;
1447 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1448 }
1449
1450 /* deassert IB preemption */
1451 WREG32(sdma_gfx_preempt, 0);
1452
1453 /* deassert the preemption condition */
1454 amdgpu_ring_set_preempt_cond_exec(ring, true);
1455 return r;
1456}
1457
1458static int sdma_v7_0_set_trap_irq_state(struct amdgpu_device *adev,
1459 struct amdgpu_irq_src *source,
1460 unsigned type,
1461 enum amdgpu_interrupt_state state)
1462{
1463 u32 sdma_cntl;
1464
1465 u32 reg_offset = sdma_v7_0_get_reg_offset(adev, type, regSDMA0_CNTL);
1466
1467 sdma_cntl = RREG32(reg_offset);
1468 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1469 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1470 WREG32(reg_offset, sdma_cntl);
1471
1472 return 0;
1473}
1474
1475static int sdma_v7_0_process_trap_irq(struct amdgpu_device *adev,
1476 struct amdgpu_irq_src *source,
1477 struct amdgpu_iv_entry *entry)
1478{
1479 int instances, queue;
1480 uint32_t mes_queue_id = entry->src_data[0];
1481
1482 DRM_DEBUG("IH: SDMA trap\n");
1483
1484 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1485 struct amdgpu_mes_queue *queue;
1486
1487 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1488
1489 spin_lock(&adev->mes.queue_id_lock);
1490 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1491 if (queue) {
1492 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1493 amdgpu_fence_process(queue->ring);
1494 }
1495 spin_unlock(&adev->mes.queue_id_lock);
1496 return 0;
1497 }
1498
1499 queue = entry->ring_id & 0xf;
1500 instances = (entry->ring_id & 0xf0) >> 4;
1501 if (instances > 1) {
1502 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");
1503 return -EINVAL;
1504 }
1505
1506 switch (entry->client_id) {
1507 case SOC21_IH_CLIENTID_GFX:
1508 switch (queue) {
1509 case 0:
1510 amdgpu_fence_process(&adev->sdma.instance[instances].ring);
1511 break;
1512 default:
1513 break;
1514 }
1515 break;
1516 }
1517 return 0;
1518}
1519
1520static int sdma_v7_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1521 struct amdgpu_irq_src *source,
1522 struct amdgpu_iv_entry *entry)
1523{
1524 return 0;
1525}
1526
1527static int sdma_v7_0_set_clockgating_state(void *handle,
1528 enum amd_clockgating_state state)
1529{
1530 return 0;
1531}
1532
1533static int sdma_v7_0_set_powergating_state(void *handle,
1534 enum amd_powergating_state state)
1535{
1536 return 0;
1537}
1538
1539static void sdma_v7_0_get_clockgating_state(void *handle, u64 *flags)
1540{
1541}
1542
1543static void sdma_v7_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
1544{
1545 struct amdgpu_device *adev = ip_block->adev;
1546 int i, j;
1547 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0);
1548 uint32_t instance_offset;
1549
1550 if (!adev->sdma.ip_dump)
1551 return;
1552
1553 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
1554 for (i = 0; i < adev->sdma.num_instances; i++) {
1555 instance_offset = i * reg_count;
1556 drm_printf(p, "\nInstance:%d\n", i);
1557
1558 for (j = 0; j < reg_count; j++)
1559 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_7_0[j].reg_name,
1560 adev->sdma.ip_dump[instance_offset + j]);
1561 }
1562}
1563
1564static void sdma_v7_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
1565{
1566 struct amdgpu_device *adev = ip_block->adev;
1567 int i, j;
1568 uint32_t instance_offset;
1569 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0);
1570
1571 if (!adev->sdma.ip_dump)
1572 return;
1573
1574 amdgpu_gfx_off_ctrl(adev, false);
1575 for (i = 0; i < adev->sdma.num_instances; i++) {
1576 instance_offset = i * reg_count;
1577 for (j = 0; j < reg_count; j++)
1578 adev->sdma.ip_dump[instance_offset + j] =
1579 RREG32(sdma_v7_0_get_reg_offset(adev, i,
1580 sdma_reg_list_7_0[j].reg_offset));
1581 }
1582 amdgpu_gfx_off_ctrl(adev, true);
1583}
1584
1585const struct amd_ip_funcs sdma_v7_0_ip_funcs = {
1586 .name = "sdma_v7_0",
1587 .early_init = sdma_v7_0_early_init,
1588 .late_init = NULL,
1589 .sw_init = sdma_v7_0_sw_init,
1590 .sw_fini = sdma_v7_0_sw_fini,
1591 .hw_init = sdma_v7_0_hw_init,
1592 .hw_fini = sdma_v7_0_hw_fini,
1593 .suspend = sdma_v7_0_suspend,
1594 .resume = sdma_v7_0_resume,
1595 .is_idle = sdma_v7_0_is_idle,
1596 .wait_for_idle = sdma_v7_0_wait_for_idle,
1597 .soft_reset = sdma_v7_0_soft_reset,
1598 .check_soft_reset = sdma_v7_0_check_soft_reset,
1599 .set_clockgating_state = sdma_v7_0_set_clockgating_state,
1600 .set_powergating_state = sdma_v7_0_set_powergating_state,
1601 .get_clockgating_state = sdma_v7_0_get_clockgating_state,
1602 .dump_ip_state = sdma_v7_0_dump_ip_state,
1603 .print_ip_state = sdma_v7_0_print_ip_state,
1604};
1605
1606static const struct amdgpu_ring_funcs sdma_v7_0_ring_funcs = {
1607 .type = AMDGPU_RING_TYPE_SDMA,
1608 .align_mask = 0xf,
1609 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1610 .support_64bit_ptrs = true,
1611 .secure_submission_supported = true,
1612 .get_rptr = sdma_v7_0_ring_get_rptr,
1613 .get_wptr = sdma_v7_0_ring_get_wptr,
1614 .set_wptr = sdma_v7_0_ring_set_wptr,
1615 .emit_frame_size =
1616 5 + /* sdma_v7_0_ring_init_cond_exec */
1617 6 + /* sdma_v7_0_ring_emit_hdp_flush */
1618 6 + /* sdma_v7_0_ring_emit_pipeline_sync */
1619 /* sdma_v7_0_ring_emit_vm_flush */
1620 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1621 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1622 10 + 10 + 10, /* sdma_v7_0_ring_emit_fence x3 for user fence, vm fence */
1623 .emit_ib_size = 5 + 7 + 6, /* sdma_v7_0_ring_emit_ib */
1624 .emit_ib = sdma_v7_0_ring_emit_ib,
1625 .emit_mem_sync = sdma_v7_0_ring_emit_mem_sync,
1626 .emit_fence = sdma_v7_0_ring_emit_fence,
1627 .emit_pipeline_sync = sdma_v7_0_ring_emit_pipeline_sync,
1628 .emit_vm_flush = sdma_v7_0_ring_emit_vm_flush,
1629 .emit_hdp_flush = sdma_v7_0_ring_emit_hdp_flush,
1630 .test_ring = sdma_v7_0_ring_test_ring,
1631 .test_ib = sdma_v7_0_ring_test_ib,
1632 .insert_nop = sdma_v7_0_ring_insert_nop,
1633 .pad_ib = sdma_v7_0_ring_pad_ib,
1634 .emit_wreg = sdma_v7_0_ring_emit_wreg,
1635 .emit_reg_wait = sdma_v7_0_ring_emit_reg_wait,
1636 .emit_reg_write_reg_wait = sdma_v7_0_ring_emit_reg_write_reg_wait,
1637 .init_cond_exec = sdma_v7_0_ring_init_cond_exec,
1638 .preempt_ib = sdma_v7_0_ring_preempt_ib,
1639};
1640
1641static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1642{
1643 int i;
1644
1645 for (i = 0; i < adev->sdma.num_instances; i++) {
1646 adev->sdma.instance[i].ring.funcs = &sdma_v7_0_ring_funcs;
1647 adev->sdma.instance[i].ring.me = i;
1648 }
1649}
1650
1651static const struct amdgpu_irq_src_funcs sdma_v7_0_trap_irq_funcs = {
1652 .set = sdma_v7_0_set_trap_irq_state,
1653 .process = sdma_v7_0_process_trap_irq,
1654};
1655
1656static const struct amdgpu_irq_src_funcs sdma_v7_0_illegal_inst_irq_funcs = {
1657 .process = sdma_v7_0_process_illegal_inst_irq,
1658};
1659
1660static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1661{
1662 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1663 adev->sdma.num_instances;
1664 adev->sdma.trap_irq.funcs = &sdma_v7_0_trap_irq_funcs;
1665 adev->sdma.illegal_inst_irq.funcs = &sdma_v7_0_illegal_inst_irq_funcs;
1666}
1667
1668/**
1669 * sdma_v7_0_emit_copy_buffer - copy buffer using the sDMA engine
1670 *
1671 * @ib: indirect buffer to fill with commands
1672 * @src_offset: src GPU address
1673 * @dst_offset: dst GPU address
1674 * @byte_count: number of bytes to xfer
1675 * @copy_flags: copy flags for the buffers
1676 *
1677 * Copy GPU buffers using the DMA engine.
1678 * Used by the amdgpu ttm implementation to move pages if
1679 * registered as the asic copy callback.
1680 */
1681static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,
1682 uint64_t src_offset,
1683 uint64_t dst_offset,
1684 uint32_t byte_count,
1685 uint32_t copy_flags)
1686{
1687 uint32_t num_type, data_format, max_com, write_cm;
1688
1689 max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED);
1690 data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT);
1691 num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE);
1692 write_cm = AMDGPU_COPY_FLAGS_GET(copy_flags, WRITE_COMPRESS_DISABLE) ? 2 : 1;
1693
1694 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1695 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1696 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0) |
1697 SDMA_PKT_COPY_LINEAR_HEADER_CPV(1);
1698
1699 ib->ptr[ib->length_dw++] = byte_count - 1;
1700 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1701 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1702 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1703 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1704 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1705
1706 if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)))
1707 ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(data_format) | SDMA_DCC_NUM_TYPE(num_type) |
1708 ((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) |
1709 ((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(write_cm) : 0) |
1710 SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1);
1711 else
1712 ib->ptr[ib->length_dw++] = 0;
1713}
1714
1715/**
1716 * sdma_v7_0_emit_fill_buffer - fill buffer using the sDMA engine
1717 *
1718 * @ib: indirect buffer to fill
1719 * @src_data: value to write to buffer
1720 * @dst_offset: dst GPU address
1721 * @byte_count: number of bytes to xfer
1722 *
1723 * Fill GPU buffers using the DMA engine.
1724 */
1725static void sdma_v7_0_emit_fill_buffer(struct amdgpu_ib *ib,
1726 uint32_t src_data,
1727 uint64_t dst_offset,
1728 uint32_t byte_count)
1729{
1730 ib->ptr[ib->length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL) |
1731 SDMA_PKT_CONSTANT_FILL_HEADER_COMPRESS(1);
1732 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1733 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1734 ib->ptr[ib->length_dw++] = src_data;
1735 ib->ptr[ib->length_dw++] = byte_count - 1;
1736}
1737
1738static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = {
1739 .copy_max_bytes = 0x400000,
1740 .copy_num_dw = 8,
1741 .emit_copy_buffer = sdma_v7_0_emit_copy_buffer,
1742 .fill_max_bytes = 0x400000,
1743 .fill_num_dw = 5,
1744 .emit_fill_buffer = sdma_v7_0_emit_fill_buffer,
1745};
1746
1747static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev)
1748{
1749 adev->mman.buffer_funcs = &sdma_v7_0_buffer_funcs;
1750 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1751}
1752
1753static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = {
1754 .copy_pte_num_dw = 8,
1755 .copy_pte = sdma_v7_0_vm_copy_pte,
1756 .write_pte = sdma_v7_0_vm_write_pte,
1757 .set_pte_pde = sdma_v7_0_vm_set_pte_pde,
1758};
1759
1760static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1761{
1762 unsigned i;
1763
1764 adev->vm_manager.vm_pte_funcs = &sdma_v7_0_vm_pte_funcs;
1765 for (i = 0; i < adev->sdma.num_instances; i++) {
1766 adev->vm_manager.vm_pte_scheds[i] =
1767 &adev->sdma.instance[i].ring.sched;
1768 }
1769 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1770}
1771
1772const struct amdgpu_ip_block_version sdma_v7_0_ip_block = {
1773 .type = AMD_IP_BLOCK_TYPE_SDMA,
1774 .major = 7,
1775 .minor = 0,
1776 .rev = 0,
1777 .funcs = &sdma_v7_0_ip_funcs,
1778};