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1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "hdp_v5_2.h"
26
27#include "hdp/hdp_5_2_1_offset.h"
28#include "hdp/hdp_5_2_1_sh_mask.h"
29#include <uapi/linux/kfd_ioctl.h>
30
31static void hdp_v5_2_flush_hdp(struct amdgpu_device *adev,
32 struct amdgpu_ring *ring)
33{
34 if (!ring || !ring->funcs->emit_wreg) {
35 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,
36 0);
37 RREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
38 } else {
39 amdgpu_ring_emit_wreg(ring,
40 (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,
41 0);
42 }
43}
44
45static void hdp_v5_2_update_mem_power_gating(struct amdgpu_device *adev,
46 bool enable)
47{
48 uint32_t hdp_clk_cntl;
49 uint32_t hdp_mem_pwr_cntl;
50
51 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
52 AMD_CG_SUPPORT_HDP_DS |
53 AMD_CG_SUPPORT_HDP_SD)))
54 return;
55
56 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
57 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
58
59 /* Before doing clock/power mode switch, forced on MEM clock */
60 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
61 ATOMIC_MEM_CLK_SOFT_OVERRIDE, 1);
62 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
63 RC_MEM_CLK_SOFT_OVERRIDE, 1);
64 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
65
66 /* disable clock and power gating before any changing */
67 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
68 ATOMIC_MEM_POWER_CTRL_EN, 0);
69 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
70 ATOMIC_MEM_POWER_LS_EN, 0);
71 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
72 ATOMIC_MEM_POWER_DS_EN, 0);
73 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
74 ATOMIC_MEM_POWER_SD_EN, 0);
75 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
76 RC_MEM_POWER_CTRL_EN, 0);
77 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
78 RC_MEM_POWER_LS_EN, 0);
79 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
80 RC_MEM_POWER_DS_EN, 0);
81 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
82 RC_MEM_POWER_SD_EN, 0);
83 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
84
85 /* Already disabled above. The actions below are for "enabled" only */
86 if (enable) {
87 /* only one clock gating mode (LS/DS/SD) can be enabled */
88 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
89 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
90 HDP_MEM_POWER_CTRL,
91 ATOMIC_MEM_POWER_SD_EN, 1);
92 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
93 HDP_MEM_POWER_CTRL,
94 RC_MEM_POWER_SD_EN, 1);
95 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
96 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
97 HDP_MEM_POWER_CTRL,
98 ATOMIC_MEM_POWER_LS_EN, 1);
99 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
100 HDP_MEM_POWER_CTRL,
101 RC_MEM_POWER_LS_EN, 1);
102 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
103 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
104 HDP_MEM_POWER_CTRL,
105 ATOMIC_MEM_POWER_DS_EN, 1);
106 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
107 HDP_MEM_POWER_CTRL,
108 RC_MEM_POWER_DS_EN, 1);
109 }
110
111 /* confirmed that ATOMIC/RC_MEM_POWER_CTRL_EN have to be set for SRAM LS/DS/SD */
112 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
113 AMD_CG_SUPPORT_HDP_SD)) {
114 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
115 ATOMIC_MEM_POWER_CTRL_EN, 1);
116 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
117 RC_MEM_POWER_CTRL_EN, 1);
118 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
119 }
120 }
121
122 /* disable MEM clock override after clock/power mode changing */
123 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
124 ATOMIC_MEM_CLK_SOFT_OVERRIDE, 0);
125 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
126 RC_MEM_CLK_SOFT_OVERRIDE, 0);
127 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
128}
129
130static void hdp_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
131 bool enable)
132{
133 uint32_t hdp_clk_cntl;
134
135 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
136 return;
137
138 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
139
140 if (enable) {
141 hdp_clk_cntl &=
142 ~(uint32_t)
143 (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
144 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
145 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
146 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
147 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
148 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
149 } else {
150 hdp_clk_cntl |= HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
151 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
152 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
153 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
154 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
155 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
156 }
157
158 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
159}
160
161static void hdp_v5_2_get_clockgating_state(struct amdgpu_device *adev,
162 u64 *flags)
163{
164 uint32_t tmp;
165
166 /* AMD_CG_SUPPORT_HDP_MGCG */
167 tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
168 if (!(tmp & (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
169 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
170 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
171 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
172 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
173 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
174 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
175
176 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
177 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
178 if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
179 *flags |= AMD_CG_SUPPORT_HDP_LS;
180 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
181 *flags |= AMD_CG_SUPPORT_HDP_DS;
182 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
183 *flags |= AMD_CG_SUPPORT_HDP_SD;
184}
185
186static void hdp_v5_2_update_clock_gating(struct amdgpu_device *adev,
187 bool enable)
188{
189 hdp_v5_2_update_mem_power_gating(adev, enable);
190 hdp_v5_2_update_medium_grain_clock_gating(adev, enable);
191}
192
193const struct amdgpu_hdp_funcs hdp_v5_2_funcs = {
194 .flush_hdp = hdp_v5_2_flush_hdp,
195 .update_clock_gating = hdp_v5_2_update_clock_gating,
196 .get_clock_gating_state = hdp_v5_2_get_clockgating_state,
197};