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1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32
33#include <linux/dma-mapping.h>
34#include <linux/iommu.h>
35#include <linux/hmm.h>
36#include <linux/pagemap.h>
37#include <linux/sched/task.h>
38#include <linux/sched/mm.h>
39#include <linux/seq_file.h>
40#include <linux/slab.h>
41#include <linux/swap.h>
42#include <linux/swiotlb.h>
43#include <linux/dma-buf.h>
44#include <linux/sizes.h>
45
46#include <drm/ttm/ttm_bo_api.h>
47#include <drm/ttm/ttm_bo_driver.h>
48#include <drm/ttm/ttm_placement.h>
49#include <drm/ttm/ttm_module.h>
50#include <drm/ttm/ttm_page_alloc.h>
51
52#include <drm/drm_debugfs.h>
53#include <drm/amdgpu_drm.h>
54
55#include "amdgpu.h"
56#include "amdgpu_object.h"
57#include "amdgpu_trace.h"
58#include "amdgpu_amdkfd.h"
59#include "amdgpu_sdma.h"
60#include "amdgpu_ras.h"
61#include "amdgpu_atomfirmware.h"
62#include "bif/bif_4_1_d.h"
63
64#define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128
65
66
67/**
68 * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
69 * memory request.
70 *
71 * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
72 * @type: The type of memory requested
73 * @man: The memory type manager for each domain
74 *
75 * This is called by ttm_bo_init_mm() when a buffer object is being
76 * initialized.
77 */
78static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
79 struct ttm_mem_type_manager *man)
80{
81 struct amdgpu_device *adev;
82
83 adev = amdgpu_ttm_adev(bdev);
84
85 switch (type) {
86 case TTM_PL_SYSTEM:
87 /* System memory */
88 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
89 man->available_caching = TTM_PL_MASK_CACHING;
90 man->default_caching = TTM_PL_FLAG_CACHED;
91 break;
92 case TTM_PL_TT:
93 /* GTT memory */
94 man->func = &amdgpu_gtt_mgr_func;
95 man->available_caching = TTM_PL_MASK_CACHING;
96 man->default_caching = TTM_PL_FLAG_CACHED;
97 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
98 break;
99 case TTM_PL_VRAM:
100 /* "On-card" video ram */
101 man->func = &amdgpu_vram_mgr_func;
102 man->flags = TTM_MEMTYPE_FLAG_FIXED |
103 TTM_MEMTYPE_FLAG_MAPPABLE;
104 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
105 man->default_caching = TTM_PL_FLAG_WC;
106 break;
107 case AMDGPU_PL_GDS:
108 case AMDGPU_PL_GWS:
109 case AMDGPU_PL_OA:
110 /* On-chip GDS memory*/
111 man->func = &ttm_bo_manager_func;
112 man->flags = TTM_MEMTYPE_FLAG_FIXED;
113 man->available_caching = TTM_PL_FLAG_UNCACHED;
114 man->default_caching = TTM_PL_FLAG_UNCACHED;
115 break;
116 default:
117 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
118 return -EINVAL;
119 }
120 return 0;
121}
122
123/**
124 * amdgpu_evict_flags - Compute placement flags
125 *
126 * @bo: The buffer object to evict
127 * @placement: Possible destination(s) for evicted BO
128 *
129 * Fill in placement data when ttm_bo_evict() is called
130 */
131static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
132 struct ttm_placement *placement)
133{
134 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
135 struct amdgpu_bo *abo;
136 static const struct ttm_place placements = {
137 .fpfn = 0,
138 .lpfn = 0,
139 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
140 };
141
142 /* Don't handle scatter gather BOs */
143 if (bo->type == ttm_bo_type_sg) {
144 placement->num_placement = 0;
145 placement->num_busy_placement = 0;
146 return;
147 }
148
149 /* Object isn't an AMDGPU object so ignore */
150 if (!amdgpu_bo_is_amdgpu_bo(bo)) {
151 placement->placement = &placements;
152 placement->busy_placement = &placements;
153 placement->num_placement = 1;
154 placement->num_busy_placement = 1;
155 return;
156 }
157
158 abo = ttm_to_amdgpu_bo(bo);
159 switch (bo->mem.mem_type) {
160 case AMDGPU_PL_GDS:
161 case AMDGPU_PL_GWS:
162 case AMDGPU_PL_OA:
163 placement->num_placement = 0;
164 placement->num_busy_placement = 0;
165 return;
166
167 case TTM_PL_VRAM:
168 if (!adev->mman.buffer_funcs_enabled) {
169 /* Move to system memory */
170 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
171 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
172 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
173 amdgpu_bo_in_cpu_visible_vram(abo)) {
174
175 /* Try evicting to the CPU inaccessible part of VRAM
176 * first, but only set GTT as busy placement, so this
177 * BO will be evicted to GTT rather than causing other
178 * BOs to be evicted from VRAM
179 */
180 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
181 AMDGPU_GEM_DOMAIN_GTT);
182 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
183 abo->placements[0].lpfn = 0;
184 abo->placement.busy_placement = &abo->placements[1];
185 abo->placement.num_busy_placement = 1;
186 } else {
187 /* Move to GTT memory */
188 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
189 }
190 break;
191 case TTM_PL_TT:
192 default:
193 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
194 break;
195 }
196 *placement = abo->placement;
197}
198
199/**
200 * amdgpu_verify_access - Verify access for a mmap call
201 *
202 * @bo: The buffer object to map
203 * @filp: The file pointer from the process performing the mmap
204 *
205 * This is called by ttm_bo_mmap() to verify whether a process
206 * has the right to mmap a BO to their process space.
207 */
208static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
209{
210 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
211
212 /*
213 * Don't verify access for KFD BOs. They don't have a GEM
214 * object associated with them.
215 */
216 if (abo->kfd_bo)
217 return 0;
218
219 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
220 return -EPERM;
221 return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
222 filp->private_data);
223}
224
225/**
226 * amdgpu_move_null - Register memory for a buffer object
227 *
228 * @bo: The bo to assign the memory to
229 * @new_mem: The memory to be assigned.
230 *
231 * Assign the memory from new_mem to the memory of the buffer object bo.
232 */
233static void amdgpu_move_null(struct ttm_buffer_object *bo,
234 struct ttm_mem_reg *new_mem)
235{
236 struct ttm_mem_reg *old_mem = &bo->mem;
237
238 BUG_ON(old_mem->mm_node != NULL);
239 *old_mem = *new_mem;
240 new_mem->mm_node = NULL;
241}
242
243/**
244 * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
245 *
246 * @bo: The bo to assign the memory to.
247 * @mm_node: Memory manager node for drm allocator.
248 * @mem: The region where the bo resides.
249 *
250 */
251static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
252 struct drm_mm_node *mm_node,
253 struct ttm_mem_reg *mem)
254{
255 uint64_t addr = 0;
256
257 if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
258 addr = mm_node->start << PAGE_SHIFT;
259 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
260 mem->mem_type);
261 }
262 return addr;
263}
264
265/**
266 * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
267 * @offset. It also modifies the offset to be within the drm_mm_node returned
268 *
269 * @mem: The region where the bo resides.
270 * @offset: The offset that drm_mm_node is used for finding.
271 *
272 */
273static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
274 uint64_t *offset)
275{
276 struct drm_mm_node *mm_node = mem->mm_node;
277
278 while (*offset >= (mm_node->size << PAGE_SHIFT)) {
279 *offset -= (mm_node->size << PAGE_SHIFT);
280 ++mm_node;
281 }
282 return mm_node;
283}
284
285/**
286 * amdgpu_ttm_map_buffer - Map memory into the GART windows
287 * @bo: buffer object to map
288 * @mem: memory object to map
289 * @mm_node: drm_mm node object to map
290 * @num_pages: number of pages to map
291 * @offset: offset into @mm_node where to start
292 * @window: which GART window to use
293 * @ring: DMA ring to use for the copy
294 * @tmz: if we should setup a TMZ enabled mapping
295 * @addr: resulting address inside the MC address space
296 *
297 * Setup one of the GART windows to access a specific piece of memory or return
298 * the physical address for local memory.
299 */
300static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
301 struct ttm_mem_reg *mem,
302 struct drm_mm_node *mm_node,
303 unsigned num_pages, uint64_t offset,
304 unsigned window, struct amdgpu_ring *ring,
305 bool tmz, uint64_t *addr)
306{
307 struct amdgpu_device *adev = ring->adev;
308 struct amdgpu_job *job;
309 unsigned num_dw, num_bytes;
310 struct dma_fence *fence;
311 uint64_t src_addr, dst_addr;
312 void *cpu_addr;
313 uint64_t flags;
314 unsigned int i;
315 int r;
316
317 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
318 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
319
320 /* Map only what can't be accessed directly */
321 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
322 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
323 return 0;
324 }
325
326 *addr = adev->gmc.gart_start;
327 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
328 AMDGPU_GPU_PAGE_SIZE;
329 *addr += offset & ~PAGE_MASK;
330
331 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
332 num_bytes = num_pages * 8;
333
334 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
335 AMDGPU_IB_POOL_DELAYED, &job);
336 if (r)
337 return r;
338
339 src_addr = num_dw * 4;
340 src_addr += job->ibs[0].gpu_addr;
341
342 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
343 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
344 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
345 dst_addr, num_bytes, false);
346
347 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
348 WARN_ON(job->ibs[0].length_dw > num_dw);
349
350 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
351 if (tmz)
352 flags |= AMDGPU_PTE_TMZ;
353
354 cpu_addr = &job->ibs[0].ptr[num_dw];
355
356 if (mem->mem_type == TTM_PL_TT) {
357 struct ttm_dma_tt *dma;
358 dma_addr_t *dma_address;
359
360 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
361 dma_address = &dma->dma_address[offset >> PAGE_SHIFT];
362 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
363 cpu_addr);
364 if (r)
365 goto error_free;
366 } else {
367 dma_addr_t dma_address;
368
369 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
370 dma_address += adev->vm_manager.vram_base_offset;
371
372 for (i = 0; i < num_pages; ++i) {
373 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
374 &dma_address, flags, cpu_addr);
375 if (r)
376 goto error_free;
377
378 dma_address += PAGE_SIZE;
379 }
380 }
381
382 r = amdgpu_job_submit(job, &adev->mman.entity,
383 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
384 if (r)
385 goto error_free;
386
387 dma_fence_put(fence);
388
389 return r;
390
391error_free:
392 amdgpu_job_free(job);
393 return r;
394}
395
396/**
397 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
398 * @adev: amdgpu device
399 * @src: buffer/address where to read from
400 * @dst: buffer/address where to write to
401 * @size: number of bytes to copy
402 * @tmz: if a secure copy should be used
403 * @resv: resv object to sync to
404 * @f: Returns the last fence if multiple jobs are submitted.
405 *
406 * The function copies @size bytes from {src->mem + src->offset} to
407 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
408 * move and different for a BO to BO copy.
409 *
410 */
411int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
412 const struct amdgpu_copy_mem *src,
413 const struct amdgpu_copy_mem *dst,
414 uint64_t size, bool tmz,
415 struct dma_resv *resv,
416 struct dma_fence **f)
417{
418 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
419 AMDGPU_GPU_PAGE_SIZE);
420
421 uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
422 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
423 struct drm_mm_node *src_mm, *dst_mm;
424 struct dma_fence *fence = NULL;
425 int r = 0;
426
427 if (!adev->mman.buffer_funcs_enabled) {
428 DRM_ERROR("Trying to move memory with ring turned off.\n");
429 return -EINVAL;
430 }
431
432 src_offset = src->offset;
433 if (src->mem->mm_node) {
434 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
435 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
436 } else {
437 src_mm = NULL;
438 src_node_size = ULLONG_MAX;
439 }
440
441 dst_offset = dst->offset;
442 if (dst->mem->mm_node) {
443 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
444 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
445 } else {
446 dst_mm = NULL;
447 dst_node_size = ULLONG_MAX;
448 }
449
450 mutex_lock(&adev->mman.gtt_window_lock);
451
452 while (size) {
453 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
454 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
455 struct dma_fence *next;
456 uint32_t cur_size;
457 uint64_t from, to;
458
459 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
460 * begins at an offset, then adjust the size accordingly
461 */
462 cur_size = max(src_page_offset, dst_page_offset);
463 cur_size = min(min3(src_node_size, dst_node_size, size),
464 (uint64_t)(GTT_MAX_BYTES - cur_size));
465
466 /* Map src to window 0 and dst to window 1. */
467 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
468 PFN_UP(cur_size + src_page_offset),
469 src_offset, 0, ring, tmz, &from);
470 if (r)
471 goto error;
472
473 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
474 PFN_UP(cur_size + dst_page_offset),
475 dst_offset, 1, ring, tmz, &to);
476 if (r)
477 goto error;
478
479 r = amdgpu_copy_buffer(ring, from, to, cur_size,
480 resv, &next, false, true, tmz);
481 if (r)
482 goto error;
483
484 dma_fence_put(fence);
485 fence = next;
486
487 size -= cur_size;
488 if (!size)
489 break;
490
491 src_node_size -= cur_size;
492 if (!src_node_size) {
493 ++src_mm;
494 src_node_size = src_mm->size << PAGE_SHIFT;
495 src_offset = 0;
496 } else {
497 src_offset += cur_size;
498 }
499
500 dst_node_size -= cur_size;
501 if (!dst_node_size) {
502 ++dst_mm;
503 dst_node_size = dst_mm->size << PAGE_SHIFT;
504 dst_offset = 0;
505 } else {
506 dst_offset += cur_size;
507 }
508 }
509error:
510 mutex_unlock(&adev->mman.gtt_window_lock);
511 if (f)
512 *f = dma_fence_get(fence);
513 dma_fence_put(fence);
514 return r;
515}
516
517/**
518 * amdgpu_move_blit - Copy an entire buffer to another buffer
519 *
520 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
521 * help move buffers to and from VRAM.
522 */
523static int amdgpu_move_blit(struct ttm_buffer_object *bo,
524 bool evict, bool no_wait_gpu,
525 struct ttm_mem_reg *new_mem,
526 struct ttm_mem_reg *old_mem)
527{
528 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
529 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
530 struct amdgpu_copy_mem src, dst;
531 struct dma_fence *fence = NULL;
532 int r;
533
534 src.bo = bo;
535 dst.bo = bo;
536 src.mem = old_mem;
537 dst.mem = new_mem;
538 src.offset = 0;
539 dst.offset = 0;
540
541 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
542 new_mem->num_pages << PAGE_SHIFT,
543 amdgpu_bo_encrypted(abo),
544 bo->base.resv, &fence);
545 if (r)
546 goto error;
547
548 /* clear the space being freed */
549 if (old_mem->mem_type == TTM_PL_VRAM &&
550 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
551 struct dma_fence *wipe_fence = NULL;
552
553 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
554 NULL, &wipe_fence);
555 if (r) {
556 goto error;
557 } else if (wipe_fence) {
558 dma_fence_put(fence);
559 fence = wipe_fence;
560 }
561 }
562
563 /* Always block for VM page tables before committing the new location */
564 if (bo->type == ttm_bo_type_kernel)
565 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
566 else
567 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
568 dma_fence_put(fence);
569 return r;
570
571error:
572 if (fence)
573 dma_fence_wait(fence, false);
574 dma_fence_put(fence);
575 return r;
576}
577
578/**
579 * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
580 *
581 * Called by amdgpu_bo_move().
582 */
583static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
584 struct ttm_operation_ctx *ctx,
585 struct ttm_mem_reg *new_mem)
586{
587 struct ttm_mem_reg *old_mem = &bo->mem;
588 struct ttm_mem_reg tmp_mem;
589 struct ttm_place placements;
590 struct ttm_placement placement;
591 int r;
592
593 /* create space/pages for new_mem in GTT space */
594 tmp_mem = *new_mem;
595 tmp_mem.mm_node = NULL;
596 placement.num_placement = 1;
597 placement.placement = &placements;
598 placement.num_busy_placement = 1;
599 placement.busy_placement = &placements;
600 placements.fpfn = 0;
601 placements.lpfn = 0;
602 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
603 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
604 if (unlikely(r)) {
605 pr_err("Failed to find GTT space for blit from VRAM\n");
606 return r;
607 }
608
609 /* set caching flags */
610 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
611 if (unlikely(r)) {
612 goto out_cleanup;
613 }
614
615 /* Bind the memory to the GTT space */
616 r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
617 if (unlikely(r)) {
618 goto out_cleanup;
619 }
620
621 /* blit VRAM to GTT */
622 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
623 if (unlikely(r)) {
624 goto out_cleanup;
625 }
626
627 /* move BO (in tmp_mem) to new_mem */
628 r = ttm_bo_move_ttm(bo, ctx, new_mem);
629out_cleanup:
630 ttm_bo_mem_put(bo, &tmp_mem);
631 return r;
632}
633
634/**
635 * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
636 *
637 * Called by amdgpu_bo_move().
638 */
639static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
640 struct ttm_operation_ctx *ctx,
641 struct ttm_mem_reg *new_mem)
642{
643 struct ttm_mem_reg *old_mem = &bo->mem;
644 struct ttm_mem_reg tmp_mem;
645 struct ttm_placement placement;
646 struct ttm_place placements;
647 int r;
648
649 /* make space in GTT for old_mem buffer */
650 tmp_mem = *new_mem;
651 tmp_mem.mm_node = NULL;
652 placement.num_placement = 1;
653 placement.placement = &placements;
654 placement.num_busy_placement = 1;
655 placement.busy_placement = &placements;
656 placements.fpfn = 0;
657 placements.lpfn = 0;
658 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
659 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
660 if (unlikely(r)) {
661 pr_err("Failed to find GTT space for blit to VRAM\n");
662 return r;
663 }
664
665 /* move/bind old memory to GTT space */
666 r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
667 if (unlikely(r)) {
668 goto out_cleanup;
669 }
670
671 /* copy to VRAM */
672 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
673 if (unlikely(r)) {
674 goto out_cleanup;
675 }
676out_cleanup:
677 ttm_bo_mem_put(bo, &tmp_mem);
678 return r;
679}
680
681/**
682 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
683 *
684 * Called by amdgpu_bo_move()
685 */
686static bool amdgpu_mem_visible(struct amdgpu_device *adev,
687 struct ttm_mem_reg *mem)
688{
689 struct drm_mm_node *nodes = mem->mm_node;
690
691 if (mem->mem_type == TTM_PL_SYSTEM ||
692 mem->mem_type == TTM_PL_TT)
693 return true;
694 if (mem->mem_type != TTM_PL_VRAM)
695 return false;
696
697 /* ttm_mem_reg_ioremap only supports contiguous memory */
698 if (nodes->size != mem->num_pages)
699 return false;
700
701 return ((nodes->start + nodes->size) << PAGE_SHIFT)
702 <= adev->gmc.visible_vram_size;
703}
704
705/**
706 * amdgpu_bo_move - Move a buffer object to a new memory location
707 *
708 * Called by ttm_bo_handle_move_mem()
709 */
710static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
711 struct ttm_operation_ctx *ctx,
712 struct ttm_mem_reg *new_mem)
713{
714 struct amdgpu_device *adev;
715 struct amdgpu_bo *abo;
716 struct ttm_mem_reg *old_mem = &bo->mem;
717 int r;
718
719 /* Can't move a pinned BO */
720 abo = ttm_to_amdgpu_bo(bo);
721 if (WARN_ON_ONCE(abo->pin_count > 0))
722 return -EINVAL;
723
724 adev = amdgpu_ttm_adev(bo->bdev);
725
726 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
727 amdgpu_move_null(bo, new_mem);
728 return 0;
729 }
730 if ((old_mem->mem_type == TTM_PL_TT &&
731 new_mem->mem_type == TTM_PL_SYSTEM) ||
732 (old_mem->mem_type == TTM_PL_SYSTEM &&
733 new_mem->mem_type == TTM_PL_TT)) {
734 /* bind is enough */
735 amdgpu_move_null(bo, new_mem);
736 return 0;
737 }
738 if (old_mem->mem_type == AMDGPU_PL_GDS ||
739 old_mem->mem_type == AMDGPU_PL_GWS ||
740 old_mem->mem_type == AMDGPU_PL_OA ||
741 new_mem->mem_type == AMDGPU_PL_GDS ||
742 new_mem->mem_type == AMDGPU_PL_GWS ||
743 new_mem->mem_type == AMDGPU_PL_OA) {
744 /* Nothing to save here */
745 amdgpu_move_null(bo, new_mem);
746 return 0;
747 }
748
749 if (!adev->mman.buffer_funcs_enabled) {
750 r = -ENODEV;
751 goto memcpy;
752 }
753
754 if (old_mem->mem_type == TTM_PL_VRAM &&
755 new_mem->mem_type == TTM_PL_SYSTEM) {
756 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
757 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
758 new_mem->mem_type == TTM_PL_VRAM) {
759 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
760 } else {
761 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
762 new_mem, old_mem);
763 }
764
765 if (r) {
766memcpy:
767 /* Check that all memory is CPU accessible */
768 if (!amdgpu_mem_visible(adev, old_mem) ||
769 !amdgpu_mem_visible(adev, new_mem)) {
770 pr_err("Move buffer fallback to memcpy unavailable\n");
771 return r;
772 }
773
774 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
775 if (r)
776 return r;
777 }
778
779 if (bo->type == ttm_bo_type_device &&
780 new_mem->mem_type == TTM_PL_VRAM &&
781 old_mem->mem_type != TTM_PL_VRAM) {
782 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
783 * accesses the BO after it's moved.
784 */
785 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
786 }
787
788 /* update statistics */
789 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
790 return 0;
791}
792
793/**
794 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
795 *
796 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
797 */
798static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
799{
800 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
801 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
802 struct drm_mm_node *mm_node = mem->mm_node;
803
804 mem->bus.addr = NULL;
805 mem->bus.offset = 0;
806 mem->bus.size = mem->num_pages << PAGE_SHIFT;
807 mem->bus.base = 0;
808 mem->bus.is_iomem = false;
809 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
810 return -EINVAL;
811 switch (mem->mem_type) {
812 case TTM_PL_SYSTEM:
813 /* system memory */
814 return 0;
815 case TTM_PL_TT:
816 break;
817 case TTM_PL_VRAM:
818 mem->bus.offset = mem->start << PAGE_SHIFT;
819 /* check if it's visible */
820 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
821 return -EINVAL;
822 /* Only physically contiguous buffers apply. In a contiguous
823 * buffer, size of the first mm_node would match the number of
824 * pages in ttm_mem_reg.
825 */
826 if (adev->mman.aper_base_kaddr &&
827 (mm_node->size == mem->num_pages))
828 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
829 mem->bus.offset;
830
831 mem->bus.base = adev->gmc.aper_base;
832 mem->bus.is_iomem = true;
833 break;
834 default:
835 return -EINVAL;
836 }
837 return 0;
838}
839
840static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
841 unsigned long page_offset)
842{
843 uint64_t offset = (page_offset << PAGE_SHIFT);
844 struct drm_mm_node *mm;
845
846 mm = amdgpu_find_mm_node(&bo->mem, &offset);
847 return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
848 (offset >> PAGE_SHIFT);
849}
850
851/**
852 * amdgpu_ttm_domain_start - Returns GPU start address
853 * @adev: amdgpu device object
854 * @type: type of the memory
855 *
856 * Returns:
857 * GPU start address of a memory domain
858 */
859
860uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
861{
862 switch (type) {
863 case TTM_PL_TT:
864 return adev->gmc.gart_start;
865 case TTM_PL_VRAM:
866 return adev->gmc.vram_start;
867 }
868
869 return 0;
870}
871
872/*
873 * TTM backend functions.
874 */
875struct amdgpu_ttm_tt {
876 struct ttm_dma_tt ttm;
877 struct drm_gem_object *gobj;
878 u64 offset;
879 uint64_t userptr;
880 struct task_struct *usertask;
881 uint32_t userflags;
882#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
883 struct hmm_range *range;
884#endif
885};
886
887#ifdef CONFIG_DRM_AMDGPU_USERPTR
888/**
889 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
890 * memory and start HMM tracking CPU page table update
891 *
892 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
893 * once afterwards to stop HMM tracking
894 */
895int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
896{
897 struct ttm_tt *ttm = bo->tbo.ttm;
898 struct amdgpu_ttm_tt *gtt = (void *)ttm;
899 unsigned long start = gtt->userptr;
900 struct vm_area_struct *vma;
901 struct hmm_range *range;
902 unsigned long timeout;
903 struct mm_struct *mm;
904 unsigned long i;
905 int r = 0;
906
907 mm = bo->notifier.mm;
908 if (unlikely(!mm)) {
909 DRM_DEBUG_DRIVER("BO is not registered?\n");
910 return -EFAULT;
911 }
912
913 /* Another get_user_pages is running at the same time?? */
914 if (WARN_ON(gtt->range))
915 return -EFAULT;
916
917 if (!mmget_not_zero(mm)) /* Happens during process shutdown */
918 return -ESRCH;
919
920 range = kzalloc(sizeof(*range), GFP_KERNEL);
921 if (unlikely(!range)) {
922 r = -ENOMEM;
923 goto out;
924 }
925 range->notifier = &bo->notifier;
926 range->start = bo->notifier.interval_tree.start;
927 range->end = bo->notifier.interval_tree.last + 1;
928 range->default_flags = HMM_PFN_REQ_FAULT;
929 if (!amdgpu_ttm_tt_is_readonly(ttm))
930 range->default_flags |= HMM_PFN_REQ_WRITE;
931
932 range->hmm_pfns = kvmalloc_array(ttm->num_pages,
933 sizeof(*range->hmm_pfns), GFP_KERNEL);
934 if (unlikely(!range->hmm_pfns)) {
935 r = -ENOMEM;
936 goto out_free_ranges;
937 }
938
939 mmap_read_lock(mm);
940 vma = find_vma(mm, start);
941 if (unlikely(!vma || start < vma->vm_start)) {
942 r = -EFAULT;
943 goto out_unlock;
944 }
945 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
946 vma->vm_file)) {
947 r = -EPERM;
948 goto out_unlock;
949 }
950 mmap_read_unlock(mm);
951 timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
952
953retry:
954 range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
955
956 mmap_read_lock(mm);
957 r = hmm_range_fault(range);
958 mmap_read_unlock(mm);
959 if (unlikely(r)) {
960 /*
961 * FIXME: This timeout should encompass the retry from
962 * mmu_interval_read_retry() as well.
963 */
964 if (r == -EBUSY && !time_after(jiffies, timeout))
965 goto retry;
966 goto out_free_pfns;
967 }
968
969 /*
970 * Due to default_flags, all pages are HMM_PFN_VALID or
971 * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
972 * the notifier_lock, and mmu_interval_read_retry() must be done first.
973 */
974 for (i = 0; i < ttm->num_pages; i++)
975 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
976
977 gtt->range = range;
978 mmput(mm);
979
980 return 0;
981
982out_unlock:
983 mmap_read_unlock(mm);
984out_free_pfns:
985 kvfree(range->hmm_pfns);
986out_free_ranges:
987 kfree(range);
988out:
989 mmput(mm);
990 return r;
991}
992
993/**
994 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
995 * Check if the pages backing this ttm range have been invalidated
996 *
997 * Returns: true if pages are still valid
998 */
999bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
1000{
1001 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1002 bool r = false;
1003
1004 if (!gtt || !gtt->userptr)
1005 return false;
1006
1007 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
1008 gtt->userptr, ttm->num_pages);
1009
1010 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
1011 "No user pages to check\n");
1012
1013 if (gtt->range) {
1014 /*
1015 * FIXME: Must always hold notifier_lock for this, and must
1016 * not ignore the return code.
1017 */
1018 r = mmu_interval_read_retry(gtt->range->notifier,
1019 gtt->range->notifier_seq);
1020 kvfree(gtt->range->hmm_pfns);
1021 kfree(gtt->range);
1022 gtt->range = NULL;
1023 }
1024
1025 return !r;
1026}
1027#endif
1028
1029/**
1030 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
1031 *
1032 * Called by amdgpu_cs_list_validate(). This creates the page list
1033 * that backs user memory and will ultimately be mapped into the device
1034 * address space.
1035 */
1036void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
1037{
1038 unsigned long i;
1039
1040 for (i = 0; i < ttm->num_pages; ++i)
1041 ttm->pages[i] = pages ? pages[i] : NULL;
1042}
1043
1044/**
1045 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
1046 *
1047 * Called by amdgpu_ttm_backend_bind()
1048 **/
1049static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
1050{
1051 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1052 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1053 int r;
1054
1055 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1056 enum dma_data_direction direction = write ?
1057 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1058
1059 /* Allocate an SG array and squash pages into it */
1060 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
1061 ttm->num_pages << PAGE_SHIFT,
1062 GFP_KERNEL);
1063 if (r)
1064 goto release_sg;
1065
1066 /* Map SG to device */
1067 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
1068 if (r)
1069 goto release_sg;
1070
1071 /* convert SG to linear array of pages and dma addresses */
1072 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1073 gtt->ttm.dma_address, ttm->num_pages);
1074
1075 return 0;
1076
1077release_sg:
1078 kfree(ttm->sg);
1079 ttm->sg = NULL;
1080 return r;
1081}
1082
1083/**
1084 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1085 */
1086static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
1087{
1088 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1089 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1090
1091 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1092 enum dma_data_direction direction = write ?
1093 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1094
1095 /* double check that we don't free the table twice */
1096 if (!ttm->sg->sgl)
1097 return;
1098
1099 /* unmap the pages mapped to the device */
1100 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
1101 sg_free_table(ttm->sg);
1102
1103#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1104 if (gtt->range) {
1105 unsigned long i;
1106
1107 for (i = 0; i < ttm->num_pages; i++) {
1108 if (ttm->pages[i] !=
1109 hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
1110 break;
1111 }
1112
1113 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1114 }
1115#endif
1116}
1117
1118static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1119 struct ttm_buffer_object *tbo,
1120 uint64_t flags)
1121{
1122 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1123 struct ttm_tt *ttm = tbo->ttm;
1124 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1125 int r;
1126
1127 if (amdgpu_bo_encrypted(abo))
1128 flags |= AMDGPU_PTE_TMZ;
1129
1130 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1131 uint64_t page_idx = 1;
1132
1133 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1134 ttm->pages, gtt->ttm.dma_address, flags);
1135 if (r)
1136 goto gart_bind_fail;
1137
1138 /* The memory type of the first page defaults to UC. Now
1139 * modify the memory type to NC from the second page of
1140 * the BO onward.
1141 */
1142 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1143 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1144
1145 r = amdgpu_gart_bind(adev,
1146 gtt->offset + (page_idx << PAGE_SHIFT),
1147 ttm->num_pages - page_idx,
1148 &ttm->pages[page_idx],
1149 &(gtt->ttm.dma_address[page_idx]), flags);
1150 } else {
1151 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1152 ttm->pages, gtt->ttm.dma_address, flags);
1153 }
1154
1155gart_bind_fail:
1156 if (r)
1157 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1158 ttm->num_pages, gtt->offset);
1159
1160 return r;
1161}
1162
1163/**
1164 * amdgpu_ttm_backend_bind - Bind GTT memory
1165 *
1166 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1167 * This handles binding GTT memory to the device address space.
1168 */
1169static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1170 struct ttm_mem_reg *bo_mem)
1171{
1172 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1173 struct amdgpu_ttm_tt *gtt = (void*)ttm;
1174 uint64_t flags;
1175 int r = 0;
1176
1177 if (gtt->userptr) {
1178 r = amdgpu_ttm_tt_pin_userptr(ttm);
1179 if (r) {
1180 DRM_ERROR("failed to pin userptr\n");
1181 return r;
1182 }
1183 }
1184 if (!ttm->num_pages) {
1185 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1186 ttm->num_pages, bo_mem, ttm);
1187 }
1188
1189 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1190 bo_mem->mem_type == AMDGPU_PL_GWS ||
1191 bo_mem->mem_type == AMDGPU_PL_OA)
1192 return -EINVAL;
1193
1194 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1195 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1196 return 0;
1197 }
1198
1199 /* compute PTE flags relevant to this BO memory */
1200 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1201
1202 /* bind pages into GART page tables */
1203 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1204 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1205 ttm->pages, gtt->ttm.dma_address, flags);
1206
1207 if (r)
1208 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1209 ttm->num_pages, gtt->offset);
1210 return r;
1211}
1212
1213/**
1214 * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1215 */
1216int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1217{
1218 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1219 struct ttm_operation_ctx ctx = { false, false };
1220 struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1221 struct ttm_mem_reg tmp;
1222 struct ttm_placement placement;
1223 struct ttm_place placements;
1224 uint64_t addr, flags;
1225 int r;
1226
1227 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1228 return 0;
1229
1230 addr = amdgpu_gmc_agp_addr(bo);
1231 if (addr != AMDGPU_BO_INVALID_OFFSET) {
1232 bo->mem.start = addr >> PAGE_SHIFT;
1233 } else {
1234
1235 /* allocate GART space */
1236 tmp = bo->mem;
1237 tmp.mm_node = NULL;
1238 placement.num_placement = 1;
1239 placement.placement = &placements;
1240 placement.num_busy_placement = 1;
1241 placement.busy_placement = &placements;
1242 placements.fpfn = 0;
1243 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1244 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1245 TTM_PL_FLAG_TT;
1246
1247 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1248 if (unlikely(r))
1249 return r;
1250
1251 /* compute PTE flags for this buffer object */
1252 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1253
1254 /* Bind pages */
1255 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1256 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1257 if (unlikely(r)) {
1258 ttm_bo_mem_put(bo, &tmp);
1259 return r;
1260 }
1261
1262 ttm_bo_mem_put(bo, &bo->mem);
1263 bo->mem = tmp;
1264 }
1265
1266 return 0;
1267}
1268
1269/**
1270 * amdgpu_ttm_recover_gart - Rebind GTT pages
1271 *
1272 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1273 * rebind GTT pages during a GPU reset.
1274 */
1275int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1276{
1277 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1278 uint64_t flags;
1279 int r;
1280
1281 if (!tbo->ttm)
1282 return 0;
1283
1284 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1285 r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1286
1287 return r;
1288}
1289
1290/**
1291 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1292 *
1293 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1294 * ttm_tt_destroy().
1295 */
1296static void amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1297{
1298 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1299 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1300 int r;
1301
1302 /* if the pages have userptr pinning then clear that first */
1303 if (gtt->userptr)
1304 amdgpu_ttm_tt_unpin_userptr(ttm);
1305
1306 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1307 return;
1308
1309 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1310 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1311 if (r)
1312 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1313 gtt->ttm.ttm.num_pages, gtt->offset);
1314}
1315
1316static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1317{
1318 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1319
1320 if (gtt->usertask)
1321 put_task_struct(gtt->usertask);
1322
1323 ttm_dma_tt_fini(>t->ttm);
1324 kfree(gtt);
1325}
1326
1327static struct ttm_backend_func amdgpu_backend_func = {
1328 .bind = &amdgpu_ttm_backend_bind,
1329 .unbind = &amdgpu_ttm_backend_unbind,
1330 .destroy = &amdgpu_ttm_backend_destroy,
1331};
1332
1333/**
1334 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1335 *
1336 * @bo: The buffer object to create a GTT ttm_tt object around
1337 *
1338 * Called by ttm_tt_create().
1339 */
1340static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1341 uint32_t page_flags)
1342{
1343 struct amdgpu_ttm_tt *gtt;
1344
1345 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1346 if (gtt == NULL) {
1347 return NULL;
1348 }
1349 gtt->ttm.ttm.func = &amdgpu_backend_func;
1350 gtt->gobj = &bo->base;
1351
1352 /* allocate space for the uninitialized page entries */
1353 if (ttm_sg_tt_init(>t->ttm, bo, page_flags)) {
1354 kfree(gtt);
1355 return NULL;
1356 }
1357 return >t->ttm.ttm;
1358}
1359
1360/**
1361 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1362 *
1363 * Map the pages of a ttm_tt object to an address space visible
1364 * to the underlying device.
1365 */
1366static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1367 struct ttm_operation_ctx *ctx)
1368{
1369 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1370 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1371
1372 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1373 if (gtt && gtt->userptr) {
1374 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1375 if (!ttm->sg)
1376 return -ENOMEM;
1377
1378 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1379 ttm->state = tt_unbound;
1380 return 0;
1381 }
1382
1383 if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1384 if (!ttm->sg) {
1385 struct dma_buf_attachment *attach;
1386 struct sg_table *sgt;
1387
1388 attach = gtt->gobj->import_attach;
1389 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1390 if (IS_ERR(sgt))
1391 return PTR_ERR(sgt);
1392
1393 ttm->sg = sgt;
1394 }
1395
1396 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1397 gtt->ttm.dma_address,
1398 ttm->num_pages);
1399 ttm->state = tt_unbound;
1400 return 0;
1401 }
1402
1403#ifdef CONFIG_SWIOTLB
1404 if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1405 return ttm_dma_populate(>t->ttm, adev->dev, ctx);
1406 }
1407#endif
1408
1409 /* fall back to generic helper to populate the page array
1410 * and map them to the device */
1411 return ttm_populate_and_map_pages(adev->dev, >t->ttm, ctx);
1412}
1413
1414/**
1415 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1416 *
1417 * Unmaps pages of a ttm_tt object from the device address space and
1418 * unpopulates the page array backing it.
1419 */
1420static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1421{
1422 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1423 struct amdgpu_device *adev;
1424
1425 if (gtt && gtt->userptr) {
1426 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1427 kfree(ttm->sg);
1428 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1429 return;
1430 }
1431
1432 if (ttm->sg && gtt->gobj->import_attach) {
1433 struct dma_buf_attachment *attach;
1434
1435 attach = gtt->gobj->import_attach;
1436 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1437 ttm->sg = NULL;
1438 return;
1439 }
1440
1441 if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1442 return;
1443
1444 adev = amdgpu_ttm_adev(ttm->bdev);
1445
1446#ifdef CONFIG_SWIOTLB
1447 if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1448 ttm_dma_unpopulate(>t->ttm, adev->dev);
1449 return;
1450 }
1451#endif
1452
1453 /* fall back to generic helper to unmap and unpopulate array */
1454 ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm);
1455}
1456
1457/**
1458 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1459 * task
1460 *
1461 * @ttm: The ttm_tt object to bind this userptr object to
1462 * @addr: The address in the current tasks VM space to use
1463 * @flags: Requirements of userptr object.
1464 *
1465 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1466 * to current task
1467 */
1468int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1469 uint32_t flags)
1470{
1471 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1472
1473 if (gtt == NULL)
1474 return -EINVAL;
1475
1476 gtt->userptr = addr;
1477 gtt->userflags = flags;
1478
1479 if (gtt->usertask)
1480 put_task_struct(gtt->usertask);
1481 gtt->usertask = current->group_leader;
1482 get_task_struct(gtt->usertask);
1483
1484 return 0;
1485}
1486
1487/**
1488 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1489 */
1490struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1491{
1492 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1493
1494 if (gtt == NULL)
1495 return NULL;
1496
1497 if (gtt->usertask == NULL)
1498 return NULL;
1499
1500 return gtt->usertask->mm;
1501}
1502
1503/**
1504 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1505 * address range for the current task.
1506 *
1507 */
1508bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1509 unsigned long end)
1510{
1511 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1512 unsigned long size;
1513
1514 if (gtt == NULL || !gtt->userptr)
1515 return false;
1516
1517 /* Return false if no part of the ttm_tt object lies within
1518 * the range
1519 */
1520 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1521 if (gtt->userptr > end || gtt->userptr + size <= start)
1522 return false;
1523
1524 return true;
1525}
1526
1527/**
1528 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1529 */
1530bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1531{
1532 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1533
1534 if (gtt == NULL || !gtt->userptr)
1535 return false;
1536
1537 return true;
1538}
1539
1540/**
1541 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1542 */
1543bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1544{
1545 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1546
1547 if (gtt == NULL)
1548 return false;
1549
1550 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1551}
1552
1553/**
1554 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1555 *
1556 * @ttm: The ttm_tt object to compute the flags for
1557 * @mem: The memory registry backing this ttm_tt object
1558 *
1559 * Figure out the flags to use for a VM PDE (Page Directory Entry).
1560 */
1561uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1562{
1563 uint64_t flags = 0;
1564
1565 if (mem && mem->mem_type != TTM_PL_SYSTEM)
1566 flags |= AMDGPU_PTE_VALID;
1567
1568 if (mem && mem->mem_type == TTM_PL_TT) {
1569 flags |= AMDGPU_PTE_SYSTEM;
1570
1571 if (ttm->caching_state == tt_cached)
1572 flags |= AMDGPU_PTE_SNOOPED;
1573 }
1574
1575 return flags;
1576}
1577
1578/**
1579 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1580 *
1581 * @ttm: The ttm_tt object to compute the flags for
1582 * @mem: The memory registry backing this ttm_tt object
1583
1584 * Figure out the flags to use for a VM PTE (Page Table Entry).
1585 */
1586uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1587 struct ttm_mem_reg *mem)
1588{
1589 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1590
1591 flags |= adev->gart.gart_pte_flags;
1592 flags |= AMDGPU_PTE_READABLE;
1593
1594 if (!amdgpu_ttm_tt_is_readonly(ttm))
1595 flags |= AMDGPU_PTE_WRITEABLE;
1596
1597 return flags;
1598}
1599
1600/**
1601 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1602 * object.
1603 *
1604 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1605 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1606 * it can find space for a new object and by ttm_bo_force_list_clean() which is
1607 * used to clean out a memory space.
1608 */
1609static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1610 const struct ttm_place *place)
1611{
1612 unsigned long num_pages = bo->mem.num_pages;
1613 struct drm_mm_node *node = bo->mem.mm_node;
1614 struct dma_resv_list *flist;
1615 struct dma_fence *f;
1616 int i;
1617
1618 if (bo->type == ttm_bo_type_kernel &&
1619 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1620 return false;
1621
1622 /* If bo is a KFD BO, check if the bo belongs to the current process.
1623 * If true, then return false as any KFD process needs all its BOs to
1624 * be resident to run successfully
1625 */
1626 flist = dma_resv_get_list(bo->base.resv);
1627 if (flist) {
1628 for (i = 0; i < flist->shared_count; ++i) {
1629 f = rcu_dereference_protected(flist->shared[i],
1630 dma_resv_held(bo->base.resv));
1631 if (amdkfd_fence_check_mm(f, current->mm))
1632 return false;
1633 }
1634 }
1635
1636 switch (bo->mem.mem_type) {
1637 case TTM_PL_TT:
1638 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1639 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1640 return false;
1641 return true;
1642
1643 case TTM_PL_VRAM:
1644 /* Check each drm MM node individually */
1645 while (num_pages) {
1646 if (place->fpfn < (node->start + node->size) &&
1647 !(place->lpfn && place->lpfn <= node->start))
1648 return true;
1649
1650 num_pages -= node->size;
1651 ++node;
1652 }
1653 return false;
1654
1655 default:
1656 break;
1657 }
1658
1659 return ttm_bo_eviction_valuable(bo, place);
1660}
1661
1662/**
1663 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1664 *
1665 * @bo: The buffer object to read/write
1666 * @offset: Offset into buffer object
1667 * @buf: Secondary buffer to write/read from
1668 * @len: Length in bytes of access
1669 * @write: true if writing
1670 *
1671 * This is used to access VRAM that backs a buffer object via MMIO
1672 * access for debugging purposes.
1673 */
1674static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1675 unsigned long offset,
1676 void *buf, int len, int write)
1677{
1678 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1679 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1680 struct drm_mm_node *nodes;
1681 uint32_t value = 0;
1682 int ret = 0;
1683 uint64_t pos;
1684 unsigned long flags;
1685
1686 if (bo->mem.mem_type != TTM_PL_VRAM)
1687 return -EIO;
1688
1689 pos = offset;
1690 nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1691 pos += (nodes->start << PAGE_SHIFT);
1692
1693 while (len && pos < adev->gmc.mc_vram_size) {
1694 uint64_t aligned_pos = pos & ~(uint64_t)3;
1695 uint64_t bytes = 4 - (pos & 3);
1696 uint32_t shift = (pos & 3) * 8;
1697 uint32_t mask = 0xffffffff << shift;
1698
1699 if (len < bytes) {
1700 mask &= 0xffffffff >> (bytes - len) * 8;
1701 bytes = len;
1702 }
1703
1704 if (mask != 0xffffffff) {
1705 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1706 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1707 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1708 if (!write || mask != 0xffffffff)
1709 value = RREG32_NO_KIQ(mmMM_DATA);
1710 if (write) {
1711 value &= ~mask;
1712 value |= (*(uint32_t *)buf << shift) & mask;
1713 WREG32_NO_KIQ(mmMM_DATA, value);
1714 }
1715 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1716 if (!write) {
1717 value = (value & mask) >> shift;
1718 memcpy(buf, &value, bytes);
1719 }
1720 } else {
1721 bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1722 bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1723
1724 amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1725 bytes, write);
1726 }
1727
1728 ret += bytes;
1729 buf = (uint8_t *)buf + bytes;
1730 pos += bytes;
1731 len -= bytes;
1732 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1733 ++nodes;
1734 pos = (nodes->start << PAGE_SHIFT);
1735 }
1736 }
1737
1738 return ret;
1739}
1740
1741static struct ttm_bo_driver amdgpu_bo_driver = {
1742 .ttm_tt_create = &amdgpu_ttm_tt_create,
1743 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1744 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1745 .init_mem_type = &amdgpu_init_mem_type,
1746 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1747 .evict_flags = &amdgpu_evict_flags,
1748 .move = &amdgpu_bo_move,
1749 .verify_access = &amdgpu_verify_access,
1750 .move_notify = &amdgpu_bo_move_notify,
1751 .release_notify = &amdgpu_bo_release_notify,
1752 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1753 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1754 .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1755 .access_memory = &amdgpu_ttm_access_memory,
1756 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1757};
1758
1759/*
1760 * Firmware Reservation functions
1761 */
1762/**
1763 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1764 *
1765 * @adev: amdgpu_device pointer
1766 *
1767 * free fw reserved vram if it has been reserved.
1768 */
1769static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1770{
1771 amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1772 NULL, &adev->fw_vram_usage.va);
1773}
1774
1775/**
1776 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1777 *
1778 * @adev: amdgpu_device pointer
1779 *
1780 * create bo vram reservation from fw.
1781 */
1782static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1783{
1784 uint64_t vram_size = adev->gmc.visible_vram_size;
1785
1786 adev->fw_vram_usage.va = NULL;
1787 adev->fw_vram_usage.reserved_bo = NULL;
1788
1789 if (adev->fw_vram_usage.size == 0 ||
1790 adev->fw_vram_usage.size > vram_size)
1791 return 0;
1792
1793 return amdgpu_bo_create_kernel_at(adev,
1794 adev->fw_vram_usage.start_offset,
1795 adev->fw_vram_usage.size,
1796 AMDGPU_GEM_DOMAIN_VRAM,
1797 &adev->fw_vram_usage.reserved_bo,
1798 &adev->fw_vram_usage.va);
1799}
1800
1801/*
1802 * Memoy training reservation functions
1803 */
1804
1805/**
1806 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1807 *
1808 * @adev: amdgpu_device pointer
1809 *
1810 * free memory training reserved vram if it has been reserved.
1811 */
1812static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1813{
1814 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1815
1816 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1817 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1818 ctx->c2p_bo = NULL;
1819
1820 return 0;
1821}
1822
1823static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1824{
1825 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1826
1827 memset(ctx, 0, sizeof(*ctx));
1828
1829 ctx->c2p_train_data_offset =
1830 ALIGN((adev->gmc.mc_vram_size - adev->discovery_tmr_size - SZ_1M), SZ_1M);
1831 ctx->p2c_train_data_offset =
1832 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1833 ctx->train_data_size =
1834 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1835
1836 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1837 ctx->train_data_size,
1838 ctx->p2c_train_data_offset,
1839 ctx->c2p_train_data_offset);
1840}
1841
1842/*
1843 * reserve TMR memory at the top of VRAM which holds
1844 * IP Discovery data and is protected by PSP.
1845 */
1846static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1847{
1848 int ret;
1849 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1850 bool mem_train_support = false;
1851
1852 if (!amdgpu_sriov_vf(adev)) {
1853 ret = amdgpu_mem_train_support(adev);
1854 if (ret == 1)
1855 mem_train_support = true;
1856 else if (ret == -1)
1857 return -EINVAL;
1858 else
1859 DRM_DEBUG("memory training does not support!\n");
1860 }
1861
1862 /*
1863 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1864 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1865 *
1866 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1867 * discovery data and G6 memory training data respectively
1868 */
1869 adev->discovery_tmr_size =
1870 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1871 if (!adev->discovery_tmr_size)
1872 adev->discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1873
1874 if (mem_train_support) {
1875 /* reserve vram for mem train according to TMR location */
1876 amdgpu_ttm_training_data_block_init(adev);
1877 ret = amdgpu_bo_create_kernel_at(adev,
1878 ctx->c2p_train_data_offset,
1879 ctx->train_data_size,
1880 AMDGPU_GEM_DOMAIN_VRAM,
1881 &ctx->c2p_bo,
1882 NULL);
1883 if (ret) {
1884 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1885 amdgpu_ttm_training_reserve_vram_fini(adev);
1886 return ret;
1887 }
1888 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1889 }
1890
1891 ret = amdgpu_bo_create_kernel_at(adev,
1892 adev->gmc.real_vram_size - adev->discovery_tmr_size,
1893 adev->discovery_tmr_size,
1894 AMDGPU_GEM_DOMAIN_VRAM,
1895 &adev->discovery_memory,
1896 NULL);
1897 if (ret) {
1898 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1899 amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
1900 return ret;
1901 }
1902
1903 return 0;
1904}
1905
1906/**
1907 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1908 * gtt/vram related fields.
1909 *
1910 * This initializes all of the memory space pools that the TTM layer
1911 * will need such as the GTT space (system memory mapped to the device),
1912 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1913 * can be mapped per VMID.
1914 */
1915int amdgpu_ttm_init(struct amdgpu_device *adev)
1916{
1917 uint64_t gtt_size;
1918 int r;
1919 u64 vis_vram_limit;
1920 void *stolen_vga_buf;
1921
1922 mutex_init(&adev->mman.gtt_window_lock);
1923
1924 /* No others user of address space so set it to 0 */
1925 r = ttm_bo_device_init(&adev->mman.bdev,
1926 &amdgpu_bo_driver,
1927 adev->ddev->anon_inode->i_mapping,
1928 adev->ddev->vma_offset_manager,
1929 dma_addressing_limited(adev->dev));
1930 if (r) {
1931 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1932 return r;
1933 }
1934 adev->mman.initialized = true;
1935
1936 /* We opt to avoid OOM on system pages allocations */
1937 adev->mman.bdev.no_retry = true;
1938
1939 /* Initialize VRAM pool with all of VRAM divided into pages */
1940 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1941 adev->gmc.real_vram_size >> PAGE_SHIFT);
1942 if (r) {
1943 DRM_ERROR("Failed initializing VRAM heap.\n");
1944 return r;
1945 }
1946
1947 /* Reduce size of CPU-visible VRAM if requested */
1948 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1949 if (amdgpu_vis_vram_limit > 0 &&
1950 vis_vram_limit <= adev->gmc.visible_vram_size)
1951 adev->gmc.visible_vram_size = vis_vram_limit;
1952
1953 /* Change the size here instead of the init above so only lpfn is affected */
1954 amdgpu_ttm_set_buffer_funcs_status(adev, false);
1955#ifdef CONFIG_64BIT
1956 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1957 adev->gmc.visible_vram_size);
1958#endif
1959
1960 /*
1961 *The reserved vram for firmware must be pinned to the specified
1962 *place on the VRAM, so reserve it early.
1963 */
1964 r = amdgpu_ttm_fw_reserve_vram_init(adev);
1965 if (r) {
1966 return r;
1967 }
1968
1969 /*
1970 * only NAVI10 and onwards ASIC support for IP discovery.
1971 * If IP discovery enabled, a block of memory should be
1972 * reserved for IP discovey.
1973 */
1974 if (adev->discovery_bin) {
1975 r = amdgpu_ttm_reserve_tmr(adev);
1976 if (r)
1977 return r;
1978 }
1979
1980 /* allocate memory as required for VGA
1981 * This is used for VGA emulation and pre-OS scanout buffers to
1982 * avoid display artifacts while transitioning between pre-OS
1983 * and driver. */
1984 r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1985 AMDGPU_GEM_DOMAIN_VRAM,
1986 &adev->stolen_vga_memory,
1987 NULL, &stolen_vga_buf);
1988 if (r)
1989 return r;
1990
1991 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1992 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1993
1994 /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1995 * or whatever the user passed on module init */
1996 if (amdgpu_gtt_size == -1) {
1997 struct sysinfo si;
1998
1999 si_meminfo(&si);
2000 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
2001 adev->gmc.mc_vram_size),
2002 ((uint64_t)si.totalram * si.mem_unit * 3/4));
2003 }
2004 else
2005 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
2006
2007 /* Initialize GTT memory pool */
2008 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
2009 if (r) {
2010 DRM_ERROR("Failed initializing GTT heap.\n");
2011 return r;
2012 }
2013 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
2014 (unsigned)(gtt_size / (1024 * 1024)));
2015
2016 /* Initialize various on-chip memory pools */
2017 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
2018 adev->gds.gds_size);
2019 if (r) {
2020 DRM_ERROR("Failed initializing GDS heap.\n");
2021 return r;
2022 }
2023
2024 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
2025 adev->gds.gws_size);
2026 if (r) {
2027 DRM_ERROR("Failed initializing gws heap.\n");
2028 return r;
2029 }
2030
2031 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
2032 adev->gds.oa_size);
2033 if (r) {
2034 DRM_ERROR("Failed initializing oa heap.\n");
2035 return r;
2036 }
2037
2038 return 0;
2039}
2040
2041/**
2042 * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
2043 */
2044void amdgpu_ttm_late_init(struct amdgpu_device *adev)
2045{
2046 void *stolen_vga_buf;
2047 /* return the VGA stolen memory (if any) back to VRAM */
2048 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
2049}
2050
2051/**
2052 * amdgpu_ttm_fini - De-initialize the TTM memory pools
2053 */
2054void amdgpu_ttm_fini(struct amdgpu_device *adev)
2055{
2056 if (!adev->mman.initialized)
2057 return;
2058
2059 amdgpu_ttm_training_reserve_vram_fini(adev);
2060 /* return the IP Discovery TMR memory back to VRAM */
2061 amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
2062 amdgpu_ttm_fw_reserve_vram_fini(adev);
2063
2064 if (adev->mman.aper_base_kaddr)
2065 iounmap(adev->mman.aper_base_kaddr);
2066 adev->mman.aper_base_kaddr = NULL;
2067
2068 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
2069 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
2070 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
2071 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
2072 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
2073 ttm_bo_device_release(&adev->mman.bdev);
2074 adev->mman.initialized = false;
2075 DRM_INFO("amdgpu: ttm finalized\n");
2076}
2077
2078/**
2079 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2080 *
2081 * @adev: amdgpu_device pointer
2082 * @enable: true when we can use buffer functions.
2083 *
2084 * Enable/disable use of buffer functions during suspend/resume. This should
2085 * only be called at bootup or when userspace isn't running.
2086 */
2087void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2088{
2089 struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
2090 uint64_t size;
2091 int r;
2092
2093 if (!adev->mman.initialized || adev->in_gpu_reset ||
2094 adev->mman.buffer_funcs_enabled == enable)
2095 return;
2096
2097 if (enable) {
2098 struct amdgpu_ring *ring;
2099 struct drm_gpu_scheduler *sched;
2100
2101 ring = adev->mman.buffer_funcs_ring;
2102 sched = &ring->sched;
2103 r = drm_sched_entity_init(&adev->mman.entity,
2104 DRM_SCHED_PRIORITY_KERNEL, &sched,
2105 1, NULL);
2106 if (r) {
2107 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2108 r);
2109 return;
2110 }
2111 } else {
2112 drm_sched_entity_destroy(&adev->mman.entity);
2113 dma_fence_put(man->move);
2114 man->move = NULL;
2115 }
2116
2117 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2118 if (enable)
2119 size = adev->gmc.real_vram_size;
2120 else
2121 size = adev->gmc.visible_vram_size;
2122 man->size = size >> PAGE_SHIFT;
2123 adev->mman.buffer_funcs_enabled = enable;
2124}
2125
2126int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2127{
2128 struct drm_file *file_priv = filp->private_data;
2129 struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
2130
2131 if (adev == NULL)
2132 return -EINVAL;
2133
2134 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2135}
2136
2137int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2138 uint64_t dst_offset, uint32_t byte_count,
2139 struct dma_resv *resv,
2140 struct dma_fence **fence, bool direct_submit,
2141 bool vm_needs_flush, bool tmz)
2142{
2143 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2144 AMDGPU_IB_POOL_DELAYED;
2145 struct amdgpu_device *adev = ring->adev;
2146 struct amdgpu_job *job;
2147
2148 uint32_t max_bytes;
2149 unsigned num_loops, num_dw;
2150 unsigned i;
2151 int r;
2152
2153 if (direct_submit && !ring->sched.ready) {
2154 DRM_ERROR("Trying to move memory with ring turned off.\n");
2155 return -EINVAL;
2156 }
2157
2158 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2159 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2160 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2161
2162 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2163 if (r)
2164 return r;
2165
2166 if (vm_needs_flush) {
2167 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2168 job->vm_needs_flush = true;
2169 }
2170 if (resv) {
2171 r = amdgpu_sync_resv(adev, &job->sync, resv,
2172 AMDGPU_SYNC_ALWAYS,
2173 AMDGPU_FENCE_OWNER_UNDEFINED);
2174 if (r) {
2175 DRM_ERROR("sync failed (%d).\n", r);
2176 goto error_free;
2177 }
2178 }
2179
2180 for (i = 0; i < num_loops; i++) {
2181 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2182
2183 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2184 dst_offset, cur_size_in_bytes, tmz);
2185
2186 src_offset += cur_size_in_bytes;
2187 dst_offset += cur_size_in_bytes;
2188 byte_count -= cur_size_in_bytes;
2189 }
2190
2191 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2192 WARN_ON(job->ibs[0].length_dw > num_dw);
2193 if (direct_submit)
2194 r = amdgpu_job_submit_direct(job, ring, fence);
2195 else
2196 r = amdgpu_job_submit(job, &adev->mman.entity,
2197 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2198 if (r)
2199 goto error_free;
2200
2201 return r;
2202
2203error_free:
2204 amdgpu_job_free(job);
2205 DRM_ERROR("Error scheduling IBs (%d)\n", r);
2206 return r;
2207}
2208
2209int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2210 uint32_t src_data,
2211 struct dma_resv *resv,
2212 struct dma_fence **fence)
2213{
2214 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2215 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2216 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2217
2218 struct drm_mm_node *mm_node;
2219 unsigned long num_pages;
2220 unsigned int num_loops, num_dw;
2221
2222 struct amdgpu_job *job;
2223 int r;
2224
2225 if (!adev->mman.buffer_funcs_enabled) {
2226 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2227 return -EINVAL;
2228 }
2229
2230 if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2231 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2232 if (r)
2233 return r;
2234 }
2235
2236 num_pages = bo->tbo.num_pages;
2237 mm_node = bo->tbo.mem.mm_node;
2238 num_loops = 0;
2239 while (num_pages) {
2240 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2241
2242 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2243 num_pages -= mm_node->size;
2244 ++mm_node;
2245 }
2246 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2247
2248 /* for IB padding */
2249 num_dw += 64;
2250
2251 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2252 &job);
2253 if (r)
2254 return r;
2255
2256 if (resv) {
2257 r = amdgpu_sync_resv(adev, &job->sync, resv,
2258 AMDGPU_SYNC_ALWAYS,
2259 AMDGPU_FENCE_OWNER_UNDEFINED);
2260 if (r) {
2261 DRM_ERROR("sync failed (%d).\n", r);
2262 goto error_free;
2263 }
2264 }
2265
2266 num_pages = bo->tbo.num_pages;
2267 mm_node = bo->tbo.mem.mm_node;
2268
2269 while (num_pages) {
2270 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2271 uint64_t dst_addr;
2272
2273 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2274 while (byte_count) {
2275 uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2276 max_bytes);
2277
2278 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2279 dst_addr, cur_size_in_bytes);
2280
2281 dst_addr += cur_size_in_bytes;
2282 byte_count -= cur_size_in_bytes;
2283 }
2284
2285 num_pages -= mm_node->size;
2286 ++mm_node;
2287 }
2288
2289 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2290 WARN_ON(job->ibs[0].length_dw > num_dw);
2291 r = amdgpu_job_submit(job, &adev->mman.entity,
2292 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2293 if (r)
2294 goto error_free;
2295
2296 return 0;
2297
2298error_free:
2299 amdgpu_job_free(job);
2300 return r;
2301}
2302
2303#if defined(CONFIG_DEBUG_FS)
2304
2305static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2306{
2307 struct drm_info_node *node = (struct drm_info_node *)m->private;
2308 unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2309 struct drm_device *dev = node->minor->dev;
2310 struct amdgpu_device *adev = dev->dev_private;
2311 struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2312 struct drm_printer p = drm_seq_file_printer(m);
2313
2314 man->func->debug(man, &p);
2315 return 0;
2316}
2317
2318static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2319 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2320 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2321 {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2322 {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2323 {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2324 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2325#ifdef CONFIG_SWIOTLB
2326 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2327#endif
2328};
2329
2330/**
2331 * amdgpu_ttm_vram_read - Linear read access to VRAM
2332 *
2333 * Accesses VRAM via MMIO for debugging purposes.
2334 */
2335static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2336 size_t size, loff_t *pos)
2337{
2338 struct amdgpu_device *adev = file_inode(f)->i_private;
2339 ssize_t result = 0;
2340
2341 if (size & 0x3 || *pos & 0x3)
2342 return -EINVAL;
2343
2344 if (*pos >= adev->gmc.mc_vram_size)
2345 return -ENXIO;
2346
2347 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2348 while (size) {
2349 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2350 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2351
2352 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2353 if (copy_to_user(buf, value, bytes))
2354 return -EFAULT;
2355
2356 result += bytes;
2357 buf += bytes;
2358 *pos += bytes;
2359 size -= bytes;
2360 }
2361
2362 return result;
2363}
2364
2365/**
2366 * amdgpu_ttm_vram_write - Linear write access to VRAM
2367 *
2368 * Accesses VRAM via MMIO for debugging purposes.
2369 */
2370static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2371 size_t size, loff_t *pos)
2372{
2373 struct amdgpu_device *adev = file_inode(f)->i_private;
2374 ssize_t result = 0;
2375 int r;
2376
2377 if (size & 0x3 || *pos & 0x3)
2378 return -EINVAL;
2379
2380 if (*pos >= adev->gmc.mc_vram_size)
2381 return -ENXIO;
2382
2383 while (size) {
2384 unsigned long flags;
2385 uint32_t value;
2386
2387 if (*pos >= adev->gmc.mc_vram_size)
2388 return result;
2389
2390 r = get_user(value, (uint32_t *)buf);
2391 if (r)
2392 return r;
2393
2394 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2395 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2396 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2397 WREG32_NO_KIQ(mmMM_DATA, value);
2398 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2399
2400 result += 4;
2401 buf += 4;
2402 *pos += 4;
2403 size -= 4;
2404 }
2405
2406 return result;
2407}
2408
2409static const struct file_operations amdgpu_ttm_vram_fops = {
2410 .owner = THIS_MODULE,
2411 .read = amdgpu_ttm_vram_read,
2412 .write = amdgpu_ttm_vram_write,
2413 .llseek = default_llseek,
2414};
2415
2416#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2417
2418/**
2419 * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2420 */
2421static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2422 size_t size, loff_t *pos)
2423{
2424 struct amdgpu_device *adev = file_inode(f)->i_private;
2425 ssize_t result = 0;
2426 int r;
2427
2428 while (size) {
2429 loff_t p = *pos / PAGE_SIZE;
2430 unsigned off = *pos & ~PAGE_MASK;
2431 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2432 struct page *page;
2433 void *ptr;
2434
2435 if (p >= adev->gart.num_cpu_pages)
2436 return result;
2437
2438 page = adev->gart.pages[p];
2439 if (page) {
2440 ptr = kmap(page);
2441 ptr += off;
2442
2443 r = copy_to_user(buf, ptr, cur_size);
2444 kunmap(adev->gart.pages[p]);
2445 } else
2446 r = clear_user(buf, cur_size);
2447
2448 if (r)
2449 return -EFAULT;
2450
2451 result += cur_size;
2452 buf += cur_size;
2453 *pos += cur_size;
2454 size -= cur_size;
2455 }
2456
2457 return result;
2458}
2459
2460static const struct file_operations amdgpu_ttm_gtt_fops = {
2461 .owner = THIS_MODULE,
2462 .read = amdgpu_ttm_gtt_read,
2463 .llseek = default_llseek
2464};
2465
2466#endif
2467
2468/**
2469 * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2470 *
2471 * This function is used to read memory that has been mapped to the
2472 * GPU and the known addresses are not physical addresses but instead
2473 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2474 */
2475static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2476 size_t size, loff_t *pos)
2477{
2478 struct amdgpu_device *adev = file_inode(f)->i_private;
2479 struct iommu_domain *dom;
2480 ssize_t result = 0;
2481 int r;
2482
2483 /* retrieve the IOMMU domain if any for this device */
2484 dom = iommu_get_domain_for_dev(adev->dev);
2485
2486 while (size) {
2487 phys_addr_t addr = *pos & PAGE_MASK;
2488 loff_t off = *pos & ~PAGE_MASK;
2489 size_t bytes = PAGE_SIZE - off;
2490 unsigned long pfn;
2491 struct page *p;
2492 void *ptr;
2493
2494 bytes = bytes < size ? bytes : size;
2495
2496 /* Translate the bus address to a physical address. If
2497 * the domain is NULL it means there is no IOMMU active
2498 * and the address translation is the identity
2499 */
2500 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2501
2502 pfn = addr >> PAGE_SHIFT;
2503 if (!pfn_valid(pfn))
2504 return -EPERM;
2505
2506 p = pfn_to_page(pfn);
2507 if (p->mapping != adev->mman.bdev.dev_mapping)
2508 return -EPERM;
2509
2510 ptr = kmap(p);
2511 r = copy_to_user(buf, ptr + off, bytes);
2512 kunmap(p);
2513 if (r)
2514 return -EFAULT;
2515
2516 size -= bytes;
2517 *pos += bytes;
2518 result += bytes;
2519 }
2520
2521 return result;
2522}
2523
2524/**
2525 * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2526 *
2527 * This function is used to write memory that has been mapped to the
2528 * GPU and the known addresses are not physical addresses but instead
2529 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2530 */
2531static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2532 size_t size, loff_t *pos)
2533{
2534 struct amdgpu_device *adev = file_inode(f)->i_private;
2535 struct iommu_domain *dom;
2536 ssize_t result = 0;
2537 int r;
2538
2539 dom = iommu_get_domain_for_dev(adev->dev);
2540
2541 while (size) {
2542 phys_addr_t addr = *pos & PAGE_MASK;
2543 loff_t off = *pos & ~PAGE_MASK;
2544 size_t bytes = PAGE_SIZE - off;
2545 unsigned long pfn;
2546 struct page *p;
2547 void *ptr;
2548
2549 bytes = bytes < size ? bytes : size;
2550
2551 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2552
2553 pfn = addr >> PAGE_SHIFT;
2554 if (!pfn_valid(pfn))
2555 return -EPERM;
2556
2557 p = pfn_to_page(pfn);
2558 if (p->mapping != adev->mman.bdev.dev_mapping)
2559 return -EPERM;
2560
2561 ptr = kmap(p);
2562 r = copy_from_user(ptr + off, buf, bytes);
2563 kunmap(p);
2564 if (r)
2565 return -EFAULT;
2566
2567 size -= bytes;
2568 *pos += bytes;
2569 result += bytes;
2570 }
2571
2572 return result;
2573}
2574
2575static const struct file_operations amdgpu_ttm_iomem_fops = {
2576 .owner = THIS_MODULE,
2577 .read = amdgpu_iomem_read,
2578 .write = amdgpu_iomem_write,
2579 .llseek = default_llseek
2580};
2581
2582static const struct {
2583 char *name;
2584 const struct file_operations *fops;
2585 int domain;
2586} ttm_debugfs_entries[] = {
2587 { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2588#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2589 { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2590#endif
2591 { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2592};
2593
2594#endif
2595
2596int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2597{
2598#if defined(CONFIG_DEBUG_FS)
2599 unsigned count;
2600
2601 struct drm_minor *minor = adev->ddev->primary;
2602 struct dentry *ent, *root = minor->debugfs_root;
2603
2604 for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2605 ent = debugfs_create_file(
2606 ttm_debugfs_entries[count].name,
2607 S_IFREG | S_IRUGO, root,
2608 adev,
2609 ttm_debugfs_entries[count].fops);
2610 if (IS_ERR(ent))
2611 return PTR_ERR(ent);
2612 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2613 i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2614 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2615 i_size_write(ent->d_inode, adev->gmc.gart_size);
2616 adev->mman.debugfs_entries[count] = ent;
2617 }
2618
2619 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2620
2621#ifdef CONFIG_SWIOTLB
2622 if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2623 --count;
2624#endif
2625
2626 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2627#else
2628 return 0;
2629#endif
2630}
1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32
33#include <linux/dma-mapping.h>
34#include <linux/iommu.h>
35#include <linux/pagemap.h>
36#include <linux/sched/task.h>
37#include <linux/sched/mm.h>
38#include <linux/seq_file.h>
39#include <linux/slab.h>
40#include <linux/swap.h>
41#include <linux/dma-buf.h>
42#include <linux/sizes.h>
43#include <linux/module.h>
44
45#include <drm/drm_drv.h>
46#include <drm/ttm/ttm_bo.h>
47#include <drm/ttm/ttm_placement.h>
48#include <drm/ttm/ttm_range_manager.h>
49#include <drm/ttm/ttm_tt.h>
50
51#include <drm/amdgpu_drm.h>
52
53#include "amdgpu.h"
54#include "amdgpu_object.h"
55#include "amdgpu_trace.h"
56#include "amdgpu_amdkfd.h"
57#include "amdgpu_sdma.h"
58#include "amdgpu_ras.h"
59#include "amdgpu_hmm.h"
60#include "amdgpu_atomfirmware.h"
61#include "amdgpu_res_cursor.h"
62#include "bif/bif_4_1_d.h"
63
64MODULE_IMPORT_NS("DMA_BUF");
65
66#define AMDGPU_TTM_VRAM_MAX_DW_READ ((size_t)128)
67
68static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
69 struct ttm_tt *ttm,
70 struct ttm_resource *bo_mem);
71static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
72 struct ttm_tt *ttm);
73
74static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
75 unsigned int type,
76 uint64_t size_in_page)
77{
78 return ttm_range_man_init(&adev->mman.bdev, type,
79 false, size_in_page);
80}
81
82/**
83 * amdgpu_evict_flags - Compute placement flags
84 *
85 * @bo: The buffer object to evict
86 * @placement: Possible destination(s) for evicted BO
87 *
88 * Fill in placement data when ttm_bo_evict() is called
89 */
90static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
91 struct ttm_placement *placement)
92{
93 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
94 struct amdgpu_bo *abo;
95 static const struct ttm_place placements = {
96 .fpfn = 0,
97 .lpfn = 0,
98 .mem_type = TTM_PL_SYSTEM,
99 .flags = 0
100 };
101
102 /* Don't handle scatter gather BOs */
103 if (bo->type == ttm_bo_type_sg) {
104 placement->num_placement = 0;
105 return;
106 }
107
108 /* Object isn't an AMDGPU object so ignore */
109 if (!amdgpu_bo_is_amdgpu_bo(bo)) {
110 placement->placement = &placements;
111 placement->num_placement = 1;
112 return;
113 }
114
115 abo = ttm_to_amdgpu_bo(bo);
116 if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) {
117 placement->num_placement = 0;
118 return;
119 }
120
121 switch (bo->resource->mem_type) {
122 case AMDGPU_PL_GDS:
123 case AMDGPU_PL_GWS:
124 case AMDGPU_PL_OA:
125 case AMDGPU_PL_DOORBELL:
126 placement->num_placement = 0;
127 return;
128
129 case TTM_PL_VRAM:
130 if (!adev->mman.buffer_funcs_enabled) {
131 /* Move to system memory */
132 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
133
134 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
135 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
136 amdgpu_res_cpu_visible(adev, bo->resource)) {
137
138 /* Try evicting to the CPU inaccessible part of VRAM
139 * first, but only set GTT as busy placement, so this
140 * BO will be evicted to GTT rather than causing other
141 * BOs to be evicted from VRAM
142 */
143 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
144 AMDGPU_GEM_DOMAIN_GTT |
145 AMDGPU_GEM_DOMAIN_CPU);
146 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
147 abo->placements[0].lpfn = 0;
148 abo->placements[0].flags |= TTM_PL_FLAG_DESIRED;
149 } else {
150 /* Move to GTT memory */
151 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT |
152 AMDGPU_GEM_DOMAIN_CPU);
153 }
154 break;
155 case TTM_PL_TT:
156 case AMDGPU_PL_PREEMPT:
157 default:
158 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
159 break;
160 }
161 *placement = abo->placement;
162}
163
164/**
165 * amdgpu_ttm_map_buffer - Map memory into the GART windows
166 * @bo: buffer object to map
167 * @mem: memory object to map
168 * @mm_cur: range to map
169 * @window: which GART window to use
170 * @ring: DMA ring to use for the copy
171 * @tmz: if we should setup a TMZ enabled mapping
172 * @size: in number of bytes to map, out number of bytes mapped
173 * @addr: resulting address inside the MC address space
174 *
175 * Setup one of the GART windows to access a specific piece of memory or return
176 * the physical address for local memory.
177 */
178static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
179 struct ttm_resource *mem,
180 struct amdgpu_res_cursor *mm_cur,
181 unsigned int window, struct amdgpu_ring *ring,
182 bool tmz, uint64_t *size, uint64_t *addr)
183{
184 struct amdgpu_device *adev = ring->adev;
185 unsigned int offset, num_pages, num_dw, num_bytes;
186 uint64_t src_addr, dst_addr;
187 struct amdgpu_job *job;
188 void *cpu_addr;
189 uint64_t flags;
190 unsigned int i;
191 int r;
192
193 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
194 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
195
196 if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT))
197 return -EINVAL;
198
199 /* Map only what can't be accessed directly */
200 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
201 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
202 mm_cur->start;
203 return 0;
204 }
205
206
207 /*
208 * If start begins at an offset inside the page, then adjust the size
209 * and addr accordingly
210 */
211 offset = mm_cur->start & ~PAGE_MASK;
212
213 num_pages = PFN_UP(*size + offset);
214 num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE);
215
216 *size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset);
217
218 *addr = adev->gmc.gart_start;
219 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
220 AMDGPU_GPU_PAGE_SIZE;
221 *addr += offset;
222
223 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
224 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
225
226 r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
227 AMDGPU_FENCE_OWNER_UNDEFINED,
228 num_dw * 4 + num_bytes,
229 AMDGPU_IB_POOL_DELAYED, &job);
230 if (r)
231 return r;
232
233 src_addr = num_dw * 4;
234 src_addr += job->ibs[0].gpu_addr;
235
236 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
237 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
238 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
239 dst_addr, num_bytes, 0);
240
241 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
242 WARN_ON(job->ibs[0].length_dw > num_dw);
243
244 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
245 if (tmz)
246 flags |= AMDGPU_PTE_TMZ;
247
248 cpu_addr = &job->ibs[0].ptr[num_dw];
249
250 if (mem->mem_type == TTM_PL_TT) {
251 dma_addr_t *dma_addr;
252
253 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
254 amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr);
255 } else {
256 dma_addr_t dma_address;
257
258 dma_address = mm_cur->start;
259 dma_address += adev->vm_manager.vram_base_offset;
260
261 for (i = 0; i < num_pages; ++i) {
262 amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address,
263 flags, cpu_addr);
264 dma_address += PAGE_SIZE;
265 }
266 }
267
268 dma_fence_put(amdgpu_job_submit(job));
269 return 0;
270}
271
272/**
273 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
274 * @adev: amdgpu device
275 * @src: buffer/address where to read from
276 * @dst: buffer/address where to write to
277 * @size: number of bytes to copy
278 * @tmz: if a secure copy should be used
279 * @resv: resv object to sync to
280 * @f: Returns the last fence if multiple jobs are submitted.
281 *
282 * The function copies @size bytes from {src->mem + src->offset} to
283 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
284 * move and different for a BO to BO copy.
285 *
286 */
287int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
288 const struct amdgpu_copy_mem *src,
289 const struct amdgpu_copy_mem *dst,
290 uint64_t size, bool tmz,
291 struct dma_resv *resv,
292 struct dma_fence **f)
293{
294 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
295 struct amdgpu_res_cursor src_mm, dst_mm;
296 struct dma_fence *fence = NULL;
297 int r = 0;
298 uint32_t copy_flags = 0;
299 struct amdgpu_bo *abo_src, *abo_dst;
300
301 if (!adev->mman.buffer_funcs_enabled) {
302 DRM_ERROR("Trying to move memory with ring turned off.\n");
303 return -EINVAL;
304 }
305
306 amdgpu_res_first(src->mem, src->offset, size, &src_mm);
307 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
308
309 mutex_lock(&adev->mman.gtt_window_lock);
310 while (src_mm.remaining) {
311 uint64_t from, to, cur_size, tiling_flags;
312 uint32_t num_type, data_format, max_com, write_compress_disable;
313 struct dma_fence *next;
314
315 /* Never copy more than 256MiB at once to avoid a timeout */
316 cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20);
317
318 /* Map src to window 0 and dst to window 1. */
319 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
320 0, ring, tmz, &cur_size, &from);
321 if (r)
322 goto error;
323
324 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
325 1, ring, tmz, &cur_size, &to);
326 if (r)
327 goto error;
328
329 abo_src = ttm_to_amdgpu_bo(src->bo);
330 abo_dst = ttm_to_amdgpu_bo(dst->bo);
331 if (tmz)
332 copy_flags |= AMDGPU_COPY_FLAGS_TMZ;
333 if ((abo_src->flags & AMDGPU_GEM_CREATE_GFX12_DCC) &&
334 (abo_src->tbo.resource->mem_type == TTM_PL_VRAM))
335 copy_flags |= AMDGPU_COPY_FLAGS_READ_DECOMPRESSED;
336 if ((abo_dst->flags & AMDGPU_GEM_CREATE_GFX12_DCC) &&
337 (dst->mem->mem_type == TTM_PL_VRAM)) {
338 copy_flags |= AMDGPU_COPY_FLAGS_WRITE_COMPRESSED;
339 amdgpu_bo_get_tiling_flags(abo_dst, &tiling_flags);
340 max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);
341 num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);
342 data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);
343 write_compress_disable =
344 AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE);
345 copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED, max_com) |
346 AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE, num_type) |
347 AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format) |
348 AMDGPU_COPY_FLAGS_SET(WRITE_COMPRESS_DISABLE,
349 write_compress_disable));
350 }
351
352 r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,
353 &next, false, true, copy_flags);
354 if (r)
355 goto error;
356
357 dma_fence_put(fence);
358 fence = next;
359
360 amdgpu_res_next(&src_mm, cur_size);
361 amdgpu_res_next(&dst_mm, cur_size);
362 }
363error:
364 mutex_unlock(&adev->mman.gtt_window_lock);
365 if (f)
366 *f = dma_fence_get(fence);
367 dma_fence_put(fence);
368 return r;
369}
370
371/*
372 * amdgpu_move_blit - Copy an entire buffer to another buffer
373 *
374 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
375 * help move buffers to and from VRAM.
376 */
377static int amdgpu_move_blit(struct ttm_buffer_object *bo,
378 bool evict,
379 struct ttm_resource *new_mem,
380 struct ttm_resource *old_mem)
381{
382 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
383 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
384 struct amdgpu_copy_mem src, dst;
385 struct dma_fence *fence = NULL;
386 int r;
387
388 src.bo = bo;
389 dst.bo = bo;
390 src.mem = old_mem;
391 dst.mem = new_mem;
392 src.offset = 0;
393 dst.offset = 0;
394
395 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
396 new_mem->size,
397 amdgpu_bo_encrypted(abo),
398 bo->base.resv, &fence);
399 if (r)
400 goto error;
401
402 /* clear the space being freed */
403 if (old_mem->mem_type == TTM_PL_VRAM &&
404 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
405 struct dma_fence *wipe_fence = NULL;
406
407 r = amdgpu_fill_buffer(abo, 0, NULL, &wipe_fence,
408 false);
409 if (r) {
410 goto error;
411 } else if (wipe_fence) {
412 amdgpu_vram_mgr_set_cleared(bo->resource);
413 dma_fence_put(fence);
414 fence = wipe_fence;
415 }
416 }
417
418 /* Always block for VM page tables before committing the new location */
419 if (bo->type == ttm_bo_type_kernel)
420 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
421 else
422 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
423 dma_fence_put(fence);
424 return r;
425
426error:
427 if (fence)
428 dma_fence_wait(fence, false);
429 dma_fence_put(fence);
430 return r;
431}
432
433/**
434 * amdgpu_res_cpu_visible - Check that resource can be accessed by CPU
435 * @adev: amdgpu device
436 * @res: the resource to check
437 *
438 * Returns: true if the full resource is CPU visible, false otherwise.
439 */
440bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
441 struct ttm_resource *res)
442{
443 struct amdgpu_res_cursor cursor;
444
445 if (!res)
446 return false;
447
448 if (res->mem_type == TTM_PL_SYSTEM || res->mem_type == TTM_PL_TT ||
449 res->mem_type == AMDGPU_PL_PREEMPT || res->mem_type == AMDGPU_PL_DOORBELL)
450 return true;
451
452 if (res->mem_type != TTM_PL_VRAM)
453 return false;
454
455 amdgpu_res_first(res, 0, res->size, &cursor);
456 while (cursor.remaining) {
457 if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size)
458 return false;
459 amdgpu_res_next(&cursor, cursor.size);
460 }
461
462 return true;
463}
464
465/*
466 * amdgpu_res_copyable - Check that memory can be accessed by ttm_bo_move_memcpy
467 *
468 * Called by amdgpu_bo_move()
469 */
470static bool amdgpu_res_copyable(struct amdgpu_device *adev,
471 struct ttm_resource *mem)
472{
473 if (!amdgpu_res_cpu_visible(adev, mem))
474 return false;
475
476 /* ttm_resource_ioremap only supports contiguous memory */
477 if (mem->mem_type == TTM_PL_VRAM &&
478 !(mem->placement & TTM_PL_FLAG_CONTIGUOUS))
479 return false;
480
481 return true;
482}
483
484/*
485 * amdgpu_bo_move - Move a buffer object to a new memory location
486 *
487 * Called by ttm_bo_handle_move_mem()
488 */
489static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
490 struct ttm_operation_ctx *ctx,
491 struct ttm_resource *new_mem,
492 struct ttm_place *hop)
493{
494 struct amdgpu_device *adev;
495 struct amdgpu_bo *abo;
496 struct ttm_resource *old_mem = bo->resource;
497 int r;
498
499 if (new_mem->mem_type == TTM_PL_TT ||
500 new_mem->mem_type == AMDGPU_PL_PREEMPT) {
501 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
502 if (r)
503 return r;
504 }
505
506 abo = ttm_to_amdgpu_bo(bo);
507 adev = amdgpu_ttm_adev(bo->bdev);
508
509 if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
510 bo->ttm == NULL)) {
511 amdgpu_bo_move_notify(bo, evict, new_mem);
512 ttm_bo_move_null(bo, new_mem);
513 return 0;
514 }
515 if (old_mem->mem_type == TTM_PL_SYSTEM &&
516 (new_mem->mem_type == TTM_PL_TT ||
517 new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
518 amdgpu_bo_move_notify(bo, evict, new_mem);
519 ttm_bo_move_null(bo, new_mem);
520 return 0;
521 }
522 if ((old_mem->mem_type == TTM_PL_TT ||
523 old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
524 new_mem->mem_type == TTM_PL_SYSTEM) {
525 r = ttm_bo_wait_ctx(bo, ctx);
526 if (r)
527 return r;
528
529 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
530 amdgpu_bo_move_notify(bo, evict, new_mem);
531 ttm_resource_free(bo, &bo->resource);
532 ttm_bo_assign_mem(bo, new_mem);
533 return 0;
534 }
535
536 if (old_mem->mem_type == AMDGPU_PL_GDS ||
537 old_mem->mem_type == AMDGPU_PL_GWS ||
538 old_mem->mem_type == AMDGPU_PL_OA ||
539 old_mem->mem_type == AMDGPU_PL_DOORBELL ||
540 new_mem->mem_type == AMDGPU_PL_GDS ||
541 new_mem->mem_type == AMDGPU_PL_GWS ||
542 new_mem->mem_type == AMDGPU_PL_OA ||
543 new_mem->mem_type == AMDGPU_PL_DOORBELL) {
544 /* Nothing to save here */
545 amdgpu_bo_move_notify(bo, evict, new_mem);
546 ttm_bo_move_null(bo, new_mem);
547 return 0;
548 }
549
550 if (bo->type == ttm_bo_type_device &&
551 new_mem->mem_type == TTM_PL_VRAM &&
552 old_mem->mem_type != TTM_PL_VRAM) {
553 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
554 * accesses the BO after it's moved.
555 */
556 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
557 }
558
559 if (adev->mman.buffer_funcs_enabled &&
560 ((old_mem->mem_type == TTM_PL_SYSTEM &&
561 new_mem->mem_type == TTM_PL_VRAM) ||
562 (old_mem->mem_type == TTM_PL_VRAM &&
563 new_mem->mem_type == TTM_PL_SYSTEM))) {
564 hop->fpfn = 0;
565 hop->lpfn = 0;
566 hop->mem_type = TTM_PL_TT;
567 hop->flags = TTM_PL_FLAG_TEMPORARY;
568 return -EMULTIHOP;
569 }
570
571 amdgpu_bo_move_notify(bo, evict, new_mem);
572 if (adev->mman.buffer_funcs_enabled)
573 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
574 else
575 r = -ENODEV;
576
577 if (r) {
578 /* Check that all memory is CPU accessible */
579 if (!amdgpu_res_copyable(adev, old_mem) ||
580 !amdgpu_res_copyable(adev, new_mem)) {
581 pr_err("Move buffer fallback to memcpy unavailable\n");
582 return r;
583 }
584
585 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
586 if (r)
587 return r;
588 }
589
590 /* update statistics after the move */
591 if (evict)
592 atomic64_inc(&adev->num_evictions);
593 atomic64_add(bo->base.size, &adev->num_bytes_moved);
594 return 0;
595}
596
597/*
598 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
599 *
600 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
601 */
602static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
603 struct ttm_resource *mem)
604{
605 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
606
607 switch (mem->mem_type) {
608 case TTM_PL_SYSTEM:
609 /* system memory */
610 return 0;
611 case TTM_PL_TT:
612 case AMDGPU_PL_PREEMPT:
613 break;
614 case TTM_PL_VRAM:
615 mem->bus.offset = mem->start << PAGE_SHIFT;
616
617 if (adev->mman.aper_base_kaddr &&
618 mem->placement & TTM_PL_FLAG_CONTIGUOUS)
619 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
620 mem->bus.offset;
621
622 mem->bus.offset += adev->gmc.aper_base;
623 mem->bus.is_iomem = true;
624 break;
625 case AMDGPU_PL_DOORBELL:
626 mem->bus.offset = mem->start << PAGE_SHIFT;
627 mem->bus.offset += adev->doorbell.base;
628 mem->bus.is_iomem = true;
629 mem->bus.caching = ttm_uncached;
630 break;
631 default:
632 return -EINVAL;
633 }
634 return 0;
635}
636
637static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
638 unsigned long page_offset)
639{
640 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
641 struct amdgpu_res_cursor cursor;
642
643 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
644 &cursor);
645
646 if (bo->resource->mem_type == AMDGPU_PL_DOORBELL)
647 return ((uint64_t)(adev->doorbell.base + cursor.start)) >> PAGE_SHIFT;
648
649 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
650}
651
652/**
653 * amdgpu_ttm_domain_start - Returns GPU start address
654 * @adev: amdgpu device object
655 * @type: type of the memory
656 *
657 * Returns:
658 * GPU start address of a memory domain
659 */
660
661uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
662{
663 switch (type) {
664 case TTM_PL_TT:
665 return adev->gmc.gart_start;
666 case TTM_PL_VRAM:
667 return adev->gmc.vram_start;
668 }
669
670 return 0;
671}
672
673/*
674 * TTM backend functions.
675 */
676struct amdgpu_ttm_tt {
677 struct ttm_tt ttm;
678 struct drm_gem_object *gobj;
679 u64 offset;
680 uint64_t userptr;
681 struct task_struct *usertask;
682 uint32_t userflags;
683 bool bound;
684 int32_t pool_id;
685};
686
687#define ttm_to_amdgpu_ttm_tt(ptr) container_of(ptr, struct amdgpu_ttm_tt, ttm)
688
689#ifdef CONFIG_DRM_AMDGPU_USERPTR
690/*
691 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
692 * memory and start HMM tracking CPU page table update
693 *
694 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
695 * once afterwards to stop HMM tracking
696 */
697int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,
698 struct hmm_range **range)
699{
700 struct ttm_tt *ttm = bo->tbo.ttm;
701 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
702 unsigned long start = gtt->userptr;
703 struct vm_area_struct *vma;
704 struct mm_struct *mm;
705 bool readonly;
706 int r = 0;
707
708 /* Make sure get_user_pages_done() can cleanup gracefully */
709 *range = NULL;
710
711 mm = bo->notifier.mm;
712 if (unlikely(!mm)) {
713 DRM_DEBUG_DRIVER("BO is not registered?\n");
714 return -EFAULT;
715 }
716
717 if (!mmget_not_zero(mm)) /* Happens during process shutdown */
718 return -ESRCH;
719
720 mmap_read_lock(mm);
721 vma = vma_lookup(mm, start);
722 if (unlikely(!vma)) {
723 r = -EFAULT;
724 goto out_unlock;
725 }
726 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
727 vma->vm_file)) {
728 r = -EPERM;
729 goto out_unlock;
730 }
731
732 readonly = amdgpu_ttm_tt_is_readonly(ttm);
733 r = amdgpu_hmm_range_get_pages(&bo->notifier, start, ttm->num_pages,
734 readonly, NULL, pages, range);
735out_unlock:
736 mmap_read_unlock(mm);
737 if (r)
738 pr_debug("failed %d to get user pages 0x%lx\n", r, start);
739
740 mmput(mm);
741
742 return r;
743}
744
745/* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations
746 */
747void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
748 struct hmm_range *range)
749{
750 struct amdgpu_ttm_tt *gtt = (void *)ttm;
751
752 if (gtt && gtt->userptr && range)
753 amdgpu_hmm_range_get_pages_done(range);
754}
755
756/*
757 * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change
758 * Check if the pages backing this ttm range have been invalidated
759 *
760 * Returns: true if pages are still valid
761 */
762bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
763 struct hmm_range *range)
764{
765 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
766
767 if (!gtt || !gtt->userptr || !range)
768 return false;
769
770 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
771 gtt->userptr, ttm->num_pages);
772
773 WARN_ONCE(!range->hmm_pfns, "No user pages to check\n");
774
775 return !amdgpu_hmm_range_get_pages_done(range);
776}
777#endif
778
779/*
780 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
781 *
782 * Called by amdgpu_cs_list_validate(). This creates the page list
783 * that backs user memory and will ultimately be mapped into the device
784 * address space.
785 */
786void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
787{
788 unsigned long i;
789
790 for (i = 0; i < ttm->num_pages; ++i)
791 ttm->pages[i] = pages ? pages[i] : NULL;
792}
793
794/*
795 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
796 *
797 * Called by amdgpu_ttm_backend_bind()
798 **/
799static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
800 struct ttm_tt *ttm)
801{
802 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
803 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
804 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
805 enum dma_data_direction direction = write ?
806 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
807 int r;
808
809 /* Allocate an SG array and squash pages into it */
810 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
811 (u64)ttm->num_pages << PAGE_SHIFT,
812 GFP_KERNEL);
813 if (r)
814 goto release_sg;
815
816 /* Map SG to device */
817 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
818 if (r)
819 goto release_sg_table;
820
821 /* convert SG to linear array of pages and dma addresses */
822 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
823 ttm->num_pages);
824
825 return 0;
826
827release_sg_table:
828 sg_free_table(ttm->sg);
829release_sg:
830 kfree(ttm->sg);
831 ttm->sg = NULL;
832 return r;
833}
834
835/*
836 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
837 */
838static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
839 struct ttm_tt *ttm)
840{
841 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
842 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
843 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
844 enum dma_data_direction direction = write ?
845 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
846
847 /* double check that we don't free the table twice */
848 if (!ttm->sg || !ttm->sg->sgl)
849 return;
850
851 /* unmap the pages mapped to the device */
852 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
853 sg_free_table(ttm->sg);
854}
855
856/*
857 * total_pages is constructed as MQD0+CtrlStack0 + MQD1+CtrlStack1 + ...
858 * MQDn+CtrlStackn where n is the number of XCCs per partition.
859 * pages_per_xcc is the size of one MQD+CtrlStack. The first page is MQD
860 * and uses memory type default, UC. The rest of pages_per_xcc are
861 * Ctrl stack and modify their memory type to NC.
862 */
863static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
864 struct ttm_tt *ttm, uint64_t flags)
865{
866 struct amdgpu_ttm_tt *gtt = (void *)ttm;
867 uint64_t total_pages = ttm->num_pages;
868 int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp);
869 uint64_t page_idx, pages_per_xcc;
870 int i;
871 uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC);
872
873 pages_per_xcc = total_pages;
874 do_div(pages_per_xcc, num_xcc);
875
876 for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) {
877 /* MQD page: use default flags */
878 amdgpu_gart_bind(adev,
879 gtt->offset + (page_idx << PAGE_SHIFT),
880 1, >t->ttm.dma_address[page_idx], flags);
881 /*
882 * Ctrl pages - modify the memory type to NC (ctrl_flags) from
883 * the second page of the BO onward.
884 */
885 amdgpu_gart_bind(adev,
886 gtt->offset + ((page_idx + 1) << PAGE_SHIFT),
887 pages_per_xcc - 1,
888 >t->ttm.dma_address[page_idx + 1],
889 ctrl_flags);
890 }
891}
892
893static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
894 struct ttm_buffer_object *tbo,
895 uint64_t flags)
896{
897 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
898 struct ttm_tt *ttm = tbo->ttm;
899 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
900
901 if (amdgpu_bo_encrypted(abo))
902 flags |= AMDGPU_PTE_TMZ;
903
904 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
905 amdgpu_ttm_gart_bind_gfx9_mqd(adev, ttm, flags);
906 } else {
907 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
908 gtt->ttm.dma_address, flags);
909 }
910 gtt->bound = true;
911}
912
913/*
914 * amdgpu_ttm_backend_bind - Bind GTT memory
915 *
916 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
917 * This handles binding GTT memory to the device address space.
918 */
919static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
920 struct ttm_tt *ttm,
921 struct ttm_resource *bo_mem)
922{
923 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
924 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
925 uint64_t flags;
926 int r;
927
928 if (!bo_mem)
929 return -EINVAL;
930
931 if (gtt->bound)
932 return 0;
933
934 if (gtt->userptr) {
935 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
936 if (r) {
937 DRM_ERROR("failed to pin userptr\n");
938 return r;
939 }
940 } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) {
941 if (!ttm->sg) {
942 struct dma_buf_attachment *attach;
943 struct sg_table *sgt;
944
945 attach = gtt->gobj->import_attach;
946 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
947 if (IS_ERR(sgt))
948 return PTR_ERR(sgt);
949
950 ttm->sg = sgt;
951 }
952
953 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
954 ttm->num_pages);
955 }
956
957 if (!ttm->num_pages) {
958 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
959 ttm->num_pages, bo_mem, ttm);
960 }
961
962 if (bo_mem->mem_type != TTM_PL_TT ||
963 !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
964 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
965 return 0;
966 }
967
968 /* compute PTE flags relevant to this BO memory */
969 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
970
971 /* bind pages into GART page tables */
972 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
973 amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
974 gtt->ttm.dma_address, flags);
975 gtt->bound = true;
976 return 0;
977}
978
979/*
980 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
981 * through AGP or GART aperture.
982 *
983 * If bo is accessible through AGP aperture, then use AGP aperture
984 * to access bo; otherwise allocate logical space in GART aperture
985 * and map bo to GART aperture.
986 */
987int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
988{
989 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
990 struct ttm_operation_ctx ctx = { false, false };
991 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
992 struct ttm_placement placement;
993 struct ttm_place placements;
994 struct ttm_resource *tmp;
995 uint64_t addr, flags;
996 int r;
997
998 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
999 return 0;
1000
1001 addr = amdgpu_gmc_agp_addr(bo);
1002 if (addr != AMDGPU_BO_INVALID_OFFSET)
1003 return 0;
1004
1005 /* allocate GART space */
1006 placement.num_placement = 1;
1007 placement.placement = &placements;
1008 placements.fpfn = 0;
1009 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1010 placements.mem_type = TTM_PL_TT;
1011 placements.flags = bo->resource->placement;
1012
1013 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1014 if (unlikely(r))
1015 return r;
1016
1017 /* compute PTE flags for this buffer object */
1018 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
1019
1020 /* Bind pages */
1021 gtt->offset = (u64)tmp->start << PAGE_SHIFT;
1022 amdgpu_ttm_gart_bind(adev, bo, flags);
1023 amdgpu_gart_invalidate_tlb(adev);
1024 ttm_resource_free(bo, &bo->resource);
1025 ttm_bo_assign_mem(bo, tmp);
1026
1027 return 0;
1028}
1029
1030/*
1031 * amdgpu_ttm_recover_gart - Rebind GTT pages
1032 *
1033 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1034 * rebind GTT pages during a GPU reset.
1035 */
1036void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1037{
1038 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1039 uint64_t flags;
1040
1041 if (!tbo->ttm)
1042 return;
1043
1044 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
1045 amdgpu_ttm_gart_bind(adev, tbo, flags);
1046}
1047
1048/*
1049 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1050 *
1051 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1052 * ttm_tt_destroy().
1053 */
1054static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1055 struct ttm_tt *ttm)
1056{
1057 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1058 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1059
1060 /* if the pages have userptr pinning then clear that first */
1061 if (gtt->userptr) {
1062 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1063 } else if (ttm->sg && gtt->gobj->import_attach) {
1064 struct dma_buf_attachment *attach;
1065
1066 attach = gtt->gobj->import_attach;
1067 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1068 ttm->sg = NULL;
1069 }
1070
1071 if (!gtt->bound)
1072 return;
1073
1074 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1075 return;
1076
1077 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1078 amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1079 gtt->bound = false;
1080}
1081
1082static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1083 struct ttm_tt *ttm)
1084{
1085 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1086
1087 if (gtt->usertask)
1088 put_task_struct(gtt->usertask);
1089
1090 ttm_tt_fini(>t->ttm);
1091 kfree(gtt);
1092}
1093
1094/**
1095 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1096 *
1097 * @bo: The buffer object to create a GTT ttm_tt object around
1098 * @page_flags: Page flags to be added to the ttm_tt object
1099 *
1100 * Called by ttm_tt_create().
1101 */
1102static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1103 uint32_t page_flags)
1104{
1105 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1106 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1107 struct amdgpu_ttm_tt *gtt;
1108 enum ttm_caching caching;
1109
1110 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1111 if (!gtt)
1112 return NULL;
1113
1114 gtt->gobj = &bo->base;
1115 if (adev->gmc.mem_partitions && abo->xcp_id >= 0)
1116 gtt->pool_id = KFD_XCP_MEM_ID(adev, abo->xcp_id);
1117 else
1118 gtt->pool_id = abo->xcp_id;
1119
1120 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1121 caching = ttm_write_combined;
1122 else
1123 caching = ttm_cached;
1124
1125 /* allocate space for the uninitialized page entries */
1126 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) {
1127 kfree(gtt);
1128 return NULL;
1129 }
1130 return >t->ttm;
1131}
1132
1133/*
1134 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1135 *
1136 * Map the pages of a ttm_tt object to an address space visible
1137 * to the underlying device.
1138 */
1139static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1140 struct ttm_tt *ttm,
1141 struct ttm_operation_ctx *ctx)
1142{
1143 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1144 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1145 struct ttm_pool *pool;
1146 pgoff_t i;
1147 int ret;
1148
1149 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1150 if (gtt->userptr) {
1151 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1152 if (!ttm->sg)
1153 return -ENOMEM;
1154 return 0;
1155 }
1156
1157 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1158 return 0;
1159
1160 if (adev->mman.ttm_pools && gtt->pool_id >= 0)
1161 pool = &adev->mman.ttm_pools[gtt->pool_id];
1162 else
1163 pool = &adev->mman.bdev.pool;
1164 ret = ttm_pool_alloc(pool, ttm, ctx);
1165 if (ret)
1166 return ret;
1167
1168 for (i = 0; i < ttm->num_pages; ++i)
1169 ttm->pages[i]->mapping = bdev->dev_mapping;
1170
1171 return 0;
1172}
1173
1174/*
1175 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1176 *
1177 * Unmaps pages of a ttm_tt object from the device address space and
1178 * unpopulates the page array backing it.
1179 */
1180static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1181 struct ttm_tt *ttm)
1182{
1183 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1184 struct amdgpu_device *adev;
1185 struct ttm_pool *pool;
1186 pgoff_t i;
1187
1188 amdgpu_ttm_backend_unbind(bdev, ttm);
1189
1190 if (gtt->userptr) {
1191 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1192 kfree(ttm->sg);
1193 ttm->sg = NULL;
1194 return;
1195 }
1196
1197 if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1198 return;
1199
1200 for (i = 0; i < ttm->num_pages; ++i)
1201 ttm->pages[i]->mapping = NULL;
1202
1203 adev = amdgpu_ttm_adev(bdev);
1204
1205 if (adev->mman.ttm_pools && gtt->pool_id >= 0)
1206 pool = &adev->mman.ttm_pools[gtt->pool_id];
1207 else
1208 pool = &adev->mman.bdev.pool;
1209
1210 return ttm_pool_free(pool, ttm);
1211}
1212
1213/**
1214 * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current
1215 * task
1216 *
1217 * @tbo: The ttm_buffer_object that contains the userptr
1218 * @user_addr: The returned value
1219 */
1220int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
1221 uint64_t *user_addr)
1222{
1223 struct amdgpu_ttm_tt *gtt;
1224
1225 if (!tbo->ttm)
1226 return -EINVAL;
1227
1228 gtt = (void *)tbo->ttm;
1229 *user_addr = gtt->userptr;
1230 return 0;
1231}
1232
1233/**
1234 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1235 * task
1236 *
1237 * @bo: The ttm_buffer_object to bind this userptr to
1238 * @addr: The address in the current tasks VM space to use
1239 * @flags: Requirements of userptr object.
1240 *
1241 * Called by amdgpu_gem_userptr_ioctl() and kfd_ioctl_alloc_memory_of_gpu() to
1242 * bind userptr pages to current task and by kfd_ioctl_acquire_vm() to
1243 * initialize GPU VM for a KFD process.
1244 */
1245int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1246 uint64_t addr, uint32_t flags)
1247{
1248 struct amdgpu_ttm_tt *gtt;
1249
1250 if (!bo->ttm) {
1251 /* TODO: We want a separate TTM object type for userptrs */
1252 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1253 if (bo->ttm == NULL)
1254 return -ENOMEM;
1255 }
1256
1257 /* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */
1258 bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL;
1259
1260 gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
1261 gtt->userptr = addr;
1262 gtt->userflags = flags;
1263
1264 if (gtt->usertask)
1265 put_task_struct(gtt->usertask);
1266 gtt->usertask = current->group_leader;
1267 get_task_struct(gtt->usertask);
1268
1269 return 0;
1270}
1271
1272/*
1273 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1274 */
1275struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1276{
1277 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1278
1279 if (gtt == NULL)
1280 return NULL;
1281
1282 if (gtt->usertask == NULL)
1283 return NULL;
1284
1285 return gtt->usertask->mm;
1286}
1287
1288/*
1289 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1290 * address range for the current task.
1291 *
1292 */
1293bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1294 unsigned long end, unsigned long *userptr)
1295{
1296 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1297 unsigned long size;
1298
1299 if (gtt == NULL || !gtt->userptr)
1300 return false;
1301
1302 /* Return false if no part of the ttm_tt object lies within
1303 * the range
1304 */
1305 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1306 if (gtt->userptr > end || gtt->userptr + size <= start)
1307 return false;
1308
1309 if (userptr)
1310 *userptr = gtt->userptr;
1311 return true;
1312}
1313
1314/*
1315 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1316 */
1317bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1318{
1319 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1320
1321 if (gtt == NULL || !gtt->userptr)
1322 return false;
1323
1324 return true;
1325}
1326
1327/*
1328 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1329 */
1330bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1331{
1332 struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1333
1334 if (gtt == NULL)
1335 return false;
1336
1337 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1338}
1339
1340/**
1341 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1342 *
1343 * @ttm: The ttm_tt object to compute the flags for
1344 * @mem: The memory registry backing this ttm_tt object
1345 *
1346 * Figure out the flags to use for a VM PDE (Page Directory Entry).
1347 */
1348uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1349{
1350 uint64_t flags = 0;
1351
1352 if (mem && mem->mem_type != TTM_PL_SYSTEM)
1353 flags |= AMDGPU_PTE_VALID;
1354
1355 if (mem && (mem->mem_type == TTM_PL_TT ||
1356 mem->mem_type == AMDGPU_PL_DOORBELL ||
1357 mem->mem_type == AMDGPU_PL_PREEMPT)) {
1358 flags |= AMDGPU_PTE_SYSTEM;
1359
1360 if (ttm->caching == ttm_cached)
1361 flags |= AMDGPU_PTE_SNOOPED;
1362 }
1363
1364 if (mem && mem->mem_type == TTM_PL_VRAM &&
1365 mem->bus.caching == ttm_cached)
1366 flags |= AMDGPU_PTE_SNOOPED;
1367
1368 return flags;
1369}
1370
1371/**
1372 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1373 *
1374 * @adev: amdgpu_device pointer
1375 * @ttm: The ttm_tt object to compute the flags for
1376 * @mem: The memory registry backing this ttm_tt object
1377 *
1378 * Figure out the flags to use for a VM PTE (Page Table Entry).
1379 */
1380uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1381 struct ttm_resource *mem)
1382{
1383 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1384
1385 flags |= adev->gart.gart_pte_flags;
1386 flags |= AMDGPU_PTE_READABLE;
1387
1388 if (!amdgpu_ttm_tt_is_readonly(ttm))
1389 flags |= AMDGPU_PTE_WRITEABLE;
1390
1391 return flags;
1392}
1393
1394/*
1395 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1396 * object.
1397 *
1398 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1399 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1400 * it can find space for a new object and by ttm_bo_force_list_clean() which is
1401 * used to clean out a memory space.
1402 */
1403static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1404 const struct ttm_place *place)
1405{
1406 struct dma_resv_iter resv_cursor;
1407 struct dma_fence *f;
1408
1409 if (!amdgpu_bo_is_amdgpu_bo(bo))
1410 return ttm_bo_eviction_valuable(bo, place);
1411
1412 /* Swapout? */
1413 if (bo->resource->mem_type == TTM_PL_SYSTEM)
1414 return true;
1415
1416 if (bo->type == ttm_bo_type_kernel &&
1417 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1418 return false;
1419
1420 /* If bo is a KFD BO, check if the bo belongs to the current process.
1421 * If true, then return false as any KFD process needs all its BOs to
1422 * be resident to run successfully
1423 */
1424 dma_resv_for_each_fence(&resv_cursor, bo->base.resv,
1425 DMA_RESV_USAGE_BOOKKEEP, f) {
1426 if (amdkfd_fence_check_mm(f, current->mm) &&
1427 !(place->flags & TTM_PL_FLAG_CONTIGUOUS))
1428 return false;
1429 }
1430
1431 /* Preemptible BOs don't own system resources managed by the
1432 * driver (pages, VRAM, GART space). They point to resources
1433 * owned by someone else (e.g. pageable memory in user mode
1434 * or a DMABuf). They are used in a preemptible context so we
1435 * can guarantee no deadlocks and good QoS in case of MMU
1436 * notifiers or DMABuf move notifiers from the resource owner.
1437 */
1438 if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
1439 return false;
1440
1441 if (bo->resource->mem_type == TTM_PL_TT &&
1442 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1443 return false;
1444
1445 return ttm_bo_eviction_valuable(bo, place);
1446}
1447
1448static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
1449 void *buf, size_t size, bool write)
1450{
1451 while (size) {
1452 uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
1453 uint64_t bytes = 4 - (pos & 0x3);
1454 uint32_t shift = (pos & 0x3) * 8;
1455 uint32_t mask = 0xffffffff << shift;
1456 uint32_t value = 0;
1457
1458 if (size < bytes) {
1459 mask &= 0xffffffff >> (bytes - size) * 8;
1460 bytes = size;
1461 }
1462
1463 if (mask != 0xffffffff) {
1464 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false);
1465 if (write) {
1466 value &= ~mask;
1467 value |= (*(uint32_t *)buf << shift) & mask;
1468 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true);
1469 } else {
1470 value = (value & mask) >> shift;
1471 memcpy(buf, &value, bytes);
1472 }
1473 } else {
1474 amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write);
1475 }
1476
1477 pos += bytes;
1478 buf += bytes;
1479 size -= bytes;
1480 }
1481}
1482
1483static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
1484 unsigned long offset, void *buf,
1485 int len, int write)
1486{
1487 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1488 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1489 struct amdgpu_res_cursor src_mm;
1490 struct amdgpu_job *job;
1491 struct dma_fence *fence;
1492 uint64_t src_addr, dst_addr;
1493 unsigned int num_dw;
1494 int r, idx;
1495
1496 if (len != PAGE_SIZE)
1497 return -EINVAL;
1498
1499 if (!adev->mman.sdma_access_ptr)
1500 return -EACCES;
1501
1502 if (!drm_dev_enter(adev_to_drm(adev), &idx))
1503 return -ENODEV;
1504
1505 if (write)
1506 memcpy(adev->mman.sdma_access_ptr, buf, len);
1507
1508 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
1509 r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
1510 AMDGPU_FENCE_OWNER_UNDEFINED,
1511 num_dw * 4, AMDGPU_IB_POOL_DELAYED,
1512 &job);
1513 if (r)
1514 goto out;
1515
1516 amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm);
1517 src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) +
1518 src_mm.start;
1519 dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo);
1520 if (write)
1521 swap(src_addr, dst_addr);
1522
1523 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr,
1524 PAGE_SIZE, 0);
1525
1526 amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]);
1527 WARN_ON(job->ibs[0].length_dw > num_dw);
1528
1529 fence = amdgpu_job_submit(job);
1530
1531 if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout))
1532 r = -ETIMEDOUT;
1533 dma_fence_put(fence);
1534
1535 if (!(r || write))
1536 memcpy(buf, adev->mman.sdma_access_ptr, len);
1537out:
1538 drm_dev_exit(idx);
1539 return r;
1540}
1541
1542/**
1543 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1544 *
1545 * @bo: The buffer object to read/write
1546 * @offset: Offset into buffer object
1547 * @buf: Secondary buffer to write/read from
1548 * @len: Length in bytes of access
1549 * @write: true if writing
1550 *
1551 * This is used to access VRAM that backs a buffer object via MMIO
1552 * access for debugging purposes.
1553 */
1554static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1555 unsigned long offset, void *buf, int len,
1556 int write)
1557{
1558 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1559 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1560 struct amdgpu_res_cursor cursor;
1561 int ret = 0;
1562
1563 if (bo->resource->mem_type != TTM_PL_VRAM)
1564 return -EIO;
1565
1566 if (amdgpu_device_has_timeouts_enabled(adev) &&
1567 !amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write))
1568 return len;
1569
1570 amdgpu_res_first(bo->resource, offset, len, &cursor);
1571 while (cursor.remaining) {
1572 size_t count, size = cursor.size;
1573 loff_t pos = cursor.start;
1574
1575 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
1576 size -= count;
1577 if (size) {
1578 /* using MM to access rest vram and handle un-aligned address */
1579 pos += count;
1580 buf += count;
1581 amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
1582 }
1583
1584 ret += cursor.size;
1585 buf += cursor.size;
1586 amdgpu_res_next(&cursor, cursor.size);
1587 }
1588
1589 return ret;
1590}
1591
1592static void
1593amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1594{
1595 amdgpu_bo_move_notify(bo, false, NULL);
1596}
1597
1598static struct ttm_device_funcs amdgpu_bo_driver = {
1599 .ttm_tt_create = &amdgpu_ttm_tt_create,
1600 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1601 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1602 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1603 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1604 .evict_flags = &amdgpu_evict_flags,
1605 .move = &amdgpu_bo_move,
1606 .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1607 .release_notify = &amdgpu_bo_release_notify,
1608 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1609 .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1610 .access_memory = &amdgpu_ttm_access_memory,
1611};
1612
1613/*
1614 * Firmware Reservation functions
1615 */
1616/**
1617 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1618 *
1619 * @adev: amdgpu_device pointer
1620 *
1621 * free fw reserved vram if it has been reserved.
1622 */
1623static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1624{
1625 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1626 NULL, &adev->mman.fw_vram_usage_va);
1627}
1628
1629/*
1630 * Driver Reservation functions
1631 */
1632/**
1633 * amdgpu_ttm_drv_reserve_vram_fini - free drv reserved vram
1634 *
1635 * @adev: amdgpu_device pointer
1636 *
1637 * free drv reserved vram if it has been reserved.
1638 */
1639static void amdgpu_ttm_drv_reserve_vram_fini(struct amdgpu_device *adev)
1640{
1641 amdgpu_bo_free_kernel(&adev->mman.drv_vram_usage_reserved_bo,
1642 NULL,
1643 &adev->mman.drv_vram_usage_va);
1644}
1645
1646/**
1647 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1648 *
1649 * @adev: amdgpu_device pointer
1650 *
1651 * create bo vram reservation from fw.
1652 */
1653static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1654{
1655 uint64_t vram_size = adev->gmc.visible_vram_size;
1656
1657 adev->mman.fw_vram_usage_va = NULL;
1658 adev->mman.fw_vram_usage_reserved_bo = NULL;
1659
1660 if (adev->mman.fw_vram_usage_size == 0 ||
1661 adev->mman.fw_vram_usage_size > vram_size)
1662 return 0;
1663
1664 return amdgpu_bo_create_kernel_at(adev,
1665 adev->mman.fw_vram_usage_start_offset,
1666 adev->mman.fw_vram_usage_size,
1667 &adev->mman.fw_vram_usage_reserved_bo,
1668 &adev->mman.fw_vram_usage_va);
1669}
1670
1671/**
1672 * amdgpu_ttm_drv_reserve_vram_init - create bo vram reservation from driver
1673 *
1674 * @adev: amdgpu_device pointer
1675 *
1676 * create bo vram reservation from drv.
1677 */
1678static int amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device *adev)
1679{
1680 u64 vram_size = adev->gmc.visible_vram_size;
1681
1682 adev->mman.drv_vram_usage_va = NULL;
1683 adev->mman.drv_vram_usage_reserved_bo = NULL;
1684
1685 if (adev->mman.drv_vram_usage_size == 0 ||
1686 adev->mman.drv_vram_usage_size > vram_size)
1687 return 0;
1688
1689 return amdgpu_bo_create_kernel_at(adev,
1690 adev->mman.drv_vram_usage_start_offset,
1691 adev->mman.drv_vram_usage_size,
1692 &adev->mman.drv_vram_usage_reserved_bo,
1693 &adev->mman.drv_vram_usage_va);
1694}
1695
1696/*
1697 * Memoy training reservation functions
1698 */
1699
1700/**
1701 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1702 *
1703 * @adev: amdgpu_device pointer
1704 *
1705 * free memory training reserved vram if it has been reserved.
1706 */
1707static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1708{
1709 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1710
1711 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1712 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1713 ctx->c2p_bo = NULL;
1714
1715 return 0;
1716}
1717
1718static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev,
1719 uint32_t reserve_size)
1720{
1721 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1722
1723 memset(ctx, 0, sizeof(*ctx));
1724
1725 ctx->c2p_train_data_offset =
1726 ALIGN((adev->gmc.mc_vram_size - reserve_size - SZ_1M), SZ_1M);
1727 ctx->p2c_train_data_offset =
1728 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1729 ctx->train_data_size =
1730 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1731
1732 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1733 ctx->train_data_size,
1734 ctx->p2c_train_data_offset,
1735 ctx->c2p_train_data_offset);
1736}
1737
1738/*
1739 * reserve TMR memory at the top of VRAM which holds
1740 * IP Discovery data and is protected by PSP.
1741 */
1742static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1743{
1744 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1745 bool mem_train_support = false;
1746 uint32_t reserve_size = 0;
1747 int ret;
1748
1749 if (adev->bios && !amdgpu_sriov_vf(adev)) {
1750 if (amdgpu_atomfirmware_mem_training_supported(adev))
1751 mem_train_support = true;
1752 else
1753 DRM_DEBUG("memory training does not support!\n");
1754 }
1755
1756 /*
1757 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1758 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1759 *
1760 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1761 * discovery data and G6 memory training data respectively
1762 */
1763 if (adev->bios)
1764 reserve_size =
1765 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1766
1767 if (!adev->bios &&
1768 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
1769 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)))
1770 reserve_size = max(reserve_size, (uint32_t)280 << 20);
1771 else if (!reserve_size)
1772 reserve_size = DISCOVERY_TMR_OFFSET;
1773
1774 if (mem_train_support) {
1775 /* reserve vram for mem train according to TMR location */
1776 amdgpu_ttm_training_data_block_init(adev, reserve_size);
1777 ret = amdgpu_bo_create_kernel_at(adev,
1778 ctx->c2p_train_data_offset,
1779 ctx->train_data_size,
1780 &ctx->c2p_bo,
1781 NULL);
1782 if (ret) {
1783 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1784 amdgpu_ttm_training_reserve_vram_fini(adev);
1785 return ret;
1786 }
1787 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1788 }
1789
1790 if (!adev->gmc.is_app_apu) {
1791 ret = amdgpu_bo_create_kernel_at(
1792 adev, adev->gmc.real_vram_size - reserve_size,
1793 reserve_size, &adev->mman.fw_reserved_memory, NULL);
1794 if (ret) {
1795 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1796 amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory,
1797 NULL, NULL);
1798 return ret;
1799 }
1800 } else {
1801 DRM_DEBUG_DRIVER("backdoor fw loading path for PSP TMR, no reservation needed\n");
1802 }
1803
1804 return 0;
1805}
1806
1807static int amdgpu_ttm_pools_init(struct amdgpu_device *adev)
1808{
1809 int i;
1810
1811 if (!adev->gmc.is_app_apu || !adev->gmc.num_mem_partitions)
1812 return 0;
1813
1814 adev->mman.ttm_pools = kcalloc(adev->gmc.num_mem_partitions,
1815 sizeof(*adev->mman.ttm_pools),
1816 GFP_KERNEL);
1817 if (!adev->mman.ttm_pools)
1818 return -ENOMEM;
1819
1820 for (i = 0; i < adev->gmc.num_mem_partitions; i++) {
1821 ttm_pool_init(&adev->mman.ttm_pools[i], adev->dev,
1822 adev->gmc.mem_partitions[i].numa.node,
1823 false, false);
1824 }
1825 return 0;
1826}
1827
1828static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev)
1829{
1830 int i;
1831
1832 if (!adev->gmc.is_app_apu || !adev->mman.ttm_pools)
1833 return;
1834
1835 for (i = 0; i < adev->gmc.num_mem_partitions; i++)
1836 ttm_pool_fini(&adev->mman.ttm_pools[i]);
1837
1838 kfree(adev->mman.ttm_pools);
1839 adev->mman.ttm_pools = NULL;
1840}
1841
1842/*
1843 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1844 * gtt/vram related fields.
1845 *
1846 * This initializes all of the memory space pools that the TTM layer
1847 * will need such as the GTT space (system memory mapped to the device),
1848 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1849 * can be mapped per VMID.
1850 */
1851int amdgpu_ttm_init(struct amdgpu_device *adev)
1852{
1853 uint64_t gtt_size;
1854 int r;
1855
1856 mutex_init(&adev->mman.gtt_window_lock);
1857
1858 dma_set_max_seg_size(adev->dev, UINT_MAX);
1859 /* No others user of address space so set it to 0 */
1860 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1861 adev_to_drm(adev)->anon_inode->i_mapping,
1862 adev_to_drm(adev)->vma_offset_manager,
1863 adev->need_swiotlb,
1864 dma_addressing_limited(adev->dev));
1865 if (r) {
1866 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1867 return r;
1868 }
1869
1870 r = amdgpu_ttm_pools_init(adev);
1871 if (r) {
1872 DRM_ERROR("failed to init ttm pools(%d).\n", r);
1873 return r;
1874 }
1875 adev->mman.initialized = true;
1876
1877 /* Initialize VRAM pool with all of VRAM divided into pages */
1878 r = amdgpu_vram_mgr_init(adev);
1879 if (r) {
1880 DRM_ERROR("Failed initializing VRAM heap.\n");
1881 return r;
1882 }
1883
1884 /* Change the size here instead of the init above so only lpfn is affected */
1885 amdgpu_ttm_set_buffer_funcs_status(adev, false);
1886#ifdef CONFIG_64BIT
1887#ifdef CONFIG_X86
1888 if (adev->gmc.xgmi.connected_to_cpu)
1889 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1890 adev->gmc.visible_vram_size);
1891
1892 else if (adev->gmc.is_app_apu)
1893 DRM_DEBUG_DRIVER(
1894 "No need to ioremap when real vram size is 0\n");
1895 else
1896#endif
1897 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1898 adev->gmc.visible_vram_size);
1899#endif
1900
1901 /*
1902 *The reserved vram for firmware must be pinned to the specified
1903 *place on the VRAM, so reserve it early.
1904 */
1905 r = amdgpu_ttm_fw_reserve_vram_init(adev);
1906 if (r)
1907 return r;
1908
1909 /*
1910 *The reserved vram for driver must be pinned to the specified
1911 *place on the VRAM, so reserve it early.
1912 */
1913 r = amdgpu_ttm_drv_reserve_vram_init(adev);
1914 if (r)
1915 return r;
1916
1917 /*
1918 * only NAVI10 and onwards ASIC support for IP discovery.
1919 * If IP discovery enabled, a block of memory should be
1920 * reserved for IP discovey.
1921 */
1922 if (adev->mman.discovery_bin) {
1923 r = amdgpu_ttm_reserve_tmr(adev);
1924 if (r)
1925 return r;
1926 }
1927
1928 /* allocate memory as required for VGA
1929 * This is used for VGA emulation and pre-OS scanout buffers to
1930 * avoid display artifacts while transitioning between pre-OS
1931 * and driver.
1932 */
1933 if (!adev->gmc.is_app_apu) {
1934 r = amdgpu_bo_create_kernel_at(adev, 0,
1935 adev->mman.stolen_vga_size,
1936 &adev->mman.stolen_vga_memory,
1937 NULL);
1938 if (r)
1939 return r;
1940
1941 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1942 adev->mman.stolen_extended_size,
1943 &adev->mman.stolen_extended_memory,
1944 NULL);
1945
1946 if (r)
1947 return r;
1948
1949 r = amdgpu_bo_create_kernel_at(adev,
1950 adev->mman.stolen_reserved_offset,
1951 adev->mman.stolen_reserved_size,
1952 &adev->mman.stolen_reserved_memory,
1953 NULL);
1954 if (r)
1955 return r;
1956 } else {
1957 DRM_DEBUG_DRIVER("Skipped stolen memory reservation\n");
1958 }
1959
1960 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1961 (unsigned int)(adev->gmc.real_vram_size / (1024 * 1024)));
1962
1963 /* Compute GTT size, either based on TTM limit
1964 * or whatever the user passed on module init.
1965 */
1966 if (amdgpu_gtt_size == -1)
1967 gtt_size = ttm_tt_pages_limit() << PAGE_SHIFT;
1968 else
1969 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1970
1971 /* Initialize GTT memory pool */
1972 r = amdgpu_gtt_mgr_init(adev, gtt_size);
1973 if (r) {
1974 DRM_ERROR("Failed initializing GTT heap.\n");
1975 return r;
1976 }
1977 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1978 (unsigned int)(gtt_size / (1024 * 1024)));
1979
1980 /* Initialize doorbell pool on PCI BAR */
1981 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_DOORBELL, adev->doorbell.size / PAGE_SIZE);
1982 if (r) {
1983 DRM_ERROR("Failed initializing doorbell heap.\n");
1984 return r;
1985 }
1986
1987 /* Create a boorbell page for kernel usages */
1988 r = amdgpu_doorbell_create_kernel_doorbells(adev);
1989 if (r) {
1990 DRM_ERROR("Failed to initialize kernel doorbells.\n");
1991 return r;
1992 }
1993
1994 /* Initialize preemptible memory pool */
1995 r = amdgpu_preempt_mgr_init(adev);
1996 if (r) {
1997 DRM_ERROR("Failed initializing PREEMPT heap.\n");
1998 return r;
1999 }
2000
2001 /* Initialize various on-chip memory pools */
2002 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
2003 if (r) {
2004 DRM_ERROR("Failed initializing GDS heap.\n");
2005 return r;
2006 }
2007
2008 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
2009 if (r) {
2010 DRM_ERROR("Failed initializing gws heap.\n");
2011 return r;
2012 }
2013
2014 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
2015 if (r) {
2016 DRM_ERROR("Failed initializing oa heap.\n");
2017 return r;
2018 }
2019 if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
2020 AMDGPU_GEM_DOMAIN_GTT,
2021 &adev->mman.sdma_access_bo, NULL,
2022 &adev->mman.sdma_access_ptr))
2023 DRM_WARN("Debug VRAM access will use slowpath MM access\n");
2024
2025 return 0;
2026}
2027
2028/*
2029 * amdgpu_ttm_fini - De-initialize the TTM memory pools
2030 */
2031void amdgpu_ttm_fini(struct amdgpu_device *adev)
2032{
2033 int idx;
2034
2035 if (!adev->mman.initialized)
2036 return;
2037
2038 amdgpu_ttm_pools_fini(adev);
2039
2040 amdgpu_ttm_training_reserve_vram_fini(adev);
2041 /* return the stolen vga memory back to VRAM */
2042 if (!adev->gmc.is_app_apu) {
2043 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2044 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
2045 /* return the FW reserved memory back to VRAM */
2046 amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL,
2047 NULL);
2048 if (adev->mman.stolen_reserved_size)
2049 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
2050 NULL, NULL);
2051 }
2052 amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL,
2053 &adev->mman.sdma_access_ptr);
2054 amdgpu_ttm_fw_reserve_vram_fini(adev);
2055 amdgpu_ttm_drv_reserve_vram_fini(adev);
2056
2057 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
2058
2059 if (adev->mman.aper_base_kaddr)
2060 iounmap(adev->mman.aper_base_kaddr);
2061 adev->mman.aper_base_kaddr = NULL;
2062
2063 drm_dev_exit(idx);
2064 }
2065
2066 amdgpu_vram_mgr_fini(adev);
2067 amdgpu_gtt_mgr_fini(adev);
2068 amdgpu_preempt_mgr_fini(adev);
2069 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
2070 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
2071 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
2072 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DOORBELL);
2073 ttm_device_fini(&adev->mman.bdev);
2074 adev->mman.initialized = false;
2075 DRM_INFO("amdgpu: ttm finalized\n");
2076}
2077
2078/**
2079 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2080 *
2081 * @adev: amdgpu_device pointer
2082 * @enable: true when we can use buffer functions.
2083 *
2084 * Enable/disable use of buffer functions during suspend/resume. This should
2085 * only be called at bootup or when userspace isn't running.
2086 */
2087void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2088{
2089 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2090 uint64_t size;
2091 int r;
2092
2093 if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
2094 adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu)
2095 return;
2096
2097 if (enable) {
2098 struct amdgpu_ring *ring;
2099 struct drm_gpu_scheduler *sched;
2100
2101 ring = adev->mman.buffer_funcs_ring;
2102 sched = &ring->sched;
2103 r = drm_sched_entity_init(&adev->mman.high_pr,
2104 DRM_SCHED_PRIORITY_KERNEL, &sched,
2105 1, NULL);
2106 if (r) {
2107 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2108 r);
2109 return;
2110 }
2111
2112 r = drm_sched_entity_init(&adev->mman.low_pr,
2113 DRM_SCHED_PRIORITY_NORMAL, &sched,
2114 1, NULL);
2115 if (r) {
2116 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2117 r);
2118 goto error_free_entity;
2119 }
2120 } else {
2121 drm_sched_entity_destroy(&adev->mman.high_pr);
2122 drm_sched_entity_destroy(&adev->mman.low_pr);
2123 dma_fence_put(man->move);
2124 man->move = NULL;
2125 }
2126
2127 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2128 if (enable)
2129 size = adev->gmc.real_vram_size;
2130 else
2131 size = adev->gmc.visible_vram_size;
2132 man->size = size;
2133 adev->mman.buffer_funcs_enabled = enable;
2134
2135 return;
2136
2137error_free_entity:
2138 drm_sched_entity_destroy(&adev->mman.high_pr);
2139}
2140
2141static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
2142 bool direct_submit,
2143 unsigned int num_dw,
2144 struct dma_resv *resv,
2145 bool vm_needs_flush,
2146 struct amdgpu_job **job,
2147 bool delayed)
2148{
2149 enum amdgpu_ib_pool_type pool = direct_submit ?
2150 AMDGPU_IB_POOL_DIRECT :
2151 AMDGPU_IB_POOL_DELAYED;
2152 int r;
2153 struct drm_sched_entity *entity = delayed ? &adev->mman.low_pr :
2154 &adev->mman.high_pr;
2155 r = amdgpu_job_alloc_with_ib(adev, entity,
2156 AMDGPU_FENCE_OWNER_UNDEFINED,
2157 num_dw * 4, pool, job);
2158 if (r)
2159 return r;
2160
2161 if (vm_needs_flush) {
2162 (*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
2163 adev->gmc.pdb0_bo :
2164 adev->gart.bo);
2165 (*job)->vm_needs_flush = true;
2166 }
2167 if (!resv)
2168 return 0;
2169
2170 return drm_sched_job_add_resv_dependencies(&(*job)->base, resv,
2171 DMA_RESV_USAGE_BOOKKEEP);
2172}
2173
2174int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2175 uint64_t dst_offset, uint32_t byte_count,
2176 struct dma_resv *resv,
2177 struct dma_fence **fence, bool direct_submit,
2178 bool vm_needs_flush, uint32_t copy_flags)
2179{
2180 struct amdgpu_device *adev = ring->adev;
2181 unsigned int num_loops, num_dw;
2182 struct amdgpu_job *job;
2183 uint32_t max_bytes;
2184 unsigned int i;
2185 int r;
2186
2187 if (!direct_submit && !ring->sched.ready) {
2188 DRM_ERROR("Trying to move memory with ring turned off.\n");
2189 return -EINVAL;
2190 }
2191
2192 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2193 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2194 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2195 r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,
2196 resv, vm_needs_flush, &job, false);
2197 if (r)
2198 return r;
2199
2200 for (i = 0; i < num_loops; i++) {
2201 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2202
2203 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2204 dst_offset, cur_size_in_bytes, copy_flags);
2205 src_offset += cur_size_in_bytes;
2206 dst_offset += cur_size_in_bytes;
2207 byte_count -= cur_size_in_bytes;
2208 }
2209
2210 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2211 WARN_ON(job->ibs[0].length_dw > num_dw);
2212 if (direct_submit)
2213 r = amdgpu_job_submit_direct(job, ring, fence);
2214 else
2215 *fence = amdgpu_job_submit(job);
2216 if (r)
2217 goto error_free;
2218
2219 return r;
2220
2221error_free:
2222 amdgpu_job_free(job);
2223 DRM_ERROR("Error scheduling IBs (%d)\n", r);
2224 return r;
2225}
2226
2227static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
2228 uint64_t dst_addr, uint32_t byte_count,
2229 struct dma_resv *resv,
2230 struct dma_fence **fence,
2231 bool vm_needs_flush, bool delayed)
2232{
2233 struct amdgpu_device *adev = ring->adev;
2234 unsigned int num_loops, num_dw;
2235 struct amdgpu_job *job;
2236 uint32_t max_bytes;
2237 unsigned int i;
2238 int r;
2239
2240 max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2241 num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
2242 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
2243 r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
2244 &job, delayed);
2245 if (r)
2246 return r;
2247
2248 for (i = 0; i < num_loops; i++) {
2249 uint32_t cur_size = min(byte_count, max_bytes);
2250
2251 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2252 cur_size);
2253
2254 dst_addr += cur_size;
2255 byte_count -= cur_size;
2256 }
2257
2258 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2259 WARN_ON(job->ibs[0].length_dw > num_dw);
2260 *fence = amdgpu_job_submit(job);
2261 return 0;
2262}
2263
2264/**
2265 * amdgpu_ttm_clear_buffer - clear memory buffers
2266 * @bo: amdgpu buffer object
2267 * @resv: reservation object
2268 * @fence: dma_fence associated with the operation
2269 *
2270 * Clear the memory buffer resource.
2271 *
2272 * Returns:
2273 * 0 for success or a negative error code on failure.
2274 */
2275int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
2276 struct dma_resv *resv,
2277 struct dma_fence **fence)
2278{
2279 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2280 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2281 struct amdgpu_res_cursor cursor;
2282 u64 addr;
2283 int r = 0;
2284
2285 if (!adev->mman.buffer_funcs_enabled)
2286 return -EINVAL;
2287
2288 if (!fence)
2289 return -EINVAL;
2290
2291 *fence = dma_fence_get_stub();
2292
2293 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor);
2294
2295 mutex_lock(&adev->mman.gtt_window_lock);
2296 while (cursor.remaining) {
2297 struct dma_fence *next = NULL;
2298 u64 size;
2299
2300 if (amdgpu_res_cleared(&cursor)) {
2301 amdgpu_res_next(&cursor, cursor.size);
2302 continue;
2303 }
2304
2305 /* Never clear more than 256MiB at once to avoid timeouts */
2306 size = min(cursor.size, 256ULL << 20);
2307
2308 r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &cursor,
2309 1, ring, false, &size, &addr);
2310 if (r)
2311 goto err;
2312
2313 r = amdgpu_ttm_fill_mem(ring, 0, addr, size, resv,
2314 &next, true, true);
2315 if (r)
2316 goto err;
2317
2318 dma_fence_put(*fence);
2319 *fence = next;
2320
2321 amdgpu_res_next(&cursor, size);
2322 }
2323err:
2324 mutex_unlock(&adev->mman.gtt_window_lock);
2325
2326 return r;
2327}
2328
2329int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2330 uint32_t src_data,
2331 struct dma_resv *resv,
2332 struct dma_fence **f,
2333 bool delayed)
2334{
2335 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2336 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2337 struct dma_fence *fence = NULL;
2338 struct amdgpu_res_cursor dst;
2339 int r;
2340
2341 if (!adev->mman.buffer_funcs_enabled) {
2342 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2343 return -EINVAL;
2344 }
2345
2346 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
2347
2348 mutex_lock(&adev->mman.gtt_window_lock);
2349 while (dst.remaining) {
2350 struct dma_fence *next;
2351 uint64_t cur_size, to;
2352
2353 /* Never fill more than 256MiB at once to avoid timeouts */
2354 cur_size = min(dst.size, 256ULL << 20);
2355
2356 r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst,
2357 1, ring, false, &cur_size, &to);
2358 if (r)
2359 goto error;
2360
2361 r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv,
2362 &next, true, delayed);
2363 if (r)
2364 goto error;
2365
2366 dma_fence_put(fence);
2367 fence = next;
2368
2369 amdgpu_res_next(&dst, cur_size);
2370 }
2371error:
2372 mutex_unlock(&adev->mman.gtt_window_lock);
2373 if (f)
2374 *f = dma_fence_get(fence);
2375 dma_fence_put(fence);
2376 return r;
2377}
2378
2379/**
2380 * amdgpu_ttm_evict_resources - evict memory buffers
2381 * @adev: amdgpu device object
2382 * @mem_type: evicted BO's memory type
2383 *
2384 * Evicts all @mem_type buffers on the lru list of the memory type.
2385 *
2386 * Returns:
2387 * 0 for success or a negative error code on failure.
2388 */
2389int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type)
2390{
2391 struct ttm_resource_manager *man;
2392
2393 switch (mem_type) {
2394 case TTM_PL_VRAM:
2395 case TTM_PL_TT:
2396 case AMDGPU_PL_GWS:
2397 case AMDGPU_PL_GDS:
2398 case AMDGPU_PL_OA:
2399 man = ttm_manager_type(&adev->mman.bdev, mem_type);
2400 break;
2401 default:
2402 DRM_ERROR("Trying to evict invalid memory type\n");
2403 return -EINVAL;
2404 }
2405
2406 return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
2407}
2408
2409#if defined(CONFIG_DEBUG_FS)
2410
2411static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2412{
2413 struct amdgpu_device *adev = m->private;
2414
2415 return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2416}
2417
2418DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2419
2420/*
2421 * amdgpu_ttm_vram_read - Linear read access to VRAM
2422 *
2423 * Accesses VRAM via MMIO for debugging purposes.
2424 */
2425static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2426 size_t size, loff_t *pos)
2427{
2428 struct amdgpu_device *adev = file_inode(f)->i_private;
2429 ssize_t result = 0;
2430
2431 if (size & 0x3 || *pos & 0x3)
2432 return -EINVAL;
2433
2434 if (*pos >= adev->gmc.mc_vram_size)
2435 return -ENXIO;
2436
2437 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2438 while (size) {
2439 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2440 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2441
2442 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2443 if (copy_to_user(buf, value, bytes))
2444 return -EFAULT;
2445
2446 result += bytes;
2447 buf += bytes;
2448 *pos += bytes;
2449 size -= bytes;
2450 }
2451
2452 return result;
2453}
2454
2455/*
2456 * amdgpu_ttm_vram_write - Linear write access to VRAM
2457 *
2458 * Accesses VRAM via MMIO for debugging purposes.
2459 */
2460static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2461 size_t size, loff_t *pos)
2462{
2463 struct amdgpu_device *adev = file_inode(f)->i_private;
2464 ssize_t result = 0;
2465 int r;
2466
2467 if (size & 0x3 || *pos & 0x3)
2468 return -EINVAL;
2469
2470 if (*pos >= adev->gmc.mc_vram_size)
2471 return -ENXIO;
2472
2473 while (size) {
2474 uint32_t value;
2475
2476 if (*pos >= adev->gmc.mc_vram_size)
2477 return result;
2478
2479 r = get_user(value, (uint32_t *)buf);
2480 if (r)
2481 return r;
2482
2483 amdgpu_device_mm_access(adev, *pos, &value, 4, true);
2484
2485 result += 4;
2486 buf += 4;
2487 *pos += 4;
2488 size -= 4;
2489 }
2490
2491 return result;
2492}
2493
2494static const struct file_operations amdgpu_ttm_vram_fops = {
2495 .owner = THIS_MODULE,
2496 .read = amdgpu_ttm_vram_read,
2497 .write = amdgpu_ttm_vram_write,
2498 .llseek = default_llseek,
2499};
2500
2501/*
2502 * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2503 *
2504 * This function is used to read memory that has been mapped to the
2505 * GPU and the known addresses are not physical addresses but instead
2506 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2507 */
2508static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2509 size_t size, loff_t *pos)
2510{
2511 struct amdgpu_device *adev = file_inode(f)->i_private;
2512 struct iommu_domain *dom;
2513 ssize_t result = 0;
2514 int r;
2515
2516 /* retrieve the IOMMU domain if any for this device */
2517 dom = iommu_get_domain_for_dev(adev->dev);
2518
2519 while (size) {
2520 phys_addr_t addr = *pos & PAGE_MASK;
2521 loff_t off = *pos & ~PAGE_MASK;
2522 size_t bytes = PAGE_SIZE - off;
2523 unsigned long pfn;
2524 struct page *p;
2525 void *ptr;
2526
2527 bytes = min(bytes, size);
2528
2529 /* Translate the bus address to a physical address. If
2530 * the domain is NULL it means there is no IOMMU active
2531 * and the address translation is the identity
2532 */
2533 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2534
2535 pfn = addr >> PAGE_SHIFT;
2536 if (!pfn_valid(pfn))
2537 return -EPERM;
2538
2539 p = pfn_to_page(pfn);
2540 if (p->mapping != adev->mman.bdev.dev_mapping)
2541 return -EPERM;
2542
2543 ptr = kmap_local_page(p);
2544 r = copy_to_user(buf, ptr + off, bytes);
2545 kunmap_local(ptr);
2546 if (r)
2547 return -EFAULT;
2548
2549 size -= bytes;
2550 *pos += bytes;
2551 result += bytes;
2552 }
2553
2554 return result;
2555}
2556
2557/*
2558 * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2559 *
2560 * This function is used to write memory that has been mapped to the
2561 * GPU and the known addresses are not physical addresses but instead
2562 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2563 */
2564static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2565 size_t size, loff_t *pos)
2566{
2567 struct amdgpu_device *adev = file_inode(f)->i_private;
2568 struct iommu_domain *dom;
2569 ssize_t result = 0;
2570 int r;
2571
2572 dom = iommu_get_domain_for_dev(adev->dev);
2573
2574 while (size) {
2575 phys_addr_t addr = *pos & PAGE_MASK;
2576 loff_t off = *pos & ~PAGE_MASK;
2577 size_t bytes = PAGE_SIZE - off;
2578 unsigned long pfn;
2579 struct page *p;
2580 void *ptr;
2581
2582 bytes = min(bytes, size);
2583
2584 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2585
2586 pfn = addr >> PAGE_SHIFT;
2587 if (!pfn_valid(pfn))
2588 return -EPERM;
2589
2590 p = pfn_to_page(pfn);
2591 if (p->mapping != adev->mman.bdev.dev_mapping)
2592 return -EPERM;
2593
2594 ptr = kmap_local_page(p);
2595 r = copy_from_user(ptr + off, buf, bytes);
2596 kunmap_local(ptr);
2597 if (r)
2598 return -EFAULT;
2599
2600 size -= bytes;
2601 *pos += bytes;
2602 result += bytes;
2603 }
2604
2605 return result;
2606}
2607
2608static const struct file_operations amdgpu_ttm_iomem_fops = {
2609 .owner = THIS_MODULE,
2610 .read = amdgpu_iomem_read,
2611 .write = amdgpu_iomem_write,
2612 .llseek = default_llseek
2613};
2614
2615#endif
2616
2617void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2618{
2619#if defined(CONFIG_DEBUG_FS)
2620 struct drm_minor *minor = adev_to_drm(adev)->primary;
2621 struct dentry *root = minor->debugfs_root;
2622
2623 debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2624 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2625 debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2626 &amdgpu_ttm_iomem_fops);
2627 debugfs_create_file("ttm_page_pool", 0444, root, adev,
2628 &amdgpu_ttm_page_pool_fops);
2629 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2630 TTM_PL_VRAM),
2631 root, "amdgpu_vram_mm");
2632 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2633 TTM_PL_TT),
2634 root, "amdgpu_gtt_mm");
2635 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2636 AMDGPU_PL_GDS),
2637 root, "amdgpu_gds_mm");
2638 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2639 AMDGPU_PL_GWS),
2640 root, "amdgpu_gws_mm");
2641 ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2642 AMDGPU_PL_OA),
2643 root, "amdgpu_oa_mm");
2644
2645#endif
2646}