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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu_ras_eeprom.h"
25#include "amdgpu.h"
26#include "amdgpu_ras.h"
27#include <linux/bits.h>
28#include "atom.h"
29
30#define EEPROM_I2C_TARGET_ADDR_VEGA20 0xA0
31#define EEPROM_I2C_TARGET_ADDR_ARCTURUS 0xA8
32#define EEPROM_I2C_TARGET_ADDR_ARCTURUS_D342 0xA0
33
34/*
35 * The 2 macros bellow represent the actual size in bytes that
36 * those entities occupy in the EEPROM memory.
37 * EEPROM_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
38 * uses uint64 to store 6b fields such as retired_page.
39 */
40#define EEPROM_TABLE_HEADER_SIZE 20
41#define EEPROM_TABLE_RECORD_SIZE 24
42
43#define EEPROM_ADDRESS_SIZE 0x2
44
45/* Table hdr is 'AMDR' */
46#define EEPROM_TABLE_HDR_VAL 0x414d4452
47#define EEPROM_TABLE_VER 0x00010000
48
49/* Assume 2 Mbit size */
50#define EEPROM_SIZE_BYTES 256000
51#define EEPROM_PAGE__SIZE_BYTES 256
52#define EEPROM_HDR_START 0
53#define EEPROM_RECORD_START (EEPROM_HDR_START + EEPROM_TABLE_HEADER_SIZE)
54#define EEPROM_MAX_RECORD_NUM ((EEPROM_SIZE_BYTES - EEPROM_TABLE_HEADER_SIZE) / EEPROM_TABLE_RECORD_SIZE)
55#define EEPROM_ADDR_MSB_MASK GENMASK(17, 8)
56
57#define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev
58
59static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev,
60 uint16_t *i2c_addr)
61{
62 struct atom_context *atom_ctx = adev->mode_info.atom_context;
63
64 if (!i2c_addr || !atom_ctx)
65 return false;
66
67 if (strnstr(atom_ctx->vbios_version,
68 "D342",
69 sizeof(atom_ctx->vbios_version)))
70 *i2c_addr = EEPROM_I2C_TARGET_ADDR_ARCTURUS_D342;
71 else
72 *i2c_addr = EEPROM_I2C_TARGET_ADDR_ARCTURUS;
73
74 return true;
75}
76
77static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
78 uint16_t *i2c_addr)
79{
80 if (!i2c_addr)
81 return false;
82
83 switch (adev->asic_type) {
84 case CHIP_VEGA20:
85 *i2c_addr = EEPROM_I2C_TARGET_ADDR_VEGA20;
86 break;
87
88 case CHIP_ARCTURUS:
89 return __get_eeprom_i2c_addr_arct(adev, i2c_addr);
90
91 default:
92 return false;
93 }
94
95 return true;
96}
97
98static void __encode_table_header_to_buff(struct amdgpu_ras_eeprom_table_header *hdr,
99 unsigned char *buff)
100{
101 uint32_t *pp = (uint32_t *) buff;
102
103 pp[0] = cpu_to_le32(hdr->header);
104 pp[1] = cpu_to_le32(hdr->version);
105 pp[2] = cpu_to_le32(hdr->first_rec_offset);
106 pp[3] = cpu_to_le32(hdr->tbl_size);
107 pp[4] = cpu_to_le32(hdr->checksum);
108}
109
110static void __decode_table_header_from_buff(struct amdgpu_ras_eeprom_table_header *hdr,
111 unsigned char *buff)
112{
113 uint32_t *pp = (uint32_t *)buff;
114
115 hdr->header = le32_to_cpu(pp[0]);
116 hdr->version = le32_to_cpu(pp[1]);
117 hdr->first_rec_offset = le32_to_cpu(pp[2]);
118 hdr->tbl_size = le32_to_cpu(pp[3]);
119 hdr->checksum = le32_to_cpu(pp[4]);
120}
121
122static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
123 unsigned char *buff)
124{
125 int ret = 0;
126 struct amdgpu_device *adev = to_amdgpu_device(control);
127 struct i2c_msg msg = {
128 .addr = 0,
129 .flags = 0,
130 .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
131 .buf = buff,
132 };
133
134
135 *(uint16_t *)buff = EEPROM_HDR_START;
136 __encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE);
137
138 msg.addr = control->i2c_address;
139
140 ret = i2c_transfer(&adev->pm.smu_i2c, &msg, 1);
141 if (ret < 1)
142 DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret);
143
144 return ret;
145}
146
147static uint32_t __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control)
148{
149 int i;
150 uint32_t tbl_sum = 0;
151
152 /* Header checksum, skip checksum field in the calculation */
153 for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++)
154 tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i);
155
156 return tbl_sum;
157}
158
159static uint32_t __calc_recs_byte_sum(struct eeprom_table_record *records,
160 int num)
161{
162 int i, j;
163 uint32_t tbl_sum = 0;
164
165 /* Records checksum */
166 for (i = 0; i < num; i++) {
167 struct eeprom_table_record *record = &records[i];
168
169 for (j = 0; j < sizeof(*record); j++) {
170 tbl_sum += *(((unsigned char *)record) + j);
171 }
172 }
173
174 return tbl_sum;
175}
176
177static inline uint32_t __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control,
178 struct eeprom_table_record *records, int num)
179{
180 return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num);
181}
182
183/* Checksum = 256 -((sum of all table entries) mod 256)Â */
184static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
185 struct eeprom_table_record *records, int num,
186 uint32_t old_hdr_byte_sum)
187{
188 /*
189 * This will update the table sum with new records.
190 *
191 * TODO: What happens when the EEPROM table is to be wrapped around
192 * and old records from start will get overridden.
193 */
194
195 /* need to recalculate updated header byte sum */
196 control->tbl_byte_sum -= old_hdr_byte_sum;
197 control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num);
198
199 control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256);
200}
201
202/* table sum mod 256 + checksum must equals 256 */
203static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
204 struct eeprom_table_record *records, int num)
205{
206 control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num);
207
208 if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) {
209 DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum);
210 return false;
211 }
212
213 return true;
214}
215
216int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
217{
218 unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
219 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
220 int ret = 0;
221
222 mutex_lock(&control->tbl_mutex);
223
224 hdr->header = EEPROM_TABLE_HDR_VAL;
225 hdr->version = EEPROM_TABLE_VER;
226 hdr->first_rec_offset = EEPROM_RECORD_START;
227 hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE;
228
229 control->tbl_byte_sum = 0;
230 __update_tbl_checksum(control, NULL, 0, 0);
231 control->next_addr = EEPROM_RECORD_START;
232
233 ret = __update_table_header(control, buff);
234
235 mutex_unlock(&control->tbl_mutex);
236
237 return ret;
238
239}
240
241int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
242{
243 int ret = 0;
244 struct amdgpu_device *adev = to_amdgpu_device(control);
245 unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
246 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
247 struct i2c_msg msg = {
248 .addr = 0,
249 .flags = I2C_M_RD,
250 .len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
251 .buf = buff,
252 };
253
254 /* Verify i2c adapter is initialized */
255 if (!adev->pm.smu_i2c.algo)
256 return -ENOENT;
257
258 if (!__get_eeprom_i2c_addr(adev, &control->i2c_address))
259 return -EINVAL;
260
261 mutex_init(&control->tbl_mutex);
262
263 msg.addr = control->i2c_address;
264 /* Read/Create table header from EEPROM address 0 */
265 ret = i2c_transfer(&adev->pm.smu_i2c, &msg, 1);
266 if (ret < 1) {
267 DRM_ERROR("Failed to read EEPROM table header, ret:%d", ret);
268 return ret;
269 }
270
271 __decode_table_header_from_buff(hdr, &buff[2]);
272
273 if (hdr->header == EEPROM_TABLE_HDR_VAL) {
274 control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) /
275 EEPROM_TABLE_RECORD_SIZE;
276 control->tbl_byte_sum = __calc_hdr_byte_sum(control);
277 control->next_addr = EEPROM_RECORD_START;
278
279 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
280 control->num_recs);
281
282 } else {
283 DRM_INFO("Creating new EEPROM table");
284
285 ret = amdgpu_ras_eeprom_reset_table(control);
286 }
287
288 return ret == 1 ? 0 : -EIO;
289}
290
291static void __encode_table_record_to_buff(struct amdgpu_ras_eeprom_control *control,
292 struct eeprom_table_record *record,
293 unsigned char *buff)
294{
295 __le64 tmp = 0;
296 int i = 0;
297
298 /* Next are all record fields according to EEPROM page spec in LE foramt */
299 buff[i++] = record->err_type;
300
301 buff[i++] = record->bank;
302
303 tmp = cpu_to_le64(record->ts);
304 memcpy(buff + i, &tmp, 8);
305 i += 8;
306
307 tmp = cpu_to_le64((record->offset & 0xffffffffffff));
308 memcpy(buff + i, &tmp, 6);
309 i += 6;
310
311 buff[i++] = record->mem_channel;
312 buff[i++] = record->mcumc_id;
313
314 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
315 memcpy(buff + i, &tmp, 6);
316}
317
318static void __decode_table_record_from_buff(struct amdgpu_ras_eeprom_control *control,
319 struct eeprom_table_record *record,
320 unsigned char *buff)
321{
322 __le64 tmp = 0;
323 int i = 0;
324
325 /* Next are all record fields according to EEPROM page spec in LE foramt */
326 record->err_type = buff[i++];
327
328 record->bank = buff[i++];
329
330 memcpy(&tmp, buff + i, 8);
331 record->ts = le64_to_cpu(tmp);
332 i += 8;
333
334 memcpy(&tmp, buff + i, 6);
335 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
336 i += 6;
337
338 record->mem_channel = buff[i++];
339 record->mcumc_id = buff[i++];
340
341 memcpy(&tmp, buff + i, 6);
342 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
343}
344
345/*
346 * When reaching end of EEPROM memory jump back to 0 record address
347 * When next record access will go beyond EEPROM page boundary modify bits A17/A8
348 * in I2C selector to go to next page
349 */
350static uint32_t __correct_eeprom_dest_address(uint32_t curr_address)
351{
352 uint32_t next_address = curr_address + EEPROM_TABLE_RECORD_SIZE;
353
354 /* When all EEPROM memory used jump back to 0 address */
355 if (next_address > EEPROM_SIZE_BYTES) {
356 DRM_INFO("Reached end of EEPROM memory, jumping to 0 "
357 "and overriding old record");
358 return EEPROM_RECORD_START;
359 }
360
361 /*
362 * To check if we overflow page boundary compare next address with
363 * current and see if bits 17/8 of the EEPROM address will change
364 * If they do start from the next 256b page
365 *
366 * https://www.st.com/resource/en/datasheet/m24m02-dr.pdf sec. 5.1.2
367 */
368 if ((curr_address & EEPROM_ADDR_MSB_MASK) != (next_address & EEPROM_ADDR_MSB_MASK)) {
369 DRM_DEBUG_DRIVER("Reached end of EEPROM memory page, jumping to next: %lx",
370 (next_address & EEPROM_ADDR_MSB_MASK));
371
372 return (next_address & EEPROM_ADDR_MSB_MASK);
373 }
374
375 return curr_address;
376}
377
378int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
379 struct eeprom_table_record *records,
380 bool write,
381 int num)
382{
383 int i, ret = 0;
384 struct i2c_msg *msgs, *msg;
385 unsigned char *buffs, *buff;
386 struct eeprom_table_record *record;
387 struct amdgpu_device *adev = to_amdgpu_device(control);
388
389 if (adev->asic_type != CHIP_VEGA20 && adev->asic_type != CHIP_ARCTURUS)
390 return 0;
391
392 buffs = kcalloc(num, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE,
393 GFP_KERNEL);
394 if (!buffs)
395 return -ENOMEM;
396
397 mutex_lock(&control->tbl_mutex);
398
399 msgs = kcalloc(num, sizeof(*msgs), GFP_KERNEL);
400 if (!msgs) {
401 ret = -ENOMEM;
402 goto free_buff;
403 }
404
405 /* In case of overflow just start from beginning to not lose newest records */
406 if (write && (control->next_addr + EEPROM_TABLE_RECORD_SIZE * num > EEPROM_SIZE_BYTES))
407 control->next_addr = EEPROM_RECORD_START;
408
409
410 /*
411 * TODO Currently makes EEPROM writes for each record, this creates
412 * internal fragmentation. Optimized the code to do full page write of
413 * 256b
414 */
415 for (i = 0; i < num; i++) {
416 buff = &buffs[i * (EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
417 record = &records[i];
418 msg = &msgs[i];
419
420 control->next_addr = __correct_eeprom_dest_address(control->next_addr);
421
422 /*
423 * Update bits 16,17 of EEPROM address in I2C address by setting them
424 * to bits 1,2 of Device address byte
425 */
426 msg->addr = control->i2c_address |
427 ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);
428 msg->flags = write ? 0 : I2C_M_RD;
429 msg->len = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE;
430 msg->buf = buff;
431
432 /* Insert the EEPROM dest addess, bits 0-15 */
433 buff[0] = ((control->next_addr >> 8) & 0xff);
434 buff[1] = (control->next_addr & 0xff);
435
436 /* EEPROM table content is stored in LE format */
437 if (write)
438 __encode_table_record_to_buff(control, record, buff + EEPROM_ADDRESS_SIZE);
439
440 /*
441 * The destination EEPROM address might need to be corrected to account
442 * for page or entire memory wrapping
443 */
444 control->next_addr += EEPROM_TABLE_RECORD_SIZE;
445 }
446
447 ret = i2c_transfer(&adev->pm.smu_i2c, msgs, num);
448 if (ret < 1) {
449 DRM_ERROR("Failed to process EEPROM table records, ret:%d", ret);
450
451 /* TODO Restore prev next EEPROM address ? */
452 goto free_msgs;
453 }
454
455
456 if (!write) {
457 for (i = 0; i < num; i++) {
458 buff = &buffs[i*(EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
459 record = &records[i];
460
461 __decode_table_record_from_buff(control, record, buff + EEPROM_ADDRESS_SIZE);
462 }
463 }
464
465 if (write) {
466 uint32_t old_hdr_byte_sum = __calc_hdr_byte_sum(control);
467
468 /*
469 * Update table header with size and CRC and account for table
470 * wrap around where the assumption is that we treat it as empty
471 * table
472 *
473 * TODO - Check the assumption is correct
474 */
475 control->num_recs += num;
476 control->num_recs %= EEPROM_MAX_RECORD_NUM;
477 control->tbl_hdr.tbl_size += EEPROM_TABLE_RECORD_SIZE * num;
478 if (control->tbl_hdr.tbl_size > EEPROM_SIZE_BYTES)
479 control->tbl_hdr.tbl_size = EEPROM_TABLE_HEADER_SIZE +
480 control->num_recs * EEPROM_TABLE_RECORD_SIZE;
481
482 __update_tbl_checksum(control, records, num, old_hdr_byte_sum);
483
484 __update_table_header(control, buffs);
485 } else if (!__validate_tbl_checksum(control, records, num)) {
486 DRM_WARN("EEPROM Table checksum mismatch!");
487 /* TODO Uncomment when EEPROM read/write is relliable */
488 /* ret = -EIO; */
489 }
490
491free_msgs:
492 kfree(msgs);
493
494free_buff:
495 kfree(buffs);
496
497 mutex_unlock(&control->tbl_mutex);
498
499 return ret == num ? 0 : -EIO;
500}
501
502/* Used for testing if bugs encountered */
503#if 0
504void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control)
505{
506 int i;
507 struct eeprom_table_record *recs = kcalloc(1, sizeof(*recs), GFP_KERNEL);
508
509 if (!recs)
510 return;
511
512 for (i = 0; i < 1 ; i++) {
513 recs[i].address = 0xdeadbeef;
514 recs[i].retired_page = i;
515 }
516
517 if (!amdgpu_ras_eeprom_process_recods(control, recs, true, 1)) {
518
519 memset(recs, 0, sizeof(*recs) * 1);
520
521 control->next_addr = EEPROM_RECORD_START;
522
523 if (!amdgpu_ras_eeprom_process_recods(control, recs, false, 1)) {
524 for (i = 0; i < 1; i++)
525 DRM_INFO("rec.address :0x%llx, rec.retired_page :%llu",
526 recs[i].address, recs[i].retired_page);
527 } else
528 DRM_ERROR("Failed in reading from table");
529
530 } else
531 DRM_ERROR("Failed in writing to table");
532}
533#endif
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu_ras_eeprom.h"
25#include "amdgpu.h"
26#include "amdgpu_ras.h"
27#include <linux/bits.h>
28#include "atom.h"
29#include "amdgpu_eeprom.h"
30#include "amdgpu_atomfirmware.h"
31#include <linux/debugfs.h>
32#include <linux/uaccess.h>
33
34#include "amdgpu_reset.h"
35
36/* These are memory addresses as would be seen by one or more EEPROM
37 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a
38 * set of EEPROM devices. They form a continuous memory space.
39 *
40 * The I2C device address includes the device type identifier, 1010b,
41 * which is a reserved value and indicates that this is an I2C EEPROM
42 * device. It also includes the top 3 bits of the 19 bit EEPROM memory
43 * address, namely bits 18, 17, and 16. This makes up the 7 bit
44 * address sent on the I2C bus with bit 0 being the direction bit,
45 * which is not represented here, and sent by the hardware directly.
46 *
47 * For instance,
48 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0.
49 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h.
50 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h.
51 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may
52 * address memory in a device or a device on the I2C bus, depending on
53 * the status of pins 1-3. See top of amdgpu_eeprom.c.
54 *
55 * The RAS table lives either at address 0 or address 40000h of EEPROM.
56 */
57#define EEPROM_I2C_MADDR_0 0x0
58#define EEPROM_I2C_MADDR_4 0x40000
59
60/*
61 * The 2 macros below represent the actual size in bytes that
62 * those entities occupy in the EEPROM memory.
63 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
64 * uses uint64 to store 6b fields such as retired_page.
65 */
66#define RAS_TABLE_HEADER_SIZE 20
67#define RAS_TABLE_RECORD_SIZE 24
68
69/* Table hdr is 'AMDR' */
70#define RAS_TABLE_HDR_VAL 0x414d4452
71
72/* Bad GPU tag ‘BADG’ */
73#define RAS_TABLE_HDR_BAD 0x42414447
74
75/*
76 * EEPROM Table structure v1
77 * ---------------------------------
78 * | |
79 * | EEPROM TABLE HEADER |
80 * | ( size 20 Bytes ) |
81 * | |
82 * ---------------------------------
83 * | |
84 * | BAD PAGE RECORD AREA |
85 * | |
86 * ---------------------------------
87 */
88
89/* Assume 2-Mbit size EEPROM and take up the whole space. */
90#define RAS_TBL_SIZE_BYTES (256 * 1024)
91#define RAS_TABLE_START 0
92#define RAS_HDR_START RAS_TABLE_START
93#define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE)
94#define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \
95 / RAS_TABLE_RECORD_SIZE)
96
97/*
98 * EEPROM Table structrue v2.1
99 * ---------------------------------
100 * | |
101 * | EEPROM TABLE HEADER |
102 * | ( size 20 Bytes ) |
103 * | |
104 * ---------------------------------
105 * | |
106 * | EEPROM TABLE RAS INFO |
107 * | (available info size 4 Bytes) |
108 * | ( reserved size 252 Bytes ) |
109 * | |
110 * ---------------------------------
111 * | |
112 * | BAD PAGE RECORD AREA |
113 * | |
114 * ---------------------------------
115 */
116
117/* EEPROM Table V2_1 */
118#define RAS_TABLE_V2_1_INFO_SIZE 256
119#define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE
120#define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \
121 RAS_TABLE_V2_1_INFO_SIZE)
122#define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \
123 RAS_TABLE_V2_1_INFO_SIZE) \
124 / RAS_TABLE_RECORD_SIZE)
125
126/* Given a zero-based index of an EEPROM RAS record, yields the EEPROM
127 * offset off of RAS_TABLE_START. That is, this is something you can
128 * add to control->i2c_address, and then tell I2C layer to read
129 * from/write to there. _N is the so called absolute index,
130 * because it starts right after the table header.
131 */
132#define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \
133 (_N) * RAS_TABLE_RECORD_SIZE)
134
135#define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \
136 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE)
137
138/* Given a 0-based relative record index, 0, 1, 2, ..., etc., off
139 * of "fri", return the absolute record index off of the end of
140 * the table header.
141 */
142#define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \
143 (_C)->ras_max_record_count)
144
145#define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \
146 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE)
147
148#define RAS_NUM_RECS_V2_1(_tbl_hdr) (((_tbl_hdr)->tbl_size - \
149 RAS_TABLE_HEADER_SIZE - \
150 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE)
151
152#define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev)
153
154static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
155{
156 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
157 case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */
158 case IP_VERSION(11, 0, 7): /* Sienna cichlid */
159 case IP_VERSION(13, 0, 0):
160 case IP_VERSION(13, 0, 2): /* Aldebaran */
161 case IP_VERSION(13, 0, 10):
162 return true;
163 case IP_VERSION(13, 0, 6):
164 case IP_VERSION(13, 0, 14):
165 return (adev->gmc.is_app_apu) ? false : true;
166 default:
167 return false;
168 }
169}
170
171static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
172 struct amdgpu_ras_eeprom_control *control)
173{
174 struct atom_context *atom_ctx = adev->mode_info.atom_context;
175 u8 i2c_addr;
176
177 if (!control)
178 return false;
179
180 if (amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) {
181 /* The address given by VBIOS is an 8-bit, wire-format
182 * address, i.e. the most significant byte.
183 *
184 * Normalize it to a 19-bit EEPROM address. Remove the
185 * device type identifier and make it a 7-bit address;
186 * then make it a 19-bit EEPROM address. See top of
187 * amdgpu_eeprom.c.
188 */
189 i2c_addr = (i2c_addr & 0x0F) >> 1;
190 control->i2c_address = ((u32) i2c_addr) << 16;
191
192 return true;
193 }
194
195 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
196 case IP_VERSION(11, 0, 2):
197 /* VEGA20 and ARCTURUS */
198 if (adev->asic_type == CHIP_VEGA20)
199 control->i2c_address = EEPROM_I2C_MADDR_0;
200 else if (strnstr(atom_ctx->vbios_pn,
201 "D342",
202 sizeof(atom_ctx->vbios_pn)))
203 control->i2c_address = EEPROM_I2C_MADDR_0;
204 else
205 control->i2c_address = EEPROM_I2C_MADDR_4;
206 return true;
207 case IP_VERSION(11, 0, 7):
208 control->i2c_address = EEPROM_I2C_MADDR_0;
209 return true;
210 case IP_VERSION(13, 0, 2):
211 if (strnstr(atom_ctx->vbios_pn, "D673",
212 sizeof(atom_ctx->vbios_pn)))
213 control->i2c_address = EEPROM_I2C_MADDR_4;
214 else
215 control->i2c_address = EEPROM_I2C_MADDR_0;
216 return true;
217 case IP_VERSION(13, 0, 0):
218 if (strnstr(atom_ctx->vbios_pn, "D707",
219 sizeof(atom_ctx->vbios_pn)))
220 control->i2c_address = EEPROM_I2C_MADDR_0;
221 else
222 control->i2c_address = EEPROM_I2C_MADDR_4;
223 return true;
224 case IP_VERSION(13, 0, 6):
225 case IP_VERSION(13, 0, 10):
226 case IP_VERSION(13, 0, 14):
227 control->i2c_address = EEPROM_I2C_MADDR_4;
228 return true;
229 default:
230 return false;
231 }
232}
233
234static void
235__encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr,
236 unsigned char *buf)
237{
238 u32 *pp = (uint32_t *)buf;
239
240 pp[0] = cpu_to_le32(hdr->header);
241 pp[1] = cpu_to_le32(hdr->version);
242 pp[2] = cpu_to_le32(hdr->first_rec_offset);
243 pp[3] = cpu_to_le32(hdr->tbl_size);
244 pp[4] = cpu_to_le32(hdr->checksum);
245}
246
247static void
248__decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr,
249 unsigned char *buf)
250{
251 u32 *pp = (uint32_t *)buf;
252
253 hdr->header = le32_to_cpu(pp[0]);
254 hdr->version = le32_to_cpu(pp[1]);
255 hdr->first_rec_offset = le32_to_cpu(pp[2]);
256 hdr->tbl_size = le32_to_cpu(pp[3]);
257 hdr->checksum = le32_to_cpu(pp[4]);
258}
259
260static int __write_table_header(struct amdgpu_ras_eeprom_control *control)
261{
262 u8 buf[RAS_TABLE_HEADER_SIZE];
263 struct amdgpu_device *adev = to_amdgpu_device(control);
264 int res;
265
266 memset(buf, 0, sizeof(buf));
267 __encode_table_header_to_buf(&control->tbl_hdr, buf);
268
269 /* i2c may be unstable in gpu reset */
270 down_read(&adev->reset_domain->sem);
271 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
272 control->i2c_address +
273 control->ras_header_offset,
274 buf, RAS_TABLE_HEADER_SIZE);
275 up_read(&adev->reset_domain->sem);
276
277 if (res < 0) {
278 DRM_ERROR("Failed to write EEPROM table header:%d", res);
279 } else if (res < RAS_TABLE_HEADER_SIZE) {
280 DRM_ERROR("Short write:%d out of %d\n",
281 res, RAS_TABLE_HEADER_SIZE);
282 res = -EIO;
283 } else {
284 res = 0;
285 }
286
287 return res;
288}
289
290static void
291__encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai,
292 unsigned char *buf)
293{
294 u32 *pp = (uint32_t *)buf;
295 u32 tmp;
296
297 tmp = ((uint32_t)(rai->rma_status) & 0xFF) |
298 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) |
299 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000);
300 pp[0] = cpu_to_le32(tmp);
301}
302
303static void
304__decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai,
305 unsigned char *buf)
306{
307 u32 *pp = (uint32_t *)buf;
308 u32 tmp;
309
310 tmp = le32_to_cpu(pp[0]);
311 rai->rma_status = tmp & 0xFF;
312 rai->health_percent = (tmp >> 8) & 0xFF;
313 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF;
314}
315
316static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control)
317{
318 struct amdgpu_device *adev = to_amdgpu_device(control);
319 u8 *buf;
320 int res;
321
322 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL);
323 if (!buf) {
324 DRM_ERROR("Failed to alloc buf to write table ras info\n");
325 return -ENOMEM;
326 }
327
328 __encode_table_ras_info_to_buf(&control->tbl_rai, buf);
329
330 /* i2c may be unstable in gpu reset */
331 down_read(&adev->reset_domain->sem);
332 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
333 control->i2c_address +
334 control->ras_info_offset,
335 buf, RAS_TABLE_V2_1_INFO_SIZE);
336 up_read(&adev->reset_domain->sem);
337
338 if (res < 0) {
339 DRM_ERROR("Failed to write EEPROM table ras info:%d", res);
340 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) {
341 DRM_ERROR("Short write:%d out of %d\n",
342 res, RAS_TABLE_V2_1_INFO_SIZE);
343 res = -EIO;
344 } else {
345 res = 0;
346 }
347
348 kfree(buf);
349
350 return res;
351}
352
353static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control)
354{
355 int ii;
356 u8 *pp, csum;
357 size_t sz;
358
359 /* Header checksum, skip checksum field in the calculation */
360 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum);
361 pp = (u8 *) &control->tbl_hdr;
362 csum = 0;
363 for (ii = 0; ii < sz; ii++, pp++)
364 csum += *pp;
365
366 return csum;
367}
368
369static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control)
370{
371 int ii;
372 u8 *pp, csum;
373 size_t sz;
374
375 sz = sizeof(control->tbl_rai);
376 pp = (u8 *) &control->tbl_rai;
377 csum = 0;
378 for (ii = 0; ii < sz; ii++, pp++)
379 csum += *pp;
380
381 return csum;
382}
383
384static int amdgpu_ras_eeprom_correct_header_tag(
385 struct amdgpu_ras_eeprom_control *control,
386 uint32_t header)
387{
388 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
389 u8 *hh;
390 int res;
391 u8 csum;
392
393 csum = -hdr->checksum;
394
395 hh = (void *) &hdr->header;
396 csum -= (hh[0] + hh[1] + hh[2] + hh[3]);
397 hh = (void *) &header;
398 csum += hh[0] + hh[1] + hh[2] + hh[3];
399 csum = -csum;
400 mutex_lock(&control->ras_tbl_mutex);
401 hdr->header = header;
402 hdr->checksum = csum;
403 res = __write_table_header(control);
404 mutex_unlock(&control->ras_tbl_mutex);
405
406 return res;
407}
408
409static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control)
410{
411 struct amdgpu_device *adev = to_amdgpu_device(control);
412 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
413
414 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
415 case IP_VERSION(8, 10, 0):
416 case IP_VERSION(12, 0, 0):
417 hdr->version = RAS_TABLE_VER_V2_1;
418 return;
419 default:
420 hdr->version = RAS_TABLE_VER_V1;
421 return;
422 }
423}
424
425/**
426 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table
427 * @control: pointer to control structure
428 *
429 * Reset the contents of the header of the RAS EEPROM table.
430 * Return 0 on success, -errno on error.
431 */
432int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
433{
434 struct amdgpu_device *adev = to_amdgpu_device(control);
435 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
436 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai;
437 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
438 u8 csum;
439 int res;
440
441 mutex_lock(&control->ras_tbl_mutex);
442
443 hdr->header = RAS_TABLE_HDR_VAL;
444 amdgpu_ras_set_eeprom_table_version(control);
445
446 if (hdr->version == RAS_TABLE_VER_V2_1) {
447 hdr->first_rec_offset = RAS_RECORD_START_V2_1;
448 hdr->tbl_size = RAS_TABLE_HEADER_SIZE +
449 RAS_TABLE_V2_1_INFO_SIZE;
450 rai->rma_status = GPU_HEALTH_USABLE;
451 /**
452 * GPU health represented as a percentage.
453 * 0 means worst health, 100 means fully health.
454 */
455 rai->health_percent = 100;
456 /* ecc_page_threshold = 0 means disable bad page retirement */
457 rai->ecc_page_threshold = con->bad_page_cnt_threshold;
458 } else {
459 hdr->first_rec_offset = RAS_RECORD_START;
460 hdr->tbl_size = RAS_TABLE_HEADER_SIZE;
461 }
462
463 csum = __calc_hdr_byte_sum(control);
464 if (hdr->version == RAS_TABLE_VER_V2_1)
465 csum += __calc_ras_info_byte_sum(control);
466 csum = -csum;
467 hdr->checksum = csum;
468 res = __write_table_header(control);
469 if (!res && hdr->version > RAS_TABLE_VER_V1)
470 res = __write_table_ras_info(control);
471
472 control->ras_num_recs = 0;
473 control->ras_fri = 0;
474
475 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs);
476
477 control->bad_channel_bitmap = 0;
478 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap);
479 con->update_channel_flag = false;
480
481 amdgpu_ras_debugfs_set_ret_size(control);
482
483 mutex_unlock(&control->ras_tbl_mutex);
484
485 return res;
486}
487
488static void
489__encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control,
490 struct eeprom_table_record *record,
491 unsigned char *buf)
492{
493 __le64 tmp = 0;
494 int i = 0;
495
496 /* Next are all record fields according to EEPROM page spec in LE foramt */
497 buf[i++] = record->err_type;
498
499 buf[i++] = record->bank;
500
501 tmp = cpu_to_le64(record->ts);
502 memcpy(buf + i, &tmp, 8);
503 i += 8;
504
505 tmp = cpu_to_le64((record->offset & 0xffffffffffff));
506 memcpy(buf + i, &tmp, 6);
507 i += 6;
508
509 buf[i++] = record->mem_channel;
510 buf[i++] = record->mcumc_id;
511
512 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
513 memcpy(buf + i, &tmp, 6);
514}
515
516static void
517__decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control,
518 struct eeprom_table_record *record,
519 unsigned char *buf)
520{
521 __le64 tmp = 0;
522 int i = 0;
523
524 /* Next are all record fields according to EEPROM page spec in LE foramt */
525 record->err_type = buf[i++];
526
527 record->bank = buf[i++];
528
529 memcpy(&tmp, buf + i, 8);
530 record->ts = le64_to_cpu(tmp);
531 i += 8;
532
533 memcpy(&tmp, buf + i, 6);
534 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
535 i += 6;
536
537 record->mem_channel = buf[i++];
538 record->mcumc_id = buf[i++];
539
540 memcpy(&tmp, buf + i, 6);
541 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
542}
543
544bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev)
545{
546 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
547
548 if (!__is_ras_eeprom_supported(adev) ||
549 !amdgpu_bad_page_threshold)
550 return false;
551
552 /* skip check eeprom table for VEGA20 Gaming */
553 if (!con)
554 return false;
555 else
556 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC)))
557 return false;
558
559 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) {
560 if (amdgpu_bad_page_threshold == -1) {
561 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d",
562 con->eeprom_control.ras_num_recs, con->bad_page_cnt_threshold);
563 dev_warn(adev->dev,
564 "But GPU can be operated due to bad_page_threshold = -1.\n");
565 return false;
566 } else {
567 dev_warn(adev->dev, "This GPU is in BAD status.");
568 dev_warn(adev->dev, "Please retire it or set a larger "
569 "threshold value when reloading driver.\n");
570 return true;
571 }
572 }
573
574 return false;
575}
576
577/**
578 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM
579 * @control: pointer to control structure
580 * @buf: pointer to buffer containing data to write
581 * @fri: start writing at this index
582 * @num: number of records to write
583 *
584 * The caller must hold the table mutex in @control.
585 * Return 0 on success, -errno otherwise.
586 */
587static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,
588 u8 *buf, const u32 fri, const u32 num)
589{
590 struct amdgpu_device *adev = to_amdgpu_device(control);
591 u32 buf_size;
592 int res;
593
594 /* i2c may be unstable in gpu reset */
595 down_read(&adev->reset_domain->sem);
596 buf_size = num * RAS_TABLE_RECORD_SIZE;
597 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
598 control->i2c_address +
599 RAS_INDEX_TO_OFFSET(control, fri),
600 buf, buf_size);
601 up_read(&adev->reset_domain->sem);
602 if (res < 0) {
603 DRM_ERROR("Writing %d EEPROM table records error:%d",
604 num, res);
605 } else if (res < buf_size) {
606 /* Short write, return error.
607 */
608 DRM_ERROR("Wrote %d records out of %d",
609 res / RAS_TABLE_RECORD_SIZE, num);
610 res = -EIO;
611 } else {
612 res = 0;
613 }
614
615 return res;
616}
617
618static int
619amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,
620 struct eeprom_table_record *record,
621 const u32 num)
622{
623 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control));
624 u32 a, b, i;
625 u8 *buf, *pp;
626 int res;
627
628 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
629 if (!buf)
630 return -ENOMEM;
631
632 /* Encode all of them in one go.
633 */
634 pp = buf;
635 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) {
636 __encode_table_record_to_buf(control, &record[i], pp);
637
638 /* update bad channel bitmap */
639 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) &&
640 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
641 control->bad_channel_bitmap |= 1 << record[i].mem_channel;
642 con->update_channel_flag = true;
643 }
644 }
645
646 /* a, first record index to write into.
647 * b, last record index to write into.
648 * a = first index to read (fri) + number of records in the table,
649 * b = a + @num - 1.
650 * Let N = control->ras_max_num_record_count, then we have,
651 * case 0: 0 <= a <= b < N,
652 * just append @num records starting at a;
653 * case 1: 0 <= a < N <= b,
654 * append (N - a) records starting at a, and
655 * append the remainder, b % N + 1, starting at 0.
656 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases,
657 * case 2a: 0 <= a <= b < N
658 * append num records starting at a; and fix fri if b overwrote it,
659 * and since a <= b, if b overwrote it then a must've also,
660 * and if b didn't overwrite it, then a didn't also.
661 * case 2b: 0 <= b < a < N
662 * write num records starting at a, which wraps around 0=N
663 * and overwrite fri unconditionally. Now from case 2a,
664 * this means that b eclipsed fri to overwrite it and wrap
665 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally
666 * set fri = b + 1 (mod N).
667 * Now, since fri is updated in every case, except the trivial case 0,
668 * the number of records present in the table after writing, is,
669 * num_recs - 1 = b - fri (mod N), and we take the positive value,
670 * by adding an arbitrary multiple of N before taking the modulo N
671 * as shown below.
672 */
673 a = control->ras_fri + control->ras_num_recs;
674 b = a + num - 1;
675 if (b < control->ras_max_record_count) {
676 res = __amdgpu_ras_eeprom_write(control, buf, a, num);
677 } else if (a < control->ras_max_record_count) {
678 u32 g0, g1;
679
680 g0 = control->ras_max_record_count - a;
681 g1 = b % control->ras_max_record_count + 1;
682 res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
683 if (res)
684 goto Out;
685 res = __amdgpu_ras_eeprom_write(control,
686 buf + g0 * RAS_TABLE_RECORD_SIZE,
687 0, g1);
688 if (res)
689 goto Out;
690 if (g1 > control->ras_fri)
691 control->ras_fri = g1 % control->ras_max_record_count;
692 } else {
693 a %= control->ras_max_record_count;
694 b %= control->ras_max_record_count;
695
696 if (a <= b) {
697 /* Note that, b - a + 1 = num. */
698 res = __amdgpu_ras_eeprom_write(control, buf, a, num);
699 if (res)
700 goto Out;
701 if (b >= control->ras_fri)
702 control->ras_fri = (b + 1) % control->ras_max_record_count;
703 } else {
704 u32 g0, g1;
705
706 /* b < a, which means, we write from
707 * a to the end of the table, and from
708 * the start of the table to b.
709 */
710 g0 = control->ras_max_record_count - a;
711 g1 = b + 1;
712 res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
713 if (res)
714 goto Out;
715 res = __amdgpu_ras_eeprom_write(control,
716 buf + g0 * RAS_TABLE_RECORD_SIZE,
717 0, g1);
718 if (res)
719 goto Out;
720 control->ras_fri = g1 % control->ras_max_record_count;
721 }
722 }
723 control->ras_num_recs = 1 + (control->ras_max_record_count + b
724 - control->ras_fri)
725 % control->ras_max_record_count;
726Out:
727 kfree(buf);
728 return res;
729}
730
731static int
732amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)
733{
734 struct amdgpu_device *adev = to_amdgpu_device(control);
735 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
736 u8 *buf, *pp, csum;
737 u32 buf_size;
738 int res;
739
740 /* Modify the header if it exceeds.
741 */
742 if (amdgpu_bad_page_threshold != 0 &&
743 control->ras_num_recs >= ras->bad_page_cnt_threshold) {
744 dev_warn(adev->dev,
745 "Saved bad pages %d reaches threshold value %d\n",
746 control->ras_num_recs, ras->bad_page_cnt_threshold);
747 control->tbl_hdr.header = RAS_TABLE_HDR_BAD;
748 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) {
749 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD;
750 control->tbl_rai.health_percent = 0;
751 }
752
753 if (amdgpu_bad_page_threshold != -1)
754 ras->is_rma = true;
755
756 /* ignore the -ENOTSUPP return value */
757 amdgpu_dpm_send_rma_reason(adev);
758 }
759
760 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)
761 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE +
762 RAS_TABLE_V2_1_INFO_SIZE +
763 control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
764 else
765 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE +
766 control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
767 control->tbl_hdr.checksum = 0;
768
769 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
770 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
771 if (!buf) {
772 DRM_ERROR("allocating memory for table of size %d bytes failed\n",
773 control->tbl_hdr.tbl_size);
774 res = -ENOMEM;
775 goto Out;
776 }
777
778 down_read(&adev->reset_domain->sem);
779 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
780 control->i2c_address +
781 control->ras_record_offset,
782 buf, buf_size);
783 up_read(&adev->reset_domain->sem);
784 if (res < 0) {
785 DRM_ERROR("EEPROM failed reading records:%d\n",
786 res);
787 goto Out;
788 } else if (res < buf_size) {
789 DRM_ERROR("EEPROM read %d out of %d bytes\n",
790 res, buf_size);
791 res = -EIO;
792 goto Out;
793 }
794
795 /**
796 * bad page records have been stored in eeprom,
797 * now calculate gpu health percent
798 */
799 if (amdgpu_bad_page_threshold != 0 &&
800 control->tbl_hdr.version == RAS_TABLE_VER_V2_1 &&
801 control->ras_num_recs < ras->bad_page_cnt_threshold)
802 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold -
803 control->ras_num_recs) * 100) /
804 ras->bad_page_cnt_threshold;
805
806 /* Recalc the checksum.
807 */
808 csum = 0;
809 for (pp = buf; pp < buf + buf_size; pp++)
810 csum += *pp;
811
812 csum += __calc_hdr_byte_sum(control);
813 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)
814 csum += __calc_ras_info_byte_sum(control);
815 /* avoid sign extension when assigning to "checksum" */
816 csum = -csum;
817 control->tbl_hdr.checksum = csum;
818 res = __write_table_header(control);
819 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1)
820 res = __write_table_ras_info(control);
821Out:
822 kfree(buf);
823 return res;
824}
825
826/**
827 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table
828 * @control: pointer to control structure
829 * @record: array of records to append
830 * @num: number of records in @record array
831 *
832 * Append @num records to the table, calculate the checksum and write
833 * the table back to EEPROM. The maximum number of records that
834 * can be appended is between 1 and control->ras_max_record_count,
835 * regardless of how many records are already stored in the table.
836 *
837 * Return 0 on success or if EEPROM is not supported, -errno on error.
838 */
839int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
840 struct eeprom_table_record *record,
841 const u32 num)
842{
843 struct amdgpu_device *adev = to_amdgpu_device(control);
844 int res;
845
846 if (!__is_ras_eeprom_supported(adev))
847 return 0;
848
849 if (num == 0) {
850 DRM_ERROR("will not append 0 records\n");
851 return -EINVAL;
852 } else if (num > control->ras_max_record_count) {
853 DRM_ERROR("cannot append %d records than the size of table %d\n",
854 num, control->ras_max_record_count);
855 return -EINVAL;
856 }
857
858 mutex_lock(&control->ras_tbl_mutex);
859
860 res = amdgpu_ras_eeprom_append_table(control, record, num);
861 if (!res)
862 res = amdgpu_ras_eeprom_update_header(control);
863 if (!res)
864 amdgpu_ras_debugfs_set_ret_size(control);
865
866 mutex_unlock(&control->ras_tbl_mutex);
867 return res;
868}
869
870/**
871 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer
872 * @control: pointer to control structure
873 * @buf: pointer to buffer to read into
874 * @fri: first record index, start reading at this index, absolute index
875 * @num: number of records to read
876 *
877 * The caller must hold the table mutex in @control.
878 * Return 0 on success, -errno otherwise.
879 */
880static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
881 u8 *buf, const u32 fri, const u32 num)
882{
883 struct amdgpu_device *adev = to_amdgpu_device(control);
884 u32 buf_size;
885 int res;
886
887 /* i2c may be unstable in gpu reset */
888 down_read(&adev->reset_domain->sem);
889 buf_size = num * RAS_TABLE_RECORD_SIZE;
890 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
891 control->i2c_address +
892 RAS_INDEX_TO_OFFSET(control, fri),
893 buf, buf_size);
894 up_read(&adev->reset_domain->sem);
895 if (res < 0) {
896 DRM_ERROR("Reading %d EEPROM table records error:%d",
897 num, res);
898 } else if (res < buf_size) {
899 /* Short read, return error.
900 */
901 DRM_ERROR("Read %d records out of %d",
902 res / RAS_TABLE_RECORD_SIZE, num);
903 res = -EIO;
904 } else {
905 res = 0;
906 }
907
908 return res;
909}
910
911/**
912 * amdgpu_ras_eeprom_read -- read EEPROM
913 * @control: pointer to control structure
914 * @record: array of records to read into
915 * @num: number of records in @record
916 *
917 * Reads num records from the RAS table in EEPROM and
918 * writes the data into @record array.
919 *
920 * Returns 0 on success, -errno on error.
921 */
922int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
923 struct eeprom_table_record *record,
924 const u32 num)
925{
926 struct amdgpu_device *adev = to_amdgpu_device(control);
927 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
928 int i, res;
929 u8 *buf, *pp;
930 u32 g0, g1;
931
932 if (!__is_ras_eeprom_supported(adev))
933 return 0;
934
935 if (num == 0) {
936 DRM_ERROR("will not read 0 records\n");
937 return -EINVAL;
938 } else if (num > control->ras_num_recs) {
939 DRM_ERROR("too many records to read:%d available:%d\n",
940 num, control->ras_num_recs);
941 return -EINVAL;
942 }
943
944 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
945 if (!buf)
946 return -ENOMEM;
947
948 /* Determine how many records to read, from the first record
949 * index, fri, to the end of the table, and from the beginning
950 * of the table, such that the total number of records is
951 * @num, and we handle wrap around when fri > 0 and
952 * fri + num > RAS_MAX_RECORD_COUNT.
953 *
954 * First we compute the index of the last element
955 * which would be fetched from each region,
956 * g0 is in [fri, fri + num - 1], and
957 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1].
958 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of
959 * the last element to fetch, we set g0 to _the number_
960 * of elements to fetch, @num, since we know that the last
961 * indexed to be fetched does not exceed the table.
962 *
963 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then
964 * we set g0 to the number of elements to read
965 * until the end of the table, and g1 to the number of
966 * elements to read from the beginning of the table.
967 */
968 g0 = control->ras_fri + num - 1;
969 g1 = g0 % control->ras_max_record_count;
970 if (g0 < control->ras_max_record_count) {
971 g0 = num;
972 g1 = 0;
973 } else {
974 g0 = control->ras_max_record_count - control->ras_fri;
975 g1 += 1;
976 }
977
978 mutex_lock(&control->ras_tbl_mutex);
979 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0);
980 if (res)
981 goto Out;
982 if (g1) {
983 res = __amdgpu_ras_eeprom_read(control,
984 buf + g0 * RAS_TABLE_RECORD_SIZE,
985 0, g1);
986 if (res)
987 goto Out;
988 }
989
990 res = 0;
991
992 /* Read up everything? Then transform.
993 */
994 pp = buf;
995 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) {
996 __decode_table_record_from_buf(control, &record[i], pp);
997
998 /* update bad channel bitmap */
999 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) &&
1000 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
1001 control->bad_channel_bitmap |= 1 << record[i].mem_channel;
1002 con->update_channel_flag = true;
1003 }
1004 }
1005Out:
1006 kfree(buf);
1007 mutex_unlock(&control->ras_tbl_mutex);
1008
1009 return res;
1010}
1011
1012uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control)
1013{
1014 /* get available eeprom table version first before eeprom table init */
1015 amdgpu_ras_set_eeprom_table_version(control);
1016
1017 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)
1018 return RAS_MAX_RECORD_COUNT_V2_1;
1019 else
1020 return RAS_MAX_RECORD_COUNT;
1021}
1022
1023static ssize_t
1024amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf,
1025 size_t size, loff_t *pos)
1026{
1027 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1028 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1029 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
1030 u8 data[50];
1031 int res;
1032
1033 if (!size)
1034 return size;
1035
1036 if (!ras || !control) {
1037 res = snprintf(data, sizeof(data), "Not supported\n");
1038 } else {
1039 res = snprintf(data, sizeof(data), "%d bytes or %d records\n",
1040 RAS_TBL_SIZE_BYTES, control->ras_max_record_count);
1041 }
1042
1043 if (*pos >= res)
1044 return 0;
1045
1046 res -= *pos;
1047 res = min_t(size_t, res, size);
1048
1049 if (copy_to_user(buf, &data[*pos], res))
1050 return -EFAULT;
1051
1052 *pos += res;
1053
1054 return res;
1055}
1056
1057const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = {
1058 .owner = THIS_MODULE,
1059 .read = amdgpu_ras_debugfs_eeprom_size_read,
1060 .write = NULL,
1061 .llseek = default_llseek,
1062};
1063
1064static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n";
1065static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n";
1066#define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1)
1067static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n";
1068static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n";
1069#define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1)
1070
1071static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = {
1072 "ignore",
1073 "re",
1074 "ue",
1075};
1076
1077static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control)
1078{
1079 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size +
1080 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs;
1081}
1082
1083void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control)
1084{
1085 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras,
1086 eeprom_control);
1087 struct dentry *de = ras->de_ras_eeprom_table;
1088
1089 if (de)
1090 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control);
1091}
1092
1093static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf,
1094 size_t size, loff_t *pos)
1095{
1096 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1097 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1098 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control;
1099 const size_t orig_size = size;
1100 int res = -EFAULT;
1101 size_t data_len;
1102
1103 mutex_lock(&control->ras_tbl_mutex);
1104
1105 /* We want *pos - data_len > 0, which means there's
1106 * bytes to be printed from data.
1107 */
1108 data_len = strlen(tbl_hdr_str);
1109 if (*pos < data_len) {
1110 data_len -= *pos;
1111 data_len = min_t(size_t, data_len, size);
1112 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len))
1113 goto Out;
1114 buf += data_len;
1115 size -= data_len;
1116 *pos += data_len;
1117 }
1118
1119 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size;
1120 if (*pos < data_len && size > 0) {
1121 u8 data[tbl_hdr_fmt_size + 1];
1122 loff_t lpos;
1123
1124 snprintf(data, sizeof(data), tbl_hdr_fmt,
1125 control->tbl_hdr.header,
1126 control->tbl_hdr.version,
1127 control->tbl_hdr.first_rec_offset,
1128 control->tbl_hdr.tbl_size,
1129 control->tbl_hdr.checksum);
1130
1131 data_len -= *pos;
1132 data_len = min_t(size_t, data_len, size);
1133 lpos = *pos - strlen(tbl_hdr_str);
1134 if (copy_to_user(buf, &data[lpos], data_len))
1135 goto Out;
1136 buf += data_len;
1137 size -= data_len;
1138 *pos += data_len;
1139 }
1140
1141 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str);
1142 if (*pos < data_len && size > 0) {
1143 loff_t lpos;
1144
1145 data_len -= *pos;
1146 data_len = min_t(size_t, data_len, size);
1147 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size;
1148 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len))
1149 goto Out;
1150 buf += data_len;
1151 size -= data_len;
1152 *pos += data_len;
1153 }
1154
1155 data_len = amdgpu_ras_debugfs_table_size(control);
1156 if (*pos < data_len && size > 0) {
1157 u8 dare[RAS_TABLE_RECORD_SIZE];
1158 u8 data[rec_hdr_fmt_size + 1];
1159 struct eeprom_table_record record;
1160 int s, r;
1161
1162 /* Find the starting record index
1163 */
1164 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
1165 strlen(rec_hdr_str);
1166 s = s / rec_hdr_fmt_size;
1167 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
1168 strlen(rec_hdr_str);
1169 r = r % rec_hdr_fmt_size;
1170
1171 for ( ; size > 0 && s < control->ras_num_recs; s++) {
1172 u32 ai = RAS_RI_TO_AI(control, s);
1173 /* Read a single record
1174 */
1175 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1);
1176 if (res)
1177 goto Out;
1178 __decode_table_record_from_buf(control, &record, dare);
1179 snprintf(data, sizeof(data), rec_hdr_fmt,
1180 s,
1181 RAS_INDEX_TO_OFFSET(control, ai),
1182 record_err_type_str[record.err_type],
1183 record.bank,
1184 record.ts,
1185 record.offset,
1186 record.mem_channel,
1187 record.mcumc_id,
1188 record.retired_page);
1189
1190 data_len = min_t(size_t, rec_hdr_fmt_size - r, size);
1191 if (copy_to_user(buf, &data[r], data_len)) {
1192 res = -EFAULT;
1193 goto Out;
1194 }
1195 buf += data_len;
1196 size -= data_len;
1197 *pos += data_len;
1198 r = 0;
1199 }
1200 }
1201 res = 0;
1202Out:
1203 mutex_unlock(&control->ras_tbl_mutex);
1204 return res < 0 ? res : orig_size - size;
1205}
1206
1207static ssize_t
1208amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf,
1209 size_t size, loff_t *pos)
1210{
1211 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1212 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1213 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
1214 u8 data[81];
1215 int res;
1216
1217 if (!size)
1218 return size;
1219
1220 if (!ras || !control) {
1221 res = snprintf(data, sizeof(data), "Not supported\n");
1222 if (*pos >= res)
1223 return 0;
1224
1225 res -= *pos;
1226 res = min_t(size_t, res, size);
1227
1228 if (copy_to_user(buf, &data[*pos], res))
1229 return -EFAULT;
1230
1231 *pos += res;
1232
1233 return res;
1234 } else {
1235 return amdgpu_ras_debugfs_table_read(f, buf, size, pos);
1236 }
1237}
1238
1239const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = {
1240 .owner = THIS_MODULE,
1241 .read = amdgpu_ras_debugfs_eeprom_table_read,
1242 .write = NULL,
1243 .llseek = default_llseek,
1244};
1245
1246/**
1247 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum
1248 * @control: pointer to control structure
1249 *
1250 * Check the checksum of the stored in EEPROM RAS table.
1251 *
1252 * Return 0 if the checksum is correct,
1253 * positive if it is not correct, and
1254 * -errno on I/O error.
1255 */
1256static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control)
1257{
1258 struct amdgpu_device *adev = to_amdgpu_device(control);
1259 int buf_size, res;
1260 u8 csum, *buf, *pp;
1261
1262 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)
1263 buf_size = RAS_TABLE_HEADER_SIZE +
1264 RAS_TABLE_V2_1_INFO_SIZE +
1265 control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
1266 else
1267 buf_size = RAS_TABLE_HEADER_SIZE +
1268 control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
1269
1270 buf = kzalloc(buf_size, GFP_KERNEL);
1271 if (!buf) {
1272 DRM_ERROR("Out of memory checking RAS table checksum.\n");
1273 return -ENOMEM;
1274 }
1275
1276 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1277 control->i2c_address +
1278 control->ras_header_offset,
1279 buf, buf_size);
1280 if (res < buf_size) {
1281 DRM_ERROR("Partial read for checksum, res:%d\n", res);
1282 /* On partial reads, return -EIO.
1283 */
1284 if (res >= 0)
1285 res = -EIO;
1286 goto Out;
1287 }
1288
1289 csum = 0;
1290 for (pp = buf; pp < buf + buf_size; pp++)
1291 csum += *pp;
1292Out:
1293 kfree(buf);
1294 return res < 0 ? res : csum;
1295}
1296
1297static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control)
1298{
1299 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai;
1300 struct amdgpu_device *adev = to_amdgpu_device(control);
1301 unsigned char *buf;
1302 int res;
1303
1304 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL);
1305 if (!buf) {
1306 DRM_ERROR("Failed to alloc buf to read EEPROM table ras info\n");
1307 return -ENOMEM;
1308 }
1309
1310 /**
1311 * EEPROM table V2_1 supports ras info,
1312 * read EEPROM table ras info
1313 */
1314 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1315 control->i2c_address + control->ras_info_offset,
1316 buf, RAS_TABLE_V2_1_INFO_SIZE);
1317 if (res < RAS_TABLE_V2_1_INFO_SIZE) {
1318 DRM_ERROR("Failed to read EEPROM table ras info, res:%d", res);
1319 res = res >= 0 ? -EIO : res;
1320 goto Out;
1321 }
1322
1323 __decode_table_ras_info_from_buf(rai, buf);
1324
1325Out:
1326 kfree(buf);
1327 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res;
1328}
1329
1330int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
1331{
1332 struct amdgpu_device *adev = to_amdgpu_device(control);
1333 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 };
1334 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
1335 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1336 int res;
1337
1338 ras->is_rma = false;
1339
1340 if (!__is_ras_eeprom_supported(adev))
1341 return 0;
1342
1343 /* Verify i2c adapter is initialized */
1344 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo)
1345 return -ENOENT;
1346
1347 if (!__get_eeprom_i2c_addr(adev, control))
1348 return -EINVAL;
1349
1350 control->ras_header_offset = RAS_HDR_START;
1351 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START;
1352 mutex_init(&control->ras_tbl_mutex);
1353
1354 /* Read the table header from EEPROM address */
1355 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1356 control->i2c_address + control->ras_header_offset,
1357 buf, RAS_TABLE_HEADER_SIZE);
1358 if (res < RAS_TABLE_HEADER_SIZE) {
1359 DRM_ERROR("Failed to read EEPROM table header, res:%d", res);
1360 return res >= 0 ? -EIO : res;
1361 }
1362
1363 __decode_table_header_from_buf(hdr, buf);
1364
1365 if (hdr->version == RAS_TABLE_VER_V2_1) {
1366 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr);
1367 control->ras_record_offset = RAS_RECORD_START_V2_1;
1368 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1;
1369 } else {
1370 control->ras_num_recs = RAS_NUM_RECS(hdr);
1371 control->ras_record_offset = RAS_RECORD_START;
1372 control->ras_max_record_count = RAS_MAX_RECORD_COUNT;
1373 }
1374 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset);
1375
1376 if (hdr->header == RAS_TABLE_HDR_VAL) {
1377 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
1378 control->ras_num_recs);
1379
1380 if (hdr->version == RAS_TABLE_VER_V2_1) {
1381 res = __read_table_ras_info(control);
1382 if (res)
1383 return res;
1384 }
1385
1386 res = __verify_ras_table_checksum(control);
1387 if (res)
1388 DRM_ERROR("RAS table incorrect checksum or error:%d\n",
1389 res);
1390
1391 /* Warn if we are at 90% of the threshold or above
1392 */
1393 if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold)
1394 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d",
1395 control->ras_num_recs,
1396 ras->bad_page_cnt_threshold);
1397 } else if (hdr->header == RAS_TABLE_HDR_BAD &&
1398 amdgpu_bad_page_threshold != 0) {
1399 if (hdr->version == RAS_TABLE_VER_V2_1) {
1400 res = __read_table_ras_info(control);
1401 if (res)
1402 return res;
1403 }
1404
1405 res = __verify_ras_table_checksum(control);
1406 if (res)
1407 DRM_ERROR("RAS Table incorrect checksum or error:%d\n",
1408 res);
1409 if (ras->bad_page_cnt_threshold > control->ras_num_recs) {
1410 /* This means that, the threshold was increased since
1411 * the last time the system was booted, and now,
1412 * ras->bad_page_cnt_threshold - control->num_recs > 0,
1413 * so that at least one more record can be saved,
1414 * before the page count threshold is reached.
1415 */
1416 dev_info(adev->dev,
1417 "records:%d threshold:%d, resetting "
1418 "RAS table header signature",
1419 control->ras_num_recs,
1420 ras->bad_page_cnt_threshold);
1421 res = amdgpu_ras_eeprom_correct_header_tag(control,
1422 RAS_TABLE_HDR_VAL);
1423 } else {
1424 dev_err(adev->dev, "RAS records:%d exceed threshold:%d",
1425 control->ras_num_recs, ras->bad_page_cnt_threshold);
1426 if (amdgpu_bad_page_threshold == -1) {
1427 dev_warn(adev->dev, "GPU will be initialized due to bad_page_threshold = -1.");
1428 res = 0;
1429 } else {
1430 ras->is_rma = true;
1431 dev_err(adev->dev,
1432 "RAS records:%d exceed threshold:%d, "
1433 "GPU will not be initialized. Replace this GPU or increase the threshold",
1434 control->ras_num_recs, ras->bad_page_cnt_threshold);
1435 }
1436 }
1437 } else {
1438 DRM_INFO("Creating a new EEPROM table");
1439
1440 res = amdgpu_ras_eeprom_reset_table(control);
1441 }
1442
1443 return res < 0 ? res : 0;
1444}